repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_sshft.vhd | 9 | 19058 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
V0RhEmDneyx2bIYg5EkqMn5D103c8LY0JwOi4vIzIundV7pB4mhwtg3bWvXtJcqVzWoRpO0iu6hd
b5vQvw4OIw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NPilDSqrDwgfnG8QwrK9pzdKc2EyBdnxvte2xUHdXc3XmUSDWcLQM8tlHwjTc0fmRllJEyeVIoy3
+OOdcqUxWRXdJnmylHty6xJAg+/Sjpcxt9Wndn8Uj6P+DnRcBtrGwDKuQj9OLMJ2nyzTdGslagCW
2MvrokQETmpzJTx+xn8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BIsdTK6SsXN9BbudzwhdR157/hy8fR+veNFLoFYP4d7KK59/1qX9WEKIjXxdh6jOd9oKlk3wq1R4
tCRvMmX9QIrfX9P0eZ0ywyvtLKYMELricLvzLddzGzGXy45L0UR5z6O6iyAmkbswbaxcV/rFdbfp
+MvPSi29zYu+Ik9PGyM0ZLMRujFCTsVjn0LMR+fwPr0R95gAkMGuKpIq0+RcQreroLO5g0p7eM5g
T/nITDKgCwo16W0hWmHYCWVIzSS+jaS6O+hzNbme01d4Haq/09X81kExJZmAz6suZ/M5pGiw45sW
uX/NO+nhlJA/4TP3Ii6Su4We30OsNmkV9XudsA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Zw5vs1IfRKfJY2nstDiEd4QSSb7enWH38yjPDIbhpMKIURm1dzfEQqhIvXlwk78QLnr5oU9yFaBT
ulET/5iZm6HXM5TLkrDD7mrsT1wRIzGsWjZJAEjdqivu/Cffrl7vEFxtjUAOwCu2hWlDOzxYA40p
EN3J2XA1bMOAqQafEN4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dnOhe7VK3QkpSD5kx1h0DtWGGzmZirboP8jSaNNmyrqJDjh6AzuWE7WlC7GznQi6/XDLxfUKzLta
BUfpsw3uzYCN4o5mq3R7oEX/c/2vvZquACpkb+6ddj4+NjUwsUcyq3b1StXepqpUUAsSPsne7xiL
Wqm5ZYKFKZkGIY51iEY/x09IrCADOEbB8KNitAUfWXQ8jJU2/5YxLeLKEUA7bO/nIoZudUMSFc+m
CiGC9wGaqecuGX/ccHA4hcqekr1yT11hr+Wr7qi13IB0OVTjakXH7phfvhCBquh3C418MF8o1PD3
zPppyLec68s7ZGvu0bZsnINA5R381Y53bX0OGw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12368)
`protect data_block
vK6cYwjcQhndWcb9L7IQrZd9Li+VJB7JOgTTZDFG1KOeomh7cKgqDeszrDqvc+zsGAdox6KWCR9M
T6W/8TM5MtQIUpgr0PExzY6QfmHbNbGSxXwKXgaGdIEuHWNG6z56IJP6pXHnYVaGTVfqdY/T9axm
5QhH/5CMyPbIvhalNFLw9NhNoxVzBXH5qQgnJ4Hc3X3f1ReZ8bbyvtHO23jOhOeVgvmwmhIEhLbt
1QhmzpYJ2Joj9sbHmbuj35xCF7VZD7Wlb3lI/U4QO5TEsubd5V0wxgHHGj7H+uCo9uZwIr+dx4rI
ZKxAhKbJX0US/511QDpquP6PjvZpEO/0ARPsZJJS0Dr/KYycyuDCIxHmRMg1LJty9iJskWsbqyIC
dBMc9VQN+o9U4MSJVvAL+VI6FlMchxyhi+3QVFEasHiU2xakPs2kc2dkr1Xvl9pwonVDXXgZrwmh
POF9z1nbYdsi/qf8n+yZDoZSLF8isthAAX0GEahqg+eJel6ygvP303jCcGLbcBerBFPLBAhpFXdU
MTQnlSbBRaMWovDXgEJAX+dpePwfl1R4S1sIkkRZsJnmVxwyoUH569DMYLiNzCIIqrR2U64Q5xbp
ZpS/0E/xV/mep08zHyMuvb7ZQhaH5SQFFidhG0lJK5b9YzizGsoUr5WtPZ2ZJhPLrMSokOqwtUsW
nOn2XO9h+uf7Cextsujkhzo4DxKSrt+y2nbUx3Z5jbzZR9EIwrqaX7y2Y1uSjk0y45E9oiHJJKfQ
tfQteFvxnfDzVLd+O4YOuFWvR0n2i7bsHIg+xWlxrilQJusPMHkWlOsLeibI8ExhFKFnUTxQBk9q
u0D7OF2gBspTExKOJo0l3lsVrmnPHHB5ms1cuWIuG7H67+jbm3sVKG+Hm5IElRP49NLNqSHOgoyu
kRX66WlKB/p7smg6ZaiJv7WRi8t+0Bi9bZbIQ4RrgmaipEtzi+HMgnzFDy5DhcDB5dmczlfUPSA0
W5fH1iwzA2rutLeIaBUHc+Wk/si6T35ZyBn94+p00FStc7w+wlBLwSdXmWGVjlDled9N4v9pFxif
lt3U+lDXLfWf2tQL0MwECDexBmubhti0E4A/1JLewveeLTb8p84dfeoeYxHjrvpLodRvz6ubuT1a
M+gLNOPoO7hsBTZUiLv12AAZZgMV26ffY2lphcxHdCZ6TgcIudt7fGxoRq55kQOZ32sxUq3M09yH
gLAwEGrYebiqrdCJl0asQPu7QUTmZ2JCY3gVrclKWWomQofRgFOSOa2F84OwR4VooRvWZgWCrZMu
gbP4r6S0pkG2gO1CDOx0eAfpQIF03UpEkHEIxHjFlNPxUhkZMOkfD0LN53FexYqoi+vrx+5SdQtS
4qJwmounb07u08bTXuI8UAteFXFac4D/R1V99Fs9oQpjs5GetuuvbeHtm9S/0dc2edxIgRPe85hG
G55rXiY57PcEm/zs+VI5wjKoLF5hY9mwUpBe5Ph0YxJij+gvbxB7692e08nlCvMfzjRODZPp5puI
cN52I1O0YckAlBfBOkbZia95KW2M0Vz6qtJvyVTVVgY/Xnt+uw/neDy9rHwHQTuuEdNrQjhNJma7
c2PpD60gaqv1epFyV9X4C0k/+WJr6I/eizGEUEzQ+6aJxIY4sy3tZlC9mrPmjUjlffp4EKe7SnDP
OWKz4snr6jueIoQV/0BmC+23j4jxyyibA2pgG4dsbzVrkwMe85R69KpRMfDR7KaOJf6WzI1yaJ1m
WBVEL/DQ6n5sLvZamZs8W0VX6yjYqzsSmIkDNdZg8EdWQn2RBu6z++t4H4NCWwfAkxewP2C/cFG9
NZr7zfF8tE5rIjiWGsJ0mwGceUkyLrCDYfHisKhWN0dKZHjZG0E1iFx6E+8U/OZGjBvTB9uKzz9i
tA/a7RIk2xTraLI5gMGv/nwBIW5L8zP3TYC0d++MqR7/faN76Peb+IExlhm3G49Lucc56nKQxCuQ
7Q2wTaYFqHzQ8WFqeK0EdVEYF79atGGXkDA4cgEROjCbRp5r0Y3uBgJkO+We842JHY94hobQEKGk
iHcEiW1THw43AY8Kh2tXbOFkPbQ2+Djfr+0Wc/U2p9FZh13yiYZlcxb0Fz2JPIvAK0xEKkFFU1Ty
HA2og2pggv/DWWP/tyiGH6tVmruGkDqxcqu/NDs0QaZj6svyRAbfIMKL2tunDWd9Gm4wiA9+esJw
YTGitIYtkWU/afo1YTTEFWNR3oo5CjG8jWIAgBVHBX3/XBLQDDqFLy4Mj39m9BN5DDBi1Hxob/0z
5PuqutP941oNUoOLrjaApNrheeUoAWN9tdm8HZaNzvV5eIYVi8gucoFfQaCflc5YaIbPKjJiQWwl
abtTUzoFW2/SuKi3FfmkddXltt1b+7+ykXE8FqZOWlEoHB0zwulllTFrJ6cp+8fE+XgfWlWfjqAZ
mnfe04feQqeHMAFGfqGNTXZNl5Q1HQIwXmvqZOcNbbRyelRvDNVuLxvvFoALKzTMaB330U8JL2xj
pNloPShp0oDJv8mwFqHQ38yO0MTWSI7uVUoHqfaUN7hMPTfU5+6u8gWmTy0vPe8bibPasbPuqaU3
72S6/U9LEShHiiHQPB0uig8tv76uMaR5xdc8oCJVtc7H8vrdOjjEnDCTble4+VG9JQROS63HAp2B
SkP3jeDE5oTQtPS7c4zIW5W11wQzBmSBncokcWMFamTBJX+prWYKaJ14CYbq+e/b1rQUQkh89r9p
GN9C49s4jQD7n2RcnHJJ0eeEdrA60f7ajwZSUVT1w6QU++HalsF1KI824b2esd1Rr11/3p2hlJa1
4jITz3Qc6SZpyYp+PBlCDSMyx8Y7zY4pwen3vlUuypnWLDuI5psUht/RgrXO9YHzc9G3GCLZpbPW
SP/WbiVSzD21IN1GXYwxNEor54nIAIsmdB+Z0Ljq8K4zoKC+xxetorjqWqtjy7dQzSOfrRX1z7Nx
nbypNc81sj2tLm8a2vH/efpE6ZFZ+08btA+fKr1XhIdLuM0+5Vw6Nrbbup9O20fT/F2AsyZavShv
Lucy0Os/frhq97QlwVRaobBF1QT+rlDJ0sT3bETHYSCWhAfw7prgbgLIUEcuLsCELo4pZk8Due3a
zzjZGHLyJiGW8yhb6TlQ491n+/jVe3bBonoZrnepXP3y6fBFjIFNQHZJ25Fb4kiAhqvvASXQE5IJ
rbhkyDsvrOTuuRTlcDYPisAB7K1N+a8JwRNVrYxcI/kNRElVC6i27rpFN+Gaoi+v3nOmJrREfn/h
0JciozVg2PZaWWHYNBSfYfZdC/ikFzrszGHffDptcUbsLawjGFENrL+mmSwADLphMFPzfY9Nv9Vf
dRNczqx1/OOGL94cXABVt/LCKi3tm6iKhL+VGfbqFS9Icb6X3g02pm21TW8Tbu+CdRZMTcbKlj2X
W2P8Gh7N8AU98X1Em4pxL/P6pdEvBJg3Tu+CO/Rr0vnkaDF4iRJdNvdD0iBKSU7TTVkaD76kUcRq
3l3TExuzJ+z86Lv0rKNOjTWxNipThIpQn4BLT1ZrfOty16vYbVx+OVEMAFVNYHNHOcqORoSuhelY
WLsfgcbHLyyf5pEHQXOZbAHom5FSIQ+XkYBDDCnP8kM9d4o8no6UoELLvYAmgt+SmuBKBooc0y1h
YPHmGwolbwe3saeIUEScTnbg94ROm2PXptluaLWgmaHQL+Qlj1rdLRc5uIuEZZAqhR+cjJ3/m8ZU
0RnNchY72mS2aVHIkjxlHkEypVpQ5vkLYv9fb8hQS249pte32GZAp1DMFgYs9iJvi38cQcpGn6ob
Os5Pdt4hTEbCxElGJQ2yL4QcAAOrndq+CqR433YJzBFpnglTu/EyIBNwu1lGO/iu5tJNC+FEyI+k
aflf8fCvSB9NLj48bUdk2L9zg0wHXNiQjer9wf46Itw+Tk4q6q6LvYsVLsHwWIcOK38ZQ6DGplpa
2JM65M6TETekR9JOKudZ96/rxlOKQ3DqRqBBqu4/mfvVd4filhcNs8TcnEVLbhiktEWT1pI9J1MX
FcB9Zpgr64XrDGFTjOciLyOz45kGQunKNebe9ZYs+xexv92q7apmjEGLbAzNkCBdJXQKsZMlpMX8
pePY+USanTzRLZZSv3isLA83P8lHtjSkV6aT409oVnvJoiGJHkjCbtp9k1EufJ1DoqpS2FCgt4v0
puj76DQykO/EyZKf3JRm/jIODHIvU0x6quB5H/9QVXVb2sQzZXB+1BX6mbNqmH4t1ek+4zr8mz0n
lEZGWnZMp10R4iMm1AIqtjB2Nr1ZHEcwjNXtPzxQvX4JlN5A0DJOkT+Hw+5DIqsRswTrteMHoJsB
QaW23ny1dPKWSola1AMJhFgCYoA76am66CurD+VOFlV0PEvqaLjM4TT1iiZtgsaYKyO+UgpglkpM
uhc3CdNJ35yXuhfHVlaGIbhSauNat1jV8Hwel0iqeszHQp3XN0T8mL3e2/LSwdZswvBjfw/AQoqV
dJuDL0R8W4H91qeCG0fACekm6ar2ST+vB9EtvnRSaHAQj2wUK5uzSE6IhPpbvhtqSWz7gmD1ymEs
gSoVtQ+Qoil62X/RIfY6fJx2BHPzLO9nSAuXCTTs3sGjHz+4YPlpDzhJdLTOeFqKIXcHjzNo6SFQ
QG7ygaXM4DPl8RSyl4xgSc4u1rNeEYFjQYWhUmccOe05Xken+E9/aom1F/gIoOyJ+ZbqbOclCtl2
fc+3zrFnys7NkSk1kVXjFBdH/RmRwvmecRNYAcYkE1dXo0hSRvA6JPfShEKmMNViqUuOJ40x3Lrm
h5pa9uCFHdtgRtWTOHMg+YGQ7qZlhWNbGNfXpCX499rAoC5QHjnRrm07UpRsNnqyW5FlQSl/h+rU
Qx2hbg/HFWn0z+ia54y9iI6oc/f6vbPfMevXx2KkBSAcA+wdsnzu2/QKPQhWQMMxuhYiHUPyeBkB
oBRkfA/YwhTl1t4NcRIXVWaGu7wxW9pswwledu5NgSxP1VvLJt4x9Ez/AREoNs5mO/i4Ab0MG7G2
3DgGouONG8p2n67Gd8rX9IMmzeNAhDb6wdjP4q+/r+W9leHVzzuAE+gFA1YvtRkMwZhYyUgx3yfg
QzohJj1t1EawU5ZMEpLV6NpOF5QpXDvVsUaGXDxzjFuS0Tnw0+9Rr/4HOPcfi0vH0jiFZB+XhOen
S9nfCMFFRktF7E4YbbI1ScByW7Abb5EhpcqSsKBHS0mysyWq7XGOhM5HqRhV1FoLCbtdE0dLUXBu
fUT9uROmh3SjACZfpI5JPGChJ49oF9hxcbO6i0KE90MrnCMBfHozv+3AVmttU/ddCTD4Az3Pn3Ft
6Nk5cTXn0+dpbFFbIqZXUF2EJHr+Gk5O4g+F8BVO+ys8GsCFYUHVwsRq4JvMzf7sHP9K9axcV1Tf
DwfuWLToe5bi+lchDQ/rEW1P00g7TSmvv0+WsQMiP8CtHvXLgLXRUbsgz9utz3ZvKDGfTQFRupJO
fsyU6hE1UBkMiv9TCVmWVKWTKt/rWTKxPqF2mKA8CmSVpkzSx4/3AwXcDz3sGKtQLHTaEWTi/DiB
6WfjCYEWntnBXWwPbvY1RhZQOmgOXTpLdSrQTpSqzjb/2OW6qQftTra7STLSoCVypgDZiqRmgHkF
mfsWvpygv1ZO7F3lHMkE6U2s32G5bjyxTjytufvQUKmHeSj7t2syhL1vfXigoOrW59UZ2bvarXVD
VTrCvjTedmmye+hHz9iQtgDgLbcEczhjqJEXyyGZTrwk3Lo2nXnlakHoqq+dlVse0iTVUcIwlNoy
GgTViJ4FEeW7/pI9nt+4bquA/Y5A3yR6l1/GIRleCKjMxCgPin3YofJ2OpQKuWWEIfd3NdqctNcO
k5ygexZtw13XTDlC3BofexvGQee6moAv5aJA4t6n9vloqqWihg0B54HyLXvF11IBWv142tjMi5jW
qswDarf88paqpFnsjNkdPlQF8QjspXoFQyt5nAF2YHjbUMn9i+yVeCOMzx2D/OtX9/WOHpyavhMZ
VAHZcBY+bC+lS9pNp2o+pR9/w6rP7coWD4uBIIQqrO2e27OmCWCX4CcMdi7gUc769u31eg0DfVaL
zkQKE+DAUfPpFj5sGbjVOZJLqXjrAPoDSeGC73S2lZH4XbtXn3p6jSqYWwtRMol6eGBULyq6Bxu7
joPnntc6MTvdXuiNC+ZaB/q09SSEkjx2cwE3MzD867ggibGYeJ+miFjzcwlUvBOwSiZa45DYrvTT
j2yWM7e+vHchK6AArgV/q+vk1QAHbpwnOf2A5cHOZ7Pg1KfeJ0HjSmp0PCFYYHIjXZj5gJdi5jwK
l8VLWFglQ7gD6XcnxQuFQNxD9Myu6/teS/cdIGDzpVZ9/VSq8rJ7Ix3qf5Ax9Bdcb4zFIlsJLGJH
9piNV43r9x8g33YZl6TYf5iUXGGwsXtnYYlf/vM77RgGB+XlqD5BYZeNpqDA117GX28PyNiMZOrL
6AeAjCqZJKKVhuf7teqOpVAu72TpEBPhZZUnXCGVVyL32W86sUnNmFNIQs6oKCqT0xB7EzhxXHNu
74d7gI5MsABf/eoUbFeeFsZ8dILbyDa000N8e0WIhW9Fn1wU/+2xuhz5i8cbJxVLYJBff6KtAmj1
Ur8RjaKewPI/GrwDX9tToN8ABAE8asgpLdHWkUC8M6YtxX+ZCmozMSl2+wngQVt7rhz3a/TeMJw+
ThbJwYoqBa+QPutOgWd1ecnicdyAcdhxwOab1Wfxj3O8S4Sl0T18ur5Hwb+7A6D6ZSxJV2/EvPiN
MN20321WB3a3ltqY5RqItls1UyxKPAJhMjXOVSj24r4idARTxly8ZDBhgQixOH4UapyE4RCHcf+l
j8joyxw6rO4YP5H+5qDEwf64NNMvwdnahOWEEUYHFY/trJBNArL8f0t+vDI3dnCwMqp4bzY9i6Ua
/fgYrqJrkaORFdE/qDsS0hDvSN979ZhAIENjxY6qhUuwkFoH4UwZtwW+Vm3zEfEjs4hPtzMnuvfD
S1zAkQR2vigShkcIE3Lp+F5k7aEJ8lrIfgqp7Yk+3O9HaOBDYoIk5w1HqnqPazAyz7FXBuKJvBI2
QHxM/N9TFhCC50pwE0EFgMIT14Pwd+k36PLwvg+z9jNf1fdzo5mjXloUrznJ4xwq5zHjx7CUNn14
tkevtaqTPTkzeQSyttcPFGZcnCc0DWt9YH2/mQrQaIIsRMmmYlZEjSCyr9hiaPZADYsps72rOSwf
5t4AfyHKb4mp29UtOR0ap7FR4Wbt4PSkQ5/pVgIDienMINBkA9zXahMC2l/ZmCBQ8wBXWXnGv0oK
6vAKkTY+xdBniduASnELiDwVaZy8NkfLLT/s+rIf+keY4IuLJyBJsl6NvHDkpFEbvktC7PM1tqy2
uZaHHiWbctomlE3fjJAJJYYyblQREe0V+5WmE0saKz9Wea8lfHKQFk+sUCUuOrkOIkAJPhmgL+l4
e22R8QbNle8UUrWIVdmBs/yyjTF60o37Fddah20nSpCIeOBhe+bycPbXjnplCdkMiOCWiE4Zc1b2
OP4+1Hr8l7aBiHVPZ5ntVrNii2hIHMg6F7lI9cJIRtmRpumdywuY5ItSpaOosZ/Bz+fMnucb9W8b
6s0WrQi+auLBj6lRIXh4eWhCCfXLr0ryF1tZ6hJ3rppB1KD1+ul38QoWtgbtxdCOXpeFah8NFmPb
x/O8G2fLxTXTuGOYfETmCBhfEnU4zojecq3pVXN2+vP39hBrqdLX6TReZ/XLhAo7P5Eo81IAjtaH
0tIJIFRk4BDINaPq7H3uoRGbZbOtpa4I67A8bprhbHzD1J7W7nFYnAI0VM0jMj31VOeXVMBiSW+K
7zSS2tvEJEqtXru0EmYpdsQ4XU7LpFzD3YvYuEyKc75gjxSjfQa0X8+iUNdznYQ3mJup98kt6THq
2KAXKj+rFFzZc6MsedD/8Bemp6SJpJNexiRodu7lmtvQJJDPs/WA9ISYovet5KlvRv9e+03ykcgk
fzPIJjwqNz/qNUNPtMnqXVq7voifbLyHSe6uIwdAzq2Rw90lOHDn0TkS7XvZ0CpVHmX6eH2GDo4n
vkj886s2vf+SsBb9SJ6r7ejsW+HveN5lCSYZsiij+QB/AH5wnQporqvNrQ1Jqh0l6tYmdOSTzhdH
+eAk1UVr8VCbCHSPsawS7H83QWNya6+yB5s4TvcI+GST3vLs//RcFkAm7EW44q/twIS2bE/LVzmR
WsS5Lls6Nqbk7OHOlqjNHHabarx8BzXzBngRkxdwM5ybqa8rjLl0gI1FfGYkhIDHh4PUHinyqSK8
waqKMzlNzz96mvuFNqHfLfzokIaOERMgnVnvmWEURKvkeSEi7+tvraDQvV4Qo7E686FfDU+Ua96g
UdRXI04KPMGN0OnG6QnwS8dx/XDOpSWzEtOYjcPRRfWCbfEE6EJ+vyjkV80Xm250h8aPA67hhesi
6F0AVvp+KHEJeI8iCLcc0p9W6VRIN6qA4ww0QX0fcIfYndmy06qrbPvtyDuj2D1M57sKH1liEo6V
BksIJMSzdgKPiOByO2kKbvM1ZQXLxA36oiJd9D0duStgrCA2R+ITt5it37vV/tAA3iFhU61zL2Mc
0S8+8ekr6YV+qrE9toaJVGMhIZi/qOWNyDBZT3kUKRkoLCyUbGrjV9rxFNmxTXhQ0Hulxm20bxtq
QY9K6rXkkG78gtk/1G+DshijBztSI0FOrUmlWIyClfvjw/4CGEGuEIfWwQh9zL8RgeI4hU03gHYr
BWU5dJXZJU+hFTPCFoh3zLLLS+NlmLwyUlx9r+4H9Qo5fQqJwSBzb3A18W1V1JwLCH1STBw+XgA9
3C6V9t+wllv74zr6gSDbKpqFmYVEGb5FJdxCQPpClIazgpVHRma74TQfzmjbIDuXqQDUDpCLPgqy
tp47fq/Go4TL5TJiI++uU7uGMWo2VtGvFZGpJh8UnEC7lSY6tmsZ2VGcYTKqz5nsy+Q/WIQrRW5v
dkG9OZNfbl6/S9e2BCpUBVjag7hVBBNc8HZ2cbaGBomswsQa7AiGH7Eosy3Z0n/eu9do4KuR3G1q
iJ3XeH+720AplATIWo2tyExl9rKd7Bt+SdAh8BXhGnWQp254Nrp2LmV7g6FrcG7jNub2qCT2PyE6
wcjbYVwpNZxpXDWl7xgZbjsZRhofllkfBbiTd9eTl8By9ohQNtEtrUuanRZM7m/gU/uTBGjkc7Mp
/dsvmObd9uD+jef3f0+IHCZQ7vw2yhy4lJQhSq+/vOdgGCGw/p+R5Bep5Zq8Qp2Sf8BeXrnoEo3t
ZOcCMUXFqXlD05AvMC0u6lYQici5tNUASnTT4h/TILFkTG2L6CWiJpoS/JnT2Ot1dfI4FxtQqMX/
OxsZ13h8ISFICPGNPhRB0hbaYHL6SiQVikAEfERgVLKrP74CCTzT5gZ1FLhuwfLAF6Q3haYrVnEf
DFKq704Aqu9vbkeFmSb/p8HXp7dU6EYLS/fZC0NpVrZTJY5mbWWPg/BJ56jAnk35PC5FaaMeW5c3
7CvoTB6fYvtFr3Ci1pr2mAdDVqTlSgEtJxupjzL8y9K+VAmF6FeHGmLP5PDPIcHfdXiT5mjS7y+l
41wk5P0WdmBRsrmu9JIkReWIgVG2kf7KCAO87RtQZWEwPPfLXY0UMqI1h1vwsdWig2sXnq34PmsW
AYNb7bRIgZfgnFiv48rv5H+cxHeWiYN7nUubZ4o4f2NXBYAjLtp+rPMBxSsy/dLiezO3TgZQpUWl
Ys/w/lOjHjGRkI8XNUlLihl8YDqWfZd2fNUCLjMDw8vv3pKuc7RKTZeqHbbnSHYHlJdZC3yT7Pp/
xcujROSNjEFNT4xcmu2TfHncvJ6bvtw2nrypvtmdyjglaD4yWoHUK8NlJpsUtv+XOa4JSoVfIXAU
odZVRHC58DUXXLCo7Ns8W7jKsHrgscAGPpDaLvF7Nj223gC9c7gHLTvNbb/7DECS8EiyILi7GrHi
z02Qylc9YpnQlT4t3UvxCTNn+ZoXxG9AezuWyFctpeVNfF91SDf5QPafxsm33GRvy8IWFTa99+nu
4fDTit2ydIcInukMTVv9VeDyaqWdDzBu9EPwBTRHqqilxNqy/nWCOnCS3wo0damjIJK+zJ0OVi6h
Pj1F5tIxhFqvfd66sMFtTBc71gGuXu8K6KNYkdCnaVF6rSVIwcyZYDFlHU9F53UXZ0/bCeEDWPx4
CuZUdXLXFchNcF87lDFA8lfj331aYvAhuf01+uFgi4Lixb0/Q2uQvJOzOKMITF/x2CU2kRAWHYFs
ydH6RKhSLFsFlc2ubKBbCaZpcYa0ETvPbAxW/7OuEsVr7VP0GDKfa44RN4LTynTu510BtihdkOIq
kFB7PdAGMBDzBcAnSMbLr44tLzq7gD/NrWJw7NCTapu/rMmZY5EinYr2N9tAZ9ArK7k7y+sfo6r0
zVYp35FL9KTXKefp+O/D94yHH3hbtaWAk2hNjQomstNHYrQQZ4ClEOwBYgeP72fMrRoHuF8octTM
1ur4LaSqDRRmlpIBKEBAi/FEdLnHXvsAqjLTH0qXwLR7BTh4q9AIvEoS6dMonfO8jGVXNpuLpGTo
PdKVH46zxi8ewyRhi6fEbd6DsORrCgVvHhMwxFiaRokIWJzWAOB5fhPzDQaUhlrPgs8sRG3kuziL
+TbmFzkegUy6Uk2mRzI9Y3bzWDy+WLN7qbcDq3DjMvfHbZjtIHboO0ZPQMTHCjLqljxlywp1FHV4
cEClM84G9xRO3BDGDbfCP0eByz4E6yZSbhq9Sd1bvsU+3tPVohYypBXG59RUr9SpIrLGNQhmXaIe
JeHdfUzmr8FZ5wd/hXzPV/6gYbl4WuyYt/pawoKkJwHxZ5LR4kNzkg3PYN8ITblHnz8tybHFM+jm
0XlhXyUkBNJCnOtCCm5JQjHstdyLI4HqBv0nc7IyB3tajtdbkUfCh93hLsCUGnHxDDTpsZ4iRQba
EDswldXapuDFTCxU5QxNDGP/YUuBQHe+VaB7N2M/7Q69mGbhXfLkXB7nn8J0zZgyEVYVA0oq1Xn1
Fir7LLR5A2veZoxUdZA5/ZM3d0FRsHURehdMVIek/vaqAdr4U8qyzwiN7VtSIGC0Qk4ZW5f0ph8I
OkAAUaIDDut1Y+khPO/csoUjY2xLBGi+f0LutqbmAcVzpAuaba9ONLLhsRO8pY7PZZ5RVY3FD+FJ
VAyn+PjyOTkUDQtemudFCVBYtS0b8MiAKIXBQnAWe8YwT1zvSwrF5d02kxSj3mbegFh4kQ3NPrLi
sJW35VQK4ugHC6K++D/5Zm776MzZoui15sVeMcfWaRLAq8Id2tyMiLvftLIA8YVcuuxprDTwN2ZA
qLQIMr5nEm791rF/bgWMLkALokpHAzT2cc56+m5P8wu8wBIdIDOEAWp/DV0mHxDPTTrT31zqUCYE
nVAgSAtV+EAVwJc62Xg+eDdV3psIcxpxY4I6UNggnluCA3M3bsSkS36MUGrvf+fncJ7HMUTrp4u4
PgISyqZOxYbvIvPCGvqoflv0jRXod26q2DCqjX8SSv4suZn4uuyH4bJcMRh9qZq6q4+T5T9LD9ev
EJhqxa7KpKdj11/rIy/wUa0Y+BloEtIq5kXlR+B25mNNrt/OrGhUUJBuhVPl9IEWjMQeALtMM10D
L6p7/zsWDdV4yZOxb9nUJaSXw3dDqjnB8IgLzTbUv/M3+3pfgpB3dIL+3pBNaPVnC5B0cAaHrHQM
Ob/+v5oT7pz4Pjkj3BHxdb8fmfzVH0DuGjTzwvcjU8HyXBOAIdSkGeTq4Ap7u4D1rUf8cJSRSLc+
7PTmhiQiLTi12cDXX+jvNSkB37FkKJFiic4XF3TQDqOQFSeieBiusbGbU+Gsi5UcKQzNDIEyY5Ze
Ob2gF0pfbR68qkytNMq6aAWBSdR/IAJt03e0vjFfT80QpmJ7hr/Cm7LfTwAHpg+BN3H3h0zE5lHm
OjHUtXKVpaxqg6yrUvxPBJ+aPxfS+5uNzfsYNILCyDiH71dXZBF0MP0IBFKUluv4/2nGJPxZMEWS
tAcTnunhYYds8AD5a+hQanIL7AB9Hlsguf+yWsCxr/ybAPx58jh3BcrkcwpA+MBXFZ5vjNJLHIa4
fVAPfMlznkay8gd27FEBQA4f6Tv+uHxyVdQJMcN3jFZ5EjtdX82gfiqeM8D1qcoi1udVlRR+Xb3B
tdX52oOhwJIomm5WZYsDJG+OYAoFxQPmdRXuYwpfxS8K6A74QrEhGI7lx5SjlVkH5ad+SJZlz28k
AdqSeRagCBNJqPVTQY9fGAifmAQQdrKrewY026yLj2U1U5EOI+768Yw0+lC6ZylvzY9NhTwaZC91
vuPLlwrnWmlBk+nhXyfMIbm0A3WLHchPH+DJHV94pKWkhpSG2xv9ueVsw3mP37GePZDJEpBWeX/e
o7AsX6LPeAB5mtMXDdKVUhKfX4kSLWtCm933u/S4HlaPZYkk+bumllK6E88N5Pxb6eCN5T+ZuiFA
k5fYAxCCDArgr3ZGZGA6XMFD2Xy25cKeoLgY9Aez6ndoqK5Gpp8mlJQ6N18ymvRtNWHe6HcVHhr0
d2vjZ6z512gHeHF6VUxPjl601D4Q8v+zXTnrz58RBFo/C994Cy6petal8g/k4zjpNCofI8M0wImd
McgI3J3UMYqIMPiDf3fyZv1yO8QqxHalNw8S7XwSFuFzVO7qK/yym1gV85ypjjDRuOu/CjjfDyyA
BrQPSSTrx3tKwpJWtId8PgjW+erKHiEDW5k40WWQA7YAoa//pMT5+WrY+1Seq3dCG1cs9P/R842j
WIDdT9WSBwxUlfT94E70nVWQ6Ba/rLXwHAUm03XsyP8RlD7q1n/gG6oZdkQ0QJM32fzKrVWoP/Ew
GVul5qzFYrW6FJ3WmnpM0MRZFW6Iq6Q52YtJ+M0pf64T/MwMLCvx/wT1ZnNLPlS0YQdH8j5BLiw2
qDWtnXfwEiu0fpNaUOxirAKjSk7qE0+69Ai+Lm8sqoGZJ3AoI1J5vQRpeszl2vXJD4Yohg8gFlQ4
CJ9kgeE1CBaBqGVdJ7LToxqw0DHUNfbaiAnuGA4aWKCYubhFmtLdQ0clbW1RJ26S6Mk7uy6kV2UG
EOjHMy8i858iVF960IUJrEeZLrmA3kIIUxaytgtN3jrhTpebN/0lvynKpCSe/IFxfFsWv7w9uuvW
WFq0+azXKcuB5FTeYpk/pXWE4KJcHz4BhSvxvoHwkj42gnMTmiRVDg9j/qEwretVdNVspsXaHsTS
xNXResDrLzLtWoSlfDE3rEOUX6x4RrtPAKpjKVlQQWc/rsomNTaahkNt4DVbRkOCosfcI5wI9GFP
BWSddPqryGB2/Tl6CGTW+QFcI5WAgeahIvj0/Hnq9H08JAfs0szoAenEZf8XqQvrHYp22EMn4H/s
NCrHid8JS15QMWimvNvcQqtb/OETbd9Wlw35QnRav9AE/ccomRUsc8Gx1RuWCMig+oDekaOIlJ9L
J2dkoeabBgv463rfio80Aoqi5HiWSWdWAbTQSjAfn6hZSsUSK6ziDwZr4Ir55l3iQ1KIEq8aGMkE
hoASZhg7m17h3yMHyW5RTZNprHLf5iC5LqrCRtGx+WoeIQZ38XAuHrVolePrlIqcMVu829SKOHCl
8fvldXvO3QxFw5zi7fxbVAl+w9BB7rtAuAfJ1UeMCWVWlQMpVTqnJxvEZe3BAy8uDGlqKXFPafc7
Z/c3vrtJ0zs4Kf8QwYvDteZqh4xZJ1JzfvwVzO5EHJ8TJUBr9fZSw2iaOlHPuk1TjLEVAibXk1AN
pz4QyacZEFBvZX7ybL9F2HYo96khjMcL5QKXVpmskwPk3GFBfb4LZuX7fQhjrpVhkQa3iKiCfcKY
R86jHq+Culy/tw5bC9qdLEzqRLvkJ7up+T5ftCWy8QPKAT9QFNi0tmhZC3iFqYVbpp80i1DMUvaJ
jdmwMzzVyL+8ueOIdIP9p03TMBN2Z1BFI7vTTmv8DzNlSST9+LWU8XEi/yosuy5imhx1EFYyv3hL
gztus6q4N90YctfRVym+e7qENTjwChZNjUCT1Pua6OKCwj51JO5QQ2/9OIzLRDYyDt/8oWfr61PX
0dmE7/Hx5wppjh+gXPzjKTwhdQUVN3eSUESgJHd+tNfsb2rMteOLddT0ZK3KeRK9xZl3N8lpN5Wh
6qQeeEfP1z8vEe5tvNdOPSvh8/CbsJOnsc7yKGBRfOmZVGpoe4+/dVlHtE4WYqQYgYhV6lHVv++M
s0V2eNDrhGHctIuSfBNLJME8OeDS1PmLNDGTDaxuCq0XLLhJiPltj8HfS0fqcey0EExpMb3OranW
RVhMFCAf3rb2KCke0ZzXFm4bkVlXQtC271iJM8QaS+qgpb56fsjKoEzsxl1e2ZpYt+nod3DMhgdG
1Ktn/lnGiICHZbDUmmeeRaVTF1ps2ffx0fPTsrK3QKJL1JkkslGcrTF2j7rhetazf0xLL0Tqjc/7
q/4zVNwMNbyBYxPnjBPllpgWLn+A+eH9IpE1wTpxVzc6tAOB64DBs7gdbnyVd6WFJFhz7TBcHT6i
feQ9SqqVaWADe8sVpQBcXTau7zjeU1doC22MY/CksOklLCRhzazmhgNk9ON5MmOoWfhq0BEl18w1
7qIdnn/ju4Prk9fuEZmByMHT+QOUiUnjKjUK2xeLRaIVpTXsZ48wdgXZC4M6JxPhoknIhvoyQZmT
86eNT88UFEvDDUcw2ib1cPYstCkyyn+Dxb8BOFEGk4/Qo8h9ZRfZ9wIKkW5ojspro67KJY7n2kLv
E1M8eSujS6Z7w6yRfFIOm/Kwot45fUzWqUei3Sd1RmzY+1HapiNX+dbSloMxsq3/5kZAaU5YVdrJ
y9+VypwcisK/XZ60HUkhW1weXEVybUco8zMvcetJg4Df5GSt7ECepcnDj4MYuMCRseRgij2ynHnf
GRetzN7Xex79qLTnEtZxsROJKSEIXIT0bdePoPD3GhU3QJ0AsPMu2uYUKgW16qSyvhYZfw9rP8Qu
E7ZMYNXmKAHqcCw4eaxpfT/tZ0roYnseOI2C//jyzcbBG7siN1ynckMqUhI1Fl38gVeUs9HGoxc1
Af7k8xfIgD0oaKEStPJ4FfNewh1qcvBPTsBHfk/muF7PJDLr2arvOcOPSqTuwkXE90FaZgQUwv8s
K6xa/pSVGF0jGgGz8IckjZLIo7twjBRbb5wsxmBFxAyjZGY98dU0DQbJwuGsj+rCNQkVzLp6Z4qu
BUg+79034AD6tzZEP80HhhjrjGNmymJO0KqqyOf51Uy5qyV0UYY9kT4xB/qHKYeeGzotv6jBwllk
xDQVbdSvi/TvrL0u51UfsTdGGVebSgluMCr0XXJyPiM4r34dFQs+z20/2/mEloZfmjsUkVmgbF+e
mr68FWpupqdpD/geEJHKobwbUGclzffJue4kHq/ewWfZ4W0xTjhjPNwwKQpZ3fJtj8cV1f9ZwULA
QRlGu/oCgmmNSUxjbPgQnLrXLBfHKE4zIpFcbXbsg+BLgj27B3Rq3yE6CL6E9jz1eokc+TI9rIMT
pdCnuO9lQjCLrOvcNczdHTMMLPLqDCXT0pn9cihshxuE75y6Ct3nFuA9YfNLoJz5DEPzxzixEFvv
aqoPixSKxHHzmZHaf2Bvbmlprp3hQmz2/NMeNcCqRuV0NuglFGr/rFg80rorZFmYa5rUs1HUit3p
2c2iof/IDzJC11JeBxua2ugjjm0kLfDz23b6KDn8iM81AjdYT6Nr8Tk1XW9z3Oqw0D4yZkc1uMT2
+eDEqt8BPofyxxhHmjisOeJxkEJTuS2KPqlFK5lKA/PHVgcnrk8bcgnlm7WHK2Vo6Lm4GQzDmtGP
egiYbU8Hnx5H8Dki57Eb7kWRzizKI9otzNhEnBWVvCE/Mw7LnX+fkylqn4D0tL6p/HMoZsM1j4sp
h7rtkxXt6WqlMk3pt9mL0ZUt2vX/oC0LlwGTFr8eYp38J4W9r/Z9EQGQhVrHvQ1OJHnTYWEK/mkf
jvsQM/fWnf5sTRY2H95FqMahjiQrHqJpOi0tLwWFDMQ4TXJyYyhLBdsIQED9ZIs8UGzhgonymZVl
ZbISwf8J/Muwjdcq2V0orxEDw/qcoIMyKcle3Xvcz+zeUjyGl9gxAnJHD+tfoTwKvmF/Ep3Vk6JL
ceMKwUg390wYK9HCHVC+kl3Fjb4RsgzQIugmzlTa7G2iiv4PdomIQIX68+EczCWCOx0L2HUgNYWZ
/aAie8awQxorexs5uFsPS+rp78bzYf6WlMaI6QSnWQlCNuwgYwRX53AmJhZ+2fUfHXlISQJemkJ8
Pg60y3wqRsAlfxI92uGdD8wVHDwOoAsoAhewEuDkHHOtjmFGVSvMBNua6O4zC+b/x75AddGRMdJA
+REPf/dEGHCkxsMdE5mr0f0+RiEYm/XhzLGfYMimnaX3RhiavwV3fHruKlQsksoLO2KOQL/RoROt
1MN2Kpr7ZE1p2oO4QwMiovKElsS5Fb9eiZ52IIYgVUBH8TRNktV0L6xN8lywfOBX
/cXjPA2Dx6Q=
`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00291.vhd | 1 | 1578 | -- NEED RESULT: ARCH00291: TIME is predefined correctly passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00291
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1.3.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00291)
-- ENT00291_Test_Bench(ARCH00291_Test_Bench)
--
-- REVISION HISTORY:
--
-- 22-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00291 of E00000 is
begin
P :
process
begin
test_report ( "ARCH00291" ,
"TIME is predefined correctly" ,
(time'pos(fs) = 1) and
(ps = 1000 fs) and
(ns = 1000 ps) and
(us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) and
(min = 60 sec) and
(hr = 60 min)
) ;
wait ;
end process P ;
end ARCH00291 ;
entity ENT00291_Test_Bench is
end ENT00291_Test_Bench ;
architecture ARCH00291_Test_Bench of ENT00291_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00291 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00291_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00054.vhd | 1 | 4267 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00054
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.7 (2)
-- 8.7 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00054)
-- ENT00054_Test_Bench(ARCH00054_Test_Bench)
--
-- REVISION HISTORY:
--
-- 1-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00054 of E00000 is
signal Dummy : Boolean := false ;
--
begin
--
P1 :
process ( Dummy )
variable correct : boolean := false;
begin
for i in severity_level loop
case severity_level'Val (severity_level'Pos(i)) is
when Severity_Level'Low | Severity_Level'High
=> correct := (i = NOTE) or (i = FAILURE) ;
--
when WARNING to Severity_Level'Val(1) | ERROR
=> correct := (i = WARNING) or (i = ERROR) ;
--
when others
=> correct := false ;
--
end case ;
test_report ( "ARCH00054.P1",
"Case statement several choices in one alternative",
correct) ;
end loop ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := false;
function F (parm : in character) return character is
begin
return parm; end;
begin
for i in character loop
case F(i) is
when SOH | ETX | ENQ
=> correct := (i = SOH) or
(i = ETX) or
(i = ENQ) ;
--
when ACK | EOT | STX
=> correct := (i = STX) or
(i = EOT) or
(i = ACK) ;
--
when NUL | ' ' to '#' | 'A' to 'Z'
=> correct := (i = NUL) or
((i >= ' ') and (i <= '#')) or
((i >= 'A') and (i <= 'Z')) ;
--
when others
=> correct := ((i > ACK) and (i < ' ')) or
((i > '#') and (i < 'A')) or
( i > 'Z') ;
--
end case ;
test_report ( "ARCH00054.P2",
"Case statement several choices in one alternative",
correct) ;
end loop ;
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean := false;
begin
for i in t_enum1 loop
case t_enum1'(i) is
when en1 to en2 | en3 to t_enum1'High
=> correct := (i >= en1) and (i <= en4) ;
--
when others
=> correct := not ((i >= en1) and (i <= en4)) ;
--
end case ;
test_report ( "ARCH00054.P3",
"Case statement several choices in one alternative",
correct) ;
end loop ;
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean := false;
constant c1 : integer := 0 ;
constant lb : integer := -10 ;
begin
for i in lb to 10 loop
case (i+10)*abs i is
when integer'Low to -11 | -1 downto -10
=> correct := false ;
--
when c1*1000 | c1+9 | abs (c1-16)
=> correct := (i = -10) or
(i = -9) or
(i = -8) or
(i = -2) or
(i = -1) or
(i = 0) ;
--
when others
=> correct := ((i > -8) and (i < -2)) or (i >= 1);
--
end case ;
test_report ( "ARCH00054.P4",
"Case statement several choices in one alternative",
correct) ;
end loop ;
end process P4 ;
--
--
end ARCH00054 ;
--
entity ENT00054_Test_Bench is
end ENT00054_Test_Bench ;
--
architecture ARCH00054_Test_Bench of ENT00054_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00054 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00054_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00057.vhd | 1 | 3182 | -- NEED RESULT: ARCH00057.P1: Loop statement without an iteration scheme may be left by a next statement passed
-- NEED RESULT: ARCH00057.P2: Loop statement without an iteration scheme may be left by a exit statement passed
-- NEED RESULT: ARCH00057.P3: Loop statement without an iteration scheme may be left by a return statement passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00057
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00057)
-- ENT00057_Test_Bench(ARCH00057_Test_Bench)
--
-- REVISION HISTORY:
--
-- 02-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00057 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean := true ;
procedure Proc ( variable parm : inout boolean ) is
variable more : boolean := true ;
begin
L0 : while more loop
more := false ;
L1 :
loop
next L0 ;
parm := false ;
end loop L1 ;
end loop L0 ;
end Proc ;
--
begin
Proc (correct) ;
test_report ( "ARCH00057.P1" ,
"Loop statement without an iteration scheme " &
"may be left by a " &
"next statement",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
procedure Proc ( variable parm : inout boolean ) is
begin
L1 :
loop
exit ;
parm := false ;
end loop L1 ;
end Proc ;
--
begin
Proc (correct) ;
test_report ( "ARCH00057.P2" ,
"Loop statement without an iteration scheme " &
"may be left by a " &
"exit statement",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean := true ;
procedure Proc ( variable parm : inout boolean ) is
begin
L1 :
loop
return ;
parm := false ;
end loop L1 ;
end Proc ;
--
begin
Proc (correct) ;
test_report ( "ARCH00057.P3" ,
"Loop statement without an iteration scheme " &
"may be left by a " &
"return statement",
correct ) ;
--
end process P3 ;
--
--
end ARCH00057 ;
--
entity ENT00057_Test_Bench is
end ENT00057_Test_Bench ;
--
architecture ARCH00057_Test_Bench of ENT00057_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00057 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00057_Test_Bench ;
| gpl-3.0 |
dcliche/mdsynth | rtl/test_benches/channel_tb/src/pitch_to_freq.vhd | 1 | 3731 | -- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- MIDI-compatible pitch to NCO-compatible frequency with phase delta and octave
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pitch_to_freq is
port ( pitch: in unsigned(6 downto 0); -- 60 = C4
phase_delta: out unsigned(11 downto 0);
octave: out unsigned(3 downto 0));
end pitch_to_freq;
architecture pitch_to_freq_arch of pitch_to_freq is
component div_by_12 is
port ( numerator : in unsigned(6 downto 0);
quotient : out unsigned(3 downto 0);
remain : out unsigned(3 downto 0));
end component;
signal note: unsigned(3 downto 0);
signal toggle: std_logic := '0';
begin
div0: div_by_12 port map (numerator => pitch, quotient => octave, remain => note);
-- pitch 69 (A4) will give the following: octave=5, note=9
-- The desired frequencies for octave 5 are the following:
-- note freq (Hz)
-- 0 261.63 (C4)
-- 1 277.18
-- 2 293.66
-- 3 311.13
-- 4 329.63
-- 5 349.23
-- 6 369.99
-- 7 392.00
-- 8 415.30
-- 9 440.00 (A4)
-- 10 466.16
-- 11 493.88
-- The frequency given to NCO is the following:
-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
-- phase_delta = freq * 2^32 / (50E6 * 2^octave)
process (note)
begin
case note is
when "0000" => phase_delta <= to_unsigned(702, 12); -- C4
when "0001" => phase_delta <= to_unsigned(744, 12); -- C4#
when "0010" => phase_delta <= to_unsigned(788, 12); -- D4
when "0011" => phase_delta <= to_unsigned(835, 12); -- D4#
when "0100" => phase_delta <= to_unsigned(885, 12); -- E4
when "0101" => phase_delta <= to_unsigned(937, 12); -- F4
when "0110" => phase_delta <= to_unsigned(993, 12); -- F4#
when "0111" => phase_delta <= to_unsigned(1052, 12); -- G4
when "1000" => phase_delta <= to_unsigned(1115, 12); -- G4#
when "1001" => phase_delta <= to_unsigned(1181, 12); -- A4
when "1010" => phase_delta <= to_unsigned(1251, 12); -- A4#
when "1011" => phase_delta <= to_unsigned(1326, 12); -- B4
when others => phase_delta <= to_unsigned(0, 12); -- Should never happen
end case;
end process;
end pitch_to_freq_arch;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00263.vhd | 1 | 2734 | -- NEED RESULT: Assertion statement in architecture body
-- NEED RESULT: ARCH00263: Block statements, process_statements, signal assignment statements, component instantiation statements, concurrent procedure call statements and generate statements in architecture statement part passed
-- NEED RESULT: *** Check simulation log for the following message:
-- NEED RESULT: Assertion statement in architecture body
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00263
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.2.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00263)
-- ENT00263_Test_Bench(ARCH00263_Test_Bench)
--
-- REVISION HISTORY:
--
-- 16-JUL-1987 - initial revision
--
-- NOTES:
--
-- partially self checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00263 of E00000 is
signal s1, s2, s3, s4, s5, s6 : integer := 0 ;
constant c1 : boolean := false ;
procedure p1 ( signal s : inout integer ) is
begin
s <= 5 ;
end p1 ;
begin
Bl1 :
block
begin
s1 <= 5 ;
end block Bl1 ;
P01 :
process
begin
s2 <= 5 ;
wait ;
end process P01 ;
s3 <= 5 ;
with c1 select
s4 <= 5 when false,
0 when true ;
G1 :
if not c1 generate
s5 <= 5 ;
end generate G1 ;
p1 ( s6 ) ;
assert false
report "Assertion statement in architecture body"
severity note ;
process ( s1, s2, s3, s4, s5, s6 )
begin
if s1 = 5 and s2 = 5 and s3 = 5 and s4 = 5 and s5 = 5 and s6 = 5 then
test_report ( "ARCH00263" ,
"Block statements, process_statements, signal"
& " assignment statements, component instantiation"
& " statements, concurrent procedure call statements"
& " and generate statements in architecture"
& " statement part" ,
true ) ;
print ( "*** Check simulation log for the following message:" ) ;
print ( "Assertion statement in architecture body" ) ;
end if ;
end process ;
end ARCH00263 ;
entity ENT00263_Test_Bench is
end ENT00263_Test_Bench ;
architecture ARCH00263_Test_Bench of ENT00263_Test_Bench is
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00263 ) ;
begin
CIS1 : UUT ; -- component instantiation in architecture
end ARCH00263_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_ecc_encoder.vhd | 9 | 20723 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bXOf+NyPOFKyAbR7M9ZG95bTMwfg0MjwviSGuv0e1XYvP1cKLa1o/YioaJ7nbdN6Cqn8/6k83/yX
GKAkr0jkLA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SnvXusHaXqdOSb/amn6FWfZ+yZZJp1Z9lvUO8MUXtsiORIX8i3qHTsucd8Mw0mWna8zNKopCr1D6
EpoUCyZP35d2y02+/MNEu/20zvEcHvTi49n6y9ilWtGQmAskTUapgzuFUg1Oh2Mrf1U4WLSmATcg
BoIl8+xN0Y0hV5y7dpQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o7w5ZRvhoe3QaU99/6ZnHuQ6ef/3WhWNxuN5zKJGz/Udt1EPoRIdjcuAt3l/WCen7yvSKp3Kd+99
HgnnX3vLBcbx8XtejxYGIpyJ9Tnm0nynVKz/VDgUFKllGx9137VVT/IJctw3dYRJNAgW6Vt6+x6R
ExcMo+6V307aGNmZ4Zd/i8kOzeXkO+Br9gPji5IXmG5GmR4HddhUL/Ns9ILw8+ehVAJyG2x8NQil
rEKKEO9h2AaJQJ4FRE1qWrRByYzJNetcjmX2Z0hxRlQW0hWhQjTtZ1UBi0WWyQlq10YvEqi5I7/y
V+etoXboYHCVZ86amqt+P4F5hHkjecHFb2Y+kw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j1XMHdGWcxH8JTR49sTmT8wZAsXlPmQMlyjf5hD7XgFoitjM4F7KuJ2NlyEwcj9xett6LNd94NUx
sywk6EC1bq3xHatQk7bEITUs1BH3rg4jrsCO0ce8idj1q575W5/JbnRdSnI3q4TPnOk/mC15beC1
E1pRqwTQAFC15BR2bdg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ggePePlyhwfpik6K+GQihwnmoPqWXxXx6PSefdfXXLWWT/C1DzU1B2K9gI6UXtidLj7C3iBKqsa2
Yhb48FmIbwidfcckyIAsWLwCAyEydWQytihhsFChsGlLbc06nzPWNqS37kVAs7yKRf9lpcQLtWod
mynnRUHpErbbNrIhQlnEE48jq+fuBk8SmolAGXwEL3//k4U2hpLEhCWocdyIHN615duJe+zr+uzO
NNSqZImbQ2TIuH9GiaZ23Js0nBbrpH2X9500mHSbsIM46lcpXDqh/WMRbqKfOe2lQmaATHcjySuy
PEaBmwm1t7gANQtYLHsJV+yXwmIeXx9EkvBSdQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13600)
`protect data_block
NiltjNPWY8nSKNjgBoEulzWB0Vbh5yfcUqiwDGv4ugKQZxoodKvGXXFM52FDdFWdH8AEuLL84VGR
gFzo/ZZAWnex1vlezN9OS1dditAniewO0Vn1CUSWuaWeTvc7K/4dms0kczzRQSt8SY7UP/AFaK15
A33+Od0RFeC1WktP6ySPBeplMkohFZsrSjY33W2GE4SJWjWcw2TAoWzn/9yZnIq+DuqbL/jsqEeA
lf0OZ+NwjH/tQ8iemSnMZFaGRpKKu3Ym4IwZmg7j2WmnCpEGtNsrMa1rDSAMFYthnedLuLUubg8H
wk1YdKh2YBL6WgiCowssZCdB7i0QcFZkOkpEJNNEtF7qY8c8O8zJcHHNNdWk7d0s4kkbKY/visH6
vEtlVnWkZAeiaquifjRadIZqOktx2h8DT8FbQUBa2mFYB1880pwdfI3Rf5tzsR8ipU05mj+oj3kf
Nx/PoRLOVxJIRx1XNtbRc8q0uLeSs/jE7CSZrHfH70xnAAtbcPdcS7gKlyPsrHWIR9B0o9jEe3/G
bv2OC0DWnHqAuaTq+x2QzvJAxQvdxZOe4Zmb4I2TPFrSsBCpB8Ml6wL5FUboqaK/ypszlc/tvfgi
u7VhJHkN2vcUrrSC6++SkjW2u6xVpS4MJ1uibf5QjPY4i8gQuVLzpNIwKKiobozgoBTPiQw2YKoN
lavgnh1JlfUxQNk6vtdx2eGwzkYx61ZBUjKRGQzcUJuV6Z0FjUbkQS1CIbAzdSCKKzKXmdiO8U9e
G5vsddl3+8Uq5KFu6DndRgaOCsPsLJVWZ4rY2qvxjF75DqdZZ8n/k3Hkrb6DJi9zz0wg/jmKUyEg
ppbJB9LcBqj0M00Xck+GlI3KGGFYZOiedeibSyr0f7AcQbgwNMRrJWhrN7ma1jbk1SOScdq7Veap
Acgfh1R9RQqbg03GAfkIx5vI6Qkp4RLpXcsAKbIeUfTKt6Zup89DWZq+OMd6U4ksjrHwKQoAvcHX
jSARIYU22HWHw3qsRmmlIibmlkPfL67H8xqTgRfT3qt+CH+ZaP+vkDLHiBa+8BZq6L4SdvSlvenL
cPJnAYpG4Bz7q3OtGa3F4/Y2WCAS/irm2uRoE3nm940Z+aNcVN9NIO1Wis7QI2zsSrPYUIxoYGjR
NMGeYagrtKfFNEvnoCUehZReuc0yP1uRhfTwvmHk8+nbmIrDGE+ONS/L1dvKgAPKbwiEyRaRsXmf
+Ri4sL8LUybC4MR2mxMHUic8wT8EZjYJy72syjCC3+BLk+XfYOrqD2eYaTRToRJDJVpDaaWOVbxA
dpy1wC8gGbYK0GhG19RsF4XR8SEP3uUanEFPa9Q/Hrou3oFVXcvW+e36tntQn9M8CVFSrXY+gbGD
NTIsJEdDNdllTQbf367qxJNI0DwptJeP9wqjW9FylsOWReCC9SVjOzTCNTUTB9Q82QkiBMIhfpI5
gCu29N58xPsN25s5+/e+FlAhcmF21QooqezbybHhb7O0flAbGm6q/mTx17Ne3xidrEJ95zdcw4jO
jWc+kdBwrdlpOUS+tvdA8ZaC34doHjMw5fCWIafKMr6j+TB/5f11JZ5PQJthh8iZqYT3ZlxA6ncU
fRuIOGW3aRHhTISCiPvVYSG2J9fZAEVaVY48JZGTqyNuKljy1oY+jveSvW/Jx2OHlFf8/c8cF9W5
+P0ksTut4TF1nMG+QFOUtRQMTf2W56jQR3x6GrSfHdpvDG8lAH/fWhS8UIiL0GZe1nVKvlJtyQwk
WFsIJD1XFzz2jLIJyA5K9jE2eDP9ZrS75o/0Bm30KbpgfTvyOq1LRqPLfdSbbvtcMZdHpyL90Gno
YY7rcHO3u80goplL10mufT9XsLnO/eUV8Sz/LgpZh6K15MJ+5T+btdAK87tDTLWksMQ9T/9w5Wu1
6ozfmcBRMB3X3LDQR4llovlZlNJYB1wqhBXLJZDuoRGLYnwAKxeI9Mirn95KKK3ASOWhZt5619hx
fuO5zAB/C0A7RgFtWj5dgdYSH1xn55+8RgwZZhI2BxPi8lCRVbj+HfvZcVBp8jAZkoexOj4O2/Jr
3q6iEBivVin7F+uOBjRVMOiiJI7NyhMFHcR6EK44afBNTT8FRGhIxv16WDeE0P7oN7qdi6ariQtI
7PHos1GHm4S5mj3EgZiYtyCGb1YP1tpZBN4OMdGUviw5adi0hsAUx6uLa4uqsB+NgIWe/oe63ESe
oERvO2whmnZN4sQtgmxm3NtAyGgwFvPaQd9JdxEjGyu7Zu0xViDmViNHo+TBPjvsF0FVr4rlVflj
5MJGhfnraBoi/r+N0w/RHgQn2XHh1GXtfXNXnm5oWTmtP3EKoCTUBSVFc3LQ4GLdth3fJ+kxaRPs
4oAmd/jjo4M7kAuflaOW6I6qw0vgmmNrhZFSJCQk+Zm/bqVAJ+yEQfOpZWrQWdOAdljvZvvdp1AP
lPYw5ph89PvfKrzIWEsB5/8byg6gg7w36NRITAIWttbpjQNZWPJ/OSJa8+7GN6b5i62hBx8pUQMt
fdkhuBpV+vLQZFPtGi1bKDuNYEEZmEwSX8RMIq66c9XHrE/TzuyGMFES4CpG3bxOBMyDKO24b9Su
oHWNvxKg/rC1ia4VfWO896sH64wRZm2syEZM/rO8wXQ7FZTs5jLJ77p1/Qy7mM660o9laIMZxHJE
xoUVZ3EyBG1nZUmofBV9C0hIx7rIZhAuwxc8yUoePdUg6aeSH2BM5uY/H9+FHRHF2EttpgOyuiiZ
ciFONEkeFBkEEfDZwn47txnxjOwI+25p7HLtA9ZW/bMHFGP5U82TcqMlWHrFdgVZ3QijjvN2upCf
OUjfYrww9oiuqgi5sXfhxmorqGcyQU2yNgmkasUrwzuj/mNMkdZBuZDLMH0FqDcOp+oGA1skxgsj
6SDrYt7k4VjU3u2kpZvVAfEJ6F7xh/PKBwWrRa05AJf31OISAses1ThcS2XzZazvQZvlD+Ac02/6
xdTJdb/wMSHefUJCRR2yVTe7sFKuP4ZSMqWcI+D4tQTbVnf1Oi0FO6kfif1+gTn27LhA+xv5xZvW
6jPb50fFTBV9bsSDe+vpkg3suaQrZLKKhFMq6Hr1ylR8aFjjB71iuXyeBgbsVM5dDEaldb4UZgEm
RhGKNQIcCXAOT1YW/dmc0hnPEYJ0BLiRq0GmIE5M+GgZSlc+YuVgD64QfjifrLjO0IZyW4sR30te
Q7Y3GKFCMPnbqhInW59gY11hcpv9s9jo724iMhTuM+Y4jdGsw+sk6e17KJzTaR5fnidIEN7mbhzN
GWleGGgqUViwDOdLnjX/aoKObPmXQ6+jC5Chey2J0n2omBDkJYsLP47I9D6Q1RIn9TeLSKT3ijFs
ImKWKHbwlwLXTK+hQCL+RGyXZzHG9v26ugYXu0aI7QSHjXm8VQVfPT5POn6+xMW2XDJSQnEjTZlZ
DDK1nx5dEtpI9I6RC4RSkpP7dn9Wp6If1k3QO8pW54mmycv+wHyoJJeomFgZw8t3dtiMwfgIrwod
2RtIDetNqULSlKMcGjKc0qLuxoCKA39KFExMsJLlyc7CA/oUVi0VXmrK1HmrqUiOg0zoFaMY6ag5
QWL0WgCGx8hrOCLednM18ntTV2hIV7tt+BVuAhyGBOOAUhEGp214YrFkVAuy1cI7/3/AVNafIrH7
auY29xEbFIZ9dOATsdhcO0UzooQVCNlvBfKztI81vZHUfpSvuamuu0/6qnSfiyU1QCCYFevLCTOR
3NJkispCrqsg38HFoQCJPNW2h7nVNZ0atOuby+fPyNOXsEB9Oqmql7paV/hDVprxhuO7PHRtSdeA
jbsuamnr6GPGTM3+oBp1LwTRkWCQfUsZoX+6SV2jzq4E8ZGXKmIPQJdXk3IcabsMZsUbHN/9/NR9
Lkg7njEOeo5WatrrXRTSI3/IX8b0jiOJau+YGJAO7J65XCjHcIHGWQcbitrR+EYI63P1b4wNNwH7
PUrJzrlWJEyUQ3RNZXNI9i7R6DYupXqVDG7KIQmeigYsKZcaJWM2Zu5UNsbaDR7yLCtqJbV1KTgg
kGFcXLc1DQsox9emnQ0Z9uBMDfbRckb468viEvf8b6CZdIaX7ZIhP+v9wF5r+HFevgsyBaqPAMq5
Q3uZA24emASAZ706SeOWbjrQL4jjOS1nSvVtkUbKV60nGaYVb850l01tdS8jS8KiB1e5GL/N1i6c
JLkyUKEhGy1clw63ykIuq9MoHH8cYipBGqQyJ5a4yvYcWkjENf9ngjBXlHa84nDXNeCx1dW9ggXd
Pi/JjqJFku+4BK+BY5dMB/lLdIovRc656l0xF6Mnpjc2l+BrP1iMaXnt71cFTOu1tG84ShnmglmJ
znbpCK1StmGt5rGa6EEERir8IMSmcj41hbCsnlmTFFf+ZpbRBIFIHILoJ2ZGhwqyStiRnLdGve1B
DiwseOW+GYW01LxuTSr4pwCOmTvRclVzd8TnKALuI91g/G6jEDGJD5U/TBR3zbZCTrPlkYhCyYpE
y52spc8h3/wTLWL1LlP2X+B3/7Dc7mVeCF2zcpH119fVNVBJapO6QthbzJ1bBr8aQS5Fmw5MuYs6
Tjosw8UNk3UKknoMX2xsaTPfRhuSVd1pCTLQJ90IQ70//jW0xjTJCmVRYQYjQlthYY3HItx4pDdt
5nBOoIJwxMLStxcjY7VMNurhqDk7WRHkiPgKkJzio0QP/mMIinQx5uwyFcSV2hyWF5fDK3Cn9bD3
kZnSRWRZY0bopFGMReGtw1YBuBp9uk3/PI05A2BdMVWpV89imTZy97OvcZGBdUtQH5mNkNTGkn3L
i0HdAdZsceVAd3IJqGansEwzNWVy2vz3ysrZFwdKSy+hIut/ubZzxwBWlqE4hjwv958NvTsHuYnE
FKzko/X7+ktZoG7DEryZQ9eDx8AKT1veNz2YyDS9MyxcLU1U0a0/jLERJdUKFImlvW7yHBJgceI6
gueS+PONCKOZKMCp7+vyZj+y26wpNNbs1df5KHRtj3czawbs4nx8mc+D+I7rfaAwO4dlXYKJAZQL
9R6XnGWLE+o5H96J0vDOuwK0+BDCLhYESRoDkD804Exj6SfPuoWusWcsBPZfKwfuK4gsPQZeYomJ
c8s6sqK3fGQBi7xPMreLECVKz22Kr6E1agI01HJeIGj9mwIpQeWLksd/4b5DNXam+GFVkXwY/RN+
5NyCmSsSA4szUBImcHuOJLW+nfIRmaZy5I20PLmvsHgHwPksPxjgUW1uoGeGpg2C1mQc55uLRs+a
rBvbiuspmiBD3VZjejJfyFKkkvO3VhNuxezyGwx3DrjwCP/GiYHDtqj4pQObNEiv/xgaFoi1EcNz
1cERcVQIDLmyxLpPUQiHo4ROLu9xt1ajCStVrUsADMN2Y3HFr0oD1BIEaAHIUXt5PhNguWu+WFxX
g532frK+q/7E3a6BWQKITxgTBU2hZJ5gZNzpHgmRpc2kdAucfXyfwCBLm4H2Kq8cLIgJp8ceXfbb
MIehEsfOuk6Byh7KVkFfMQQ46oT44LqJpJskhHz1nXdJqH+0dA837vM+FWtmXj0xsAdCwLul2saf
97I/wiWqGLTHPfpsRLvhETyQICjf8f0ohU3uY7Kb5aj2ljnwXS1DNhAXOG3G8zFuS///tIXidmLq
h3xES05NNjauhf5gM/dC7AsrmvLS3FD0wsEB5hUw2/7chCHH9f7ub9f8BYVALU4dJdoAEAnokVmM
/4koDfG5k1inXvF9+NKJUaskmN5OMynfafZkHCpE3yWnNBZfOoKDhO99U1BCP3nUQsr98Fv3ZWyl
kBsKI91yeZvaHXJGks2NNMlCGw3NDZdGeygSa0JIS/1PI/3gYbbxS2PNKd6qEesV3XSHlJ/QTbM6
TJGcpu2YqDbj01bpk2DHZGj4btCjY6dInty16vyd+1jN0fZSOvJPNx24SOf7hGuCQnB63toeFv6F
x25Sq9QeW35jx5iDT8O7HfSwhd1sZuFNZRz4wcXt77eeRJzJ81pgRUHwXQrms6bzYTVF2FP9C20j
XueAFGTxECTZI0ercSeNN9xa9N6mWOCpN7ZbxvxoihrKDdeipJTSa1Vxx4qhzH8r6PH4GZKI5NmO
P1bO6tOrkOZtYoaKKXw+blZH/IkFXoPAKT0tXEaGtxhGlJFsYHJLomPfJVFeWq9cxhZ0uY2bn5GU
Os2kklNTwDpReFBywd6Ph3BBRDgOuPpd3UAKCB1Mm+P6Q5ZIu5ZIBFguhqcqo+eas0vkUFxoCudj
F1xEOj8HAczDb1D1YKOs2oXe4ARHJ+7BKfKq6sOYU3gXjNC+snuO0WR2KEEFyyt2LOgFm5Kk3TA9
6mTc/uTrTEOg58kfjphQqGVHyUSwmg74y5+sy5UG7DnmbJ4R99Ws1nhaSEBbT3aNg9qxnBtIlkoB
XS/5UBrMWa/r9PzT4FPdP9xAOifzNoZxycU1BIq5cgi6oi+Vpdvo27bIwKtRGrM9pa4EK46ZPoWF
yIn2RF2Jv4fXga/uHAYAYU6Y02VnY7tuSsXwYMqQHs6KJA+1HmBYu+dPPh7xOCZ7JnDCihrhtB4k
hSjPtWJF/Mlt0AHSVTwYSYkC5CPrs1PLqdArpmg7TkwuxJCHvOAf56WZ1bE5HkICDYOPUvDCP6Q5
dRiG7BZ7eaPb85X0ipiPcHZSuJptljgusp0z+ZmWwS0KvwA1rSP4aSrUaQLnFu5Qrz7RIKsxkTl1
PNxdW8MjWSJqAhyuv9fi/CvE/VBNWBDTlYK3iIN02B8n1wFp4h5Cn3+u89jkDd/8R8cNkRaynoB8
cPtRhGg/bDgzpb0WfSHNIsvrkxUy9SEWexhZ3nMTjOU4tw0j+CZh4wEc7q+6Sqzjr54/7nugoPPN
lVeG+3ilYRSGVXlIfcvqjjOp8SSU+Yr/yMqHLKlAB1TYZp5SDdmvxp3BNMavCU7tBoFzLiIzgwt/
WCd+u8x7iHsFAtD9A7j/Xn9nx4dgRAihqGNqMdHw5nmPdUHMnZWWSZ0BGDIfTB7Yed4ZG76pedxZ
JnccLV6fqpOkkY/HM/HziKQZ/Sbx/ERMv6BOEK8vnpW1jW+mg1CwkK6CMvbMhh5e3nMduMRXiAQO
Xq5su193B1xlb7lWQqw5vD/ceMcaBPXlvIz5R8K6f0RlKzuTrzpsufaq1KBV5pcZEm5SyvkkJfmF
zj6i8z1EQLzMEn1LSwcpmsaEKdqte72HYG3oX4ZZ/gcng/bFaYnqDIBqtvamAHOUbObw8d06kVYR
k3c2svsSTso0MGnA7Q+3mvnY5tPQgrzP30aQlIhw26JcInEe3blDgKpvbpKxsq8B3toKtX7hOt3U
8Gcx15lr6iDJu412/mgfacnBoVLEzbCHR3230DZX4mirf2nLFTxvtYy70VpLwvhQsB0RMrGUzvU/
+Sr24lKW+2yWhVQe+uirvTXpeMeSWUD5aToE4ss+8hal9E0vGkiUWUJoW/ftxrivi+wtoCCyiuZx
si40hXVqlbAXkv6Xxd83xz0P69/OXoMhQUQcRTWPM+rVtaMg2TDFW3pWur/cnzp72dC87J3ee8XG
tV8mNnkP3Nj6xGX1XSk4cqax97CcJjllk3XQPJ/WJO5Bn9q2AvYp9//18uOnevqCve0TejpG5wzD
fCmqhkHBivET3Q+rX56dw8wPF+oHKrfjfjpTVL7i5pbTnkZtCNaOmyFJQ7TvuqH2GbyP5R0TIjv6
lWjGY9IchsetrE86EcepvzNFGR53QZ21K/wOb32B2xuS+TAOwgKyNLqOMvxXLDVpBhEHhivPw+7x
CUQ8zzou24BUB6QeAQAPQYoFu8tsLbrTQhUZKPAV6x+8NX6QMxpyiUZeCl3LcaTBlzYTvCrNU2Pn
pvBEx6gj+b7pN7/TXqNzra1vpe/vdBGp/wh4DmwvGeYRlNLdteOdh3udL1MYuQeIeylUqZM6nZDm
LRxXO93t6Z2mRx718ftWBRmBDg+Z0Zcj7luSW1D38ScpLiTz3hrC2C3+zEI0x1MibhsoYMBWE0aF
0tIyBp/KDL0VZ7mvxwg6V31LqXxtkVdLP3BPJo57S+vpXWIBX/vQQd2LCPbtQfuly2gNAokjHA0X
trUEEtjObwiEtd/Qg5h5Qq2SEeGt2XTlmE3Rm8wEuoY3G1emtmMkhdzavOgshQqh2o/fVFoe462X
z7Hdw92V1ZHPwXTK7E8JzihbpWCyJ5WEU/LqEP2+zRKRSe5sNJGqSlFWzJNRmZCqzxieDQdNVEi3
PF+iFtIThMECgOGpNqW1pLvMwwtvV/td1RSAcuEQFM20/SuJqSH41p1THGw/Mv3zzEfa1kvLts7O
/wGFfx18bjEgCbQiAfKLdUzYxU6RfKwMwY0p2fa8lGAlNlMYCONk2DHjjMlmVAo7d2j52DiO/aU7
W38+fYuDScwAaiKvg739LL5KneyAOEu36r+JJYyiPXhz9cpvVQpXfdNgAvPV2fAWmXhtCWNoD7IP
muJWhXC4DbhaqdbCm+SoxbXyXNOBS2zl6PutII0d0wpU/W/1dHne+PzG4ekW0Hn3Sk/H+CIQWsjd
XJcMKSyTF+qDnzkfv/RKu3Dw+BFJ+hkgiiKoyRCSd5eNB9h3DOjqK5DyZgkZWLg2BAaTYmvlzzUM
bdwZecpqM0rxmXFtybefyd3K4v0UGvI4Seb2WM8iSjnIjwEBXKqiWnLmHza7v0q2wQhxuOQB4P11
NE2hYiTytegG8iXvjDclCBzkPWJtT13Z7aemhtjWRKlsExQ+cphE9sYu4u5wC7dHnHhJqDxjADCA
gx1r9KaJeT+QVycfC+2McORcMdkg2raLQ2JLqsi5uvjnBkfaBPDkMzH4/0k8YJfXy0dmXuY7fuGi
B5JBZz26ym1JXpWGGiatran5S7EwRxwfIfMOADvjX04YujXp7y+KiLiREFkvS2tRkMH7Wkcgqvu2
pRzc6Fl4KcoQdvxkzYDZMzCc0pynidXzbvgkbQKRKCtXIWZnrcAp+VAGv2UziDY+YWl1R2ncZPnm
FT64rsm/RIbxn0PPOuJsK78SEpjPLIgF0Ll1xqtZnLFVeL7b6vGxnWVBUnj651t/6LUuJkbWvrpj
mCxaoHtxUm3IXpVWJwBS9BvJK0qwaLNIy9/OC4yi6Rg80qAoSUHfYy/NR6PFTvf+6UGKMG2TQH2H
7wwXC44ZWOZR7Y/3kSbcxOHZOMdyfXJ2V678diQP/rr0m3Xgw2gOJP14AqRIqVv7NypemT/Pqg60
ISEuF07LsKyFn+o3whEbo5xKP2iOc7xhvHr6pTBFtUy6jPXO566HnSBjT1ueeAjEfqeOMWafjn54
0rFP0emvJzAsconPqeJn6HUUZhduuKXnIra0JfS34opa0DqeNtEip4c2fUuSw9vY61zw2i7n4NQM
+YVnjYmy6CuEO0uGYAfZyzMfpThx2EmeDgldEJznZdB2wP9MgzhF3ca4puL92KQYu1MUvKj8nOUk
FlmghzLQ4RCVre2312FKklQ2cv8q4PwddcsUllxlHtuEK9hrvCNf8FAXa9Q4Prr2H31IqBqwKP1v
f4oWxRZm0pqujikj2Hs4LVoCfCbs4Vp3IjGF/T1JAzOl1fVlZC14bSQTgwnTB0uhjh6PFbGRIHIi
ocpkVp/ftcCwHMhJHeiF4lVDvF35EZxWOFL59WjG4XQRQEdUgIJx4lqbbIxuA69wjWff0dSLDOWn
okLFsD9E99ROu2TJPSN5COgFuAtukYhM4xuKyMNLweu6qPMsjSD0P1f48VOZa2O1n3dCcuETuJQz
ATTlFknKa5cDdfb86IO+Q6DFBK7xBxihmLE0m+8biMEO0pwYrLBt+SxYI4UmMVecj6yZ/gZW6onZ
bY5nr5m3Cc9psCFXickgG4FyuEPejR8dFYzO0PjNl41kwheGNbRwVrP29piWggLk1fDwbft3M0Mz
pvABgDvOf/BgedNjJhiyUQTc166mMM1wINndW2RIlRO9iBZF4XEMAkDJc54E2vREeiM2xMitwXdG
+HbL3O8qhCNaB0ugcKY2hCnBxH6LtijG328V+a6tab4U0cMa7MS5ejXJHu6joFPwtWEzzdSe7H8L
NQTL0YKfJbf+bM/c9cso1DT8cjT6z6cowyidKIQEQLuK22BK7O+gOryTXP2bpuVM7QgtZMDCAZVr
daEO+llYE1g4wEPtiylFZJTM16RbrJA/ragjGNWVjfMcfnobmt7V7AyO3do26aPqt6iI4IBeSuVk
B1hTiG/XsGjbtQlD2lxSQ5kWzUsRrbHW3+3cH+8fDQeF3u7YIvzEmo05JLOVXhASx9QLMYOaTshg
GI2YKuf/9BKEqk3eh+GfDWA//lMZpTqU8WLU7rXEgQ2hVt9LY9DhlcW3pS3pC+r0CMuSdmuYIrvG
lJDRdEbXKCfJDi1bw7myWxWnKp3ZyhJQOWe/yU6Ad77N4Vmn3jQwwAmyAcw8OJQ2SuTOvGAJhiN1
0z9siCV3zWv2fIPuEhVxmqVR/hQ6UI+4sVyoof64lmkA3cd6DG7atME3hkNk/QUGaVIyFozS6oZO
vh5QuGfcvvxK2sdXjk8lfbAliysoM/4t2Me2qVSxI8WT9yD2TOIg9pUct+3VeFrOqorfdjEf8Lro
09VPSck/c7+zAjjS8aXgTiXPRVbwMa9hl2QjEvvFAWHJeVNXzolf5H4O2B1SfU04ePEukGMsMkH/
MpXxoz1k4T3gJ3OTmDDKJYtGP+ZOcA2zppDZwZImcllnEf2oS2NgeTswN764nM9NXpaGIZAfwG9J
uxkoTLbJkfpCuJaMNb5E0m4umdBwfOGPZ3qzC/mZJL/kowy1MovEPYQNcG6UFGLyBrWe9srHTZna
k2D7wdlZje64AJZZcNh3Ve6t6y20eJNtU8+faaR2Z9NOeb0DlhGEuL8naPKClxQVrBL+s1GHOmvK
XysvojLd8fyDwip9AbyCgXVqdYMrE/cJEjBwJwC6fwQTBCasyM11v4Hu66a9ZVDFZOYNznFDNROR
W4CQse0qK0wWzWx/vv8xEjlAwQh8Q42vpZjWLN/jbMhpZCnKztWIEBpvXPpHML2l5YWDq7RPWJjr
1gfMDIDUvx8GtL+KFzPtU0vYlQr7Q5MeNB2eW8jKdo+w1ZBn0wSPf+JpvvXrzu8mPkbnkhY8C7DB
zI+bdNdqP4+6cT6fdZB4Jl7IfErx35vh6fbxFnwbGAhVo3qiEhNq4PV1+jZ7fHI6nV0/AjnchGQd
tphFZiwlZdfMB2VC08T/WhF2Jha0azKf7paM1BT5xkeWUR3SBWp51+wrad5ic18nov/5G81awkc2
rZSk/PWrrAqX3ilbKilxx34fSsMJVcFve8xia8OgQ/uSPcve9gKveNaBTrrS+TeCcQ9YxdaFAhzV
vyUfe+yQlKkqqX0/p2sE6jgTPM7lt4jSG8bvuNPfD3zQ/zObacd6bHBKyy5WYcy/+I7boLAFfa/u
s8lMiArM+HUUCb/4JX3GEB1gxmK0UP3N/86y1Jl0495+NP+EpN23lfH4/pNkRwsuO5jNpXz8A4zo
M9cr2ZDhQzLC0dZJmyDXvwhBu79AkLfIAwdRkIN0CcsRx3UOMMjArIcGa0CHKYYposplK3iu6+bG
mVIH0x4rc93ry16MKrDNKDJ1G8voJKXat8IA6OZJUb7NrFfdpPayk8qBNGgxZkbklb+RfIx1N3QW
9a5VL582C0pplFlWh5oqrqtnPorEjrTFeAOlt4owofLrnC8wzGMnnoRKYt3BblHRRnyNOSlf82rL
ciifCJc0uJ+2hinNn8Nx13XfjDrXab46OhTcWG8d4CDyck+HQLC5eEIZBpsMzaaYzsPPswFuCKVZ
pou1fqu2TG4t3A1J1Up6OZZiKZILVyXNLEYUYbZdeK3r+OB4tznfHpr0BPucfE5nz/3dXpqtqWpH
5Gs9tbiIz6mFqrvOe/qW9YQTTszs0s3S7DeTzAxrpjLzsTXHvgy1SDZxRuK+aVzJm2btRnf6NyL8
alc62+LIYZmpsrzq0566aUwKbN/M6G33LXiGi6+3h2JuqyXvNq4AnvlApXZ1rH78lkQer+n8ZaYO
pv3TLiE9nXziUSq3DrYbOop6HXrnDU5+gWaVL9coWBWiWQ4y2ow5Ceb4/iqZe12zIkN5g3qy3BIq
H3/pLXpc8QORGEZihQd02ep/pvu21kjlV5dKj7NYgLmzt2k+GGi5YZtn04uYMvjD24a++yRwxzQR
Tu3peBgDlGZFVxJL/94ssvl7AnXmzRojVLlX7i6ByghYHvkOvfGoaXCQJKMw31ukL8cYafUwqkF9
dy6t4aPFwrT5+ZA5iEi3Y/iknMlbARZMZoebHeiDWbHiYLi8N8LRHaClCFvGQhNBgbGn45YPm1Js
BzgmfgP+e2M0XydUvzzk7UBsT4vti9JXa8UsSknSffod+Nb+fnibMocR7YM7rr/bcLCYo20D9ugk
fXClnFmGrNtKft0YGbDS2tjAIyLKHv+8Fzu+wPwNnZqCQkjIEgtmwNml4IqllayXxdW2LUXTE+Tl
0qkQuLnBZvH5JfzreVvaQYHwdtYqrhul3XwYBkNi/HoAYx5hoBpujD87K2oIHEAKm/yrip1IBcqa
vbT0UcwunZqQGabMeWuV83tSAUWgzS4kUjIVqcDqZZfzYa76RaS74HfjePL73u1fGhBuQX/ptd/H
Wwb1msewSCLd9qvpr+RR+xl4wGLYM1l6BHpkAb8Wr5znHkT3w9LpHs1qR2hEzaqKUCfJREYZFCyq
z0cGZ8A6ZaxRCqMxBZ6VyZhS73NzcZTEjPhqIX2vQlH+tArA1Jk2xaVylWwp2eQJ3qMQ90qZYLDs
28wPCJq2Hz1ImIyws9fGBZDRyGuRZBJoNihA/GljHK6qQ6m677LeKrb6V3UV6i7aNwjb4zeCRU5E
z3L8vpUk8Mx6fahG5h8cMZoK2njQh1NXxWQyahqob5EzksacDznRQEQp1821bJHy1hUCiTTbZspe
PLJBkU/J9spoPI/RV+4efKRU2uELO9IrKl3jL2O3TNsNz65+czLf6U5N2wdWPzSBsgDWg1uKJMVj
cVhW+oS8HPMsxmAJE1tzqMljgRJvV7GZcAeK+6mGXVWjj8n+S4AcPHMdFsPilTBDnXQ9dlLrDrrB
1yncOCfhQWUrUGpaOQog44e9dak5OcJLT7fA2e1ByQMHFHShaKy7T5F2nFNE8ngbh4m9O8nC4LvL
NxjZSlM5qqWSx3NIpvuQMd4/RmlbeanoVQ2Icy/qqIWXfJ+3GK/FDm3S1ArgyPzjsWzcZf7irgsp
4jiRs3RQAcACyUsPeVRYvKL8OIB+IKTIIrcxA9Ioy9kZ/gynYVvLUqa7W0PUu935HSpRegfr8Xqt
cmwR8QoNGNC3NVgHpS5CuxgFpCpawBES/qQ0KvxXCj3GS1DSVcKxD614/MDx8s1OBRKfTS1ANACY
qMqttqHgl2R1hLSFXq3quv40OiLyC0Ku0gMPfPo2xHf/ho8/6nZtxoSUUG2jBcYp4B3OQrHYl84b
oi6UmBWe55p0DS+cw4Q8RqgJkuwb4u/EPCPHvhg+QxNRhgo5xPrKWjzWGAVwSSb1/KuxjMfgZZ4Z
ua70cEHdFNhZhfiu6E8j0ByUr7xmGJndhL8xrpGY/BSFgyovEjjXRdaslxDMcTxyC4O6CcMcxEZQ
e6vgrAFrDcNVcnoGE+fkPQ9sZdbEqYK1TVXt2BoMHmPd8YYy9tbYpTwiTn/S3mjIGGQvcmejHp17
zy6Dq6rbQ0A7SiqldmEc7UCM1+MLj6GouuZXe2myZKJ55TjdkivthQDuZ0lEMR/fwog3L0oB2LJc
Vi57sW3Tuz1YUywS+9YMzmPBm6ZqSFOIXjsCWJ81VfmGwkwFf6C8tjR6JS8ZnCiM9zawJGCUFjrd
MpaV0mFoWZGxErFPVFiZlh629HmJnDq9JJPLLTps3YMOOp1gLZOTyRCTGQO5yenhyA82ftai7PpC
qDYMHyeiwLvP8nC3GH7R2N6CvyTbLoEivBWw/N0/NUwGLd7W562aMPjB5g10gb8M3cEioJyYNzBw
rirGELmA3ZGQC8VlOgPMSAKphomWslGWAAiGRlb36uLPNwgKGqMKHPPdjDj19lwumQ6SpQ3lA0FC
a9kfqpz6N9Ta5xv/tGgnXNnnFi2h8OLDI+V7eqCIl87MhovQYknQ3MIN7qI5fn4nuCLkMjvUKZrO
O7sOdq6Os9R4rj3OJo+/PXVy/AKJzjwU/ILDhkJfSYPw0m91qMRmwDzCLYCgTsnnCQOnCkqbKQfH
StreLKrzfkJmJyjT/3C9RJt4Je29nED8CZrRvjMSS4zpCXfQQY0qBsPZDjC5O7gMUyY9aTfOOfh2
B48d70oJoEE0SiO8LtNsVCtCG/fXPwpJd1fOTg2bF9pxmb9WvfuI1FWHU1sVLpZ5/pACnbZ1Wn8b
S64nEWJ085RCoU/4JxwB2DfJZKr5RJprfqvhotCReKFTMCl4CFWBMcx++j7vrN8K4HHtiRGQZuce
5KM5ZVrOEU+iNY9zyA6kxov0py+eddo+i+Y9trQX7LnUL4pvCUSBSdf1jwGP5Im4sX0qRk/KgIdU
uQFErsDp0CyRZ1ldlxs5fDhHUYCn+BIBiHQMQ3JvIup6ZHbiYhIsNXvpNkzl+I33NiFUzkIB9Y7o
2PE2HAho/wEi4m9jSptQ8cgssDZ+LbhfbjaisFYcrRx93RlMV364XnPvP/1mi6O3v8KDZ1/zeoA2
8Gs3XkM78tm47g9DqZr87gswJivtumLZAjnENeVEvdud+tCvNdGaLcGPkWVYdhORO9ZupzUMrGVY
0fvKO7WWW402UjGWUeyOGMGURkHrhC4vGHJrvJ99oGWvBWKIOoweT4u54pHG0Y1qJ1vSfYCYmKV6
5YqiE8C7PFkWpgONMNN/hukWWK19GpwuwOHn7ACADqlTtoDjD1dTGNAMog0K1iM3xF/K4QVyRxzL
nFJKBV18kXaBEFpEqSzQ6f65+ZPKv05ro7PVwqLcv9e5/DrWSQguSLHL5WfgIeUgNI/DNM31mzE1
KMwlW1hAVZ4plUnTOZJNE5BTNF/rWAR+k1attXmKbjrwEH2u9chU+KqX3X6iw3e7N43kHTX9YKab
y6BsjkDWgwOGw5ksbejymBrO7bfzXXJIOoWAaxSiE3eDOwtme3ElQ8W9/k83JrFEQlTP6+c9/IY2
W0clvyPSYehQbRCkNNsDICck2N0StBik3v0Y+nTo3GLQPQsal51CVfL5MbLo/Yp5n7FL+vjVN5V+
wLsBpGZHPw3SulD/jeRQ2OKRvunGpJ6dCyRvR90IJHhFP3fXR8t/XIRDOVhhjtVyG+AAIlrWirpd
sHLtbzmOfqLzAk/+qK36N2keH13KoVK9rJQ6Uv/jWxujc/4QTSos6z4dcUHR704McGr4BCSpqxMF
27Stj5TNdamraORGry12tYWTLSq5qtQ2iDV0k9I2g+EEnNi5hYULUtTBUzwjtFbz0sUPPLzHkkXX
xSo39Wt+1DeHwLga7VJomucucmEoa3G3RMroRe9fhGqUsCpKxRDZ6MOh9k/J1RHuAvWsJ2uo8pj+
v8mQBJk8glzy9d/nEwgNExck/1/wysfpFQ8H1jvvgSByTFRmRF3oV06lzMdkmOICFuIVBGNmfojp
4B3GhYGDP1BEYw9uxxNGnGAYrJJfgFcfvJNtImP5A7fA8I8lJTMDPj3H7z1W29nESiKJH/UbXe9q
KPgMWz8+GtlCn/P+WswwqnC7AHNHfz42FkY5RBuelZNBIvew1VSI6ypC9l1xtpU08uCitK+tfws7
piCmiPWg4HeGmWuEFD/KtzqObEA9izoc3XkmM75MExGmOCgPwS+XV8E63kN5zmCBU5L2VbmtfS5i
AFMKgx3MumKgIyRapBVraOaNL4EvrwJdyxGgJ1g99VXiq/WCtjCsjDKc3JH75ZP9iROlvR/aYl+3
NPktkLMH5y3Ikq4Hl5d/IPJ3VdNDACmfstrMgM1uaYt24Fpi7Nr/o8wtewCc3oYcSWaw4kgnhWvQ
oku4DWELilbi+OKG5FAYdDozFkgJSkIL94AJJbqLDVvpMRK4h/505SMoZUNniENQ0UFunZWQnclQ
zGM6GCRyBNO2bhrYDWxTLz7mZR7N+EptEmh4YjQ0PFx87TXntgBNa2aMd7Y5QxNj+QmJGrCjjBnf
Grjc5/UYveMPMde1gV9tLwzG0ClX4ee9myVCw4HLO9pqp9UhQolgm7V6i0zWeEtjgcIPfkBi8O+i
6W9TXkEndMo7xwOiTDQRn4/my16MBJ3rEu1wxhUKsyO1XslsJt6gTCnuQfb0+b/9z0FM6p4C5BDW
bJf5dJfZpYs3Y4E6n3ixnwXU9QRaVcm11Mra9kcILM9oKsq5Tp/e+p6+hThtNMldBOBk5XRrTr5s
a4+q6kIUvgi6UFgxOx+NjA3JeKnH1/USx5ghB24RU/bvLZ32pTMwt6wOWXNGL5ekLoMFCr9i01ra
wAza8hPEVhW80zoyGBJpl1+yH5nRCqbS3abC/3ZZue3XvfRDUYCHgXqyqat5zaHfmXn3+gOSsuru
YGcUkFtbstvCd2d+dl3mXkb4Af/zsNz4b36G/Gt0f/M/V4Eb9NWDSqgtEh3u4a9frAx6KK6VRHJr
xO+KuS37ovzIfq9JD/eI+NdQZpMzYpST2Ye0Gn4Em/mpLVUotlmmy3MosRLlTbAI0zdqUbtEKxxY
fWfe+C7eoh3ZZ8xtparA/59JS85AH/ugj4jXxJCiusm7PBaNAPPvUc5IPDt3NLZP0d6F4FKCCjPM
3qS96U0GlXkYsF+uKlDF56/UZbBp3utyXWwwj2yKc/87U+pl9fRI2Q0jL2acgscL51CfQc1sKvag
0UV4YyD1NKJyU0mxPjxZzsBO2cBYJ0BmlQ/sN0DN7T9UnOwuvhFrFjw7RkxxLYAr2iGtv59JtPNG
x0WQz0O2Nf/jyEcBpna+8NLea+pM60z+k0WPXefaWN/wvLo0E93Z8VPPH6pLW/2TDSTqTbsblbhC
eqD35VeM7Bc2hcSfvnCaeebp2/EusBjQX/MFS101qf7THRar63dULvUqKiZrOPe34KEJxXKj2aYY
cH/QF2XAPNXJoUNrV/zegGDODDglpiIVl2Z3zN2Han58h7RtWJgtVRjKOP4f3u9pm2/a1DSGG23g
AFEqIHV2vqYozbPNoaZFG3wxx162kTnZyufxKSOUmtbkH9WWTdbEBSwu7zpfHPpLwwQUksahOSdR
juTIM2TonnmROqx0q45XMLMe0E0Y8FR57FPilIidQYb/eKIcCvyByL6mgRoVJ63hWHjpfdXgqhiL
tHkt2fY+xkCbZCzBcOV5ApTLZQ3fXGe4cDyp7xkFWJ32XUiNXGZKK0r9nkOOkOW4bol/kbvt7y7K
xenFV/+2kCr5KtdpMjSiiOQ9k2itmyr0RvZhRQo08ZQzf7n/m4maVKlmIRwXypIkzjl5YBz9dJ1W
PqFpXyogVnvFp043d8lkB/Bvj79SpPuEoOWyaYWZyRmRwnmLPOwi2gcI0It/TpCyaKTdGzXe7jOc
8Q+ExmgU2GNjjWZM8IM9zeGMlsOY2k3+jXBoekYUBqsSDxjnXRW+DHFOVcHSvHMpg3gaKFvmWTGj
lj4QF3BZRPcUyTa0ytMmySQVKzCUhA7YxtB7giAGphiSgkYNE6pPJG4a+IeCJvkqO+3gRm1BNSa1
FXA3N0d7L2nYSELMQEmUznOYEp9paGKN/Qp14b9BknfXO8mWu7RVJbt+cu5MsPibFkMKb+jeiD60
zGzJAWc6NkEqXKFyaNBHi5n5cifH69+IsrefCrlPiG/xNxwYPWvwRNpnk/g/NE0fVFer9Gw46Zb8
rfoMQg6jtn8bWEAtXBz9tCD1EuZGbAlxhUsu2/YTq1B/NAGrXtWGkntkaFLulb7TxIVXd02gA4xx
c2qqLcJTsGkkU7je1NvsLP9TlLkwlrmr4U2mDSsbV1xvVYlUSvogdUxp4uCoktZoGR4BhwZGGeOk
Gi/c+7Foh1fzumnKx865lSvXrTJUAwJSs5VY4p8xmYEIdDEHoxxEEQDSwZO2/ZRqk7S5RZwb9lwy
+7NVgUY5IaYII40KopazfLdDKbwov6o8ehob/nnvZbil5o6ZlmGhm5IrqUgahbKA4AdlWI3de198
krPSHzxPJXO8R78WmXEDB7wILhdCeYUhKiXkFJcUjFjt+g==
`protect end_protected
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_ecc_encoder.vhd | 9 | 20723 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
bXOf+NyPOFKyAbR7M9ZG95bTMwfg0MjwviSGuv0e1XYvP1cKLa1o/YioaJ7nbdN6Cqn8/6k83/yX
GKAkr0jkLA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SnvXusHaXqdOSb/amn6FWfZ+yZZJp1Z9lvUO8MUXtsiORIX8i3qHTsucd8Mw0mWna8zNKopCr1D6
EpoUCyZP35d2y02+/MNEu/20zvEcHvTi49n6y9ilWtGQmAskTUapgzuFUg1Oh2Mrf1U4WLSmATcg
BoIl8+xN0Y0hV5y7dpQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o7w5ZRvhoe3QaU99/6ZnHuQ6ef/3WhWNxuN5zKJGz/Udt1EPoRIdjcuAt3l/WCen7yvSKp3Kd+99
HgnnX3vLBcbx8XtejxYGIpyJ9Tnm0nynVKz/VDgUFKllGx9137VVT/IJctw3dYRJNAgW6Vt6+x6R
ExcMo+6V307aGNmZ4Zd/i8kOzeXkO+Br9gPji5IXmG5GmR4HddhUL/Ns9ILw8+ehVAJyG2x8NQil
rEKKEO9h2AaJQJ4FRE1qWrRByYzJNetcjmX2Z0hxRlQW0hWhQjTtZ1UBi0WWyQlq10YvEqi5I7/y
V+etoXboYHCVZ86amqt+P4F5hHkjecHFb2Y+kw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j1XMHdGWcxH8JTR49sTmT8wZAsXlPmQMlyjf5hD7XgFoitjM4F7KuJ2NlyEwcj9xett6LNd94NUx
sywk6EC1bq3xHatQk7bEITUs1BH3rg4jrsCO0ce8idj1q575W5/JbnRdSnI3q4TPnOk/mC15beC1
E1pRqwTQAFC15BR2bdg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ggePePlyhwfpik6K+GQihwnmoPqWXxXx6PSefdfXXLWWT/C1DzU1B2K9gI6UXtidLj7C3iBKqsa2
Yhb48FmIbwidfcckyIAsWLwCAyEydWQytihhsFChsGlLbc06nzPWNqS37kVAs7yKRf9lpcQLtWod
mynnRUHpErbbNrIhQlnEE48jq+fuBk8SmolAGXwEL3//k4U2hpLEhCWocdyIHN615duJe+zr+uzO
NNSqZImbQ2TIuH9GiaZ23Js0nBbrpH2X9500mHSbsIM46lcpXDqh/WMRbqKfOe2lQmaATHcjySuy
PEaBmwm1t7gANQtYLHsJV+yXwmIeXx9EkvBSdQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13600)
`protect data_block
NiltjNPWY8nSKNjgBoEulzWB0Vbh5yfcUqiwDGv4ugKQZxoodKvGXXFM52FDdFWdH8AEuLL84VGR
gFzo/ZZAWnex1vlezN9OS1dditAniewO0Vn1CUSWuaWeTvc7K/4dms0kczzRQSt8SY7UP/AFaK15
A33+Od0RFeC1WktP6ySPBeplMkohFZsrSjY33W2GE4SJWjWcw2TAoWzn/9yZnIq+DuqbL/jsqEeA
lf0OZ+NwjH/tQ8iemSnMZFaGRpKKu3Ym4IwZmg7j2WmnCpEGtNsrMa1rDSAMFYthnedLuLUubg8H
wk1YdKh2YBL6WgiCowssZCdB7i0QcFZkOkpEJNNEtF7qY8c8O8zJcHHNNdWk7d0s4kkbKY/visH6
vEtlVnWkZAeiaquifjRadIZqOktx2h8DT8FbQUBa2mFYB1880pwdfI3Rf5tzsR8ipU05mj+oj3kf
Nx/PoRLOVxJIRx1XNtbRc8q0uLeSs/jE7CSZrHfH70xnAAtbcPdcS7gKlyPsrHWIR9B0o9jEe3/G
bv2OC0DWnHqAuaTq+x2QzvJAxQvdxZOe4Zmb4I2TPFrSsBCpB8Ml6wL5FUboqaK/ypszlc/tvfgi
u7VhJHkN2vcUrrSC6++SkjW2u6xVpS4MJ1uibf5QjPY4i8gQuVLzpNIwKKiobozgoBTPiQw2YKoN
lavgnh1JlfUxQNk6vtdx2eGwzkYx61ZBUjKRGQzcUJuV6Z0FjUbkQS1CIbAzdSCKKzKXmdiO8U9e
G5vsddl3+8Uq5KFu6DndRgaOCsPsLJVWZ4rY2qvxjF75DqdZZ8n/k3Hkrb6DJi9zz0wg/jmKUyEg
ppbJB9LcBqj0M00Xck+GlI3KGGFYZOiedeibSyr0f7AcQbgwNMRrJWhrN7ma1jbk1SOScdq7Veap
Acgfh1R9RQqbg03GAfkIx5vI6Qkp4RLpXcsAKbIeUfTKt6Zup89DWZq+OMd6U4ksjrHwKQoAvcHX
jSARIYU22HWHw3qsRmmlIibmlkPfL67H8xqTgRfT3qt+CH+ZaP+vkDLHiBa+8BZq6L4SdvSlvenL
cPJnAYpG4Bz7q3OtGa3F4/Y2WCAS/irm2uRoE3nm940Z+aNcVN9NIO1Wis7QI2zsSrPYUIxoYGjR
NMGeYagrtKfFNEvnoCUehZReuc0yP1uRhfTwvmHk8+nbmIrDGE+ONS/L1dvKgAPKbwiEyRaRsXmf
+Ri4sL8LUybC4MR2mxMHUic8wT8EZjYJy72syjCC3+BLk+XfYOrqD2eYaTRToRJDJVpDaaWOVbxA
dpy1wC8gGbYK0GhG19RsF4XR8SEP3uUanEFPa9Q/Hrou3oFVXcvW+e36tntQn9M8CVFSrXY+gbGD
NTIsJEdDNdllTQbf367qxJNI0DwptJeP9wqjW9FylsOWReCC9SVjOzTCNTUTB9Q82QkiBMIhfpI5
gCu29N58xPsN25s5+/e+FlAhcmF21QooqezbybHhb7O0flAbGm6q/mTx17Ne3xidrEJ95zdcw4jO
jWc+kdBwrdlpOUS+tvdA8ZaC34doHjMw5fCWIafKMr6j+TB/5f11JZ5PQJthh8iZqYT3ZlxA6ncU
fRuIOGW3aRHhTISCiPvVYSG2J9fZAEVaVY48JZGTqyNuKljy1oY+jveSvW/Jx2OHlFf8/c8cF9W5
+P0ksTut4TF1nMG+QFOUtRQMTf2W56jQR3x6GrSfHdpvDG8lAH/fWhS8UIiL0GZe1nVKvlJtyQwk
WFsIJD1XFzz2jLIJyA5K9jE2eDP9ZrS75o/0Bm30KbpgfTvyOq1LRqPLfdSbbvtcMZdHpyL90Gno
YY7rcHO3u80goplL10mufT9XsLnO/eUV8Sz/LgpZh6K15MJ+5T+btdAK87tDTLWksMQ9T/9w5Wu1
6ozfmcBRMB3X3LDQR4llovlZlNJYB1wqhBXLJZDuoRGLYnwAKxeI9Mirn95KKK3ASOWhZt5619hx
fuO5zAB/C0A7RgFtWj5dgdYSH1xn55+8RgwZZhI2BxPi8lCRVbj+HfvZcVBp8jAZkoexOj4O2/Jr
3q6iEBivVin7F+uOBjRVMOiiJI7NyhMFHcR6EK44afBNTT8FRGhIxv16WDeE0P7oN7qdi6ariQtI
7PHos1GHm4S5mj3EgZiYtyCGb1YP1tpZBN4OMdGUviw5adi0hsAUx6uLa4uqsB+NgIWe/oe63ESe
oERvO2whmnZN4sQtgmxm3NtAyGgwFvPaQd9JdxEjGyu7Zu0xViDmViNHo+TBPjvsF0FVr4rlVflj
5MJGhfnraBoi/r+N0w/RHgQn2XHh1GXtfXNXnm5oWTmtP3EKoCTUBSVFc3LQ4GLdth3fJ+kxaRPs
4oAmd/jjo4M7kAuflaOW6I6qw0vgmmNrhZFSJCQk+Zm/bqVAJ+yEQfOpZWrQWdOAdljvZvvdp1AP
lPYw5ph89PvfKrzIWEsB5/8byg6gg7w36NRITAIWttbpjQNZWPJ/OSJa8+7GN6b5i62hBx8pUQMt
fdkhuBpV+vLQZFPtGi1bKDuNYEEZmEwSX8RMIq66c9XHrE/TzuyGMFES4CpG3bxOBMyDKO24b9Su
oHWNvxKg/rC1ia4VfWO896sH64wRZm2syEZM/rO8wXQ7FZTs5jLJ77p1/Qy7mM660o9laIMZxHJE
xoUVZ3EyBG1nZUmofBV9C0hIx7rIZhAuwxc8yUoePdUg6aeSH2BM5uY/H9+FHRHF2EttpgOyuiiZ
ciFONEkeFBkEEfDZwn47txnxjOwI+25p7HLtA9ZW/bMHFGP5U82TcqMlWHrFdgVZ3QijjvN2upCf
OUjfYrww9oiuqgi5sXfhxmorqGcyQU2yNgmkasUrwzuj/mNMkdZBuZDLMH0FqDcOp+oGA1skxgsj
6SDrYt7k4VjU3u2kpZvVAfEJ6F7xh/PKBwWrRa05AJf31OISAses1ThcS2XzZazvQZvlD+Ac02/6
xdTJdb/wMSHefUJCRR2yVTe7sFKuP4ZSMqWcI+D4tQTbVnf1Oi0FO6kfif1+gTn27LhA+xv5xZvW
6jPb50fFTBV9bsSDe+vpkg3suaQrZLKKhFMq6Hr1ylR8aFjjB71iuXyeBgbsVM5dDEaldb4UZgEm
RhGKNQIcCXAOT1YW/dmc0hnPEYJ0BLiRq0GmIE5M+GgZSlc+YuVgD64QfjifrLjO0IZyW4sR30te
Q7Y3GKFCMPnbqhInW59gY11hcpv9s9jo724iMhTuM+Y4jdGsw+sk6e17KJzTaR5fnidIEN7mbhzN
GWleGGgqUViwDOdLnjX/aoKObPmXQ6+jC5Chey2J0n2omBDkJYsLP47I9D6Q1RIn9TeLSKT3ijFs
ImKWKHbwlwLXTK+hQCL+RGyXZzHG9v26ugYXu0aI7QSHjXm8VQVfPT5POn6+xMW2XDJSQnEjTZlZ
DDK1nx5dEtpI9I6RC4RSkpP7dn9Wp6If1k3QO8pW54mmycv+wHyoJJeomFgZw8t3dtiMwfgIrwod
2RtIDetNqULSlKMcGjKc0qLuxoCKA39KFExMsJLlyc7CA/oUVi0VXmrK1HmrqUiOg0zoFaMY6ag5
QWL0WgCGx8hrOCLednM18ntTV2hIV7tt+BVuAhyGBOOAUhEGp214YrFkVAuy1cI7/3/AVNafIrH7
auY29xEbFIZ9dOATsdhcO0UzooQVCNlvBfKztI81vZHUfpSvuamuu0/6qnSfiyU1QCCYFevLCTOR
3NJkispCrqsg38HFoQCJPNW2h7nVNZ0atOuby+fPyNOXsEB9Oqmql7paV/hDVprxhuO7PHRtSdeA
jbsuamnr6GPGTM3+oBp1LwTRkWCQfUsZoX+6SV2jzq4E8ZGXKmIPQJdXk3IcabsMZsUbHN/9/NR9
Lkg7njEOeo5WatrrXRTSI3/IX8b0jiOJau+YGJAO7J65XCjHcIHGWQcbitrR+EYI63P1b4wNNwH7
PUrJzrlWJEyUQ3RNZXNI9i7R6DYupXqVDG7KIQmeigYsKZcaJWM2Zu5UNsbaDR7yLCtqJbV1KTgg
kGFcXLc1DQsox9emnQ0Z9uBMDfbRckb468viEvf8b6CZdIaX7ZIhP+v9wF5r+HFevgsyBaqPAMq5
Q3uZA24emASAZ706SeOWbjrQL4jjOS1nSvVtkUbKV60nGaYVb850l01tdS8jS8KiB1e5GL/N1i6c
JLkyUKEhGy1clw63ykIuq9MoHH8cYipBGqQyJ5a4yvYcWkjENf9ngjBXlHa84nDXNeCx1dW9ggXd
Pi/JjqJFku+4BK+BY5dMB/lLdIovRc656l0xF6Mnpjc2l+BrP1iMaXnt71cFTOu1tG84ShnmglmJ
znbpCK1StmGt5rGa6EEERir8IMSmcj41hbCsnlmTFFf+ZpbRBIFIHILoJ2ZGhwqyStiRnLdGve1B
DiwseOW+GYW01LxuTSr4pwCOmTvRclVzd8TnKALuI91g/G6jEDGJD5U/TBR3zbZCTrPlkYhCyYpE
y52spc8h3/wTLWL1LlP2X+B3/7Dc7mVeCF2zcpH119fVNVBJapO6QthbzJ1bBr8aQS5Fmw5MuYs6
Tjosw8UNk3UKknoMX2xsaTPfRhuSVd1pCTLQJ90IQ70//jW0xjTJCmVRYQYjQlthYY3HItx4pDdt
5nBOoIJwxMLStxcjY7VMNurhqDk7WRHkiPgKkJzio0QP/mMIinQx5uwyFcSV2hyWF5fDK3Cn9bD3
kZnSRWRZY0bopFGMReGtw1YBuBp9uk3/PI05A2BdMVWpV89imTZy97OvcZGBdUtQH5mNkNTGkn3L
i0HdAdZsceVAd3IJqGansEwzNWVy2vz3ysrZFwdKSy+hIut/ubZzxwBWlqE4hjwv958NvTsHuYnE
FKzko/X7+ktZoG7DEryZQ9eDx8AKT1veNz2YyDS9MyxcLU1U0a0/jLERJdUKFImlvW7yHBJgceI6
gueS+PONCKOZKMCp7+vyZj+y26wpNNbs1df5KHRtj3czawbs4nx8mc+D+I7rfaAwO4dlXYKJAZQL
9R6XnGWLE+o5H96J0vDOuwK0+BDCLhYESRoDkD804Exj6SfPuoWusWcsBPZfKwfuK4gsPQZeYomJ
c8s6sqK3fGQBi7xPMreLECVKz22Kr6E1agI01HJeIGj9mwIpQeWLksd/4b5DNXam+GFVkXwY/RN+
5NyCmSsSA4szUBImcHuOJLW+nfIRmaZy5I20PLmvsHgHwPksPxjgUW1uoGeGpg2C1mQc55uLRs+a
rBvbiuspmiBD3VZjejJfyFKkkvO3VhNuxezyGwx3DrjwCP/GiYHDtqj4pQObNEiv/xgaFoi1EcNz
1cERcVQIDLmyxLpPUQiHo4ROLu9xt1ajCStVrUsADMN2Y3HFr0oD1BIEaAHIUXt5PhNguWu+WFxX
g532frK+q/7E3a6BWQKITxgTBU2hZJ5gZNzpHgmRpc2kdAucfXyfwCBLm4H2Kq8cLIgJp8ceXfbb
MIehEsfOuk6Byh7KVkFfMQQ46oT44LqJpJskhHz1nXdJqH+0dA837vM+FWtmXj0xsAdCwLul2saf
97I/wiWqGLTHPfpsRLvhETyQICjf8f0ohU3uY7Kb5aj2ljnwXS1DNhAXOG3G8zFuS///tIXidmLq
h3xES05NNjauhf5gM/dC7AsrmvLS3FD0wsEB5hUw2/7chCHH9f7ub9f8BYVALU4dJdoAEAnokVmM
/4koDfG5k1inXvF9+NKJUaskmN5OMynfafZkHCpE3yWnNBZfOoKDhO99U1BCP3nUQsr98Fv3ZWyl
kBsKI91yeZvaHXJGks2NNMlCGw3NDZdGeygSa0JIS/1PI/3gYbbxS2PNKd6qEesV3XSHlJ/QTbM6
TJGcpu2YqDbj01bpk2DHZGj4btCjY6dInty16vyd+1jN0fZSOvJPNx24SOf7hGuCQnB63toeFv6F
x25Sq9QeW35jx5iDT8O7HfSwhd1sZuFNZRz4wcXt77eeRJzJ81pgRUHwXQrms6bzYTVF2FP9C20j
XueAFGTxECTZI0ercSeNN9xa9N6mWOCpN7ZbxvxoihrKDdeipJTSa1Vxx4qhzH8r6PH4GZKI5NmO
P1bO6tOrkOZtYoaKKXw+blZH/IkFXoPAKT0tXEaGtxhGlJFsYHJLomPfJVFeWq9cxhZ0uY2bn5GU
Os2kklNTwDpReFBywd6Ph3BBRDgOuPpd3UAKCB1Mm+P6Q5ZIu5ZIBFguhqcqo+eas0vkUFxoCudj
F1xEOj8HAczDb1D1YKOs2oXe4ARHJ+7BKfKq6sOYU3gXjNC+snuO0WR2KEEFyyt2LOgFm5Kk3TA9
6mTc/uTrTEOg58kfjphQqGVHyUSwmg74y5+sy5UG7DnmbJ4R99Ws1nhaSEBbT3aNg9qxnBtIlkoB
XS/5UBrMWa/r9PzT4FPdP9xAOifzNoZxycU1BIq5cgi6oi+Vpdvo27bIwKtRGrM9pa4EK46ZPoWF
yIn2RF2Jv4fXga/uHAYAYU6Y02VnY7tuSsXwYMqQHs6KJA+1HmBYu+dPPh7xOCZ7JnDCihrhtB4k
hSjPtWJF/Mlt0AHSVTwYSYkC5CPrs1PLqdArpmg7TkwuxJCHvOAf56WZ1bE5HkICDYOPUvDCP6Q5
dRiG7BZ7eaPb85X0ipiPcHZSuJptljgusp0z+ZmWwS0KvwA1rSP4aSrUaQLnFu5Qrz7RIKsxkTl1
PNxdW8MjWSJqAhyuv9fi/CvE/VBNWBDTlYK3iIN02B8n1wFp4h5Cn3+u89jkDd/8R8cNkRaynoB8
cPtRhGg/bDgzpb0WfSHNIsvrkxUy9SEWexhZ3nMTjOU4tw0j+CZh4wEc7q+6Sqzjr54/7nugoPPN
lVeG+3ilYRSGVXlIfcvqjjOp8SSU+Yr/yMqHLKlAB1TYZp5SDdmvxp3BNMavCU7tBoFzLiIzgwt/
WCd+u8x7iHsFAtD9A7j/Xn9nx4dgRAihqGNqMdHw5nmPdUHMnZWWSZ0BGDIfTB7Yed4ZG76pedxZ
JnccLV6fqpOkkY/HM/HziKQZ/Sbx/ERMv6BOEK8vnpW1jW+mg1CwkK6CMvbMhh5e3nMduMRXiAQO
Xq5su193B1xlb7lWQqw5vD/ceMcaBPXlvIz5R8K6f0RlKzuTrzpsufaq1KBV5pcZEm5SyvkkJfmF
zj6i8z1EQLzMEn1LSwcpmsaEKdqte72HYG3oX4ZZ/gcng/bFaYnqDIBqtvamAHOUbObw8d06kVYR
k3c2svsSTso0MGnA7Q+3mvnY5tPQgrzP30aQlIhw26JcInEe3blDgKpvbpKxsq8B3toKtX7hOt3U
8Gcx15lr6iDJu412/mgfacnBoVLEzbCHR3230DZX4mirf2nLFTxvtYy70VpLwvhQsB0RMrGUzvU/
+Sr24lKW+2yWhVQe+uirvTXpeMeSWUD5aToE4ss+8hal9E0vGkiUWUJoW/ftxrivi+wtoCCyiuZx
si40hXVqlbAXkv6Xxd83xz0P69/OXoMhQUQcRTWPM+rVtaMg2TDFW3pWur/cnzp72dC87J3ee8XG
tV8mNnkP3Nj6xGX1XSk4cqax97CcJjllk3XQPJ/WJO5Bn9q2AvYp9//18uOnevqCve0TejpG5wzD
fCmqhkHBivET3Q+rX56dw8wPF+oHKrfjfjpTVL7i5pbTnkZtCNaOmyFJQ7TvuqH2GbyP5R0TIjv6
lWjGY9IchsetrE86EcepvzNFGR53QZ21K/wOb32B2xuS+TAOwgKyNLqOMvxXLDVpBhEHhivPw+7x
CUQ8zzou24BUB6QeAQAPQYoFu8tsLbrTQhUZKPAV6x+8NX6QMxpyiUZeCl3LcaTBlzYTvCrNU2Pn
pvBEx6gj+b7pN7/TXqNzra1vpe/vdBGp/wh4DmwvGeYRlNLdteOdh3udL1MYuQeIeylUqZM6nZDm
LRxXO93t6Z2mRx718ftWBRmBDg+Z0Zcj7luSW1D38ScpLiTz3hrC2C3+zEI0x1MibhsoYMBWE0aF
0tIyBp/KDL0VZ7mvxwg6V31LqXxtkVdLP3BPJo57S+vpXWIBX/vQQd2LCPbtQfuly2gNAokjHA0X
trUEEtjObwiEtd/Qg5h5Qq2SEeGt2XTlmE3Rm8wEuoY3G1emtmMkhdzavOgshQqh2o/fVFoe462X
z7Hdw92V1ZHPwXTK7E8JzihbpWCyJ5WEU/LqEP2+zRKRSe5sNJGqSlFWzJNRmZCqzxieDQdNVEi3
PF+iFtIThMECgOGpNqW1pLvMwwtvV/td1RSAcuEQFM20/SuJqSH41p1THGw/Mv3zzEfa1kvLts7O
/wGFfx18bjEgCbQiAfKLdUzYxU6RfKwMwY0p2fa8lGAlNlMYCONk2DHjjMlmVAo7d2j52DiO/aU7
W38+fYuDScwAaiKvg739LL5KneyAOEu36r+JJYyiPXhz9cpvVQpXfdNgAvPV2fAWmXhtCWNoD7IP
muJWhXC4DbhaqdbCm+SoxbXyXNOBS2zl6PutII0d0wpU/W/1dHne+PzG4ekW0Hn3Sk/H+CIQWsjd
XJcMKSyTF+qDnzkfv/RKu3Dw+BFJ+hkgiiKoyRCSd5eNB9h3DOjqK5DyZgkZWLg2BAaTYmvlzzUM
bdwZecpqM0rxmXFtybefyd3K4v0UGvI4Seb2WM8iSjnIjwEBXKqiWnLmHza7v0q2wQhxuOQB4P11
NE2hYiTytegG8iXvjDclCBzkPWJtT13Z7aemhtjWRKlsExQ+cphE9sYu4u5wC7dHnHhJqDxjADCA
gx1r9KaJeT+QVycfC+2McORcMdkg2raLQ2JLqsi5uvjnBkfaBPDkMzH4/0k8YJfXy0dmXuY7fuGi
B5JBZz26ym1JXpWGGiatran5S7EwRxwfIfMOADvjX04YujXp7y+KiLiREFkvS2tRkMH7Wkcgqvu2
pRzc6Fl4KcoQdvxkzYDZMzCc0pynidXzbvgkbQKRKCtXIWZnrcAp+VAGv2UziDY+YWl1R2ncZPnm
FT64rsm/RIbxn0PPOuJsK78SEpjPLIgF0Ll1xqtZnLFVeL7b6vGxnWVBUnj651t/6LUuJkbWvrpj
mCxaoHtxUm3IXpVWJwBS9BvJK0qwaLNIy9/OC4yi6Rg80qAoSUHfYy/NR6PFTvf+6UGKMG2TQH2H
7wwXC44ZWOZR7Y/3kSbcxOHZOMdyfXJ2V678diQP/rr0m3Xgw2gOJP14AqRIqVv7NypemT/Pqg60
ISEuF07LsKyFn+o3whEbo5xKP2iOc7xhvHr6pTBFtUy6jPXO566HnSBjT1ueeAjEfqeOMWafjn54
0rFP0emvJzAsconPqeJn6HUUZhduuKXnIra0JfS34opa0DqeNtEip4c2fUuSw9vY61zw2i7n4NQM
+YVnjYmy6CuEO0uGYAfZyzMfpThx2EmeDgldEJznZdB2wP9MgzhF3ca4puL92KQYu1MUvKj8nOUk
FlmghzLQ4RCVre2312FKklQ2cv8q4PwddcsUllxlHtuEK9hrvCNf8FAXa9Q4Prr2H31IqBqwKP1v
f4oWxRZm0pqujikj2Hs4LVoCfCbs4Vp3IjGF/T1JAzOl1fVlZC14bSQTgwnTB0uhjh6PFbGRIHIi
ocpkVp/ftcCwHMhJHeiF4lVDvF35EZxWOFL59WjG4XQRQEdUgIJx4lqbbIxuA69wjWff0dSLDOWn
okLFsD9E99ROu2TJPSN5COgFuAtukYhM4xuKyMNLweu6qPMsjSD0P1f48VOZa2O1n3dCcuETuJQz
ATTlFknKa5cDdfb86IO+Q6DFBK7xBxihmLE0m+8biMEO0pwYrLBt+SxYI4UmMVecj6yZ/gZW6onZ
bY5nr5m3Cc9psCFXickgG4FyuEPejR8dFYzO0PjNl41kwheGNbRwVrP29piWggLk1fDwbft3M0Mz
pvABgDvOf/BgedNjJhiyUQTc166mMM1wINndW2RIlRO9iBZF4XEMAkDJc54E2vREeiM2xMitwXdG
+HbL3O8qhCNaB0ugcKY2hCnBxH6LtijG328V+a6tab4U0cMa7MS5ejXJHu6joFPwtWEzzdSe7H8L
NQTL0YKfJbf+bM/c9cso1DT8cjT6z6cowyidKIQEQLuK22BK7O+gOryTXP2bpuVM7QgtZMDCAZVr
daEO+llYE1g4wEPtiylFZJTM16RbrJA/ragjGNWVjfMcfnobmt7V7AyO3do26aPqt6iI4IBeSuVk
B1hTiG/XsGjbtQlD2lxSQ5kWzUsRrbHW3+3cH+8fDQeF3u7YIvzEmo05JLOVXhASx9QLMYOaTshg
GI2YKuf/9BKEqk3eh+GfDWA//lMZpTqU8WLU7rXEgQ2hVt9LY9DhlcW3pS3pC+r0CMuSdmuYIrvG
lJDRdEbXKCfJDi1bw7myWxWnKp3ZyhJQOWe/yU6Ad77N4Vmn3jQwwAmyAcw8OJQ2SuTOvGAJhiN1
0z9siCV3zWv2fIPuEhVxmqVR/hQ6UI+4sVyoof64lmkA3cd6DG7atME3hkNk/QUGaVIyFozS6oZO
vh5QuGfcvvxK2sdXjk8lfbAliysoM/4t2Me2qVSxI8WT9yD2TOIg9pUct+3VeFrOqorfdjEf8Lro
09VPSck/c7+zAjjS8aXgTiXPRVbwMa9hl2QjEvvFAWHJeVNXzolf5H4O2B1SfU04ePEukGMsMkH/
MpXxoz1k4T3gJ3OTmDDKJYtGP+ZOcA2zppDZwZImcllnEf2oS2NgeTswN764nM9NXpaGIZAfwG9J
uxkoTLbJkfpCuJaMNb5E0m4umdBwfOGPZ3qzC/mZJL/kowy1MovEPYQNcG6UFGLyBrWe9srHTZna
k2D7wdlZje64AJZZcNh3Ve6t6y20eJNtU8+faaR2Z9NOeb0DlhGEuL8naPKClxQVrBL+s1GHOmvK
XysvojLd8fyDwip9AbyCgXVqdYMrE/cJEjBwJwC6fwQTBCasyM11v4Hu66a9ZVDFZOYNznFDNROR
W4CQse0qK0wWzWx/vv8xEjlAwQh8Q42vpZjWLN/jbMhpZCnKztWIEBpvXPpHML2l5YWDq7RPWJjr
1gfMDIDUvx8GtL+KFzPtU0vYlQr7Q5MeNB2eW8jKdo+w1ZBn0wSPf+JpvvXrzu8mPkbnkhY8C7DB
zI+bdNdqP4+6cT6fdZB4Jl7IfErx35vh6fbxFnwbGAhVo3qiEhNq4PV1+jZ7fHI6nV0/AjnchGQd
tphFZiwlZdfMB2VC08T/WhF2Jha0azKf7paM1BT5xkeWUR3SBWp51+wrad5ic18nov/5G81awkc2
rZSk/PWrrAqX3ilbKilxx34fSsMJVcFve8xia8OgQ/uSPcve9gKveNaBTrrS+TeCcQ9YxdaFAhzV
vyUfe+yQlKkqqX0/p2sE6jgTPM7lt4jSG8bvuNPfD3zQ/zObacd6bHBKyy5WYcy/+I7boLAFfa/u
s8lMiArM+HUUCb/4JX3GEB1gxmK0UP3N/86y1Jl0495+NP+EpN23lfH4/pNkRwsuO5jNpXz8A4zo
M9cr2ZDhQzLC0dZJmyDXvwhBu79AkLfIAwdRkIN0CcsRx3UOMMjArIcGa0CHKYYposplK3iu6+bG
mVIH0x4rc93ry16MKrDNKDJ1G8voJKXat8IA6OZJUb7NrFfdpPayk8qBNGgxZkbklb+RfIx1N3QW
9a5VL582C0pplFlWh5oqrqtnPorEjrTFeAOlt4owofLrnC8wzGMnnoRKYt3BblHRRnyNOSlf82rL
ciifCJc0uJ+2hinNn8Nx13XfjDrXab46OhTcWG8d4CDyck+HQLC5eEIZBpsMzaaYzsPPswFuCKVZ
pou1fqu2TG4t3A1J1Up6OZZiKZILVyXNLEYUYbZdeK3r+OB4tznfHpr0BPucfE5nz/3dXpqtqWpH
5Gs9tbiIz6mFqrvOe/qW9YQTTszs0s3S7DeTzAxrpjLzsTXHvgy1SDZxRuK+aVzJm2btRnf6NyL8
alc62+LIYZmpsrzq0566aUwKbN/M6G33LXiGi6+3h2JuqyXvNq4AnvlApXZ1rH78lkQer+n8ZaYO
pv3TLiE9nXziUSq3DrYbOop6HXrnDU5+gWaVL9coWBWiWQ4y2ow5Ceb4/iqZe12zIkN5g3qy3BIq
H3/pLXpc8QORGEZihQd02ep/pvu21kjlV5dKj7NYgLmzt2k+GGi5YZtn04uYMvjD24a++yRwxzQR
Tu3peBgDlGZFVxJL/94ssvl7AnXmzRojVLlX7i6ByghYHvkOvfGoaXCQJKMw31ukL8cYafUwqkF9
dy6t4aPFwrT5+ZA5iEi3Y/iknMlbARZMZoebHeiDWbHiYLi8N8LRHaClCFvGQhNBgbGn45YPm1Js
BzgmfgP+e2M0XydUvzzk7UBsT4vti9JXa8UsSknSffod+Nb+fnibMocR7YM7rr/bcLCYo20D9ugk
fXClnFmGrNtKft0YGbDS2tjAIyLKHv+8Fzu+wPwNnZqCQkjIEgtmwNml4IqllayXxdW2LUXTE+Tl
0qkQuLnBZvH5JfzreVvaQYHwdtYqrhul3XwYBkNi/HoAYx5hoBpujD87K2oIHEAKm/yrip1IBcqa
vbT0UcwunZqQGabMeWuV83tSAUWgzS4kUjIVqcDqZZfzYa76RaS74HfjePL73u1fGhBuQX/ptd/H
Wwb1msewSCLd9qvpr+RR+xl4wGLYM1l6BHpkAb8Wr5znHkT3w9LpHs1qR2hEzaqKUCfJREYZFCyq
z0cGZ8A6ZaxRCqMxBZ6VyZhS73NzcZTEjPhqIX2vQlH+tArA1Jk2xaVylWwp2eQJ3qMQ90qZYLDs
28wPCJq2Hz1ImIyws9fGBZDRyGuRZBJoNihA/GljHK6qQ6m677LeKrb6V3UV6i7aNwjb4zeCRU5E
z3L8vpUk8Mx6fahG5h8cMZoK2njQh1NXxWQyahqob5EzksacDznRQEQp1821bJHy1hUCiTTbZspe
PLJBkU/J9spoPI/RV+4efKRU2uELO9IrKl3jL2O3TNsNz65+czLf6U5N2wdWPzSBsgDWg1uKJMVj
cVhW+oS8HPMsxmAJE1tzqMljgRJvV7GZcAeK+6mGXVWjj8n+S4AcPHMdFsPilTBDnXQ9dlLrDrrB
1yncOCfhQWUrUGpaOQog44e9dak5OcJLT7fA2e1ByQMHFHShaKy7T5F2nFNE8ngbh4m9O8nC4LvL
NxjZSlM5qqWSx3NIpvuQMd4/RmlbeanoVQ2Icy/qqIWXfJ+3GK/FDm3S1ArgyPzjsWzcZf7irgsp
4jiRs3RQAcACyUsPeVRYvKL8OIB+IKTIIrcxA9Ioy9kZ/gynYVvLUqa7W0PUu935HSpRegfr8Xqt
cmwR8QoNGNC3NVgHpS5CuxgFpCpawBES/qQ0KvxXCj3GS1DSVcKxD614/MDx8s1OBRKfTS1ANACY
qMqttqHgl2R1hLSFXq3quv40OiLyC0Ku0gMPfPo2xHf/ho8/6nZtxoSUUG2jBcYp4B3OQrHYl84b
oi6UmBWe55p0DS+cw4Q8RqgJkuwb4u/EPCPHvhg+QxNRhgo5xPrKWjzWGAVwSSb1/KuxjMfgZZ4Z
ua70cEHdFNhZhfiu6E8j0ByUr7xmGJndhL8xrpGY/BSFgyovEjjXRdaslxDMcTxyC4O6CcMcxEZQ
e6vgrAFrDcNVcnoGE+fkPQ9sZdbEqYK1TVXt2BoMHmPd8YYy9tbYpTwiTn/S3mjIGGQvcmejHp17
zy6Dq6rbQ0A7SiqldmEc7UCM1+MLj6GouuZXe2myZKJ55TjdkivthQDuZ0lEMR/fwog3L0oB2LJc
Vi57sW3Tuz1YUywS+9YMzmPBm6ZqSFOIXjsCWJ81VfmGwkwFf6C8tjR6JS8ZnCiM9zawJGCUFjrd
MpaV0mFoWZGxErFPVFiZlh629HmJnDq9JJPLLTps3YMOOp1gLZOTyRCTGQO5yenhyA82ftai7PpC
qDYMHyeiwLvP8nC3GH7R2N6CvyTbLoEivBWw/N0/NUwGLd7W562aMPjB5g10gb8M3cEioJyYNzBw
rirGELmA3ZGQC8VlOgPMSAKphomWslGWAAiGRlb36uLPNwgKGqMKHPPdjDj19lwumQ6SpQ3lA0FC
a9kfqpz6N9Ta5xv/tGgnXNnnFi2h8OLDI+V7eqCIl87MhovQYknQ3MIN7qI5fn4nuCLkMjvUKZrO
O7sOdq6Os9R4rj3OJo+/PXVy/AKJzjwU/ILDhkJfSYPw0m91qMRmwDzCLYCgTsnnCQOnCkqbKQfH
StreLKrzfkJmJyjT/3C9RJt4Je29nED8CZrRvjMSS4zpCXfQQY0qBsPZDjC5O7gMUyY9aTfOOfh2
B48d70oJoEE0SiO8LtNsVCtCG/fXPwpJd1fOTg2bF9pxmb9WvfuI1FWHU1sVLpZ5/pACnbZ1Wn8b
S64nEWJ085RCoU/4JxwB2DfJZKr5RJprfqvhotCReKFTMCl4CFWBMcx++j7vrN8K4HHtiRGQZuce
5KM5ZVrOEU+iNY9zyA6kxov0py+eddo+i+Y9trQX7LnUL4pvCUSBSdf1jwGP5Im4sX0qRk/KgIdU
uQFErsDp0CyRZ1ldlxs5fDhHUYCn+BIBiHQMQ3JvIup6ZHbiYhIsNXvpNkzl+I33NiFUzkIB9Y7o
2PE2HAho/wEi4m9jSptQ8cgssDZ+LbhfbjaisFYcrRx93RlMV364XnPvP/1mi6O3v8KDZ1/zeoA2
8Gs3XkM78tm47g9DqZr87gswJivtumLZAjnENeVEvdud+tCvNdGaLcGPkWVYdhORO9ZupzUMrGVY
0fvKO7WWW402UjGWUeyOGMGURkHrhC4vGHJrvJ99oGWvBWKIOoweT4u54pHG0Y1qJ1vSfYCYmKV6
5YqiE8C7PFkWpgONMNN/hukWWK19GpwuwOHn7ACADqlTtoDjD1dTGNAMog0K1iM3xF/K4QVyRxzL
nFJKBV18kXaBEFpEqSzQ6f65+ZPKv05ro7PVwqLcv9e5/DrWSQguSLHL5WfgIeUgNI/DNM31mzE1
KMwlW1hAVZ4plUnTOZJNE5BTNF/rWAR+k1attXmKbjrwEH2u9chU+KqX3X6iw3e7N43kHTX9YKab
y6BsjkDWgwOGw5ksbejymBrO7bfzXXJIOoWAaxSiE3eDOwtme3ElQ8W9/k83JrFEQlTP6+c9/IY2
W0clvyPSYehQbRCkNNsDICck2N0StBik3v0Y+nTo3GLQPQsal51CVfL5MbLo/Yp5n7FL+vjVN5V+
wLsBpGZHPw3SulD/jeRQ2OKRvunGpJ6dCyRvR90IJHhFP3fXR8t/XIRDOVhhjtVyG+AAIlrWirpd
sHLtbzmOfqLzAk/+qK36N2keH13KoVK9rJQ6Uv/jWxujc/4QTSos6z4dcUHR704McGr4BCSpqxMF
27Stj5TNdamraORGry12tYWTLSq5qtQ2iDV0k9I2g+EEnNi5hYULUtTBUzwjtFbz0sUPPLzHkkXX
xSo39Wt+1DeHwLga7VJomucucmEoa3G3RMroRe9fhGqUsCpKxRDZ6MOh9k/J1RHuAvWsJ2uo8pj+
v8mQBJk8glzy9d/nEwgNExck/1/wysfpFQ8H1jvvgSByTFRmRF3oV06lzMdkmOICFuIVBGNmfojp
4B3GhYGDP1BEYw9uxxNGnGAYrJJfgFcfvJNtImP5A7fA8I8lJTMDPj3H7z1W29nESiKJH/UbXe9q
KPgMWz8+GtlCn/P+WswwqnC7AHNHfz42FkY5RBuelZNBIvew1VSI6ypC9l1xtpU08uCitK+tfws7
piCmiPWg4HeGmWuEFD/KtzqObEA9izoc3XkmM75MExGmOCgPwS+XV8E63kN5zmCBU5L2VbmtfS5i
AFMKgx3MumKgIyRapBVraOaNL4EvrwJdyxGgJ1g99VXiq/WCtjCsjDKc3JH75ZP9iROlvR/aYl+3
NPktkLMH5y3Ikq4Hl5d/IPJ3VdNDACmfstrMgM1uaYt24Fpi7Nr/o8wtewCc3oYcSWaw4kgnhWvQ
oku4DWELilbi+OKG5FAYdDozFkgJSkIL94AJJbqLDVvpMRK4h/505SMoZUNniENQ0UFunZWQnclQ
zGM6GCRyBNO2bhrYDWxTLz7mZR7N+EptEmh4YjQ0PFx87TXntgBNa2aMd7Y5QxNj+QmJGrCjjBnf
Grjc5/UYveMPMde1gV9tLwzG0ClX4ee9myVCw4HLO9pqp9UhQolgm7V6i0zWeEtjgcIPfkBi8O+i
6W9TXkEndMo7xwOiTDQRn4/my16MBJ3rEu1wxhUKsyO1XslsJt6gTCnuQfb0+b/9z0FM6p4C5BDW
bJf5dJfZpYs3Y4E6n3ixnwXU9QRaVcm11Mra9kcILM9oKsq5Tp/e+p6+hThtNMldBOBk5XRrTr5s
a4+q6kIUvgi6UFgxOx+NjA3JeKnH1/USx5ghB24RU/bvLZ32pTMwt6wOWXNGL5ekLoMFCr9i01ra
wAza8hPEVhW80zoyGBJpl1+yH5nRCqbS3abC/3ZZue3XvfRDUYCHgXqyqat5zaHfmXn3+gOSsuru
YGcUkFtbstvCd2d+dl3mXkb4Af/zsNz4b36G/Gt0f/M/V4Eb9NWDSqgtEh3u4a9frAx6KK6VRHJr
xO+KuS37ovzIfq9JD/eI+NdQZpMzYpST2Ye0Gn4Em/mpLVUotlmmy3MosRLlTbAI0zdqUbtEKxxY
fWfe+C7eoh3ZZ8xtparA/59JS85AH/ugj4jXxJCiusm7PBaNAPPvUc5IPDt3NLZP0d6F4FKCCjPM
3qS96U0GlXkYsF+uKlDF56/UZbBp3utyXWwwj2yKc/87U+pl9fRI2Q0jL2acgscL51CfQc1sKvag
0UV4YyD1NKJyU0mxPjxZzsBO2cBYJ0BmlQ/sN0DN7T9UnOwuvhFrFjw7RkxxLYAr2iGtv59JtPNG
x0WQz0O2Nf/jyEcBpna+8NLea+pM60z+k0WPXefaWN/wvLo0E93Z8VPPH6pLW/2TDSTqTbsblbhC
eqD35VeM7Bc2hcSfvnCaeebp2/EusBjQX/MFS101qf7THRar63dULvUqKiZrOPe34KEJxXKj2aYY
cH/QF2XAPNXJoUNrV/zegGDODDglpiIVl2Z3zN2Han58h7RtWJgtVRjKOP4f3u9pm2/a1DSGG23g
AFEqIHV2vqYozbPNoaZFG3wxx162kTnZyufxKSOUmtbkH9WWTdbEBSwu7zpfHPpLwwQUksahOSdR
juTIM2TonnmROqx0q45XMLMe0E0Y8FR57FPilIidQYb/eKIcCvyByL6mgRoVJ63hWHjpfdXgqhiL
tHkt2fY+xkCbZCzBcOV5ApTLZQ3fXGe4cDyp7xkFWJ32XUiNXGZKK0r9nkOOkOW4bol/kbvt7y7K
xenFV/+2kCr5KtdpMjSiiOQ9k2itmyr0RvZhRQo08ZQzf7n/m4maVKlmIRwXypIkzjl5YBz9dJ1W
PqFpXyogVnvFp043d8lkB/Bvj79SpPuEoOWyaYWZyRmRwnmLPOwi2gcI0It/TpCyaKTdGzXe7jOc
8Q+ExmgU2GNjjWZM8IM9zeGMlsOY2k3+jXBoekYUBqsSDxjnXRW+DHFOVcHSvHMpg3gaKFvmWTGj
lj4QF3BZRPcUyTa0ytMmySQVKzCUhA7YxtB7giAGphiSgkYNE6pPJG4a+IeCJvkqO+3gRm1BNSa1
FXA3N0d7L2nYSELMQEmUznOYEp9paGKN/Qp14b9BknfXO8mWu7RVJbt+cu5MsPibFkMKb+jeiD60
zGzJAWc6NkEqXKFyaNBHi5n5cifH69+IsrefCrlPiG/xNxwYPWvwRNpnk/g/NE0fVFer9Gw46Zb8
rfoMQg6jtn8bWEAtXBz9tCD1EuZGbAlxhUsu2/YTq1B/NAGrXtWGkntkaFLulb7TxIVXd02gA4xx
c2qqLcJTsGkkU7je1NvsLP9TlLkwlrmr4U2mDSsbV1xvVYlUSvogdUxp4uCoktZoGR4BhwZGGeOk
Gi/c+7Foh1fzumnKx865lSvXrTJUAwJSs5VY4p8xmYEIdDEHoxxEEQDSwZO2/ZRqk7S5RZwb9lwy
+7NVgUY5IaYII40KopazfLdDKbwov6o8ehob/nnvZbil5o6ZlmGhm5IrqUgahbKA4AdlWI3de198
krPSHzxPJXO8R78WmXEDB7wILhdCeYUhKiXkFJcUjFjt+g==
`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00331.vhd | 1 | 1576 | -- NEED RESULT: ARCH00331: Component instantiated with no port or generic clause passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00331
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.6 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00331(ARCH00331)
-- ENT00331_Test_Bench(ARCH00331_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00331 is
generic ( G : in Integer := 1987 ) ;
port ( P : in Time := 100 ns ) ;
end ENT00331 ;
architecture ARCH00331 of ENT00331 is
begin
process
begin
test_report ( "ARCH00331" ,
"Component instantiated with no port or generic clause" ,
(G = 1987) and (P = 100 ns) ) ;
wait ;
end process ;
end ARCH00331 ;
entity ENT00331_Test_Bench is
end ENT00331_Test_Bench ;
architecture ARCH00331_Test_Bench of ENT00331_Test_Bench is
begin
L1:
block
component UUT
generic ( G : in Integer := 1987 ) ;
port ( P : in Time := 100 ns ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00331 ( ARCH00331 ) ;
begin
CIS1 : UUT
generic map ( open )
port map ( open ) ;
end block L1 ;
end ARCH00331_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00144.vhd | 1 | 98224 | -- NEED RESULT: ARCH00144.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00144: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00144
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00144)
-- ENT00144_Test_Bench(ARCH00144_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00144 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime
) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00144" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00144 ;
--
entity ENT00144_Test_Bench is
end ENT00144_Test_Bench ;
--
architecture ARCH00144_Test_Bench of ENT00144_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00144 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00144_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00175.vhd | 1 | 9358 | -- NEED RESULT: ARCH00175.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: Inertial semantics check on a signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: Inertial semantics check on a signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: Inertial semantics check on a signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00175
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00175(ARCH00175)
-- ENT00175_Test_Bench(ARCH00175_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00175 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00175.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00175" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00175" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00175" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00175" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00175" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
--
end ENT00175 ;
--
architecture ARCH00175 of ENT00175 is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00175 ;
--
entity ENT00175_Test_Bench is
end ENT00175_Test_Bench ;
--
architecture ARCH00175_Test_Bench of ENT00175_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00175 ( ARCH00175 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00175_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00060.vhd | 1 | 5092 | -- NEED RESULT: ARCH00060.P1: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P2: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P3: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P4: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P5: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P6: Body of 'for' loop is executed once for each value in the discrete range passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00060
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00060)
-- ENT00060_Test_Bench(ARCH00060_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00060 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in boolean loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00060.P1" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in bit loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(bit'Pos (bit'High) -
bit'Pos (bit'Low) + 1) ;
test_report ( "ARCH00060.P2" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in severity_level loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(severity_level'Pos (severity_level'High) -
severity_level'Pos (severity_level'Low) + 1) ;
test_report ( "ARCH00060.P3" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in character loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(character'Pos (character'High) -
character'Pos (character'Low) + 1) ;
test_report ( "ARCH00060.P4" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P4 ;
--
P5 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in st_enum1 loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(st_enum1'Pos (st_enum1'High) -
st_enum1'Pos (st_enum1'Low) + 1) ;
test_report ( "ARCH00060.P5" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P5 ;
--
P6 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in st_int1 loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(st_int1'Pos (st_int1'High) -
st_int1'Pos (st_int1'Low) + 1) ;
test_report ( "ARCH00060.P6" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P6 ;
--
--
end ARCH00060 ;
--
entity ENT00060_Test_Bench is
end ENT00060_Test_Bench ;
--
architecture ARCH00060_Test_Bench of ENT00060_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00060 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00060_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd | 9 | 17048 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZDbLXMCW/rFA4qQp7M4XtRAVOMy7+62OqdKd3dOe4Jvb/C2JADukHaa3oslAf5TtlaTLr3ozEohl
VKGhLio1ig==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y/syMaBfRSQ9MD98NKAleGixPcntMfRl9i4DpBCi/l65gO8EpoXWOhQZbbZ/maNd7yin7yuO19Yn
GGuE9YDWOl8XBpG3phkcKzJdSu0mKYd+0AQJj9q1lFv6qrGMoUttsl/IpN2yMUpz5fUapnIBd6rb
mRz2FHrHicaebKc88GU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FF+Cl3PgjNR7xzwHRMbIHqn9oRbNDNLj8DIaO1Hlm+2QX1CI/VCFdTgjthL/wOzU50VEXfI4vdA+
5GN341oMmZ0O5YACNPw0jsmb5K/Axml5iblkv1aO205Ys1mBMBZkaFGlBcZsIV0uEzUDpOvPfeVc
ABQXYw6KbTA1+NUfxZFROZrc/rjF2mQh4nDUCfFYZPrriJZjjyEjlSX+cy4KzCuZbbpJBCFd6XxQ
koLohsN3xKemISIPZsKR/aiic3+A4CLGXARU2+NNZ8Y9zw6ZjLQLvFiy4Fb1QeehEhg6MMEY/h+t
IjJP8sZ2k68e+ilMbQE8db8f77x7eXxc0dya2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WftP1jT77k0S0KW6WZKPHR28tgdkvbiMqDTC2VCWXKRGglkNUJl3J5a6mxg7KN6NyWhnYj6a5QQx
8Hz0va2ePEpBUyQNGP6NCbGXeaRe8pCPsXgRKTVJmrMqDjyhAZagmIXcKOaLXzSspWEBEQiSDaSF
bOXSgmj7JNe+zDKqwGQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RqlUBtgum9dv43EmKmtzWIjfHZGaDUNQ3TN8Yu3IeXyJKi5cWCoW72Oqm8t5IbLFWHnY2SKPDquO
q9pnAH1xYve2UU/ki12sb1zBNCPYJNGoVMVoYZ+WBiTxkJRS6r3QcID+4PLSLBrCx6FOaNYxyz+N
HNXn1tfTA8+dazSGeer4nW4ht7uWxXKe8ZcSvezFDU3/Z+p+x33qF8Pn4hTSjcYP4oZL0Zy9vG3Q
RhJw+4Hx1YmXbpfrBWVqQOuYui18fd1gpad/b4yH9e+H5xWbSO//cFWXzEE/cO+APY0/xbSvI9qd
ejSJhSc7iuIlnvzmNk5U33IYSygGzh0yfq6Rzw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10880)
`protect data_block
RnRPKi9jEml7Lu5FUKT7enOKOvnc34gbCzO7zvUDeHtG+GUynXRcFA+rsSsRPbZpqCjxxTzp5Qun
6WLhdv9L8FEaS9Q1jhKlkGFB55l3+p4qQKTbx5MVd+YUJ7Zu/kMglcFpSUa+KoqO0Z5hy73i0hJN
4NWbm8nVqK+W+TFXMYBWUUv8aiJpbk5rUX8c6NP6epVkFpLlR9+peyLunYEUenGU2yYjoi+w4gtO
OAZyJQPBi9ZX8ALBo4pje3GMW8fT+0WHbsQkbKnYPch58C5QTU8YIT2U0NIcMcjLTsDD+GLUXDQU
aP3GFY0KrHDO38Ke6b0TZ8R6ZgY4JLkL71PDr2vR6Od+oeWjcrlbRoZ31NGIPlUw/vRIHffn0MhN
n6Oe1LnKgVQEoM0cMX2+Y8CNaQziX0WvHey9nc+tDwS6a8IM+cdehwfaq+v9e1w4nHGXFHvMrv7J
XgLd+PPj396aHL6S2ZYlNiHfhXRYUx3DE5auKfrIjltk3Bc5PmZdzU1DuM+PehEMoY+41BzATXuO
M0rimqNeckoKlFFfyzpEKA/YyHms8EilZ9c1PQBQEet4iiy01BfHig40wlrTze26i5PhsCcghh6g
kxThOdU4t2aU3UQaMQuWIxnuWt4Ms5Ob5sqoAX2hHVEKvP2U8s+LrZqG+dELEpbkIhAgyCMBNgj0
Inhi82+4rU62Zsus9Hlq/pKchL9ztrRYBH9hrpcl8bIqvnNh3vlWmZdcwrpfjG0deANc0vHZstJt
Bux6IBdaMBCwPHADTTlvQeXcyZO9VTy/D93ncxXeaJ/FuzjaBl7UQo1T4y9eRYCni3N8HqoqDfcO
EtYJmnRFzVlQyk7tTpWXKhu1JRkOd86AUtW6n2bth+0bZsX0trG36iSx4BZaMZeiEAejxtWZ8kJu
1KgWqEPL+pbgmjoeYfma2EPnJ/UAM9rTbFS0Bai51DLaBlNC1U6SfXm6VPLkwFVyqn7+GhVh4kRs
Q9BWCrDMXyJGW+kaZ/EuSavt/v5hXOLwrq6LVA5rtiETpgT7mqQL99fPqpqX/qYf0mMtJyfCwJTC
bvOM/L6wHzNAcMQK2E3h8hiWJxwMZyl33SuiaHuH4bxd6Bf58uN80KkwCsMsOT/5hd3U5yWRnrPp
BwD7Z6zUtVxmvJT6eVMnzfy5dkJyk6aBT79JiWZz7ITFWyFn8k/SBtzeQTL0Pb8oHDBmNOkk3qXB
g6fhSUJAvTp0Rjf5K440RObNehIbuCZ3uMvp/PhUB/KhfzQdCgduJxkmcOT0UuzyxRdMgK5LE/6x
9CLyhKqHxOY7Y9yjPF62alcETmAnXFqdyUnVCutzYUwo+VON3IKhy/pdq/PjXa6yRrCygAmVw92B
cre0eVZLOE5ew0k0fS31pORFlo4LuowaC0yJZm3TYYCQSTFYxkJlM6jeK4BWmSoPmfBRBwMjDpTR
8v0r4pThYzeSWt1CBCmEYq94F5gKOo3cQ/lchV5zKIrdIA11jYExInchOGFvdWSuhHyKWEmiouKI
Adt+ttvJEqRlSdVZwdnUI6+oqIhBrZIdBKMXRNA+0lWs4MzFdl5odIpqRfoRG+Ck2LWdfUoygEHK
WAdLmxQyhHkmjqoq/Mg3uujQLFrby/gMbq4A2udy2d+4oh2tAjWSLd+4qvxuiUMIlSEl/RPqFFpz
Kl69jJkW6MHYQS4WG93Ui+ANIRpFYz7pGGPEbEu3p/pUVI2uI6ImNLV75vl4f9VNDkwCrFZ2wzUI
H+eTezozAHiLmLHJZOOuBrXbBEeiPomOHeqQ9RIXe4w4bfFfarpyIsGLSkxVZbiPYVz/2uzZngqy
+1n/FVO+S46DODztVlVVGMI7Ty8An0jFsKZS1Rw8Om7udaY5sFOdmp8NTCzeOMRiKU993LbyGf08
QXeD3OUratg46nyrMATDQu0xOAur/bdd1dxJUbWiY8emyKA0A/OFYQv98Dw5A/5fV2ffZnRvFYn9
p819ZVFdaGG25z83D53gM72aw58WtvDBThrfhPYiOmGCnsNwzevdhYuxXzVVoRm3XiSkkFlVkzYW
kAPtY9cl4YqdkJicSys+5Lo/n2NqItSj9TJ/yVO4Hbf3/hwuomKyNZ+0uYjetwhGFomSuDrdTKLs
wnudxVbD4U5ceP0Xuob56QwE4ovuR17hOy8fw6ZA3pXf1hd5WDA/tQCEriKruwJ2x3dfatTREspE
ZiCXueZWz4iUCRgFtDZAWD37FVVb8aJ7Utj/KuPDyIqujW1uTHXPC8YC4rFOiLsp02Fk/HRTXrUu
6a+RIG2x7cfYFP06joczzSRGLcg+MZlpwv2H9AlteR3Dmom0B6+h5/EwV2DEU/rht43L5kOaDmDK
sPtA3cL5+CJnnclUki9sq2W//NhWAxAsrF8Z1FRtq7f6gmeNRtP7D81NRihHJmAp6mPdepYnW+1G
bfxFWRqiirXLzXGWRENU9VGJ5mRxZRloFknCJb1tEf4FKsBy3XVr2dybjeijp4AHBTSmlMgHP7m1
yC/y+OaBc3fPnOsr8eQ+iwpFGWfLuQxpm2ozCW0uGT0sxh+dXO5lPCHXAAs28ygSLeq6EDi4ObD4
uNm7vEG0yewGgcyBcaKmjDmtoECVUsMVnDc0VuFR9xgTnJ1BTodWR+9nA5ENs1prEHe2fYQE0gsx
MycdXoYIxZekXPbVkgxLDnEgYg4X8ElIwCpsMdEnbkOZC1dlZZOO8h2P+BvjynE/3DGBzbkHVtRP
dOqMLVImqDhmrk1JrbeIlbg/Qrbts70QVTCmAfw081DhqzFHvGnmcPqJXkt809gPqe1joZ1+K+0R
qDDqTzPQL2tA569sWN7UiPX+yqzfqibwJxFXNJ4Li1F99xxyluiX2cmkGboac81yO7OqziAoSspJ
YyjrtwRIy4Rjuf1BAOd6bhQVSXaXDVJbr1ZGk1Afyp4ddLZWQc04NYriBsCgFw4iSl5TuK4OTvOv
871+VmklUyogTiJegUQX2M+L7T1Yq6pAYKsufo3an6zUSmbMN/9kY2dPJdKKIC03G/4/OpxlLo/a
WLhxMkWVjPemmHVQhibRl1IlVIrLClpSvhE7n/na5EaM1xej/J4CKwNZFwhG40xfvUXSWxSjIpG7
zVvTgB3+eVKFS2t2/JUvHsTPN9Cjad2EiWY1lanZ/pkkYYTbIxAqHj0rS+l66aXqb1BmatdcZIOd
sjTpGPK7fRvwYlOZUJKqVM1epE8Fm1jMdL9cY4gfCNrFu50rIT9VvnCVduuuA7lDtxauMVWR1qKz
0ecD4kMWpK9pcX8eRgoNvJnqrP6wzQdAzAl78qCaYyqF/YQePBbHO7M8ixvaBI6rA+XUWK9gV8U8
QySkkBt+OByPVsZ56m5hCAE/3NVLKlBev9vPGuVVMiXLOyXYIwTRQroN4YLxNWqtJM10XHeKADoG
7OmWKpCjh7AGxzAYcaeEdONW5GvVQ/5M47evphkKxMpaXlMeMMgQSICjN18dm75lpXNjvurvdZrN
GDDhJb73T8yct1yQGomqbth82tcKeWQXGdTuj94yvDRwb7TU7wXa/84cbmHzXJqXRST7j6mc3SB/
43Rqa04OHWf03U1mP/aVAr9OSaOr08Do/MA/6iayrCBmFGlOjmh5csfUK2cKhl/yPWHe9uW9Wl4p
mlg6UyeEWR8hrdr6tvIN1VwfsiVoYVfQi7uwvM4dsT07KlfxE1x8Vi249sy9KyTCa9RWBu7SOQcn
MIFvnlVDY5wSCht5TP1hxXQct2F4k351/xGqvqB1Ouikn8SCmfbtTgOdL3CeEnjtVLKdCN33ryrk
dSxgdpwEUrxKyNVr8OvJY/RVrC0HoTdSoh72Imw7Waj+M+vpqDk5GwkNRxNQyR+CkxFCpzn87980
dJL3nEuy8zMqqDue154EpRiz6SajQF+dKz9iTJWLedGtczEkBuCL9MP8gd0K/umt6vQTiWTLy/As
XPVo/2ISYwdcU4vQS+5jjzp1OSwu8CyaeXq+F4zm6B4fY7Jhhn/0QQSuxGy0sxLayuZvJ/XUqf0F
uJubjPFq4paAz66mB6ZiYHCubiX65Yv2DOyF1jVObZE4WcCNhc69RTgeQ8s6JVqVztWpRSZBMGLq
hj7ZcZQn1SUU1L//bXTN3Zf5qPi4iuhk5TDjfqTYnwAs/dHQzuBsaClL6fLkHgHbiR1nAJ99Ga0j
qrRFBq7kk6i2MAO/7WtPfwnuV4VtFJsFuASGp7pgv4TLlG+lJwE3Bx/X8AK3+hd9zkrESZPZfzJh
YyVI/SjId9fwoyEgrOGBZFe5cB5GRetIxHVWvEWdR+BNv30GM7puwMkSDgQfULraG6j+BufnYfGo
qxnlc8pmmySIBYd2XDvCZWdt+LLTXCGpu4tRcpkL2utiRXkUpoaCqO8ZI55X1lSigYQg9PzgmpZb
CYkITKloliol+rhHMBx9X8sOJubHfkkkgscxcMoWC9Q1dQSAONR+dg7XHdadzg3YZSWzshF64TI1
hHgdhKNCQvBr3E3jXN8wQLmy311a74zy4USwRB9lwvSEFyVjx083i/3L/98ymRlhnlO9rfvWeE4T
vnGn+qyJEoZmjY1zhjMc9zHisj4Vzpd60I8g1dxsxlSoPEwBbzz4BscQYyrpJKIRkS8hrGunPBLl
0H2lC4CZLO6P4+VZ/oiK8CahZ6ZiYCvpiVvfa+y2PJs5sBqldgwLdtFBGFh6+dsSkD5SXOUAc4Rd
Mqp8QFAOKZzOdtJegswk67ch/0DxGdDLVm6awQ2VsM+yk8YbPW1S2C0yEtO4FgNHt1WUC+BWARHb
a2gr6kcCfaMKpw/H44709wtU83Rys6T2Fbdw+1KpqPOnAs1xv1ae5TO7qFP2JNbAeZQns6dJHskq
CPmgQ6S83j8Cx3hJBmynvOErv5hPVphlfl33ITpwumxR17lBCC5qD8WvLmgRhKHL/nL1VJITTVBO
jJ8Mc2aecViN1F9bQZOqau2aZyUMVNFmBrPhM9xUDcBiga9qXwX3rwGLtI+yfhSH8wA7c2SWwN+F
08AW/edx29X2cqRXhJBNI+CndbcECfZ92QE+YldnTPwYnlXciv8hcKRUCzxhrLrzzHCIBU5VUB3V
JiWnZMzVOVvso6gX1s7cD2/gsDZkKcTcSLfC+O9s+8NKcZ6/jezNnnZMB65LeUGBr9V68BqF6uOk
6WoahcUciuohCvT0s42Uak64KRT9jWSIF14tzLqTH58mNyeFtLOwxEp4L31qQZ0+LcLW9uCYchfP
Ixdtgo42dBrhEpl0PHGmV3WfFdO6JEMQLQyfv0octd064fEYYGph8+2L8cp34jztfGljtbEVZePq
lxRBd/B1gjsqH1geSHj79gLywLfgnkM48NXw7Sx0PHkDsyEo58ybiyS3x1sF2LkE1e+Q32ukxxxk
g/ZUXAvwhB+7UU/xtX6bkGc4bAI3yRaVkQC5Ur5mBzQvH6LzGcsV0jdEqFTQKrT3Rfebi7W2I5oM
FwuFD3MCho0yY1dnmVul8pNutzBZuGXCT3jMUf9IQN5rxCdPqgbpwfetLuEoGFWhRTOyiSPjmPli
vQ++IUHQe1kwLBAMaT5mf7eI5D3TJytxgMY7sStxyH/bMDXQs47aKoWC9jruRUcGve8l8RuA4Rql
aXPyI1uEKhoIYCfFOYCJDCJblHLsKtQYoKtqZsd1QLpT2QrSa7ApsZikziWLXRXoedkprdvm4K6O
x6G8zP7vlmSC/X5SzYhu9KqiPUWfb+MuTy6COJqLLYcTwxXFvlPYX73/+TQqB4CEpRglX6Ovqkxd
qIQrX4Bedx8t5ppQ7ZqQ7QmIBQ7nI0Xl3Tj8mMrdSZQyCZJIilcJ2ZpTMDrLytYnXUUueundrxHZ
j8Tx+sDWzpB0oO8guFPYG3nLYBWZxOnVB9DK393gGTmcdIAG2S55UJf6vKRUl0u67iEv6y7WYc66
U39NTbTLElgYl8qDed6dcBxF3d4OKjFoy0vZbLG9iRCWvPBz/X93FYeK//u1zOm5CIi5cU6sG6m6
M6MAUPPvi8/Z/0FxyRWeCvMvwRGjg+YXqJg1xXOMuiMsledRHTmbCfQuxuCERzzCxPiwU9gthViA
lUQc96DLsaaxozWrHY/bL5QJtq9JN30KJR4/fgPNHhBYWAvHD7oDhuFrBqZyn5T8ukRfZaQxEEDS
8r6GuRLD83yvpAyqJLEgwB7rCRFIp+9Fwh4Hm1PvyIKh+j/luPInNWUJWJZfwP35W4Nreg2olAm6
L2i2xh5AZQvB2U3pR+Marlw4pLj6LNM3blmmibUn837LXLAlYlijJof6N5tvi1PV5DX21DWuh8mI
grfbTMd/B+jrOtTI1NIcXXNHRAWgDfnfhH+3C3zgfIIMRuWQ92gRKE8U2XVngejX5ObgJNIYm0u+
pivXrJxHwQ0xnR5koAg6v7pK93Pv9SXmKz49aknXl1Z8ZtDOvKDRANtMtaP9Eh3r/VQksT776Sn+
63zTDGuHj9jqWLjGt+OnbtSG/IDT3v7W9HOvuLvBKaZc/Am3cX5oHbC9QHcBXAhsO/5PGesdDYzR
9tiaROWgDUZl8zi0EOM/171FL9W96CGyOUH4JBNZI4YGQDt6Zaou767sXsJTrXd5VHEKcnX6gqUS
y3K/ycfn+NUx8YVr6Rh1VRD5RnBq40DLBQPry2kg8grqf/lFKeRZxioKelcrndbqPXhZ+tujaTnO
CmJ90be42ovBjOz/WDm/BFHnGyH//AplCg02QZLC2yH0UihxubCPQQzbR3hxdpKp/WeNlt6PPDXW
MAEmXOquvia44bZ16IZGs2pU6vnqBxdLKzCtTFSpuULo9jNFyAIt0EZXO3uX6QbkpXPfKA6W93Da
K2X8heZHSnpV8Eju2IUusC2Tn3BrKpXd9JagIQToGFxzwOFEveX+hYyuWYUxz2T04jEDzWYRx3nY
Zicut1JNKebA6w8c9FKP+55Pbc5OCgTBZ2m+Rk/NZgHoR2ID3k0xzSl0jDUikDxRWVqMi/NTnhB7
Dghi4Tw5XiaMqmYh0C31b07OEkTnIMuOvSx+pc6mxV21iOHbdJsu1qKNxCiQo8/XkdtzBz5PeGnz
bUaFy6bDVROaCqrzTg4lo0BxNChneUdakpQcQXbMvHcDF0Z6REFHXZYn3tpNSOU1LG5YBzgVy+SX
E2vE2Fm0BiG5Z9MmbzehF6anRINl6ltHAfINNu0nu5HYLDnnwOIKkfjtJzD1wE5qxC2nCxqMSapt
UpQIh6Ff1w7FHjbWoXTNONQPgHR8f+CHHcDKdYExpbWgQ/hIPBl0qC0UODcOqB/xMLXcSGZT/iRT
OrLjhfxOccu3+J0Xf0TpW57/LnjUXWl/A5LQ9OtulNLnNM7MAiYd5riTTDIBV3fjGN1/ggqej9U8
+LEjwTv/XByTgNAyb7PKiwixxFoA7jWjslLSY1w2hhnLE4pBLpb9IYAY4bEDNKbbDFFSH0qU3GTt
bQh6TlOyyGxKTAnDnw+vclF4peFLbTmry1pZLVtn+okznV2RvwVBLza8+h1ISLNw1Pkj4qpp1cCA
N5u+53tqAc2kdaNfPXzRguMI71UDMAoBX2dJHc9BujqQPhb31nu/8L+GbeXkj5pNraYO8x+q9wNC
6SGuQ6+JP/QlMCVVRPbl3NQ01S9agqYOP60ws/V8dEIqYRDmaobyxA782ts+wJ/4eA+D6ADIWm2N
SeG58t5RiZubDk8AqDoXLUPrSnLIwQT7bNATJkrn3KOQ+FBM7OhCs6UbUVmDYtjApNCM0T+FWvx/
dknCxMOj/39PY+hhgSqRsr6Ak0Uy8vARua96VI0TAFpmbm6zvRvI9knO150la9RTuZvz4dU7YcsQ
6zhthtN0DQjaodQHLw+wLpjZw1M7uOiQEBBwV/r3E9qvRyPDwXAL3SdYfQclGnn0GXNrZvAhEp8i
/hjJyzrYvgyDyhruCI4oLiMk8edtU+pUej3uWIiFTPSCfZfuExw74PmVlOm5RUT/1ILujdtQ1kMm
r62YIyUZdBUK8iwb/O6aGo/VPE+BSg0kEr1/0lptahDwuRuYPiyS2N84xSRYYhgBkS3OasRxWZg6
Z9n6GS+fQZFCkK2icDFzIQndMm4gz5f9q7sl3+8SBIrZS4xzFJu71S413Gq4qQcOGeMaDxujUVDY
H6v7SA4nKZ+MRKBoGgYOwEVfTPSo91qpDKBjWxz7hBGQnGvE39CY7ww9Kn2rEi3NgmNczV5UNdKZ
HWN3ZlBl/IknxoBjHs3qPfYC53mR78QOgImVZak1IupgFsNEPSBKLvZtp5w5TIAhs/UCPtG0WmlJ
dUd/U60RBTVWosIAuJsmpTE5vrFxKB4Rv5GfWjk0xL5p2EwqVB718Ti0XEuVR28Yv8+sxSswbDje
Sz6NtfgfnsBIodX75fNNHraYEmRNor0dfGGMAl/UaLdy5ktbQd//Tak8DftrvFP1PdJ4NXpPg6ad
Ch4RdJQ8dYwPCGY/h9cjx9aK0D2OEESND4Hen7w+EC0LuPHFwy6EBxzSuqhcPZRzuBPy5jJ/FXid
9n1oxUqfbKsc4RlXy4RyhwhjJcCWbcRaBD2V1csyfSO8BMjfzUV142u3QIMY/IXx36ZYrBwuw12e
x1+gUy/mqdn8rDJPaX5hkvrzXHLWgVo54THWG6/Spebao4iwIizqiLhO9YR8qpCsVp8XQ9xgQd/z
h9argOxMLRle4851DhC8ekFjaDdjUuZmW3ea3H+DQyWDSSOnrBk0lm0GoTX4aeI3LzHEJ7xAq0qE
r92o04i0OxLD0yfh0bO81kMXVM/xd5oXb64AwWFV9WjUq/MV4ZGYBH4HYc/BonjNSgi0rLBBvutY
5K7JtVRH4UArwk9Ev6ZK9BlnvfftDZcOZqNEaig0ZWwNV7qlUGAbCcS+XLJZJIyZ6H1VNjcAyihS
PQfZtuHL86ALQ0xOQZbWZUHF+b+vWWlRQnyJFpoHiJrOnDM3sYcPF1kiVy46J6P13kkqkGfXPB71
zB1Du6QamjM5RdfMe9r0tvtSAzgApA7R7Jd3fg7BKQ60guO9sbIQHh45Lsh18b3DznO7IkNhTqLo
UzZlGLuMheNgO/RsdULEYvpKAzVXkm7J5IjISsiBsA2aRpl+EelOI1UE68CnzJzLZ9P8uaSHTVEC
JF/CiDU5TL2kBMahLS+iBeJ76kBd6z/J3vsYhoa8WUTRlbp7UWduumM91R1B4zBwWnDII2TU3iF5
EXGwZMLqCylT9O60F0MYh8wPYZLhZiLoMC/OhZz3QT5jC36Y56VBB2eCKH1iWY3J/kn85ogyxuEZ
Cny0SbmG7QYCFE/bchI/BKqXmNr1RFGaUD1Rmv93sLu+EEAZzF2MM+4WgDQxIEd4omJzsKFufTRu
/Gvmi/MnSJq44cw5Cg2W2ToIB/7NeErcBuVe8SBkVZb3TO0hHoUD4a4k7bdwuTfyFfJ8X92qqqX4
Qn+MWp78c4V3r36FKMbCrWWgFz1g0FisfJujLbAbqLfP1UQgYllcMMIAgBt7RMGBIlQjiO1nWAQr
+C7edhlPKnUJMdrT5RG02j8+rFKKEloxEA7Z/4s7NXVul2l/b+EI/KyNUSpVRAOF/Je5yWZTY60L
YEg12lmThMo/mlKbPuFmyCfYh1GKdor1IC1tm9nNlrFcfzPJl6L19jar4l4noRy7dkQHEipmhQHb
oTx81tjPCGZqMnUJeYNuzG6RAxnF3+CJ+jEbnh0twBo4SibMHlw8LsPucu6HwXYIlwAYnv/YVvJP
nSNyCBq5T6UT65Huy0Np5V9oL6Gg/iuuqdWv9SxDa+GqAnQVVaw/I/abJfo7tGTEyTrlvS8EGHkh
0dT1HQJpF87JrEO7L8Rq+wtaLP2PVonR4KU1cGxfmkC+Cb8QdXHXrKemep9VejZ4gIvK4tKC+z3E
rvCDC5uP2QhRC2+swOhDuXMAMWYviJP5Y9aid7EoKG68mu0hbmxJdUqY+JhxLPKt4DQOK414xrnH
vqnLOU1aSP86m3/EGdNi6hsjg4RiP8Pc4Pl9rpwi7gVc5Jrv53CAIvh0MW/PO8jTuqLlndx4Ga9w
BMocuP9D0C77isVKA4RG9Ztn4obkGUBlibBAMigP02StFUw/4u0YxDrqyIGMoiO6p3OmfUnZBkKz
XUoPuI+SeyTvuWZ7K8X6J8NXGFdqjvbdkpN76P/DZxd9U/CIVUhQJewrwgugepBzXNEhUEULpnAd
OW/YeFz4uO2J83c/5kJyVNFKjCRD9byBtqlgQ6Bi+AOB6xYL5H1PktQJoE3hfZG8CRHfyGJF6+hR
UmpmDkVW3fslnRLeaW3Y+dfxxg77HxQxEZGeceWGUSAsn0c3kJJL9Wj0DpIF759goYel2Mu5PFqs
duQPo7MrZpitM1cYpOxtnSIUSyEFd5Jp6zpMqdijsaOQoAZVJ0wVGCAys4dxpySp9k+mnisHZiNt
VIDRl0ieBFpWDn/ZxuylFbT+B4hnVJ7Z1tzSXHOyrYJjUWLgFy7eT0UfZgL7Odoj4Y5q+DteiN8G
mvz0+mO2zJkvW2hlontPhH70OZMb63blB18MVTg8iU97z9Zmsay+vdZ6SH9Zcor269eaPQNlGOHr
X00bcntX3GbjnWF6VkBoIvabW6x2ILuDwmAp1CX6h4GYY2z9H2MNe15EuBLn0VZBBJpMmGkMF0fJ
1i/7NVnkCKwVFgqT4eikY+io5NWMokxe6+NThVk/EJUZDpmPyYRjc1xNXGt+BqqTrZLnvAuborPF
4KmEo0Gra3uxHq14AIB0l0WsadUmg3Tf3Rbi3kmhB8msJy3pWACvcvyPv9v2YG1zUMxI/fL1q/uU
fcUEEp7+MAaJB8p/hTtNkRmmQjg85uNChVQ1imDzyRq8w8mp1Ke5TKoa2k8S6KyFMfRFtACOXp9Y
OG+ejDu2ycSQe1wHNDmS3m4CvrZTYb/ivxGsqCvqVb8OxUcp/780nvJy/KAVFQ1NLbuJj5ne0OGO
BX9f3UQVzjCyuu8aCE6r4Jd3gbs3gnly0irwGOZXSFrXfVJFBuNkOaW8T2h2kf/UoNg2fMaSTBUR
mWhPwJh/hojDh21Yy6vqwlcv5xhbHEkJnFDge5Twgi66IBmNFxVt51tRQNkYCdOIFcCFwrBcKhz0
0cvYjnp6d0gzVN9LR55M+INHPQfXroNNEvPNw4xJPn1vn889k6TOSP+XhcQ2f6QNhVi1JxrjA1Hd
gqe5fDTeUMgmrWVnPETuuWzrlT1L8XONiB3+YgH+x1x3sLz6ivvtKgdO9Os2f6/nYgIN4LH/Nvtj
139xeWAPQu1txhhe8R4JHeuGebV7zlMAAIda9JAUceq94crzyOkds6X83tGovmY5FJiZ7h9uq9yT
LMTVcbxxb5Jvnn8btyfX5sFHp5vl/UpT4fvAmc687nbBnUZn7CJjzEbGi3yLdPkN0kACveWeGQUq
2iH4ubfH1SFLmQSFFz5/sPlkA+pa3VqBLEfSbPlOvF/SlwxjnWPDSrZp9F3aNfBYkbzaJHD4zun8
2g1rhwslT8GCQr7xo/dukSuH6J9eQFp2E2YGfHJvXj+lR7CU9PX+uvm+2jocpftUzzF0rK8UndGh
GD8Vi290fLsCgBZSFmNxq43Njum7RKsXqpXMTsQC0QO8TUdHpQF7mDTw7Amv8RO4kutWwmGjiBqx
LsRaL7+hNHixTBta8kNro2VO50iJD0jizX0TA62mdt7o8kGwHW7RecXIgA2wngJC5R4kxnHnEWDz
MjcTlfgoMr1ZNecwn5CvObQ/Yq83IN8CmDJQgLWlRyEgkIci4MUTTAVLqze9ikCS1DVmXIGPjR3y
ZkKYSE6h/cJc0lNbiDOYoBZ01aiY8KaRWp3sRczazvmMF0EEw+vBYhB2gt3mZhqM58bpuEPpFgYJ
nVOV9mp8u1I4V7TVplLZNw159/vUTLtJgnLDdEvxpnu5GHKCNrZULsXJycuJyzJx9tCYKwpNL9KA
4XyhU8hnnsDG2HiXC82QwLa9M+7HWXrTuUNYaiWik1Ame1a0G67k1JpyM2kd+i4/EK/9KvV8HWAy
KIt7mDtZiwYuIG2RyX6Tb00RpcuhizO5wh5v1aBuhyypJcFPDQLlL9m1d7s4v1gRw2iodCif1pvr
zXGdrjnOsD454zU6neM/YynRLKV5qG8MMX3fbm8nQXM8GqgiRcMuoFDLPq7lHmGqmKNFjhnI07x2
HtSSqhM8rde9l0kwoyex0l1nP+0Tw9BQ3UOl36cAO/7wlPgizyNEfqN//ZnLktvyyDfVbSAiJdtB
53iSTz9mJeEAYCVfQfzGix57/BzhNqguhhtKUcv0XZ4tJpa34zsXmEVwNGABNtf4n2j6b+XaG2wG
m1T/qmaUH1+vGgJ2BWGypLGw9+nIjbioDb+pTKrGwEErARavXFga4FxwDIidvuyvxQeekZQP9JaW
TJMj33AcguiXd9KZeUdoUKL2B6amg3h1zFUnPF7i3IL7bYvFnDsNy7s/w8YQvObfpZomms89c06A
uQ6XbVmEP7DakkeZnhb+yi7bmMe3K1RJtf1hmXS+bem/Qf3zfa010pMZOYwS5nLO+H/bTJpPJIh9
aJbGwledxTOJAGbMk9Tq0Bu1optAH67G5xsfhC8JFfxMzVcrWmR1+lScit1TVj4HdtJZKsMeaHyr
9Uq/EpJG85uDMiNyvd697NDbHvZtb8NbDAkyS5zM8c3jHwIYVDZHx3tVCpXZCh1WcXRFQFB4Ikc4
zJ7wpi3SdlzTUN8uyVqbUW3WlNPiAKAWdRvuFCqZN9yLolQbL1T5Qz4x6L+GYYte0O9GKtQ+3OXU
8T1y771CaoSSA1qB+EaQ4BrSB8iu49r6gIWwBh6EXELQG1mpYmlzsB7l2tnkHGDMq/cNX5LZIomv
Lg8P6lPT6cGw0Aa394wDV2PaIcPgvWXoegskJmoWliGvl9NVF0WnkY2mavC/10l9LnBC9jxKqp+X
9UfobTpqEbTMwo4oiZ+QkW6g/muxR+8nJOfETk5v2x5V0dCJHFZF+tFOtYks7/9EDDP4e5ivh84L
KKB03x2a+WV0D+ULD3PDL8Sjv4Ovdgh04D6zW/iD0nxkZNuu2vRFzZmY7yhEJVQijC9iNSSuiQQZ
mxmz5yBhcPCiPcKh+R/iDoey7CZw7GHtd81UxJjjlQ3tuwoMSEPRI5JnXjuZqo0GHBmMKCzHPtrK
KBuL+skZS3GMno4EIH7kAq300N5SfQj3TpKPckAd5EzC0t+5+MdCbpE5AlXsGxYj3v5HW/ecu6Pg
2CJvM5yxSjPH3Z/J7sag4NDrCT5/dXYZn1Uld54ea9lWKs4xxJuX82k3FOn7whTnDyeY2ERLRVWS
wE9E7jHWLXCgv6aVtM8REWrOaF9GBiytIVqsQg5odvKIGriSj2OXvX6UYtYwv11jgRye85qNVAq1
CkFZOkzRy61FGl9SiewnpPoyCD+EbpvJCfGWW+JGo/g6PTElAKA7poot6xCQabUtDPe1IscMhO0E
rGlZ2ifudtv1q81I5KRPcvlisMwUSfZx0sZOQ1x3xF/uxtvN26dKIhFY5E0p6X//iRXgXiSTD8+5
fj1Id3W5c6kyabNz5t0JoJ70M0zgaGz1khqsGzfo/JiI7G5jujKlrfWJCQGzyroQcW/eidhTPBx3
i9ST+7D1JlyTbyX1dLeqCs0aHu/T1JPT9CTrgM9Rg0GMqx9BuDr0b1BJGXOzhMLj2aRVLWLdy4Vl
+pU/sPQoyemJCLAB2gokPWIVIQWF9Zji6DBdpiDkNVZspwyuoRUSfLp/l8NLKfe4GD+xdx11Hvwm
sOupTXxyPTNOEoGGs2h7BFj7rQ9Ca+0tLM26IqSetolR2SoDR7/nz/wVAd3Z+fFdT1mAQmTQH37E
rurjR2ceR478lD8nVO5w529D7O1kQQdrnsUuJB/75cjq+yNAN7qnR8+rJRhR5imICWzvKPDGrCOw
EDfN7QQpz1deqLsVea4S5C0xhVq2o9VaU/3J3kOZPaehnIrl3TdomFdVJfriCobQoGoM52d6Yy8A
ZhSOrp7hoAulnuBf0L9H9Wi6F5DxSnbUFmZU2OAyd/8cmRz11fJJYJzFJKBt5vMoACp3HMU7PXwU
OAtXsdaazzzjuqdQvqyB4qvBl4UZsYdiyzF+xdIHmUWtzsQsEU1VymvANQTLU7S+oQ6P1aDP/bwe
DtKLL4RuHWRRHA63gc1glo5q0rfT4pLOsqWFtMfY/Lbvh4Hz8so0u/flIhg+gfma4jv4EPWuIZt5
MYU5LFeGpSa/s2S1QjgLZijv5LnTgpRNOVMV0kYq1HlQMfYDyXcVzy1zyREgbOaxLY+E7lxdGCm4
c7PDwN4bFxHmV7HnI0cnlfCO9pCLaE+SntovN3oT26HuVDa6YMKv/gW2+kSOWryvXVYhlFEcwXfB
JMIPRmT4WiJ+QtAyt5Pm5Wzari6CvBHhH8TavjyilqG90ekpP5/QAIeHSibwcppAde3sFRDWV7FC
A/wQVpT2Wbp4/AxZfAngDC08Op7TxierG2hjRrlwjryhLqNvQb17bGB1Kn6tf/xz
/Qc=
`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00655.vhd | 1 | 8201 | -- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (globally static) passed
-- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (dynamic) passed
-- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00655
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00655_1)
-- ENT00655(ARCH00655)
-- ENT00655_Test_Bench(ARCH00655_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00655_1 of E00000 is
--
constant r1 : integer := 1 ;
constant r2 : integer := 3 ;
constant c1 : integer := 2 ;
constant c2 : boolean := false ;
constant r3 : integer := 2 ;
constant r4 : integer := 2 ;
constant c3 : string := "a" ;
constant c4 : bit_vector := B"0110" ;
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
signal sinteger1, sinteger2, sinteger3 : integer range 1 to 3 ;
signal sbool1, sbool2, sbool3 : boolean ;
signal sstring1, sstring2, sstring3 : string ( cinteger1 to cinteger2 ) ;
signal toggle : boolean := false ;
begin
process
begin
sinteger1 <= c1 ;
sinteger2 <= c1 ;
sinteger3 <= c1 ;
sbool1 <= c2 ;
sbool2 <= c2 ;
sbool3 <= c2 ;
sstring1 <= c3 ;
sstring2 <= c3 ;
sstring3 <= c3 ;
toggle <= true ;
wait ;
end process ;
process (toggle)
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
if toggle = true then
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (locally static)" ,
vinteger1 = cinteger1 and cinteger1 = sinteger1
and sinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = sinteger2
and sinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger3 = sinteger3
and sinteger3 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = sbool1
and sbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = sbool2
and sbool2 = vbool3 and
vbool3 = cbool3 and cbool3 = sbool3
and sbool3 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = sstring1
and sstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = sstring2
and sstring2 = vstring3 and
vstring3 = cstring3 and cstring3 = sstring3
and sstring3 = vstring1
and vstring1 = c3 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
end if ;
end process ;
end ARCH00655_1 ;
--
entity ENT00655 is
generic ( r1 : integer := 1 ;
r2 : integer := 3 ;
c1 : integer := 2 ;
c2 : boolean := false ;
r3 : integer := 2 ;
r4 : integer := 2 ;
c3 : string := "a" ;
c4 : bit_vector := B"0110" ) ;
end ENT00655 ;
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00655 of ENT00655 is
--
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
signal sinteger1, sinteger2, sinteger3 : integer range 1 to 3 ;
signal sbool1, sbool2, sbool3 : boolean ;
signal sstring1, sstring2, sstring3 : string ( cinteger1 to cinteger2 ) ;
signal toggle : boolean := false ;
procedure p1 (
r1 : integer ;
r2 : integer ;
c1 : integer ;
c2 : boolean ;
r3 : integer ;
r4 : integer ;
c3 : string ;
c4 : bit_vector
) is
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (dynamic)" ,
vinteger1 = cinteger1 and cinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger2 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = vbool3 and
vbool3 = cbool3 and cbool2 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = vstring3 and
vstring3 = cstring3 and cstring2 = vstring1
and vinteger1 = c1 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
end p1 ;
begin
process
begin
sinteger1 <= c1 ;
sinteger2 <= c1 ;
sinteger3 <= c1 ;
sbool1 <= c2 ;
sbool2 <= c2 ;
sbool3 <= c2 ;
sstring1 <= c3 ;
sstring2 <= c3 ;
sstring3 <= c3 ;
toggle <= true ;
wait ;
end process ;
process (toggle)
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
if toggle = true then
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (globally static)" ,
vinteger1 = cinteger1 and cinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger2 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = vbool3 and
vbool3 = cbool3 and cbool2 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = vstring3 and
vstring3 = cstring3 and cstring2 = vstring1
and vinteger1 = c1 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
p1 ( 1, 3, 2, false, 2, 2, "a", B"0110" ) ;
end if ;
end process ;
end ARCH00655 ;
--
entity ENT00655_Test_Bench is
end ENT00655_Test_Bench ;
architecture ARCH00655_Test_Bench of ENT00655_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00655_1 ) ;
for CIS2 : UUT use entity WORK.ENT00655 ( ARCH00655 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00655_Test_Bench ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00174.vhd | 1 | 8695 | -- NEED RESULT: ARCH00174.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00174: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00174
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00174)
-- ENT00174_Test_Bench(ARCH00174_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00174 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00174" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00174 ;
--
entity ENT00174_Test_Bench is
end ENT00174_Test_Bench ;
--
architecture ARCH00174_Test_Bench of ENT00174_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00174 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00174_Test_Bench ;
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/input_block_fifo16_patch.vhd | 9 | 15036 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
a72d+j/QkZDkv8eDO5pA9BEngzdbQGQHhuxY2nDNAEhnIoRf0SgDQdLQUGAjqTT/LgQ/F0Cs+16w
c1P7TVYYIQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
l/1IXczTwKQBVElHEsh+Zvo7KblkXaJxo8UlygCcRw3ZY3tWBi5BiOQVA9yqXhof3R4G5ULkurKn
46GuEoIAY3OUXtbKoFE/fg9ET9kDVkPf1jISgRyi7rAeyld9i/Cbc18E0R0zSIcXYm0KkBSXRMxF
9wuwdCtkYN244/gGxpo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
l2DcCPLVR8IEoJU3RMy+SjLkstHNjHjhsTPyvJyG55CosrmHYPJF1hv5Q2QL/s+a8qVVv/FshWre
ZhgfOLKwFsPfAotMElv4nD87vdWuiTfoT02uJ3qo+dMgqdK1NTGcrQz44sHgvLPLWzKe7hlF6k6o
Rvf27QkEmCc2RIz/44tOQ/UppDCnrsrSVyntb+a+7BW1A9KnQCNSmFmxGUvHpVhP12cJTZtxVJbJ
Gqk5MrAj6sMn7uGnVNgQNANDDB+DZgaG/rX6HKpInZYt8BzBk6ItkozY9t3z7oLm8gSHD9yIsJBO
9AMq0Li5R/GGkBoyk8LpfwkWqntHfUWm0bnNZg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DjQz1cDtlzfTydRyrY+CZqTPGwZEHHaCGldw1iTUBh5QfXaAiR1uKl2S9PniOeC/cvZgRRDpmcaN
zNVXhjOeHU3dnRVJvgmKq3SSiJA7PuJ5iq48dVkI+PqLpzJqKub/4QXlIW2D3K0jO9cEZznt4pz4
zGK6KgjZ7aPbC7aR/LU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cCj1sFiXTorUE6cijFjReKgoLQpZZhe3m8TlSV9f5LlFUKu+l0WXSJg/leWTQZO2OtLniO0g6v1X
Q3rtBRwm8GhMcNcwV8oh3DFFtIhPAWIx8pc1IWS1flBcINGtXYVzaV9N47/Rfvj7bD/mJLL+3Y8M
w37oj3YyxkZJ4Qw01CkXNmjP9Jdaf9l8rl9mPrRqfpwkMT2Wu3jRZhr19CZISAVqAU1dUMwyXjha
uuLdqvOh9S6lQlkmMyjmEIKbqZUMj9jqGdqIEgihmrcRH4TEim8XRv6avaaNKbCDz4oCy/pt1FkK
6Op5z2R8h8lf36/aCuM+cJu5Sxegm18sIBuy1w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9392)
`protect data_block
VvIw3u4z644M9oCnXrN11AFyy7KcxZsZdyLbnBx3LqVMsNcmmsh1iowZ5ub3Cw5awQgWRQ7wnJ1Z
BFJWLXjtihrCL6nd2ENzmEtmUjzQroqjkhWIhGczCePlbDZGh+xle1VT1ImwLIHiJX2U7Vg1xQOz
rxEV+8WYJtP7X80ztNSsy8Z+wRQnNeNHz2UBN08bcEd8nr0bVgWmJNpOGVz6/MihqxlHNXdZuS35
iiiCwUClBpNi/pVXiEyw00gmNhN/pys+TsAZJ0hVVwH1tdgqXQPQ2q0mPdIjOhQ3CGb4FtveZq0C
d7qo04frJZMQ8OoaCLzu6EyWNQUjqAJUw8nPEMG39SHNyK7PRLdEEXg+AoLmHY9WaVGf/FgZppDK
cpwuLLRukVN7yyJkZ1Fgh+ixcPoaiKjebdS9mlZvXKyquMxa9EbvJllsgghk0KzVjfLD37ERzOJf
PMMFKyP1rRONhUl3Mf4K1AkEnlHOCnvyFAtC4QyQ05E9vVbM8lssPnZAr/Q565IavqgcrY2PMiWO
0ZKwMa0SYxeYyy7uKRpQDb1KOVFlMws2F15F6CTAloUWRCkKXDOoJO0SBh/+3j2wbUXuo5CVptD3
3CE07EcuAUYcMPIiPFY9roF4w7fDPbxtTbJBqvxREEudd64w4sUm3sES1SkRmrIi7CPLz+uFjDD4
NeFssnvqQFHxHcmYaNjzy8iWzpZD2iFoNZ49VKTFeSyDAJSRfUGfsFDNYwYezryThNx0z76hZ9iE
brpEMtwuYy4fVBgcJ6+aH0tdeOFAH5VirQ7QcLoz6QyCR54lLpuJeOBVuh47gZkuuxA4+73AlNId
fnOh0idbguclxHVzLsAMzCFhfnT11FlcIIyDrE9mWXj8O9YPM0RwpM5MIBlUv+GVV4ysOysyy1qF
ItOTnYFJLc/EzAyY+EkGY9XNRvFAGf7oZexCjVwPbYhbs4fLgSP/nxY7W9oIaX+qrjKD8JCbL8cD
D64ky7gssk1VxWSQjCrRxhcejYw6annUtLojDB0wcXseo7/XxOTBCOkFDxGl2U/EUYq2Yz3d1J5f
n417zhS7PfyHauWQoInrcMP4KRQpw0/L7Z2VA6dW/hP+Udnfr/z9gADglJtO9UfNF5cswhUJWT6M
Ye5ZhDFUxjGY50hciJqGLQnRGsOrAEYiqlfg2A5/G7hPhVht5oRFh57vNv0hkskWrbVqX9u5M2+l
EvhwbLktgYFLRaqoevI96gklToiO7MK7ML/O0xKR0x0WcNWXbxxiYiVWVJKDpDqBNbswQaqceRnw
+puj7OKCkNGrRFXNoIIsk/DZEXCmuqR/WWcFTU5pqsQdYFdgcCEXoWSVMdXFQlX/wTq6MR/08eqr
gByMfU6PjsTm68/P7E35DKerC/blX12tRARkYueL2WOHRG13rLwXJczEJXq6IAfgmyDCCK2X+LNX
nrvVHfn9YXP8k/VbQUddXxUQLVDteu4/zhd+CMk6MDP25N4kKP+Nog9UMYUw325D0jQcGDKlwJzv
g022IhaCQP0s4ApZb/heP+xgPFS8kxCpIVxbuKd8o3EaotsZAl/u9ZLQ2L34wCpj7OPuN6RiqXMT
8N4+ZvMdoSvjNsB2doffrv3wdFqrPaIXVPJQmDxTeLq4yHYVSbw/L3HE+8KmBdg/1/vazPyEnJQ7
/f+jKFWf+KjSg58K/3hzm3dzCoy07ImxveO8jEUGdgi4Q6nM/i0tqwnjeGU+JofpGMn7OPlLIXty
NJON3yzqTXwgiwvC+n71brGm+qBTAfRhaSq/+kOJDTPx9QHPL5YCztXaWrkyvzdzAsf7K0sTIT9N
Tvs3IEXhIX6T/848IqCj+MDQpL/UVNVt3lwOq9JxvaEyx7pOU9QOdIlXaSa/g3SdBB/OE9D0eV/L
Z2Szowo0HksKj+mCRpOykmfT9FkiPWaGqUx6akGQC2PagVlFDTiQhInp8OSWr7bNKPdKIfkXF+Nd
w3FyYWhvo9uNJle/FAr9aP4maR7ZFYyCw17BpRjR1O23C+IAcmbrpBgxn6+73a9nnnvN/TVYCVtM
4DBBnzpVLdp+GkEY9l6HSxBBxFoSVeGm5vwKG0o1RthKPoRYsWRqH0dany7GCT9XfLp+N9ZSwVLL
DbQuoR471RYcxMl7bglAhI2NUEOdl9kRfPYNffO/b+ga3bSGZ5eYzOJiIUKmYIma+s6bLKXvuqEk
ol/6uCGXDx//Up3DGB+cSbLWti2WR3ux2z6pt1JaAzvU/PJyN3+JsIBFqZWA0eUIckJeYbvruUiF
to4ScJOuwhHpNc84GtiUB/S1YShXMYaakQDJ1AduMQaWsg3ayh5LkRoeoSg0cJ4QLCef0l+ghfCo
/22Gr2/oJwb/wu9YTAMa1SppOK2z2L6xJAd8aiJqsT/XEtXYHZ245FPifP5zM83uYCeAsNyZpeIQ
wLE727z1YCIl6RtnIttA5hXTqNTcVWUVf4nc9k3mfBqu2SaqfdNUaCMZzB8ewkSNhLvIxy52UPtb
oT9/8J9yNwkl+Q8wOBivRj7WJQIe+qVq3XVeoda8ja4BYpzLmGjz4Uj+Gx7Y84+Yr5nHLaLC0I4M
fzhKgMOJJptowhnXroSskYF+LuYHefJdJt2O3XjObVo/FUOwMPKrwHuaOr8ge8f57lcgxue+oc11
Z44qy+5s6NNJsKzo9xp2Z8CisYzvWPmj9eVqmADF6mR7YAkgS3poHJjXf51NRwtKk8fGbHrpZDA2
nJZP7eldtKw3Sq4d1hKlm9HmEdf0nUgq/sYgUYSsqFoy8EsiLZi/gylnsFRGgKAPyYD+jUASNUAb
go95eu7YOq+PYVV4fpenUsh9VG4wnPrR6QbEco5O03Bmkk7nh7hyJbydRtcEUCRUcrpafh7+JWOW
bx/jAVIqgx8lePe7aPhWTivdXv3aR2OiUQIzi2mYlwHtufp1Q5yqtozMcmMuA5UtpdXy11NqGtLh
fw6ojztUOszKeb3km6lv7DO/UlQ658dL+25fsB8f0SVH93XqawREwAwQ+Y9Q8547SAVRMRmRIq9G
lSejmC85f/CQhUpyMiPvHt0alea1RzEic1Z4UeS3HCDTp0yIX3yxnGwz8Fsv8cHeV11bavAo55lx
MeXH/tKGHEDL9KLEvPV1+zLLXY0Xd9NqHdnW95e4+gnmYWPWqHbIDtAgq6a1luU8bKCFGj9UYZ1z
BMyXBGz5jHW19rRIPSr92tjNbc+RHGJAu/ZO2TdDX7Blb8OvAt4nbXGD9qojkZkUjV5vF6+RSBQG
qWk7RgIGsgfnT4HYWYtHkxhpM/ZHgiPrfzg85ZQwTUqEEo24pxcHEhUBEXiQphfgilE56FKaDk0y
X41mZraWVnfpSYYJLwfScx+mDSC4zKxA9Q3sp/pXVplnN81R3+5rp7H4GgofIu+0DbIdeAFhC7In
xXOHlok2y9IVD6QnxZhVnX9EfV/AhB+4QQvwwSdlZR5BtitKeDilmRmX56ESHDOcJUCkVe5srkqw
J+gPKG0Q+24zbyPjzKrJWOWYPV3Woyue4bWlHZmbrrwueleTzIjUmILjd84SQ/JqT0YElyMRwcvO
kPrnGVXd9L9c3f8amVPK6a3BmHm7SCZuTcgfO9N3tiEjirNGIubrcyIGZ7WeVUZRGrUJY+jMJwz0
L8XFj2JsWAJyNZoxSQItptiSMK2z8oas49B/iejdGoBoheX+92eF6SNqcbZbfMPvM+jS04oBOK76
xmofg7tbGwySq/hhHBtzYLalCrPNebWgw5MAGSax9fLeqK33qbiAxTVOvmkrO6KT0jpUR39empi1
LWVXTHOvdC+PireT0gdL1MkFnZgWK/W1+t+OhiOOUP9Muqa5PhcZThLOerhn+WHzcufwKLtVPvbM
Ba2JJSUYhK2M2XcimPd2PE/rFyC/DZE10CIVFrlmAqCtFLu/slV9Q0AEU8huTpA2nl0OukyQoVaw
NvknUHtieKYpQzpPmsb9y3t8aH2667aBcAdSjOEhlOV9PduYzFpHNvJDFthC+Blxmjr0x8apFZbo
bYtEylkIYptj++xtiJH+wRvyE/w9nsHNBvFkk7+Q4oQ9Oj8GkMlD8miKCb2nF7HzBhcYEMGv+j4W
2M7dAxndHjqGtQii3U0B7Jmvq4VshtMy+iO2c31MXwEk09CmLNGNR4texRmMCYsx6l+zjAm1QKUk
6hdwzt35PrMXQBPUOCdt7J7du5uNewxBsWlxy13tC90atHtMdMdqt3JIerNbMnTPyZyhlQbHfZ/z
vpWUoTJmn8zGlpjP/HqK/KDoG1Swke1f5b9+eZ+Q/5zCiwwgCQi/Ab1qTBjQdDdSDasiWdC5zI4A
uj8MYDTRVUmISipvxHO190BvcvYY+HfirIIUfSZ0hS4hBlTawWO5GPnoIwztTUjXidRZLhXmBgJp
vyDzZwlXeDbde3ygZALtnXX6N7NBf6BWWdQ/jhDQqEerWbzkUgxQdLCzccJ7E0Fi9FbSZdR23jXV
nZJLpbLEbcvZEO7XoaBVmnz0vY7Vbwv4UpBPnWQToarGEHMemQtePCPnxD0c/iJD+yAZC1OUoxdi
QrSrXfVjS68vTGop7nTQ9vb5UeL36GWar8DH/SAPiK8Mw3Um0QKqNDuQ20TlXRA80xTZCEZFI6K1
Ll7mVKCE1ox9POXno9cUQ3UxWsqt9CkL4JkvXnL424iPEQ5v+M6XKL8SZDreafO/UGT9gD29oCWf
y8PYTaoo9V9RikY6sBHb5tEpAzmkWWr797K0EgFp2LBQMGoobCj6mpMx5FOuSypa7+T/fmo1avdS
FeeOS3MQjOEOgNVl56qVIFBRdiIQRCV5poFgaNlAnjh2aF74RLwmMXzvfAqOvGFta3YeNJIfgBfA
ThExU83rqXqicT7/H422DzJzJ1og/9M7xPSMeve73oPiOHZkoEcRhaCk439AuOY7pavF9ZJ8piwI
UPkHRxtyzKEONig+qLFa7mLBrHJfINsaSFygQVMMxpL5MAJuyAYUTGGhKVb7GvJ9RHWURtV42LjX
qp5QfFy+p4cl/jz69PG7Xs7+ztJSIjDjqTBpjuXIHBZllG2u20GasKMuymLqtTVKpx1vqOVrRzLA
rnDSVSXjDm0xwdWI46UOMwFz3aC9OEHxoPl6un44lkWt2XBYw9Ye+tly0YLaKHixc0U4XZHiTraa
HnLk3OE5eB00/q+hie14wTEDrT0ksEmDZi+Z0kTQIP5dkbjmBvj5iYdfhN/IEMfFUVg+81rtm6ml
a4q+MvUPjvR11JcFb5iX6Ckc07vHAf4LVMHMRxvDFNckeX1WCOgE893ipuZDrq06wluDLnMnDIm1
JwElJUR2w1jp81Jlg5qeYjZHWgPxDNeSmuF60eeFHzOPs8Zve8zWre7UeSilPY6bz4fq0KrUC2Lc
/d+wHupiZIRIr7auw53cyAxAjQnmA0PNxSLAz3UuAMFb7E1gLVNnoXvO+5Ln3nSdL8m1EBW6+1gI
86MjQPAGLlHPk4TBJkbbCbCZnDEAk7LiJrdbqSE4dQBEjozl+9Rjiud5D8LS3Hn3ISOLbjxTX7RF
zhOghuLjBDtwR7AlqlsMfj6q3I0eE3lYcXEA12lJdF+BKqL3CJx+h0iIdTutIp9XXWO0PDiWhT0u
CwaAPzC60vnn+/r3KoqFwGAGxbB2sgwhskeKDyh3sdXxTOdoP6B9Ljc4pEFBEjFO3afgquugWxQw
7uAYG67zo+DqYVFOX78aTgr+3t2LO0ptV7v1WvscURi+4+R0eR+C48pZ/GJD+hj+thzj31Tv6ynJ
Oev2RyyBG0GweZCZ3LWANiZ+ZR2AGQf8ImAxaFu7mJh3RFsdw97WzXFUWJ6jSs/7dF/tVjtm3EdV
iy6LRc5hGeFlExe2llFL0d0ugh2EAS5LzJJXDBebO5wlETdXDywAIVJ2ZUJIlUtqanypIiqNWmbA
VTq//dBKdUQFY8P2xS9zAW1DvDlwlvF2ceaMVfolbec7hLpOoato8bTn+o6miDkI44WiLlY+DtX6
Rg4AbVvayCLqF3K5woGGb+TAAxgPDsnTpYtHxy0kERwYGeCpthnZW0oqYaLP5PnqGrEXIGJp3ysr
vkSUx79bxPZ3E21wiw1G3mmX+f/3KhZXL0ZXyBq+bdJmxBNE+LNLes9XlQe5Z9Vtj0sk2UmPENe5
pOzQHwNMV1ONhQ+r8M3licVa7ycdGEdFIz0JHkDQnLOg7kodNckmeM34gDfqZkUPqEFDRhVPEP+9
YN7eCq5GmviIivi7r2pQoiqAFc1VMCJsYNzxnSAV5TvjW2WhkXRRJCt5If2vfMi1tfG240ke5hiQ
Gb2gtubhfgnwLHmJsLXvKYwjCqSChG12m6JV9RnlRhA7DQ8yb438qsMqLK105PHomVUGrb95XfVK
jQ4mdcRNvvrvcuhDxTodsHEDaLBF6PiJ25Dv5cDWFEIuwesOP+hGAKUIrlG0TCofj+S+D93M2i+Q
ihgzVzN1DLEbrKxNeEBkQqI11GB5GXhOY+UAM7sv+NdJLL4UBErBYBveFmwucME90FuuAWrdS23i
/PCHpqq0KIlY3/kUv9lPmMGPhh9tR7AvVKEpFmxud+ohm4dyG0a7T85muelDly9HoQwid/EMCYc4
sdvEbarUC1IUzG+6NRR3ZnV1fy5gJbp8xw46v27lQZCjAdGm/GfGobpaN9acCut7kz0UkXaZhZzT
1PqomSDbjZNNA2Z/89B+Wdy7gLumWxc4cllUno/SfNJZOoduvEXz+7A5mXgmgSyb32EaA9ggUfdA
PvseAU96yG4XFpf6Y97j+BXnwszbS/TkplK8+M1PGGVsnumH/0xDi8gUY2T85oGfMSqkjaewzHn/
YZXYoOdwX6qFZMaA2huT35EGNQwUwkOgpfe05su43jrLznlhUq9oIWUwipfJADUJ555gvG8smHci
gopG9nfB2atVa3rpMWdX46wVoiEZh0bb2r1C0bK46CXCe7xfaIbN26smsErrUSD3w0aTJOuk9dRw
W+c4MN2HxSuWu/d4Mrqv6V7UqZdv3dYCeqPTPn0rn1OG/fMhGXpWkkhHu8DnJ6N++dbRb60thDUB
kX7UEeADj+W2PI4MC/hX7qg139Fi5h0F1r09z3SLSjEHtp60ykJ8D9sWXsY1NTHhvx8eZvDRWVk0
kFHXP4O0OOZvl4ee5f/ymeNEXubbKPq5amDIhzXXuVRH7xBoubZ8gJjVb5wn39sbOOwsD69r7f0R
eEUPPyRVPEH9VtGSC4MznJZQgpTHoPA9PAJJtQMxzaSvGGy81q4EAO8vWagVQBk+YcdSO+KwdfGb
CHJ+hCJExMlwLs+e66B/Q0Vmv3WG2tWkfzqfU/C0SxgOaQ0OsXoJ1vnteilPLDx85Nzr62x5X0DI
+b+NCcKVbhbDI0sg2g4tf2emiTcbxqxDr1Qf/i+giYb3al2Jj5kil1ppjzY9tNXtEFWliDGJ1bNM
T6HirUcxwbtCFhqTSQhSXVnbddi2Fu/DsBnlf+uDQrvm3Mj7EQRubWj2RudEGp497pnoughGvH1m
7oUb6LfX0SS0x12euXhAbzkkcfS+caHcSSj38Mb+HUNqlS/+VyunTNHqTVt3zQ7zDZBH7jhuEa8V
ZiFGq96daS5LNPntj1YsLszVPUdHkzbq3YdTYySGYJzT+giY195ubT2XireW7t5D4okfSIM6UcFK
0/X4azuvzemVGw+AkHWaULNWKOqYPwGXtNr/wV5DBEhFoWEvHXX1ACuRigPS/CM1Zu1whnj7FESe
tWpMN72oAHpXJktbjj8zNuRNjz2kLdFMpQHk0t8Ttu6PjhE/0gaHotIv/SkXE3kRGAnNqhrmsdNf
92I7jy+se7NH6XjejCR49eiwQ0OtYoU5tiqDwrrXKfTBovS0zwVV+IZbryFXmL931VnMccwNGUZX
DngyxxXYSDV3x8mxTdSGhzBlEsa4jiyxCaQQE7KMRsWPL4Yu/qVob6LatbHxhZowmJV538SmmqRy
8g/oDuEIA4OrxbpjArjLxR6XdJGG9ji8K3po8F2AfwjiMycCZemIhlUdfl9uOuXx9kxb9YxZi0b8
GJZE0S6M0mricYu9LoQ/G1X0DtWdJjjmO1i0Kd3WjbTLyRYMoFq7roAAbSnPTxxp7vWx2w6eOS+i
XKvOrPEJEiFSYHqwidlxvnP4F4ZZ3NDuTsC46FlHV7Wnm1o7LeI5s4XfTuzpZCO3MVMc5cnOZKZm
bBb6DnbE+eUWbXqD0d1+twTJPgXURkf4TU0tvwrFmmTwkN8PF3cyzN9O0jSBGfijoRvjZfdFJ+Ni
CBynYLYZpiEWu4oSuYjHhiL3oRYMEdQSRFT9pOPeLp2yDbiO6nAptRph3NpxUMNLDWetUDW5wgks
w0ECOY2/6nkRmazytMG1Ab8cerz4fzvMYfq26azHwXIntIXIL/d8d+Md/EfUo2vv+0uU79sOmQCC
j5WeTMYmiCirZMnZEuV9VpVwjrusuuh7SnGotzX5waGiDC2k9zV6283HuN4MDHGzjc4zI7ZZRnVy
etRhwUJF0SO4LPAnUjuJVDA97Cm6qP4rAwOAht5aNwGYW8+srEyDsuzrlR+XdJVx6ffSo5UOJVr4
a0uv5u8VQdzE5pZpxWv2KM85YL4rGgROXNfLcPMCo7v2yfe4e76Ct3xfxMJjGtN4OPduhGlXgyqh
XZ+HBW0xjbAoIUf1srtFlZLEu7rgJhV3+uBDjHVlzm/JPBUWPcX5LcACbZPGisRfS5GHjBA0cHTa
BU7a9WaxjQ+3aeIp934wsjY6JRWP0mimVTQhZGGK/DIv9YzSh8iGfUwdoNFv3QGMuKbOEGIpbJT7
hSj7HPKLByx8ru09dMDgbSXbeGudHVoZqaTtpeIrq39hDZwlNIlj7QNVm687RqfDfb1yF+1VHw8c
B0jnmn49lGUrx0lXcZQf88aVhpinLQ419gLzD+ETsOJ8O0mDuflQ+cyhaOcn69JNAA039ic76H1r
RxZTsrv+0wKLag6vynjuDrxes5WX416O76rC1mNNfjFtXCmd2FcC15fFIW2//WwgL56dI2AhpMkd
+iwidtdFtNrIeaCZuLKaqsr3v6rkHjJCyrqMsl+7piWvwYil9d3kvKzZgY9MK4tyHHlhZTG4AFyR
lVMVSK6aefVWR/WO2OVUTD3D078SU5XiWe4M0NG/QN2hTIDPjicYvrqoFfVf/zTW4hc57Jk83TLx
oSSITqLBSnLIV3viCot/rehmwLXd0sSXHWSnvxMdAZ5tVA6GmkFzmzLUCJHl/Ip8l4KhtW9mjFJi
EsojqB9PgHUdHpZCdhHWLncA1+f62+5SGD+o+La/c1LEGxnF30IervNyV0FrUFvmacTvy8hDVCic
V9jhVMQvPWjC+BGcoHhIDQHSI9ITqzsc97YTH6WB4Jm/b6GQ3xGI7V8Ro1k6efc1hpZEDJyjG6fH
RqSbb7T5WGmmVbN3jtbZTGaGinDfXy2RH8UmGgVOavk6GmqUfb4gUH7/PFYPoE7F8N9eE5hBZ6mJ
KZEn+O2/fZTZxA/RBNd5VrC7Gy9aZF/QqMtQjmw2Auiy+dtaxSnHQwyxVsslvlIQixMR+zTKbTmv
+/i6SsGM2AficHCT4EkYQSoJXyklSMHZ6qdcHY+B8gMeUqPCRRt5kJb3eTq8X9Okn4rK/GL3+L52
B8Jp7T6AciqkIZbfvSGX2YADvXOmlT1QngiOoXxB9U18gS96hDI13HPTkz0NjVegFXE21ekt5/CN
JiWkyFYoIelUifMJRJMLAY4oZpFVCR1GhI58djq2GjgNKUCBGtUijujDhgs2SgUJlZKfVlEZmqu7
ubcmGn/W5HKXvIlpJaEDSQqmYrNLMUidwqEEGVufGwlaFErSTFyDvVNpD6lUvmPkD9nnpyYukUEN
BwimUcjhNpKA4IhBKGawMvNFpeAzpBq2DCpr7t5NN1SCSqv0QzyhvLnZOAAltJTHruoFqYC5+Nky
scgVMOBUzcoRqbOXycFg8vyUF0tevLiZkIFq1vQ/hdSoYYwBOMJ4H2Md2+hVUYhPRM8K2rtBaOcA
fJ+kEo3jwRy5+QN0HuwGHaWiEqkdPzIk3tLlYZM6lVejZP0egS0VOUwaS6p17WgT/pYx8Tty12Ge
2JKaRTKFXkXdmWP6jsrC97BlS87HAjugQJEiGcJnF8JcuxunzscP4XRiv1gPvL10pmX1rjorPPnk
As/zoRNW6bv5Y9GdUZFwExkeHzKEY1axFGE8Zbxme4oky5n4ciJ1CDOTEieUUW+tu/W2QCh7ysLi
cl1rFOQxnU2a3h2xV9Kvoy+ENwCR/+jsyKzzdC9psKduoMWhnPxVT2T7QKz+Ie2yJft3PYfhvFHU
jjisZwgJ7GCUbfZvX4WPDpv+wQKJGhHY4y6O/CIZFW+ayZ2ROmTMwJM43tAkT9wr5bxE1usKf4Tz
gaBgs4QDKq7NfBQQ9F2hzPNOZe+zo4Kc16FYjVcW8F+sVCmw5z5YLiN7sMKSI/sJFT3X4MuQt6By
NmBdoNxMjhnJAS4+ffCdp+BlMPC1gQyV4hDFxIy5P80pIguijvHQS2ZRiWt0K+DLuZ3Eo8CjCFgN
AcslcZySg2ZwhP9hD5a6RjBDCNJAzOXMiRoKDlbj+UfqTeFO6jgDGzH71sQT0hBHiPbUe3v7yvey
r43PG38FzbRw4W4A+lKxp5gJKudojjqsJ4bq+4PTw/EPr1gkPyjKfbL6BnvXvYi0GXnt33Chl35I
z8SBhB6btAiIBd6tHaOdR8HBHwdQQE2b2Kw3kxwKXVTOHzcMjr1aKL/fde7C3bqbpiG59yQIJDny
rXJkbZumDQAwHHEfyuAsl9/H98Qky0xjuN4WOEA59fECCdQ1AtVMX8OmEtKsbSvVG1/6WGPsB0hI
LQOG6t1+hV+hSIjE0LyvqelXCDAuBZm4P2Gq832AKTpxsnuPAX7eAezsolFJIf1ZkxaO+RwEiici
kYnJfoh4o5uLjtdJ4dOdbwcSNdOh5ledvo1rydnRQifgS8dg18bGah9uWehNkjpkCENTdUhWMj9a
XSP2nZJ5iLFqyLNNjnq6wPyQsy6eIXFt04XmPWcm9+l7VhhEUTvmX5yHwokMFzyjf4KErstg//3t
ejxNCwotBVE9RNDBXtBNji/1XfqrQDhXgcFJZA6ySgA6SGqp3MVTUprVQt4t19yutWr8ZvK9wuPm
7WHASVKWmLconviyQy0BKr8vYn6sOGpj/ulYJ4TT3Cfb/E58WJlDPFU4BjJioL7JZ6QKqfzIJGva
bgNKIeiLW6F3uuI6xGKpMcCoIjkTBnRwEpU6GfI7U2aFed2Z8tjZ3IDnDPfjeBwCtMKijw62ybFB
EIhYX73F/90UE9atCyaoaOcfzL0PDNEmjcAi7KbxU0Cr071P8/pKswE0AcGyI+Ls9wbLAl7w7NvL
D3fg9gLIBbZTGRD55gIWOHZoULZFD5LEVgYJnhnRE+zILf10wa8prKuRzRCbuzNSmm9Vs38lmztd
5QUT3fLnAYjgJLoxw3UtuxskAnVFbUS67Cc+tHyVnlsbyWUWw3QQHvlsT49E5Lb6B8D5QpetJixn
+wTs1HQmOZUP2W1js8uRUqPwuHmEgreF8RvYCb8dp1SAH0ryWl35MhFBzcCfLjc2ApSqwlxPapLM
nqLfV0bC5b5D6R5g+19xX3DeFs/xik3+H9CpIDu9BsMmCLqLRRGHXAWRZcHeyX/hpfFTe9O3QGUV
KzBi9nfhCTrJ1AW7hyGcxTzBosCr17rHcbpVZTB5+jdP9JYCI5D81PDtbYKgFSPDzqp2IV5vB6ds
U3wGO1rkJhYn5wHZRXyfbyRpGXOfRzWSGR39GuWexRDEQIBWj/Mtix4GlblCQUwjXfBjVlbBhrrE
yWteWravr6YEhPTJ1kDux1NTsEaEZbZPj4+NigrqXFwah9Ah/xjEVUMZm10R00zTpbJ6OG5QThRu
sUIt+krru/SDIokLGGJhHbpuaeA3gzdMV2wSa24YSU57kfYoZkcjJtrFkyk3Z32++8M1rXL2vOy8
k+ImH+cAfXDteqklwkqlQ4XfDmxEmKfv5sysafvCodzu97resoNNTxOG6rcN+8s2pUUU5plTEGVR
T07o3NCJCddcyKpJZRFrruM1YyG1yTtWoaxnngV8iM7hu+B9LNEj0aDm03gT5sraKZjEfWDoJv6d
7hT3Eq+NisqnSn/C95FlfIMda7wY2kLKrcM5re8n3QaSCfTQ71L64N3i0UkTuMC7I2y+mU/wgr0A
93V89ydO71QHjjZIKvXOPxcP9F1DyUq/FBLb+gOlr17C+RGQlUGg3kEzIr9XJTpkNVRPwNmkfJjJ
t6V3S+hsu4aMbITmq/cCa7q0L+hkyUfmW+HtwOG1pDR+uaIICtcs/Yh9JkeNJsCE0IkTCZPdrYK0
+lcmlLD9iajgelJeR8oKU3xA2dHcphdXcapPhY1dRi6GvcgADcPkkAw7uzGb5iG3HgcPlnx9kyJl
6bQTYIQIPE4BnwljpcRwpAQ9bbnMgSMvYvtoxHV9so5vgdmelIR5YREhWWM=
`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00015.vhd | 1 | 4991 | -- NEED RESULT: ARCH00015: Associated scalar generics with globally static subtype passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00015
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (2)
-- 1.1.1.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00015)
-- ENT00015_Test_Bench(ARCH00015_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00015 of GENERIC_STANDARD_TYPES is
begin
L1 :
block
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
generic map (
c_boolean_2, c_boolean_2,
c_bit_2, c_bit_2,
c_severity_level_2, c_severity_level_2,
c_character_2, c_character_2,
c_t_enum1_2, c_t_enum1_2,
c_st_enum1_2, c_st_enum1_2,
c_integer_2, c_integer_2,
c_t_int1_2, c_t_int1_2,
c_st_int1_2, c_st_int1_2,
c_time_2, c_time_2,
c_t_phys1_2, c_t_phys1_2,
c_st_phys1_2, c_st_phys1_2,
c_real_2, c_real_2,
c_t_real1_2, c_t_real1_2,
c_st_real1_2, c_st_real1_2
) ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
test_report ( "ARCH00015" ,
"Associated scalar generics with globally static subtype" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00015 ;
--
entity ENT00015_Test_Bench is
end ENT00015_Test_Bench ;
architecture ARCH00015_Test_Bench of ENT00015_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00015 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00015_Test_Bench ;
--
| gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top.vhd | 9 | 40066 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
N69BdjVBL3zr447/IslHpcQt6uxnKlEGffBeT6O/HPhIhs63hO+yBTBpbZe83b9oQQkb3iO1iekX
AN7IS+Oj8A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Q2gSgSjShBThnpN7ocpVeIiupKozmKwVJ1Ka9owDuAS9y4GGTKN6eXAv6ND3rH3bK2m5rmiGc2dQ
GqvMSafR3R5aQyLhHV0vE9ItdvwRv/PiR6RGhNqN3zMe7lJ+6AH2FuJN2tV2YbHEWsMpvrS/ozM1
eW8vym4p2Nmkhc0/Q74=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rgf/hTKzUgzPmpRNjQkGUhm/PJt/6MCtp6g+tuGzA135di4HysJDD1buAgwquHID3E9k4d3QtgNV
jT7ynZQIoMsXOeKCy7IbT7749cprpDjO1OSVrXQIUUcP3F+gMYUpeL/mjQnfdCEN743AXdvxRnDc
gVeJsjU9N64MxSJjbMUJmaddW7RRGip+wgYF1dVschvt86zUuMsTTbRlWaGT8/PVkqEVuyGg73ia
FsMYBM8Oi9K0SgUyaUoQqHE7F5kjUaDy36Xg4c9dGuC4pkwoUfWUCMZPrgk/nygkA36gY8gDvz6U
20GmRwirRv5LPFdEu9omr/mfCV1tJE3cL2wf2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
whJ+Mq4deBZDhR4gHJnHCL7JxuEJqNFrWBV6Ksnrye5rfDk+zUSuuj6k9MLoJRMZ9NpZeM9BbEn/
lx4N2zpT3HX4I7gsrzePK4hxagplucoM920UdfcilS8ZUjm0BM3SKRCGqgigpDbBNz1MyRAauRR2
TGMcoxB5Ne7BWv0iUBs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZsJUyEeEG26LW0tiqAAVmbPXGV42PcJw5qTIOROOgw6cXXLb+KKUvI0qo0WOH27D2IG2UjbZ7zpK
8frckgj+Ei6f1HtE74Q6zFaEuZsJ5XO7FGsTfepBz2OcwZ2tArvysAeDtRyFjKM04fsTIg4zCndt
4Vdzk9lAcb45wumS3BULfbRVGBM9rMHjGQgaLzK9mgTtjibUERm67lPM3rx4Sli2JlzzgXGzw4cK
3Pr3iYBz4/HwqPFPp/u4PgTZaWGmrGjaG+cGYqnmk1B2xC16prjJLhkisxGz7rsLaUay+Y9Qtah2
0cQFnUESovN+P8/1qwaKLu4FVsSMVNnVAlt63g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 27920)
`protect data_block
oUSJIenzMgR4/U5g+t0OV9b2YzRljk+3vTKsVmP/tjyeDBM/ad42F+YNEodlggZdHX4Uv/M2JDnX
F2Bh7bgipZFJXIBYgIbFzF+CYRIfBn195Mur30OM3bc9K2TZSqS23UiRqfv1EprYZe5PFr99TMIu
K3wlq3slmtPtuNGDxh8MIdZXbXSWWC6Qo6DIF9Y+jzxVZda0AhojaG3I0FHVGMyhk3bMbzvvMF+p
V9A8JHk5PIvvMCmMJ7BjSRz3Xp7qLx9dM7lFM4W4WlHlKAH9mPMFlrjcbjo4j0iQ6WaA1k9i4O6g
uL5tY6I/9Mr3RJuHCOvXOfdLT3aw2OdlbZ7aIqq+i16S7m1mvfWseFPy1exlEdhbh0QPzc+xsbic
A19eio1NUsGNUGcqfGiQRGpScFomvtfYsV+riUorPxwf9+xBaw/Fvyxuqb4Qm1qkJAl9g3xCbtZO
oPYqKV8mIKcUuTctDjSz6WHNX0Fi9ZHCrt2bnNVPH3fJzAa2u+QoRvebrnzpKVvR3z3eVtN2epCG
c1aFNiOhI77bMav5qlA8mJ8SJJB/r8AtIRPasi5t643Ypw8ejBb1LN1LnDENUP2tFrc1r0eIlA6y
XQjP+8wr5r/1BmsIrWwICOIkjxUICe1tNTwP2aa2YB9azPrG8INODj/XNeU6kcgBuFYJR3Ku9vCW
hDqCM077hhDT6Jw+X2dPC6F+Pv6ARhHcFRRC9nxu0JpVHPuhcnTARvCG5Z1SJPYekPHoc5dv32py
Ur5w9npZhvBOw4/QCloCLLCiJEAl0iCRFm0Tdz4US226nLjvMp/YKt6qQH6zdWQ9oqtcYWwGs/5L
VnXG7xMDtLz7CafNLAHqGM132lsGcueDH5fEzSrZwEGNkHbLEBpBmNCVwryOgFRDCW2fqWrNr0A1
Osb7EDkXvg2OaHOF+Cdv5VN1oEHYkOhDsIKfRtzyWgO8WUiyNhHpAbPXtCArwkoL4FmcY1hFAz2g
s3h4JZocLMppbqal6/Rk6YjvrxaZJYAZT4oSeJdUjR3hBinQJ9YzYlZ9bp9bWQp7fE65K9L4qnBi
CR3PqeQmks6hmtpC0CbcuTcjs2/oDqrMZ+avAALZ6U1Svw0Gm00xLlF4p7BlTdXE8HZH/4NsSSP7
8AWOnjnEHwlZf1OEEetUDSfxWmFylSzIbqmdGIE9xI6v6V0NzSGraJiepSHX1zaMdEd3X+3r38n5
XNWjxxh4wotPfVRuL2/6wbQ6YSjwArIgJTkfbU8JKg95uytqIT3xpqB6+4GoA58gzgXZ0qvuezqb
iSF9FYXAEYVGY/86JvltODA/Lo9uq0q8Ad/XZY34rnZys2C36KRAlraoiAN+v0hAVhwqKhKuz1ll
Nl0jEIPh4iU9rB+npZPlrZsqqgViIvc/vPdUCW75ZPDBz7NnOPWYgGJ3AoCwwVNDw5CmF6ing1Wa
jHJrhXdD/EN3pZVL+oBDrwD67QJ9eETq1KO+vAq9HbBQkCcxqOqI6NieFHk9RnaIZxDqn8RdTmaH
5Mv0crhxCxUYhuisW4QtIXgHx6J9UiV1z/6yQvQkJ2ksuwZGiN2vbzk6WXbNvBXex6B+pMn7wkoI
69hlJNy4Rmj92qxFhaeymjbBTDzTmsN4sM9OD4W0qpvsJV2MEYnvwn8Kq+JAJZygAKJlA7KyLiD6
XHwp+kyWuGgXjt6cUGxutWi+vyNrdZGhOsNYTR1Zzp7BifaWZVLPvN+x5+gEUvQIKcXyp5m2rlLj
X3Zce6d44129LbzVijWnfBWibpuytW4vNdxpmHkwnlEvGRY6+NT1fujpIj0QzVU1IeGOqBVIv8CU
/p5/fcIlho3td1ydWgnyf1aAcFRJ98DgQC0+QR7PobeVlDEGSpSmbenRBqIzL1FXtO1R27eJTkwl
WaA6gyTntGM5ZG0Lfn/GGABCaIrwxADNvCElxiYlY/uW3wAYGawAV9NOHmUb2xeC9bH8R1a42EHX
PXSUoJjZMyTZUDh9OQ9MLOELvdxAfsAOcKorPmLC2hKmy/qaKQekgPRuMHCXSDNgcfAhVayFUgun
5OOWh8Rm5D6XjQZuV4jC13M5giDDOJY0lz3dbbe5hgOYwKKhhxPfn0x605RzuXSIXUr7ii8iOv5u
wXVVA/pkfbmgAMJwd8zKeyJY2EeSTNTyDFIw2ZKTJOu6Ija3UxGv5Edon1U2Qex9pHqn05zz1M8O
eB5W8ISWQHX7/9PBNhMBYb683izyfATGF0TRpwjAnVg0ulYUekjGNq+uT2+43zXbCOhRR6OYFb2h
MGxO+LYdRyDwrFAZ3AIzQN0i2xl1Gea7m/9Yg3bIgkiCLbLXevEswynzdTW6mSstwrUY7I5bnGVC
kMHk7LJCH+pQpYXH8knc8biwuH0HLIgiINQxuKKAScIMcn9HQZTjhRXQ7Ygl7SAEy1Vzlb9dVsCR
cyvDyifCVmOh64OV1Oy06/1O0B3rhwxYal15LAsgFDiZ6Ealv5i49FseagSCIQBBht2mnOSTIWiS
4wc6m77G1dFYLtVyC9t3RP629zMxa5o4deOi1aKFlKbDeFGPr48J7cJW/oYl5pEREgt+8UDaCPAe
adwF6Qs/NkISAUKvsSgET2ZhXRNMqFtrcD+JbzUequsIJ8bnZv+IbxyJRXTKJ1vu/ldUDB7dDs50
K/h4rcRaqQ8cluDv8iGnbX6ECMwafwtlnHN+5P2oGLqn13nBEbZtEto2ncQ28ZlTxzJQwgA94BUU
cCQfzyZN2na4ooJRZUSZddl4HdL/RzzQNpqx0GUPdy7BGxSjdL0Yq/F41H0GycCdL+UgcdUWSeZl
yu+GY6Lco2TEfIjRgm4X5q6EuEranUumNkaCidHVgYhKItj6SpI7ybljgw31gbgB1cZP4+6cSkUp
hnFcBEFO+ubUsG3HaXKTFNgRdCdCLRCuYjgPpGSckeys1qIg7XsO/7EL7gJIolIFb6ehaGcEBL6I
CUfozmftZ8nLH//Q6aWDuEfA51N6vpHFo8VH8xEYBt1IiGwYmTQCrBgPdtUCXIBzXBbR5H2VFxml
l3HxuHj0hnS01q3KFaeLM3v0cBQFuASODdm5rSjElwMocRYceVjlf4GD5XaxX0Kutgovx0c/b0ip
olOOjO40DiKvU5Iab9QkMHkXmdlqE+s7Fr84m/W9jGR4i1IYyJe4bIbWuhYu2wiXLCTSLLpKIFnK
6souCx0zXVJLuVfW8sviV6dYYi/xPnWQvs2E/Ke/TJPqe6qonauwh6YYNyLy68m5cw5fXo+SWDi0
7+cDM7vLhEX3ELh25i1xlzowDQsELJwWskfJA2yNUrf5g68UJgrJyVjyrMkh2BJaFvqfA3jbAvEb
9Etx1JE97CdOqEuKqnPexYljewjMdXGz3UyzBBvNVcLA/migawlEKxPHvLpfy/GJBSiWIyTUYJxU
IrOWhBfdNuXTF6t61l2gPo86+ok4kiKMR0JZEbvVH2kxxrKDcZROW1ytkI3W0iWdRrJ/zmiGpqUL
81np8Fss50oTs6TXz7flk0nKyuT6shUqYd53udBu4CUjYYMcR1bVel/iGCOuctHqtw4OJGisOclt
TPOm70YaTFdtOlN5V/1DIsThRzlvFCm3WiHg0x+MwRwfa2RQ61Noth2gQe4+UzNyv3SQc0Il01ci
hB+sVFEmOjoWctbTHR+13ZSZpo1HetpUEW5dMP189nNiU1x2v7u7bo/tWYHGhNkmGv0s81Miw86G
TxbFvaTTuw4NwEaIFXko7o5XG2YrkaM6Gwd7LtBXKH5XsStJxdeY6zdtKzziK7P3W1TIJO4m2qK0
iVH8Y1Ao46A9Xr8VlC+/4E2LnZ97+2gAlpTbuhiPAp5NFz1cgqPG242/mdvQA13HC4k9ylV2hTdi
MMQCq3NuZ5WEI6Zd5yWsFmzT2EvFEo01TUQ1yy+1fFB+Ae6bV3ca5+jStAVVYSZ4O4EOjJcICv61
uktBxXzR28Nr2ZglbeignLWIy2sKEvnOMynEC7nlJrlwJl3Vyic5cAkVvfo+MFupHVPLr+/bhTnV
iUuhWZH++Cv8Ufp2VF25tpJ3kY0Yya+y+DvgpO3enxF1eDCTO6CSwM//jWHjR3cnK+CK2VeIjhbN
jY8vpd6mC7UIoZ5EtxqujAxlEsePn4AC91/x5sk5JbDIEA0aLhu9msXe5HuSmac6v8v1jeM2D9vr
D4cgnHP9gXDVVw1z8P6fCUZSNyhtDVsnkD80B71aADN4T3LFXx3Z4walWbazbxE7Fa83My87lQrq
sAl9cOxtu3KMkzxp2nZedpMPwYKjaSXti7dSWRpm+TPk/qudacrIrdCc+/BlOzEfKwfXI2N9NuJE
QgQwNyaNYaNbW4sVkx+yV+O2aF4HzvJrhqYulm2Xd1P8BLClX9MdSFZY6CIziSAc4J/Z3QMLu3O8
6hQ6Sja1wiVLJ4n0Mf6GkMC3Dk5GhJC5mvfp3qFjQctSN0l5s1e0lpBrq04LB0MalXUEoEF1o/Rr
7ffpK6J8WW2QtwXQYD9SzZ7vyMMTVg+3rbgpsTZiTJqtSpxPFI6MmpG+xqeGfi0INaIv62ptYgOB
ogTei2duZx6qrNSVd7tbtj8y66db5AbchLeFLktXvwahU2buyFkRhMTadtTpKwbWDqM6PpDgV9vH
fPC0gGBBFzDZgkY0HEVOf1p5zIPMWaF/i0RB3RgOQxfmFBVNDko7fEiOCFSF6Ghy85ghMxcUDYuD
RPpcjmqCP0DkKE7GYgvn2rqy+oPqfDk0SRnaa4U5Mry47MMtWLyte9ZuIxftEHtO0YD4jYMda0Hx
RVTwOlDj5C5pPM8hJ7WeQkrB9sr62PhyBLpvimw8i3jqaEyJY6eDcDcESvJJVf9hDJpUzdIq4gtM
FPOjNEBs+wwXDFqtryYvNrJQ7JcrTH0t+ACTyagiX04x1S2Id2ZgYPftgm1GvTr5DWkHGr72LqDj
v43k2GXS1+BXBjxBQ2xZRWfnVHLWOXT2ZGwquLQXEwNJgk/6NHoJNY3X9JMWe2iDidXPX8I/HUd2
FwaAGBFMyN6DTDN2rkgmZloF17N9ls3J67Y59lTVxQ6qwlcQem8IUZ59t8DAPipNr7ZpiUM+zHos
WlZFmO3mj1aDcWYWn+GIFo1YEHse0mWOH+1IJV0dZex4Uoz4pqdh/EKbgxc7KghGKSxyDeOWb7wk
TdINU6eAqPhil6uHuAbfLFnATIU8hY82bnc2ERrr6JDPMaEKiTdfUv/edsQXiA0Xx174Tba1Ne6Z
7ElEDcc0M5Mq51YLPfeUOs98i4Q3Be4L8pnSN1BoMxN34YCgJe/t9eUxdibUuf/pDd85LM+g44gb
WcG9Sm4ilEkA2dnKE9sHBCDOgSMXC1jfun/jNGjxcIi2VQ3d543VIrNzbRpzEtqK4dFrxSd+qZvB
RKlk6jR+Y2pmi+PoZdMkRnuECJFsmaUKF0zW7mgER5+Z2hQZhVm/TNzc+pYl4oLEI9Nyzk1f3ycT
u7ipmVUlWx3Jn3rp7Rt8xQ4kFBpYpUCfW6XJ++HRybc12EbtynHrRoW/TWdT11OjQp9nITW3ihIM
LrcS4wQlzqEXVuZkY5x3MEfPuhIMyMODcNgtsSnYzGd7qLKlolxXwxcOuUI2r1ZKtjBi1b3wHWaZ
666owtdmApoR8ffW9rrK0ivtW4FH0FYqTSFemaILBWI7QZ0Vg0bhc57nxyITJ6b0G1SaZQT/z+s8
wgvuf0+872WjLIVCEkJ1VKSUBQKCdOTVSFKXK215cZDQSO406dygsRYaqz73PlgieCyI2lU1rSx1
p2m8oGYkUTkyBWByOf7FTLRnFrdOxiqUxtHZSWt6RLAk+Zqz14InSTWijUI1IDdtvbZ6F/bsVHBM
3NJxxDnPs14DG1qCQCDwg3TFbL6Hr9q0SPfk1ks1qZrspEshfDj8jfGImX0sni4madBco17+ByJF
xLG57SaT5saRSHNSqDdAkM/hQUqI38VSyi8/2UxDRvBICn+ZAjWQIzWpdG1DneljRMDALOTUMvTV
aqtZi6Ogku0yId+8AOfJMNTFwO3tUdzCYG0oBaSRFCV7XuDkrFktZwhZnovGKmrp+gBH9G4J4vFb
YsSxwvDBLyaI3elMOVt+Ww4llZrol2UWY56VtXA98i4hhA01hDsfjmVv+9iF74fe3BYQC2ewKC/+
uyuvQGmfpxJHC6Ju/Vq/DDDEL9Wld22w05FaynpnyFyhvevt+HsG/YCII1AH0NByCHVPHBCO4wXF
HYjH6UPfiL31cC70dwg0IPhX/YFhQSmpAboja9M2YZo9mMfg/lSup7l2BBEyBK+QVmVjFmz7HPF2
xzC9Dy7LTEXm/xT9aFbxZ7NC0JGVTaRnAIZ0tG3Y0tkCvA4E6R9YTv5MyNPMG/UiUZ8T9TBl2XQ7
EujK06jFo/dYC2sImCOr2qESeWLqKcnRsYxdUb3xfsxqJV/uIe790XrDsMOj6LZ9DZytSAtPT9kC
TLpo3mv+SHUJV9Asbs6T2ZotapMeUydl44fJ5a+s3LCE1aiFX31BcXiJocZgV1Gu0oBKW/AL6wRC
cOw3TnyQFK/j2u+qaL54FjJMgOLYCnNvAQtJ7sYkIbgoP7Qnku3nN67mCSJx5+AzBk48PFhUGgqb
5Bsha3ocJrJPsm2MYbq9BbmBlBM4slXqUpE7qv9SoG0Ibs7lMBi2DnG9gM6SqhbosZ978/h5Zm62
I7wq9J43L+2gQwEHelH8ImVQm+V9lMKQsU0ta3WG6j+w3pWkqAw0++XZ8xK/Gsd4zQnudN/sUajx
q15xxNgYKoZ/WSJpnlT5RircfzxPnAIW4j/LJeUDAwl6oBmeznerkBNaTTS05Yi5m5IiuSGk2Z8M
cGsoD8DPpzqoqq2mImJiZnNnxI18lHXF+/i9rwqmDMD8eIU8dE/qadcDQXM5+Dwgu+Fqrm3TUlgF
n8/+kvJlhA1LVyMVahfvZZeWfoSCPkfZmUqc+AM/eF1eOEwy/UJQbENvPNIkJ9wBpT4X2Qky83yE
fbcou9CDU1D1Km9uqAMDCA4bM6aviZUtRFafIFCd13Fp79yKZ6ZNEu2VO7loeznrr/evqVyKVexW
O290EQxIvQvO4pgQAPs9x3V3sBOksHEPM4/vMoYlu89jlxuQdU5yAWLRg3863wZ+9ue3ij1DnqFI
AXKIlLspRmmTgPTGhyC03Nw07L2TeTwmQuCe7/dTTtm55yyedh7lTAmRIBrC4o1Nxp5bvPKMFU6z
ZhYZ0qsvlrQd/1jKH26cC5F5uqXaorgVuXv45VyITomobrv+cCauhUegWtl8HdRCXLs7lIMc+MGr
jTaExid9pIZf3WP1aoNMmN+S5IzX0mYMUJDc1V8uyhrdt66Za9gSJhanNZDmYMRGUe2ju1Coq+2h
Zt3cpKzZEODJN3Z9K4W09zpDZ+kMCDw9z+Jw9imRvJl9AceHUPo7uQyC8g+ADSqBZqdkJLlgOP3/
H+/WSEpbgcouelJ/DNKD5ZUhpSPG5TGZL3pqWve7zUEHFX8VMlu1c8twZQwi3tdauae16uX9JBEo
oQPcZ9RvaOqDcQ2MFucY/k7ZLAQv4OpjjLVAKNMnmjkog9seuq1OiZZiGujBi2v2S0Z2o2jgVCKB
1qfzY2CHTuWyclnR+MNNbuycY5mIJxg6G3cPA0eXc0lDg9UcMepTj0ZuDThV4uDBE3klDSkGXkPg
WyM7YDdln6WAV3OqrxmrKZqMuI2f2ma/BbF24cqS6oLNJE9DRcfpkwYk9WZbkOzc2Yoh4epCG1xW
P7rGraND8ajqXqq51PIo21NYsthm3lZXMeOA5sCoCmN7+3817SnlCvc7JBt1zs5QF+DA3TRTnrBN
4gkAwAcFhT0jUz8PlDg4Pie0/GJDXIm/dH+VJ2zXmb11djk8YhP//+lOLkHlNunYhQL5QI9TwwOI
Xe7aKlWv0tJ2FcuJOh601/KPWxsWvIzNPFsE6z1CsntQjHaunkmqRMutcJrpKTXbguavJmsm+zGt
xdTCd1EjxBTl35J3Tt9LFifC9ThnfxiubgxlliKnTpg9iWJog1Cfw3P4oBNcFpkGueZXlAx+uy8M
0IftsancCJMNOkpdQBZ6muOWEBqGLE6yP0Q1XwJKfz89Np+fFIyclYAwl7sctptEM9m+4RcoXumm
iwS8zDNFwzWhzr/x5udibIJNkkwLS+/jCVMBFEI/gyWfVkrr/Wxb6QR8Ob4K3GkxfayYdyWzxRH+
tWUbKoNq9g0vPsb8x3AujGVE7CkUmePulDXq/nOOZCaw9//MH0iVBaMR6obHJxF8S34zaLMWVtmW
Hid5NbUxOmUsDvi99ZTrfbzWqPDZkjuFcPXpIteH+XAyTOir6EJiezTOd+tWr0aPFxEgA2wtqzee
W5i9rXlX+EXDDb1JUBlRyIV+RqpY8Vlhe00NnpUJlkfBPj684Qmsp5JYXo8AufhvKcjemRTNPIvE
/OT9aZyZy3Lg8U8hwFh2VBPtns7KhsthcqyTgNSj2Jgxz0obaQIOZ195d/3KMvEgJnFYka5WMNuK
j8YPUZRVxqjgAXrW+AP/rUFoYG4ScgJqGoLiPboftFX72BM0NYWF6NRM6/Oh+hgnIFqEfdVTCpPj
365GOMC3HQLqEZiM9/UOQ+Xtp2a0kaAHqtW7Azl9W7L69cwPIkZIO7QG0z8Zrfu54CnKHoiaW3da
0E29NWeNY7I18NirX/7giar58JZtH2unUOo+earRInRIg044FdesiYwF2s3mzes50TY5ymOIyiaV
W1iWF/NPVf3cX8YYn/CGhRFUby/piZrFcsM2EjtRJ9YCRlRp0CiatQS9Mrw0F4ks07k6Q1waXShW
2JsO4dWDrBqMMpYRDuw8eRDymeq1mIdo1VI/v9Biv4lqdkU8FwLQ1m9epEltkfSy5hbeIAaMnk1s
0FS0dsQA/HSWbZ1EO4MWfMR4OAV0JxAmrbQgbWYiLduWtMbC97im+ZP9JoSDUTNNAqZriI4BRdah
3fTFt5fwNRMm+uwTfi7/jRpoU5x0VIm6AxJnAFhFNkrSZJJm9urJ0QkmOPhUxWdU15oYrcI2qHHk
WZV32eYiJq88yi3jN4u2DjzKpEc51OFiczR2G/kGZVsq3fIObGtsF0Vb+n2xXoF+V5KES6dpjQoy
yXjSJDWMZRjtZS5M8rKz3XeVcTT7K90ucgnwg+QtkVvcY2KPGEn8xFgH8r11u5ooC+5M4DW959R7
NQpI5rzMLlIE/qYzy9XC2VYAaFaCCptWT0HQRlNPZWQgQ6EpG4Yxh9//KYWPvOBsiK834HrRYHRA
Mo07OrYuBfkEuxo8WtGss/4L7CeR6E99Gqisj2TmMN9HiON4+KYwYpz7wMXQE2I3L6AmUa2jhd8D
peHv2EulZicX1HQw57T4Y+a62lH1dKYk+xc5hWz9bw2VX74VuaFVOE/8Z1XCC8gpQAOr5jzePNOY
MoQ+/Zq4URvOwUtgRVBnHO3vRpL2Iow9s+0tOZnft5dcAeMKKVLt2LYRFjI9Dm5+Gpu3TiPD/d19
2prtKQkpCNFL7XBXy8l/WmRmoqm/oBfc82yB5B/hdfcOmLxUIeWIG/lz6+hjh98+EzGh0TIhzjfP
LRgfY+xmrSK/i/E90VU/AM2k2LpMW4O8e5VQqKEc79FUT8AuQvSx3s0IMFeTSF0zojrYsXuUwKwa
OBj7Rf1OyOy2S7UusWrNYSvmTfMqyn6qMjP0fFSb4oU0Yfgc78hdZbSax++bRLHbagX4EiFPloMw
GSwyBn+bqsVSXwjOF9qxb9qA+Ws/8j6OAm+C2XdqksDha3g4fC1bJN0w1rHmMk1CHbUDDd6QZBgh
+sfYnA6EBaTdqoA+uFDBKYAkxtg2iPMy3cN4HHEF1iOdrrJwOvyaNRO3/PJA1JBwvYrYd93ISToF
7+bT9+7FJHAgF7cz6MY1vINMhwSNWSEg0tCRGdg7Yydsi9QBjJyf5czQIcfvZp7i87dSh+Pu2CxZ
Xg55KNevGN0oaOjjgdMFvANJRwQgeo7oP4HsF8HvWfPWr00axULI7sOETJTKTXCfkixKN5VNPUMt
wks97zyVsrRnCBOrTX+FwyPEnweyWWXfYL8lJtb0iMyzEFpls0vLkKCP+qG5QrQybwaGfyLg94bN
6ffcpoEbXfuliJTGX2CuWbPqwypfmq32LK7Tq4QGSr1oGvFRYAgLLrDaMzZIYmjQbgOrnyfyRbVQ
uRj64Cu9qcJwhbEKHVf4oXxGoAdbcg9W6mu4ZtBIWmPIBc2R4v+iff2iK0RzzMmxa2EQ28p3Z0uW
7OMeznHp7kgFgeVH0b4DgV6+tT9+IzdPW68l53IqIexTTjjTj1SAKnmuBNYnkZAHCXEaDb8/h6tb
P1a3QpzS9mV2IU42LNwUu6bJtQRHL3tkyINxEHvSV5tBIo0bEd+G4yMCBPNxV9dCR/RFp/Bu6D9A
qUBW7Y+A++m4AgB/NYd3vsUJKj5I2dsmNMJSoksFfEwLHqnXBzmiRRyMQeIIc+BqE/UkbWJHIPIN
ZE54w1vaEwmrtNxwNoJP2rU7wdB8dfRstLiMWkIDTbgHt1LAG6nt0If1r1go6ooJiWNUkiPUyxf7
HrshQn8lTmpHxCpSnPGfBhm1hao4DaFC2SQqJ9GOaznXmwaqOJvObiNYVVCMqe7KSBe0+xQF8Qwy
+HROROYu0dcQDjKpQC2GgTScxYbzCNBUmIc6WVKgtq80k27C9UG0BUG2v8C7HCJm86kCJ9K1JS9q
3pkra+Lz0yoOjn1aukl+O5l69li30yy/J/YNyWRVXiD25ygUlCdwgDMYbY42E89TIl8hDBQTWHas
Zp9OwaUfwQLYEQidVi5jByCkE9ynSEDf1h2EcszKQAz5iHqPsXjv/yb8GdbPDWNrW37cyhSj+d9/
l3aa6vZt6GsjCpgJh2tt8kxbPg6/0UzUcSQny+oH+gaIvoL3umXIpVmN9vIJWWprBUpEKreK+PCJ
1qtIF3OB1kI2KkyJTqglnNFya0Gsdq6RPjSQc4+pWCuGmZphNZOWMlo4T5PHrIqRv5rlnfSyFTP/
XHriZd+5BdS+pMcB7KtIYDBlRj1UZQykETTWgP+B726L6If6WxaAlYgmhzVwMVqUyDZzjQE1YSID
VhSSyQqIKwBSN50SW0M9EdDuiU6tJ0Id/ZwOGmdKqbOtKarA7cinh3IYdP0UBtnRz0YsI8vLRXZf
sRlL5on9LTfigwpndiYKO+AD3iMrz8o5vRorn6NfA14UBXV2qchW/6Yqw0sU38PCsBhCxBV299JZ
0lnQuOmwNDqOu4iNWVkHf7iA5hiJep8F8P0gdtKqTCRIE49jl5u80sH+KQ88Vj8BuTCKO3U7Aade
q9AcR+BotZZIdC9PTJHLlb9xHDKKC848RuGv8EGEfcoq+4q5/QP5a5vfF98MbfMeddguwhNAVLrC
K1FjvmxE5BcWF7tIlezkowO+JHx7G0lLxAHqKiML2hY1wUyz2E/9ChIDSKOft1IYZGpDja65vDFR
KT/qH57KeR1EIBVejNfm/oAdnw/YO1cAWrniOqQvgwwUlYEhuTLTu2YuJuGbZbXR5en5yaSQjRrN
EGcys7AmnnjI211ZdjOjvVAeLRr3jSQqZfhiGa30wNUgxlPvMX5WLOslKRSKA7gjzhULCrKA4qAH
bRmOiAm+robXxgQIPJdwgkKWUDatkXT10QaGjaMOQrvJ+5WCAqFPr39qJq+ao7DJ7ZhnQFdnLXtD
63Wrj5/0Vxkc9GPxEUo2bH2qpkZL/Td1CYv+oBnChg/S4wcJdikHvN8wb7kjgmG0l0RKQP8p46y+
1W6dZXKDL5m3U81B/F13OkflXxz6ggKRCcteQh55Lw6SABqJSexRWoHDNgc9siP96TcQAP6evIwb
IjptNf9wQ0IoQM6ZBIBDJ29HYoVfNZNw9YHb57rmWLNhmBAwn12+GQLtjJIaj+RD8+BBnDheJtuI
Q9DsMfdEph2GiOj13qju2/EZaCwoBQSvso0WWkdF79BGmtPF6twYlZLsmWt07ZrsI9xNlwk3DGvs
n8RWb9A34PMDVLiCJKMcdJ4ttRnRNmlR6U+QIY9VzCfM12mGASXrCib8o3ZF9ZjWy93u6bcDw/2k
q+1k3yTzXfDcfQejEzl8Cr58pEiHWhjfgmSv395Ondq5btEbh0hcQUGejd6c/H/2a0R3jtaQehCk
KtB0gB7wPINjA25DTXHohnHMiwNUbT7fn6jH7kC92etHZe5z+4FS6o0OdnY8I9Estgr/L3nr8XXV
mrwKLHuT/ygnTZ7F91Dt97XFs8A1FnPZuI6GH7QUiHp3SnJv/7SAWbVYPNT7D26XFO+JP5gJ672K
prrGv4PD86bTmMf/bUIa6yNquFcaQaD2U5PK5pPleh3fIiegem5GOVVrniPOZ2ob0uEO4Rq36JCX
UH11Tp05gOKr5AdPV6OtulqHp+JA+8mSfIR7S26qu7Amhbf93m+V1Zj34iARI5gnLmVv5MbK9UBV
89YI6uH/dQeOvrHRsqV7+AkCpEEsezTzCwS6+U1nFMnowjUNOE1XZYX4gUv5/YraXywxXyYofECF
dJPxJyo1hL0pDRpDzyQF+Es3udsxKn7q0u77f9I8uoBh6hh4HP8KQYResvkZZrgxTwQQTxiiaxqR
52PMlVjeMgqJ69ol0HaNdLLXDWxw+2z7SyFBtv8wBnp6byKzn23VWArM9E/nMh/m9HLm8YqNzd5s
J67DZumP4jIF8KN7ygAp/+LDsXVXj5/habTNycLSXHeSYKE1X023JjPqpyHpimOL22tnh/N2C+iK
1WOMkbAx0FZUkqb2lIIv7/xJEwvHx1W1tyWMEW18+qUvMx3Xt6ABgKAMJk94WW5jgNqzvMDvNbzF
V2J6Xkk8XqGZycLQtk4byLI1BGdgk3GjXADzqMLo7fCv/c6NS86EdWukaxa68HWRLf+jBFZrZB2C
iO0fvOiLTnqfUiuS+MRqi9Smkojl1PQnKSuGidDlBpdwo1FrcOJ5cu9IZcc1dvru4fa5WPxYbeHb
LV/3hHvqcixlMAPwmZsPxEg0C3dHzaVJM6UC+6x4sfnMnFLgrI6sUJF9whnDNGGgPOzBDDzx5W5f
v2KPXDtzqmAhpSqBS+x8t1xgmlvz/LDoXMaLbf1m8ERAM7ZU0IXXSEn6qA00tSd/MPTMOC9Wj4GN
QW7P5p26iQpANY9wI5Ki3GO5DmCqVj07leODPqBeEtKV0xseaCwnH3kT7FUqL/Y8xixO7wpq18qr
w8xdAW0fbYSmDZgOqUo6rFdeFq1Guk2CegdbR6Ny1QxCRP0aH4LsCkmmLWuO0+T9cgJe7jAuVnuv
SF1UW4RN0eVFdw3Tj36EfQqVOJmfBycSSiuhKjmI/2F7815WukvQCKhZmnstLC21nkZOuE1O/1Js
eG27dQ4PeYmM4iumvDxUSbpuWkMpDhdqJruMs/BssTQrViPTOLta/uBxYsNu1xN+tu36U7jJk0qQ
xvO9Gxy+Fd/W/6NFJMinjBMoA4lnyz2CtmQ0MyEZczVVn1YkP88Tgor+1jMMh5BCWRx8TPUfr62U
dRTEMGK8by6i4kGjmR2IrS8hKyqOjZ8VAT05FAfRQQCYvVyXA6L6jgFKGAfve8txKqZDeCR/UF4n
pOsgQUzb3bg4/GGSELqYct/NikR+6nQWJKkcCQYWM56D7pu/KGmjrSoEjESKjfMetvE9MKjGF24K
gpOJPU3w66PKO5U2ODSOjrxMJbmySMp9FHsQFKcp4mzEvfyahdaVTDaLiTnjQ2Nsdz92SRo9xP0q
33aTEzczQg9HJ4NEnUXxQ+j1K8d0iYnOFFOW4eAwfpzJ1S9NhJVuoWAjmrPP4Jq3S6Liq7vTyFYp
KqyeaWjIT+VQSLpEZLmyocip1IEdh+uPJyHVCpb3TTjtUZSHoy1oOAyhwjxV2WbRjKp48XzzruHT
UzxP1CWZYV4oFAp1Tl10UrXP+g3uiWAh2CHwEAW6Q08t6VQSskgGj4m32kmvAO/UQNUn88sKjyer
LM36W6eOWJAKG4hVzYNeBfQSFIMc5MHXnswYNrUIzcV50GCm4ho9wUeekzK4XIKV1pJvK78LNOS5
QBRKiq7a2gFroHnE9TV6U5dNmEcGVEIDLUqqlVr8YoyFbZKADpgSD3Ovz4Hb/ZeB4jY49pTHnPPR
zFSq4hCX2f2XOEf9wMsU3QOY8Mtw21ebcaJ/cAPcGTzbaBdBLAEm+xnXLnfySbkxwH1XhwNa+6ER
ldDipQaTWZhnzTMG4ZBzMRXSrhanm1lxsKtKXeGsQWhhlpRShOAu1XmVBeTz1frphiwNEziBjLBU
Olqw+MVCVFgN0IWrM/Gpak+Cgmo62SHvRXhFYB3SqL40nupwNjHELoTRcyfSlEN1HpRnLywC7vWz
iSl6O+tyCmB6G4lP1cWS1FDiPeglDqI0BgJbAOolPBJO/wHEQFhRYyfZJH5SdgUxExrpbxio6VOe
RqHfZoJ4XrJoyJYokJHDGmZ7hv5fH0/4Boa1H2zzXY5z1ieIQJZ+1c80cxMQzQqv5ccmFF6aQAyd
Z9BAZHdI4QU5jXfnTGjksKkc8j3gJ0Pbhv9YLB1d8vWXWlP87TulKfPuoHxGXwvXDvpin+7PzDhl
1so4g6jr5DC+gaG0sOTLXZB+F8ShzT0JxWxAUvJ/ECPYcDDgwZqbXj6PgsZLf5pxmPmNzHlgAK+C
I7t5dyFPYhgQ1hjMyIKHFRXgKw3sB8Cmwr4f+5rlMrKmd96KGGlJGQQLD2FrenwYbxpQ/RBxBqHn
WF8CVjSMHLnHEaG2LFFtLvKKXS9ouIe0WO5ZLPfqy2eW0Y6Lkk7nTo2Pl0Igg/zriODrINLDP9CZ
rtPnTWmmq/Pf/M52mKjMb0f5rSGepmGImmjuKLWCyc1AsqgivaQt2yl0XOzEr5kMF/C1+Jl7UN2L
J13OswrtaAg9yquxzYISvvx+YBnMUJ+e9zcLy7xLs2xXUPg/eeaHwM0YIoZEcQ+/h0/bQfMFiMUf
9efj0hC9h2450PvWK5pIt/os/gXLNTGDTiDmMQzOJLfCriPmi1c1qPm60AAsZstun3JByz2sM1oj
7KbdU2QZotS+Gd4r1atIcywRQrIUYPxcVNxgWCmw5EiDNBYXxIR7x5nbjAWxmKoE7Z/jXunTBqk0
c4mzCa3K3vq1z8Jh65jn8ch4sjNQkBoYuiIwWCuo/KmquW6tLuC2RAHB0K2JbUEJBAjoTvNwKWW3
1oFRIro2LGWbvNxYzYen1rJ02D5APcP7j4Jx6L7TjQ2NKv8cPrRjxFL/Ag9JLh7qd7xWyj2Bl2VO
D3D1niYmUm8KU/OC9qN42HHcx11O2k9IezTu7UWP3TK5wi2qtiJVrlyhzh2qYLMmkFwYzw3j2RWZ
z9RaceIR9ZYrfVo6ct2uCL1AkcZ5gruhDnOuxHb68jiI6yA11xBD8O2lYuqaPPUHDh95vpDUQ7QH
4TH+RI7vknEEl7eE7tEKb68QWVCESAwyuWPmq+ZJ81qTx11IhjqixV6RB50Wt9Wmas6N6FvkyX+L
SVXG3c5MpWmOBWb9pvTKYNvapocrdYLNF/Hl/Z+dxJHoMCBvtWm39Lvdu8lDOmnnUZSwTmWhPd0n
5upvGL13Ohv39nVhZofkpP9ttecIxGBJRtVKyV1LUvVoXf2rJAWZ8TgP8aqjodlfgsmH+rAlfQ/o
G6mN3rzSNeM00OsuBUKi37D1kzdZCLJKrF1CDsrR4nwku81zSYlXRBBjvmkVXeprhz7ovxFHTxkr
PEQyh2rHV2POj93jjQBQ4cy9T3HQhbpr3MDt0rvupqnPamLQVwSmNMisCgvhO6MTEu7EYm88pjcT
QVRfoZlurUqbCwK/+pQBtm3DAzK5ZUEWcNsSmETOPAF6CmBbEjAhMbZRFIkbfU15Wa+7BaNsRdn1
GvaIVHZEIOMqTwbrszhoUTDvurwRb1wSsbXmZQ/LswCjJKQ7JMB3ruKd/ay02Ega2I6yGvXhNbrE
xhF/BVt2wTGuhUJXQs2pbYVNfWZqeO4TViltyghMuNVc25+64SlvLj41Bg0Sub1LUiGMK8rZrj2l
3Is4YHEZY1phqaj92t2loCHR4C/PudiWj3Ja2h0eXSiYqPeGAwgsK65fjtJdFGhF3v1L6rzRJ4Mi
Q/D89/ZlREQ9PCKmKO3fWnOpTFvoCV8GK4Zy0dw7+ezxHI7TTD5E1WxxYO5coSFdY6r2NpkugpNX
F5ckupSi50adj9oqSwyCi/PxB7Zf8f/QVYZ8P6c/TNdGC9svHU9gQSbwzxmroMS+uoMQ+ZRHZ7Wa
7PFo1+6eoTpNnVqHW7HqRJf+Jl7k5rgWA/IoELzugSQLWhcSAWfgLL01I5AfRwvGUlBVJXFiAHk4
nNQPmE90E4Xjj1fft6EEUxax86L+UpR3Yy2wc0XDvqINC4TEu4cBeYwzYLCuhHM70lk/hgPfPUJ8
RS6gwJfrAD2JU36fs9nFUmEjp/GZsvAtnUkOrZTuCxFOXeZH8bW1hZWblHm7qlyDcEHypbYMdUIj
cct/gtGpyu5Q9NEx2mVrpl3dw6g3nhwb0pzJm5q6nOZx30JRZ2BcV0noqbIN6S3H1RhLhPeW+ftT
wNUuzam2HtTjJ8qWZsVo0F9d0uYZkCbfv3HvoCJLsqGEi+4uX6aV3ldzFq6Y4k5K5ANQDX+/cFfj
PGotvyPP1g/ylB3H0rFefzFcJ+y8vhGOm2GKJNDerX9j/boq2mnxEojGbBWkiNb8eF6/vcdTMtKD
YYhozzq6DxvKxb76kUFmlFg0OMB/BYQwzPKShQbVa2m+jfhaCuqKGF1RyNf6E0fyWhgWxDZyTKm8
5nnybao4wT1ecMRYWLHBiI56PTRhwlyRlQfmHfswCvTa7S3214PoWj9c9I3LDYVPtt69cWyQgWLi
SHNuvxNDec64kZ7WLE5RZYRx8qh+33U3Z2BYr91OSKhNSnWSg8NO4xTBpaKlnCCgqHOwdxOnEtYe
YMzLIzFtU4dNGGXAwyKKjcjvXnE9PAOn8m1ABYmuIA8FqsM4YBxDo73onclhiNz3NMtvGD+8qPxG
m724nfQ81NfjLxDFd7WUr4Ws1CtSr3XKkz+jNXbb8XH/d02gD2xLaZzG/YF7Sq6seh/ob6UQGCcD
zVzNlCmNBxMwT+bBbhssSrkRNxoo8bPvFOieb/isHugMGoVfUX1l4vy1OveO/lBrNZ69E5AxBO1A
7mFtanrAqRo88DXkIylGHIlJjpL6jGJZeSNzGu8lDfSmK8eKob5fMKbcNJW9bofIk5t7TXWtQ3bB
WIPd+mnfuKX62y9N0vVkAKwUfi16c9Zh+VCUJZNWsV/G4g7iakVKH1oDVkvF3LUP6VzkEcNcgf0V
Hii8ldtUY/ExNhJyThKLT08IrZwWj6P/QBDKZLkyVfrsB3PuzNGbfPbT7e+PNtTOY7y0S7yl/KU/
+AaBSsufapvQ/lZxJEbeMJHHBQuhqWbIU/LhFQNiddmYt8zmrY7U92/3ozGLF8+gyRf3tjUbeCdh
EQZAgQj9CXV6zUqvpiob/9cOpvMufSxwZcTynzMpRpBm7uTC0ZxjcuutQvlJofsBeSk+K1cd3Wif
cY0IxbanmjbQUQXJ5GDmvl6LeTeCSZrGElI9a7iY+SsL/bHDKI7Ohk3hlJ/aY3AzJHOFkpRVs7N+
szsMBRE4pJgT23ABEpHH+YzjJpjq4qERuE/3wvD8LVMx0B9hnuAfMzDT5y390sfJI0xHoxEhMJxs
fHL1GpWqGDH/NnzWQt1gOWLJmqmvjx3qzk0vrmEf0EZyeAMHvephoxCNndJDCrLiswlP6/98FL7/
MCi9Tm9hCBIJ7QfN4/1drNmIK3ZqwM0lWfkkpQ7zlbFKgoqTYnNHF6ZQ19lAmYQrOsne3RKmw8XY
dTCPPKadMbm4fyFctYKHZGVnzksoigIr3FlKGgmax6BmIrHcHAH86XBF51AKmqf1qWasQx4c3rR9
khm50lTpn2sZitB2KTps43WGB6PlpU70qBBDxjB8TR5AMGgkdMdHJNoKGjydIvW5lm9tXT4iVm+c
J1SeOm43NdCghm06bDHY7gxBmds9+kGIScSIWK3sWYQfTVwrTSLNLvvzNUd4BukoZ64Np+L5J7WY
jENmN+Sz1t/C+ThEq5I0PZ9KpmGWC+YIXtmfRzVI59ZeEzyaahoVwo4ErhEUXvZ84VfhLCphB0iV
LAG9mhhzU6SMYvmOKZmqrspo0hi9Ol9NQvskcK/kCYkbtnRZyoG3+MOYLVQzUGaw02ki3mWc0S9n
oGlQ0mbpZ9befQ0yJ1KX6XSiCSz2oe74Xzla4u51Fl6DERbs4Aq++vaVXJnLrlmQdw/+i4hTBTSU
8QF7qvX9MdXsOu4RdOX4gehoJWaES316w41v2SdZeg/Jutru8tD9L5bcY/43JAAanK6OxOmm+/xS
mlzmX54Z6tLP1FXWpeRUY6CH1oCHJ3oUhJBhMrSE0tPHV/SA9TV58Q/sbriYKLkZwvA25bfJJxT5
DKDDsxtIsX5q0z7zz1aKp9g2T+DyVqZDmqFxt0p49Uw48b/rwg/OkiRr7JD756kCn2lHlWt3lysh
3EMezATH7IMC6pgqokTri0KP6r5C8vtgj9SWbagmTPBLEf5PUkHce+k4GhLSjMKNmZfTle7ApTvM
UtEUdBox0yUIdAi34UDiRqVKNBeei3HPa16ghGEGONcZOWMrIM/00+/XKLECa7SYO28AlF+pDj+S
kTqfkQ5IWnQ4lFPjtS3Dz73WSPV2dVc4v3JFU4qweYC6Vdy3fCZQ/XESJC3rFcEN+JSlETneAanU
5JrIJ5+9/zn+h9dF21vW6BsvuUnvESpfvu9BixcnO1zrY9pzAKDUtTWt7KgLsL/Cq70otQTZGKFQ
vW1ae4w+q24LFTdpaLtnXzQtSm/rCLHtTXHKzBdjq246ddhvBAde9/a48sAQiuZtkqtfOWmcwwWH
24j7VDjthsimNgYh3hiUhsL7wqN6z44N9eZUjbxqleh+i6MVgBN0vKSRvd8ugX8zwqcxgVO+u/9L
4O9XxJX8HYUPF6mITMrTODisWohE6z4BZGPuFLCK6pE+oNh9GXFEgzRHeXJfJtUWwKxaZMonqfkQ
HukrnevEpaYq28rbKh+iDumIhLM+br9KjBgZAJBga6Ra1Tu88meMSJc5/u5Q4XcnU5J3q7SWg0ZU
8cO7O9sBwJbs0faW94h+/Jzm8/dAK7byxCsG/qjLH1uq+Jvsh8XT6eccwDQzxWTTBZJei4/9DaRz
Ed4z7CBu3aqU4IsgGJGxHRBy62bRn/vi2ZBFzM0IArek3m6OSXiJSIMoczDEsmbMCePSrLeUkn8y
TO3B8a3yCdvGLg0KSz45aedeSNmJUI4Ee5j5rNbINs1jQnwVnXHXvVWHjXX9rhEAZuZWIB4/u4pw
vQcCakig8fWQF1PjkIvxGsA47LJEXD+4j2HkfYoKOpxaVdVy4E8JJFv+0Uvi7qZv6i6iR/BkVMWb
v79kuayjtu78keD52ZCMyqi38XAmjlrQZYNfw5L9U7H+Ljj3VSfrpnbkReWJbythcrzZUupnQcuF
Mny52gHVFAffOtp52YB0JWKVZnVl27mfHJcXOXMwhDf65I0SiAAF8m44J8lA7INRHu5YVh0IPUqz
kEYXCxpPqy84vKLzv/bMHs+rYOKFIUpnwDSzcWCwBiz9FXSRDUurv+tg++LN6zdNdYhcUi1ubQ74
143GQsupMTPsoKVViA5G1/t0hJwsMY8Vn3hrDkwveO8yAvjt2Zu/kW1/5ohl1latD3TSsx6JZHf/
wCoby/0soteRlNobWzZAA29wDVptPAdea8dS/QiRK6BTyI6u+8DtrY8D/2V1i3WcXjdJOcXs8erO
X45H0WkNZjny+Cj4DqMwgiN2w1x8KROkK4X5NWQ9LapTu319/EKbQ7omwgU+O68QkrEnIseJEcYK
LTy0wlt3hJTTdlNv/FVEDibdB7wm7mWkTixd5TbYh1MH/wivMdgUgaIGS8KKmiwhY5yO44wkJ+BS
ferzfJKpR+ORiS5DLjQ/jv2aLESfC1N1oPIpKj+UmRfsF4CXMvgcsompIkQ6VCKKOYPDaozkE81j
kYCOnAwCbi7ApzUznSnfBEtx97I5MEbGgyheyX3zMCEfJAZAh1K15Z3prNCbH0cKUSXbwEWFxdnj
OwVPl+/+y8ggDiY+1uGm1p/9nVTGaB92q4cVdMjSM86xRaH9cpYcGX/SWpUzTWyvnhhRLfiEbtaH
sIh4TnbGRI/bXZ5OShJrgovQiBeaaFHQhyqAqLz6EbxJSZUmL24mQ25yhcyAvYoFd53UZvBOYL72
uHC3SUE5mObb1RFaxJjGH0VJgf52CIqh2AqdF7BnLxHRMMcD0p+IdQ/rfiv4+3AuJ4ZFriafbRRC
hpuOvs/+cLEwGOt6w1WfZUQJYW9O58rOWBaifdaBxEmvNb2MIMX3l+A4UA+iKx/PelQDPNJme4Xf
m41Zfiv79bW0R9ABJGCt/qOaQjO6/Y+gvG3QB5rPwtSEONq258S1bQVdfSs4//YNIfeb74ty/Qw+
Q71qmethXpNOIxRfIAksrcMfpOZstIwwXqzf008oKsAREZVK2qPCNtNQD70psq9FxdbczUoot00j
RpzIJ1aYjbYs0KjzD6b0Fc+YBJcLjCiiUA4XscudG7E4Q6lhiojYnlGvGeDmRReWNqsAJHG72O9+
kxlwkVMqAKvZgqxJWY0p6cBBO+oMLaahW8L95aK5EWvAtnzooi3hetCuuELrrhg+KmJegTmyvXQ4
DXglf+P5GSsVrp4aIYcfNmEj87a7MBs2fx+1K5s7VBq5kLkdHVnAoB9thWd4jLxoplhuFAUwa091
naoHAgWQNA1tA3HDeQViqvhvkznOiagOBNg5CJFgA0B6gksQAi5yE4LquZFeaDpzO9qU4I5+2rjh
L1JbwcQqiWQR+eIeOCzA1sKzjC30ZKsJbgUBEYYAuRv13e+lOxRZH5fe9/spTIWeIZr6Iqp0TKAD
XjMHsnpKL+dViCOu0BnwpEgg2Fo0PWAhPVICTk57QiSI9QNcPskRQsQK5GjNtFk9TmKkay1IZEuj
7uWuEr2SxZhO/33Mgu2p/IY/PV5gvfWsXU05REZZ06aiCz2dKqAc7LJOjy9X5b+CuW1p8l47qumQ
KjvUcj71GeTWbaAmoxb8g60d6e9ppnKMfen7PmTfb/TSE/Pcu126QEjkuSZF3+oR/WDE1dKuSgsx
8IdLX+/amFV5PWc0AsyZd6CuInMzL1otXXsKx/VVxO9TJq2lgUYZJNU7XX2JPf5oUM9+37tw5nSi
rzRydoUFPo0XH20SaZ4zPJaPmLlUdvrFveuHvwU40CvQKBJN6wCkwPjYPbS8DTCMgUwfBdeFYkXo
VOScDv3OkcpZcp8W2oAI8Tr4mPaW6mynOuw8idnY3BjruLhUBRmVWZNJEYjygEIhlQw8pOq3NtSW
4qXqqLtl9Pn2vA/7UNRwfPgvInj7PuWFlHsjzLbXLDSi2sB583WnP6DgJU4bKnrgwreg3aXCwybF
GFu9sYiXzYThtm04Z7KgaF9OB8HdslvR75Y28ZRkfHkSDvRmqiEjjasmqqRQri2Lc5kpGlS3eFjv
XJFKMM+tNiDdf2cBJ37EJ2F23LydmTWY2GgaKbUALncqRNXOVt0IlUPmq1mjnuBTiLvKQ7XQNTou
oeHaJptA7u7ZgBKjX2gVgZrtG4bzZuSfjFasyRrW65h0P2OeT5Mt878nay7auoFCpmgrby/9aNaK
jhdVPrfoSBDZUrfb5PMJTTpcorOhD7CwqU5AY+jJztpcjAGF2ICUz5a6wXpISu8JTHjH6/Ohig3S
qS5g2xgV2jSi9R3SOU7HWTMo7HW1q0/afnf16cPeO9O8HDzYm1bYWenKbISCfZmGxoIeOYxv+rpK
zFFEK65/AZEyvI+8PJslCItnZc5B2bwsOwfTSHT4yG+CYFOqK/MQPxFmqnw8XrHnwFCft5QVtfdt
lOOU7pQHOWh9Fv+nOAf8KKHB2wqw/WLTmXdutBKHllmiPmTt6baVefxloCSb65FaVUCmDlFdLktZ
RS9lZtTAZD1O5T60vNhTdEf+1V7YZlPig9UjOcEQrPVgfbDTsMWIylVfdXBQ790FhoJ/ovfrENIf
ucu8mWzl/uw+5pBmA2gaWOuUJgmgkHbElonhOnBBzwWOyQWPGC6+MjhZ312EoNIB8sz1H1D/bztf
s8oLoOUU7beBHuIaK8dBzF7EY53CZHXjKvT3vJRTkEncyG7wAPEwcIMlsR+YLguIjo+tWFRY4x+3
HsuH3boX4u59+/dD88XNIH0zs4RR/++06YPfrpMa2sUJ8hW/9hJkI2VZT5Sl9BWwtQaZLBnDZWXf
mC/fHW3QoXTuLBXaWPZnpJ67bCLED3GjhuFkLwnI/YDIeQIk/igPK6wtaWGQBmGruChClb7me3kz
f9pqJG7/P+lrkZAxBKT0hMRbf14uH94Q1vPCigpSYVOrS7UD1tmfkN9qNhE+Lva/HxtRgAvBaMvy
wnRXNqkjG931+8IJPAG3YB6FcpySzdKEaHETx6iL5RuHF4rFbo/C1g09p5B6L0FnDlfPujm0kuPC
cGowOdNoOAx92xpEf2G8UrLCA6a+3RTMCpO9gLw7+fzSOo1RZuQTDOnB37TYehSGU8W1d2o/5PzO
+tzSS48piN3E4FJoMbqjQVWFNHTKCPxtCPqxjfI+AyxI1fU7aDGpc//CfrEiDeJP02or92nIq/ax
Akkslnkn3edeOA8oLUWsCCqgd0qcuOSCQZDeWeCZFfZHXEgeH8LrJqtickAC9b7moC/xrURANWl4
S2CXMcY+vB8NaebxkAAjv8OaCPgL4sDoQL/A8De5wabCjzLxw2oXSQizT66b4PD+xI/OnTlvdm9O
E41EPATfBCONLcJcMgnb11Qxo4q43n0jylMh6mAJw+SmHjQUQavZnJGmpnuoHxXYaRGhIcmgCBho
SiUdO98fDYrE+OKjf3Cfiuf8s19G88W6rlVyRVuInC//3Xkn09XoLmKClYj29wO41RGwY08m/rgR
EgxoP2quNV2geZfdpNKlLJL2/OVnDVSfbcK/8IeeWJYjZSZMrcLkf/fg3Rb1xYth8MC0w1Sz2P50
JShm8dZbjJXXxfo6kw6bmE6HMz1FCwnEmnhvAZEy6Bt7rHEhr2eBYojoiXUiAjUu71HSWBVPAwXw
b/CRLYHMHVoTceu7CDv/FyGQItau8ZFETPY23qYvnwwzm6HsJ57JXZkKNkNnurmxoyKtdwHPBWer
Q/Ln4K4HPcZ1BRR7pFbG5+1ojwH5FJIPCiCg8jAs/9cq1WkSvkgo7YFBQjawpDUjJE8qj755h47x
tlVv+71+SK4SY9UZVCAwQtFDAX8HJN8yNHkkBqHUjiLOlfxai81pdf+71aztl33YC/qXXTPx59Ip
49x/IHHGddTbhRIwxdOUe0PXGJL3h83OZd/vymxkApcN/KXzhSRK2UJdWffZtKsRxXH+Bg3uWjCU
+dIObeNbmO9PFDh+te8oOYQWntuY7Sw+UURgs73ORmFL50qI7UrOH7/JxtUBp+5IR7SUY9gy03Y+
aCcPWJD+uwkHdaR0tXcyzWxuVRIaBl2BskTXWzIgAEluciCpBdxbqaSIL8B3vBLJ6MOoNe7WRIP1
eaRGntyCu2iqQypQ/fNktoGAwz+TfoHwBpLucZkl7Yp81zuQrEs0TSFULMGBFmm2BzevAN9kC6dM
i3qR6ws1ODZHfbb8RIRKgFeYOFqkxYASjuK5OdxsjYeuOTRG759vgZCkYw8etE2rzNcx27oqaASE
tEjGzCDSRz47Wr680xZINrEPmekdgcz69/RlHAccws5J7VDE+6EuI9xwgH6C6pnU3/lBWIG7+7uC
xq/3voidE64NB3TRuY81jZU0I8/JCDLHWqNsOCobT16aBBxHnuzEyMuWORQYVPNGlQipSwTNCtQ5
TM0Nb2SBeh+OQG9sGSWwVW4SkBBBoXtUFb//3aayRG9JLfJQzB3YWv099t8lsayx8I7qAcHbbUoX
JTkrCBhWNtx4ppm/U+KSQaoS887yLdtho3bkfJX/Z9bWlglNeSEo3BEuVSz9OBt8KQrmpv7v6DRB
gshyn4v6rFN2Ppqsc4GSeuGxDu9VKTycVzyr0t2HhcmckMQOcX5lKnSR3s08ncZHu6Cjm/P+dwDn
xXhhiG0tB/EfHdc8B1SKvjNhqSiNayUNTRUxWZ9phN0skyq6YQLi1Y8QdIIFzFqG4Ertv9Uu1+a8
AvqbjDig0ZpfUY5W0w+9ucjJG1Bp7Yjb6oQU2DjjhU61Kk0dVYJ/Kch0yWxW+BV3RHJUu+OF4Z6S
09oLpetNsWPVeoOcBEgRfchpQvRo7DU8f6xSBJ33OApMPHQZurQNjK3jU92mfRiHPEJjEa497xgu
p3Ok1wuEpp/EQstau0s/0Mi5cLFqNgLxoGlOjD78LVBM/34wUksMuqPA3E7zNqctN1youPuM8HGk
9yGUY6RvYXmUFbEVfZXrkw9k+w8LgZhKUWhgDy2Lt9bfn1jNRGewhIayFgpRZewleVIStE25YiUq
lBsk+RjnZaMOe13NRNic+P9z/xW7G3cqq5spTWgfg0PGO53/+jFeW6MDj6DGyDKMkpl85zL1mvKQ
SMl0TJ5Dvl3G++XbcVIEzXg6ZSQ+9EFV8c7zgrj76QXiatsb6KJoxJnaYN7J07fC0kJD2m0vd+eX
+z+QHXeyq8ZNDSgAym0P7V4emCcM94KhEcGrsxd2yoxmhGXpG3QNzYnAwQrcGf7IZZ/pbPliP0Bz
pyX/z4pDTuGSg70JvNLPCrDy9JHJVLwTEQK+/9rsOoU66oqe/wv8DnYVE0g4Qz7tqQhtonq//Zw8
AnEpXU1R2IiEwWIkzj2gT+cEHvvtwqyLMj5Iis1csXLjM2KXht2JMwfs0f5tW5Ni0lHJ3BqQxdTC
owaa2FbZfFzmuPNDl3alfYg+kDDaBeEYmF9mOfa/hdT3+72bUKVZDx3PRouq9MRPp5oXOTQmuzWx
2X60CaCj48PobENO66IAq9NBTC0FCOeMh5RLkP8oFibVfizBKkt3kh3BAKRZC/c7v8FOGOACjUYN
aOMsZbF1/7hdwsikdof8J4yUhFYJaogiCpkyVgvmF3CzAxd8ppGS6YaL6gx0xWSzBnjkApnmsFTv
cG/E+ffVjMJZRaypwepaYX4TwwkWRFHFUNboULS5rQDtG9BvBajyg23txZT5npyMcYEVw1kmBV/F
5erWlwx9TYjsWpPSZD5MjDAjChxmk812yI+drLwqv8pHZeqGEGVuV43vphYMKGcjMcIfpGTfN5mH
DBxNRHUdEPxmascSyw4vbNF1PGwj81RPODflan4v6+rwMTTmbO8gWP5nwzZe1BTflHQRXuGRB1sH
WabManfJhjbQb/3nQMG1Tnnlh50Ja1QHZrNjxWOr2mqWmj/dL8cUXZq94PKIyEKMhgerVX7SV1YB
yhNqOp3wY4qJmw6g5PKSlWeM1Tb/JN9kJLdiEoEm7ZTj+ZWgOykKw9V7vNnMYZ4jdlO1IMBXp2vR
ZV0FyfnwSfgKxDCp0gPry4zhxZW+E7SQYK4ao/MCyI6QD/ZeVLqciRrYQavi7PEnT3b/PsI/EgWz
oTdrbPJEQAfvkobI1Zo4LmdWKZqR4qkGuxXstJod8AcB8GsCuTi+u2bv6/EC+ZtSj3L1ACUSCYqx
6jcUhBTgygrnNqKR2HwxRAEmu8p08Co0Fzh9OvabsyaEoUavEF+zZSGfxdX1/9yfmEV6QyNMRnQX
xVjKKKYGGjXedguMOLdoA6cQDltLrlDK7JLj+2iJZXhjLWfEddJiWZHvh8eoTG1k/eervrayQM5p
MbFukix5zaY0S+r8LN26ITEnIkHAPZUpjOO0dXbVbanGak6SLwQlpkP6fD8fFF8NZDG3jo/b8I/J
DmjaAUQupWA2Pfu1If0V2OklziX/kQQdSmA9XAmOS3FlNqlcef+PH7dpTzDBzKK33f/5eyaJpQkf
h2cxaCoaVzjUQXMb5BD/pHgM5E401UJ+GnAsao/utocsv3gYVyMKMdPz0t/C/ANjWFgoFuIwKjLf
7/G2lXIz0v8M3PpjvmMRc5kKSDLoBwN2l4oJrNtGuE2ajOgS1N6POFn/gHa5QXIZiYqG9USoVOs7
Kb1eRt9jmsPf+p1xBpA09Lp/RJpezPCheipGxEh4Zt/XaPXcAm+6SOXGiFJnxGL1RvH2NTiPpP81
HdDogp39vNG5a5WBdVultHuNWZg4xuTluAoG0yHM0t6zIhEPXhBZKUEB5VtJMWSGm9BKbG7uNGaE
N0/KYTnZqpOfo7IP30mOVu1t3gMdk0X2OcU0ZOse4BV6iloKNR0leUYAMZP+nVt9O3MaSBLnOETC
K6b4Xjdf+acLDPCjiQGWnJmfat15sK+OL8WSteRcMBVoOw8Tq82w1gb32bSwqng/7pewUl9g1K7I
XTEU9YDb1Q1v79z70Pbqtjx1k/HqAcDhp8d9lrcm2Zik1E8MNWlIBaYKCjf2eoFLFlsaisJF/Axq
n3OTpVewxY2Zl8k8JchVVxtSQiktJWjRmztqXM72WygNbifjJjJv0mLIHo7yCqdszG2vVBamZesO
I/rph2Ba6JeMKP8nHOnZamOGUxQHazk1L8UHtsZRX4KBwYZmxRMTpBGNk57S0u2KyRaY64Zw6W5g
gASgqE12zR8JktTvxJ2pHZBsRMoyhDQWQ6TkvTdEa4UVoQ8ixpaHuKba2ai6obd+ZCWl7b0FbpqO
UA8W4fIIMU64UCJBWN89h5lnXfWVoBBoeJDf0xF0Q424qNv4EJGCN9HT8yvdbHCuTzPXP8xLO2DL
xucJ6ShhFdmosQzpOIiIjjU52spCTzTjkREvJJ1rZlmNu9D8bI6oSZRMOVraI4t9a20ySY7p3HWH
QA84G42rF3SyAtakhfNyGa3ZAf2HubfF86UUDFl/CVNH5QgTnVPJTddpABh0ZkXhqZa7Zt39KrBa
eP2IK0EqW6at1aEoodBPCOd0gx7W1XrTpkKER7Vgdlg04rHeHyCqWoVdFPMXnSrn8QoaQteH0uPM
DETgPuyNWXAT5gyXMF0uktf97VO9Eq/aBRr+POaYkrTbIl/ITYmlQyR2haJu189p/oCIbPPuWB1I
76kCtVnaCbcoekUE1BvAfjanax2eJmg4boLpStlAtOSKATLleYFNG0lAOPwo6PF2Stz/SAO+4+4d
3551HDBqL04+KnqtpFHk61Bo3XkA280secRxJn0OkM6qKsVVeQMoqVBCsyyMPwVLtvSpo5MuKsnN
H9sW3O/1u4CH3tqYfL/Lw1ZopQ6iTUnA3qYh7X1aflHHJTyY52IHfMUwCvbbg51dil3nrLPBDCCX
+YSzyqD351eRApn+CF0P3DhBV3edbYj2DbcyfnhVDSiYi/NyIntLIGiiG0W+2JCj59hvmylLQK5c
Mmv/2oj6pFwfO7/8XWipjUbJ2Dl3M1uvJBtmrm51TWHmcdD51qGmsF6czF+8kwPu3LriJFhT8/Jg
qAqcjRDqr8BuX0hnnO9u2nDyovTJBVnxkgPcIkNUeISuMOsmWIG9sSeu0URoAXhXIBcsRoaPSotL
MQX45nwma4aBQjxMGDMI0+GDF3Tb+1e7FapRhh2ZUGupEYaRvfjfBysTKaBzAPJy7SHpnHwH4vJC
ubR+aE6juj1v/fmVEn6JCPO9qJJvA63jxOGqVJTEAGD7q03VWF3jrEHMU3ze9IalfF5MYoiOB6DS
qQYsPUmvgW+grMTEueGQeR8QL5dY8R0uN/I9eYD5Qls4sexz3VLAArzA8QfCLi6SC53SBMik6HFa
uzmBkUYlRfJWdLfOvL3x4PxnbdJSAem45hA8tshMxfm0tAs/rskho8Gg4ZWiQY3WNcKlO7TaV/1f
/0p28LQ9ClyuZlvO6sKQfz0BvQkAwHtZKRCSG2PrHu/D2hw6FFVCsHYrUEni2LCSSbPvxZicTA20
9U0jAm2PXZrUobCYtje2ACkD7p1UdXHs2jW2XyEqPrzCyIa9DN0Uw+EKjBFrIeM3b2FzUzjLzD34
/9NpVY8a325TTWiCSM0N8J+ZA7SZcnAx5JZsax2Brl+WExBAKxYhZVY3r+GEXlGLaFN51CBQ/ZKS
Fidq2w9khP5rDvWXOd+2jPMuTCukUcIqMaM/BKlg3aeXLRFd3cs6Nao3msoPjaKR3rI8Axo3t1D9
3NNjLJQZl7eK54V5ozXY1r+VsEXunP4gHRZzjBk2KOaHSo6U+ZFKcCLsgwQBjPA9iDoEmfNW/v5T
MisoP8f4NTz4BlisDXodQ3a2LbMyxgYzZ69stWIqupZtzEyjLFmGn0AdUu1O3hJEnMIQ18iC6x6r
U/jy6Y3uYqa1lYr4DFJG/Jy0R7dXvX31JrSNhNEfXvPQ5FmPgF1orBzGtSjB2i8qkl863cNwfsxf
w1h5KF2HdCRw45S4PFDrdE2Bt9IqA139iKX3MNQUVkxvF6+uIWc91lMRWcA30leS7BhyIvedzjgS
XRH9wnmZw8JkW0L5Bybk9SE4HSAIs4KN/f6V0odBTywySmDbWIOmKL0BZDbudS1dOBeOiILAl1jX
xUUwrLnVP9p7dE7SEVJMvMJdMLdM4LRkh71DVOj+jE08SS84j+HUT56XEY61TJo72JdE5SPQSb4f
ckzbeRcbZyFvWvmiNQNMRMvKDy8CemWc/uyV3k+xumTtsBXKWA851zgEVqzb6yh6oJje49sag03j
vR+Z9XopigcF1Glcxx/FPN6SmYBoLE8uW305CDqGr6GufTdhf4HVtQHxBZd4baQ+2A6WRl7E6NYv
wcLml0k4h/eQRMxFEiij7uieLaTIPsNI8IDVMKS4xIeeTWGM6rdXJ0PBb/885qmehe+etJvX55Ya
cYpdi6UVII6wQYFCAS4XjbzdcuMrjarfwsfVyTN60sdEhv+HP/NzNdbYINJaw5wdUBSQ5a6T1lCs
i+H5dHJhCWhrl+H+34HB8+RJxHkXyhPvynYLmqCKqpa2lcBh3BqeUcxwTsxRXBj0jYysKAlkyfHW
Dw8fuCRpAWYukIaP0KoqmWlQVLUuqUmqPH7Zl9uu6krsxUf9Vr7RZ8FHtGVcf0KL75+OHzuHRX24
MgvC4j4Sf/OQq1JZa+lQv5r6Hy7cxvcuM9bzNa1Sc+N5mp1oLXFoHdUc99ZuNh3tmhlKzBPhtOkW
700kCmDcHxGM039xGqPy912vDH6YXwyWBD02jDDxLTMkXZ38/T4G7gUHRf0WjGsJ/088o+39NuzO
ooX61IszakvGjC6YHo1n2BvkcDaDgunLhlbcMg4/dAaFdkVsaXkVpp2Q7D7tTiZpgfWtsZjc5QW0
o//C60TX3gOiyKMApiQMe0Gl6UVq0V+XIq7Ia/sekqVkfJmcRw7/7LWp8+ZXwS1unbLghfFxQ6Cn
VGO4IcXd91DMl+5Q2ArstBXAQdLzPmJwpjaPjvNjNgqBD6CMmu8ZllLjaxfzIxyVLtAqwtp/Rc0n
ZwN83daTvnAG3U6ZIPctg/+HcHPpgiYWdrhdOwrH/7FeFGva6+kAnRb040ajr1R+LM9O3ggX07qU
kt6K1jcIQ1WxfBtdnIt75ro9/Mxl8iQw1P26LXCHc9Zv/Pq/ph9vpL4dXTmm7yrWahW8p2XCPkbw
aRRdQs3BmyqypqnwJYYzUPn3c7xywrB73oqNGgvdpSP19NO7OkWUxIYSRFOJ6YFfAwcDtGKGoLmt
sClU9CKDk0scfCpK5S4cGlrDiHxdZfrVSMuse3n7zgKTyfRofJEr2GL9Ckc/io+noJU/S9f/S8dl
Aj4HV5jnJ3SNSr/DGhwFMDn1ZG3FmIR6G0TJs0iJzQ/mreFvKA1FAEhgE2RB7FzuEKxzmPeIx3nn
IrFJFUpfHDRJURoY/KUwJsaxYgRFhVkH3fhq3R5x9YQX+4fVABqn1fP9d0zWnFZT0rudK/14QYlw
61Gy0Q1ZCwsWCD4SiHGD66pv4xspATRwTp1krZ9pOK5lL0B41Cn1yzs0tWd3YRmJf71qjck5SBOQ
TbbwrDYG1Tfq0Dk6o4FXHd1KwAYHkDda6I6HzrecnKU0tbnsitRcEB4kq2t8PD8XJxWe87eDhHxD
e3zG1rEbjS7eREbFq6O68WF7EMTZYWBS4/FPbIpI99dIArCdhtmBTjttBlikxAy8uqKqxKouIxtD
/5JsDNInX+acVysnwjv5GyYfogqCpeF55DTxN72g1x9TI7iWOO7vuVlxeKUWo9GdjfR3S/1vnHKw
7q8iP+b4fufvbK0fS9Z7gt5455cF28HMnCLKbIKeXITPKCUlClVZCRHbAs2+TkbD/KHLOZuj58MU
k6UOX+MgQBGPg7EpSsPxq+nGYj8I0JRtW6pBFxizzHbKhvIrSv01K45xnUXbj6xov1bKXRk5KpuG
/G3Fpt1yVl8hqyUiVzDiLqsXdIFG8wh7R2uCX8/Avi4VxJtOS6miMVC6P4Vw2zYQqllOd9/sKiEj
9GztXhdaFAc9g13h/bB5Ismd6+ymY8DBd5t//8H96JUn3lWZ+4E3Y5AX7FEbYjvoBBfHkt3HSbSq
rz38KxZ1w/M+uZV8Tq1vhW96sOJW6tPVoKQpSb9BiOHaqibJ+T0BVK2j37OY5gceDukKl3O+wqAD
wV6tm0mIFTHMtOyt+t10JEpqea+CknxbERITzAFjxxsuVMeoLSQyGEnBGtpgRgMA0KwmjqAVNaKo
//8wG63e5aKe1zSgsIgvphL2u2y68ZY9xRCxV9bLtGQbCB8Ih0FvbTreOXbMvt6ymScAVm7afup6
yTNFOhp5iED5Vy15rtE0exA0C2Ky6ThjlccaONZfcSWguHtcmUZjbMaSjZFy97i8LY7kjiXHA/Tc
GCoSAZ2cElD/WeEYE9XxL9d+5mtLeZkqkZrXFb1wWwOFisJFVOeqgUdGudSZKACPRh2kEws9RXcc
K+NIpLTKeKL2UZ+cSpQDynlJj5NJqmymJMHOLNASmXnN5t+vrm1Rzw8+OO6Ct4CxeVQo31FXdmr2
0R6sg3EDXrDEvKinhPa/6p43ILc9TbFOJI+2IWK8+qfpbmPJZucOADxjjMxYPoo69h6uSbACFNdE
2AKD2FwTHPqJJf0F1o7SQtMvmG4FmwekmGmzmgOWy2jcLYdxk9CnYeDqnu1i3J8WzJx3MzmEFi+c
QIfgoZXwxTambjG/NWPMrdzKZSD7k+pLGdPBIgM6l5FzHI5J4OAGXspRJN8OZC87Tm0M2Z0kh+GM
ctxDGpYUX7RziK6rqobXTMk6ui3aqHqawobe6BeUn/cc3QmQJQrOVhdj+0OSBtCnexdMw9Mm4myC
f6Z5qI3zjdNwvZsb2M/sAK+AqAYDCtz2eWjzA3Sb9CPtoeUnn6+ivPUx0nBq6k1FHBCDeDIPHhhi
hHUFYi0v192G2nBXNUs7b7SCnsvw+wmEKB4dfbBf4AITXPBh/xAkZY/8TxuSNfGFezapRHXcmv+5
wC4a4+KDmy3JycR2rbpEq/B3U5+NFdEghLk/n+lkPxFddVChnui2dDZFM89ovbS/RczOk2kZnV8o
BqzGSiaJnXJrFB3otwGezV5264J9TxVCU1ADHRZl/wMY7V9DX6oKLBqp4PDedDhscFbsc1F5xcZd
DeDruAn3ic7+geUEOXY1Vstdj+5W0D9lnpQKCU35j8Nl1EYY7RP5ZaKA9tJwdw1mIXok1kZLCx5Z
NSolPLSzBclmwyfqf45m/nrsC4b5rvSsa8QITbSF9jAXYsJROz3VhytW1xSRtvcaywVL2p4x7W2P
b+Cq2YpV9m83ZIzWiaQPKIkgTJ9oqkKg64G3M3OJVoSFgD8SktlVMb1rJmZ4+qRR++m8eThzXK/P
TPlSoZYFOxRcBl6b29K89pCarYL/2g+b8gSJfO8i1/ZS+fPTmUMEW91RaHwr4cdCVOWTQV2AsZTD
I07nd0F4bUUnNOfwGcYMoqBOzY+Bj+iqssEAWpnLIgvlH67irSEUbiTd4z+ytie6bEujXuca4nFV
IzELW4lo3MFOjPet3gPMurfZvSI3odoX2s1VsuRnrZW9lz/cFA7p3M8VrxIdJI6vdfXyGlVY96JD
esltaTT++REQG0VQrRrqLPi+e0/YFYfm6Qo8MeelitpHlCexFc96NfGHEcPhc3QVHqE2nk+RmRzg
SM+jxPZnvGWb/oZclVVKbpE75CAkwOLoKoKfLi1gMwKg4R5uNqGO7WevMdKHMp9jNFnaXCfsd/nm
+EPOgmm2x1WCdvZDhMbB5GGQy2rZtvylqGEPJpZWgppZr2bLuyPgzOQHgOO8erO5ELAdpHPzjw7A
VL3DQKBUsWaP/Sf6CKtU0kJO8j//2UUeRX315e6JyqYNGBDNbGpoW72Ufy/EIm9dqjEJnrJVqals
XChcFGMJfPxBxSMAek+5JKnQ2s8omByexF9SBWxGpgteZrnapyXVARfKPpmEVOA4M7AJDUE4OLIu
e5c297I7PcvuCa19IFzw768eQgnn8pElskdqHZSPJE0Yi8NRLLXW2nqD5xcAeCVxPg7AnJFwlCJH
XX2Il5pIVGDgmTNyY9+a+8VdH/lvXKjh9sEcGCBuz817Mws+Kj7k9PYvFZZZJMnL5/kAI3HCS04e
RZFI7Oywpgq3i3AL0F9b30A7CcjgjpNDyj9API5m1mkXeyA4/b3qv2h3jBeWfdCLSjGzchb0fUFM
mnZFklw0DGClwzgH5y5TexB/EX7JS3TkdmMXYj2/UTL2S9HwIaC8C7IDryIoUBk2zwOGqVlmzhe2
UAI9hEzuvY2OXie7+zpk8gk88wdIPv6kH2sR3zCdGydp1wIxTDOfjEzg4VIo5QfWA5sfOQuAL297
u4/VvHaO/0e44sCtMzyXxjwguFUfO5BjzrdhUFv5Ii38ms9PRAjm1epPfREeE5Bi6yNk5s6GyoBA
Q1Haz5fjJLZ5SDgdtQxNg2wCnI8Gk3x4+ijcvu54RysAJaVzHcwHDUwOhQiwNZP56JqSek59e93q
NZEqiUGhriE1XHE8jBTQJNA3fy4ietluXe7x4VMj8nb6Q5QmvSJV9663rjEDfkVRtS2v83AE9Wp1
FgLzt56m+5hijuEc8UtTTymivw1f6aNU9WNhlP1ktUZLYMUgUjKW+GEiOjThB6m5s1s5rCYjqUGk
r5bmkCVniUYdxmwVbyW4zxm0Fsyn8iOWbkdBVV9hmRKSGDqsAF8JkI5qvvY8r++tNcjnFgRJBnVT
HFdfxq/ik/RQ5Tvhkfv2XJE5K/Nulb75AXQ9yfl0CNWbdxrpf7Jnyq5kASBuAvj/Yy1EygF8f5Wa
0aEckqe5rOsIseLvwdLsNvBHHTP0egQjic7QqitXz3nlVj/PQ7mYwB74QrV8PGOSwl0U75b5JSX6
BO3qd8lLrrGr8Q4nh+psyZKhzuAa1YKvMguw6F9N+PAg2q1wrx96Y8ABITa3/G6pt3gCvaUI4M9d
c2Cv8+UxYvrr27jGL41qTeSn3IubQVQEYRXcOMenPAMHlaKgnqU6G9VpHiX6fpXhSX7m/KCWBTFz
v8LlIiDMeUfv8SNPnyXoXU0iEvdta2Zw3PD7MxyuBbFRx95uWghvYrArqhKzVdcVoeLxRZt0iD9M
e4o5axou2ipj8NYH0LPPhd+Oarmn721t32FjO8IsRwm2irjkI4pnp4/7ZYvSy0OH657YXqBSNOWZ
IZVZQGIvVqv+310Vmrcv8TO6HTyI+H9pM0A6Mx98FSMcbofNSG5bM+e80Pi3MZuc64T51dFVnti2
Tkbg/n3vswBAGEU25/gWg/eKmwnXmaxgHMVkJYPn4ktOcxFjpe9M/zXBmSxgu11xrj2xg1kDU1X2
N1M58Ej6VxzevCblCu5CYLU+xszE+dK5z1DQjOCKiXmlYFDZFiqKCKp2dIT8B3hgzUlM/WRCofXM
dij23uWkLbP1nRprLwe32Ov2acJwPPXHit1tmMpNIVAC0cnsFmNrWQqiX9UpXVKUn+FahY2ypqaT
81IDe517Z4wu3KkvB4Pvs+dHqTnnpHp33nMLUM8O104nhduG7HmKiRMOTX2OXG8t5j7Cb4ezKPfA
RlQ/DMFIp+N2R6/Iq5w0Nj+ECMfpScy9rPKC2W70NCs3R1Lp/WLoLbPS8Z45GPxSyJJbk0dVxrbV
++UfHuOJ0Y01CBQ+8M3lRnmUTZtRJzjYLHrkDzFLxUQwtjB8sIi1QJpSC290bpLENfqtxJ15YoSx
yY13ZQ4TPZfjsFYPQIqipUhUiPtzQxKvaRgAWCIyXg8gdCbXjGK5TMuPi/xCUa3wtWCcKCZtDJEB
+4HQG6EUI70f7YEVc9ESImpdoGxh/pMJhM7UF62Nm3tWlfLTWiI2KrPr3G8nAY4fxGQ5A9HajS0f
j+qcMqhVLF9P372STEaICvGsnJyGdI7sw2tQOlsslmG2hk4nAIx5A1PlxryhrUm6ALKsDKHpI2M2
eeBW3DSommZEyHRYGjSdPwACJa6b7eP7QdRVd18h0oK66BVGB3Pgtro2nnSTCk0oX/qGbB1fxerU
SjpRVHHfgpHJTEUigdkMDMpkB6qubYp3zS6oYIucJSilkFn58HZQO4y4PR5SCZF3VU9CFMe/WJew
YPiZ7nZliktTvyl/P9Ms968Z3pvkhfz1wiSd4aSb8p7cL/jOkpUIx9xw7D3qOIm0oN+MnIIqXeyQ
E+K1EmHlbkhfkxH5oIbeTXjfyDRNXKb9bN4AsQyB8kR3YNeeBRmoB3fYHdDfw3Fd6jpoRGjI4XJm
Xz5dWXbDxwdBmGF0R0OczOmzl2iaumXx9IwTlzK/xryRltTC9jvV39ap1ZiC/9WFNAyOP7Nk0G60
0uYfqJGHlB7EGXxCZ2eu9Pz9HVHT87C+tqoj9f9xZEQtbrs2tN49sCdGUa3+jlwP3rLt1xTtW6wI
EAbFrpWGzMstwsmYm/qD5emjjM5oSdyg4W95f+5Tmhm3u4dwZgLPAwPJlGgLcoiyFNF9L0wHSGRI
LPataXZh8Uk0m6tGPSl7TkBU6ii6cnWdRb+R8yG9iCjq0AQyhGmbJgmUdtgpLkHmdVwmgpK5vKmU
HfaJl1bLCxvYbl2S2dqsLb22+3rF/+VM2L65ReNqC8jYbd26Y2wVwVzM0F5A8BPNvH1k4fz/LmZY
axLCGQipFsDBImjWEQjoJzDDRoXOUe5cPeO/EZAQFB+Q//4A6tu0eJXSpWSSve8G5OrGrq36cu4E
IIngDNqQDlCN6ypenNEkPdhshTUGv5BSa8O8zSZK5nY+hnqB8c5/PhXyfJO/YrCUUaYfmhRw/bMX
K0qoCXqHNsWOWYTmbYLnf/N1nZR+nCLnCCID7OdltNy1tnsOBxoxivPnmv6VKpSFmeEX3HSgGrqd
YNLAQijyGuRIUXrXO4PpadOFdh++0bBfAHzyImD19sPQzRT5GVmkXYjmi44IyLbGYsyxVlPiCx8o
LNniHdKjWhfQUKytLWX7S7BM+MKU9+C8wnOmvpqmCoDFtL+IPUnFQthDR0WSyJf6quTFHAl+ZPiB
fuiYnoqYWQcpyIgZsyhiyweEJhAMn2KG8NMRJVi5k4YrKP/5Am1upEl02RAeX8ef5QZlge4xmHW8
YlsdwJLWfrkLIZEN8UoAIEtBXRlsvxnp8vK7CkNnFJgaT7fLCy4LBHZ2nbWG2RfUhe196wMgFaaU
ENCx78VWMYlUZ9khM7EBnxpTjBqQdQrENzEkNfVWZpQpBm0idwHo9jNM2XuV3XagazjJd+jU2hM4
jIv2ypf2nw/om1CdlEFogb+rECZDeBMUeWT2IGKr2yDEvoOMg3f6phnCaQdLt7/GBIJ5aW2kvdKs
G86UFmFwTEG1Y1BgVKnoyHG3OxgDa22Rs4zVamZQYtmob28FnryJwmpzyKsRaMCOvt9mqcIYeTSl
Qtoetyd0SFo9LBbvz94kHfgf37aYpYB8BUuqRigajBEKwFm/+4nDk8LzjJ7jocKSVECG6Gfk1TlM
rq8jjbLR5rY4cZ5QtzsZyUlwywE0UpnRutayaeDn7MIx62iH7wpgv2uCM3Ulj8BJQdT3K0HgeHvE
DoQ1fs0yZ+RvvmflCAGZjHqB+5savcC4WBwjKdAvi3MDZrqUrIS/u8W/Po6WUxF7TrYFG87cTkXM
K1IMa0rUu2kLMxT+exSr0FNwsi69TwkMPaK4h7x0UF+uGRZRgtzP8x0MZSCslmOfb26ei8MmRY2q
XZHiTdrK+JVD9EedfENI+Q9zc0hrgaTo3NRf27vNU8ZUEApsGTSJOUbLW+jcZDVAsKEXXInkuxcz
AGpwaxnRJ0kNjsDZZchW7jjJJI8OSerhcGbUFUeBdCBDUCcIMGmGPTfdgltjZX8P+bM4xipd7a2y
2hYYMtVbpxBjpyHxBLIqk4ToDBfwz+MR3TC8Yftn34qEyaLbaHnigItjKRCjDB/yEDJd8qw+rsvc
i+Qbng1bTWpcJstn3OnEP77mWZ47zC8/UmLMJjfC40VBNxlH4yBKriCIhQOCLbNKO0hVDkibSny/
En/2UyEbzbiqWjv29YSa18Y+iv6WgyaQb9bCIhNhJErWdeh33UW86tnRBZgoOMohcFFIX0p/jZt6
eaLl5qHMHdQmgwsOIOBebX2gtIKaAPFBRYEebLkeAWjMTx626QbG5njkB1bqUwHo+Nafbd4sBw+j
UcLKNJpJR/AbbFwkHqw3nBv5f06zLTRrFe3tLlcexFGqNHEstU5hMxCnmLbuPDm1vNnqxihP+rmt
neIFUBO2I+hym81AswSpRxQpZ+5cpknTbfLwXmC7Q872Tr/SSeQtIKGu1prDPQ/Uhzotbc8qDE7j
J2J/zYza4wepX37S2podyJbeG9DA2313X5dVk8sNHe5zCwC3AuElMDiB+uRstpN5ENtbU0XeXG7k
S1H9Kko8u81p/73xyu6MeT2EuSzgDB6zPrnMZvfG0RfbK28iCDXO0177DiPsA67Zi0rcjdXTZ3zr
Upxum0U31TQrxTMxiWSehFMSjpBpWAEUbCLYs75seGbO8osjdUcmTHcUlsRWBEfjY81R5OefsbSP
mHi+L6J8M/7CL0kVVAX55A4mueeCh5CPbNd/sBtmTtu2KHzpCZVHQf3zLLrWGxGKVLaE1Cfl8cQn
qQcKlwbp7JyLqKbMAtWO6pQIXy7fGF7iaCOEN6AFAz29F9j4dgGTv/0Bkv5v+LRXsq9xe4gvq70L
jgLzH2a8d8DeYdopnYUZEwR3kPbcs+7kKwwl5jyBzX60O1ykJIs2MdizlawNp/c=
`protect end_protected
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00116.vhd | 1 | 5934 | -- NEED RESULT: ARCH00116.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00116: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00116: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00116
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00116(ARCH00116)
-- ENT00116_Test_Bench(ARCH00116_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00116 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00116 ;
--
architecture ARCH00116 of ENT00116 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00116.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00116" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00116" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00116" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
--
end ARCH00116 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00116_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00116_Test_Bench ;
--
architecture ARCH00116_Test_Bench of ENT00116_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00116 ( ARCH00116 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
) ;
end block L1 ;
end ARCH00116_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00151.vhd | 1 | 16749 | -- NEED RESULT: ARCH00151.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151.P2: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151.P3: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00151
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00151(ARCH00151)
-- ENT00151_Test_Bench(ARCH00151_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00151 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00151 ;
--
architecture ARCH00151 of ENT00151 is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00151 ;
--
entity ENT00151_Test_Bench is
end ENT00151_Test_Bench ;
--
architecture ARCH00151_Test_Bench of ENT00151_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00151 ( ARCH00151 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00151_Test_Bench ;
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00546.vhd | 1 | 2484 | -- NEED RESULT: ARCH00546: Architectural library name visibility test failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00546
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (11)
-- 10.3 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00546(ARCH00546)
-- ENT00546_Test_Bench(ARCH00546_Test_Bench)
-- CONF00546
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
-- 19-JAN-1987 - replaced selected name WORK.ARCH00546 with simple
-- name ARCH00546
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00546 is
generic ( G : Integer := 0 ) ;
port ( P1 : in Boolean ; P2 : out Boolean ) ;
end ENT00546 ;
--
architecture ARCH00546 of ENT00546 is
begin
process (P1)
begin
P2 <= transport Not P1 ;
end process ;
end ARCH00546 ;
--
entity ENT00546_Test_Bench is
end ENT00546_Test_Bench ;
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00546_Test_Bench of ENT00546_Test_Bench is
signal S1, S2 : boolean := false ;
signal S3 : boolean := true ;
component Comp1
generic ( G : Integer := 0 ) ;
port ( P1 : in boolean ; P2 : out boolean ) ;
end component ;
for CIS1 : Comp1 use entity WORK.ENT00546 ( ARCH00546 );
-- reference in binding indication
component Comp2
port ( P1 : in boolean ; P2 : out boolean ) ;
end component ;
begin
CIS1 : Comp1
generic map ( open )
port map ( S1, S2 ) ;
Blk :
block
begin
CIS1 : Comp2
port map ( S2, S3 ) ;
end block Blk ;
process
begin
wait for 10 ns ;
test_report ( "ARCH00546" ,
"Architectural library name visibility test" ,
(Not S1) and S2 and (Not S3) ) ;
wait ;
end process ;
end ARCH00546_Test_Bench ;
--
configuration CONF00546 of WORK.ENT00546_Test_Bench is
for ARCH00546_Test_Bench -- reference in a configuration
for Blk
for CIS1 : Comp2
use entity WORK.ENT00546 ( ARCH00546 )
-- reference in a binding indication
generic map ( G => open )
port map ( P1, P2 ) ;
end for ;
end for ;
end for ;
end CONF00546 ;
--
| gpl-3.0 |
grwlf/vsim | vhdl_ct/ct00586.vhd | 1 | 27065 | -- NEED RESULT: ARCH00586: Attribute declarations - composite dynamic subtypes with dynamic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00586
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00586)
-- ENT00586_Test_Bench(ARCH00586_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
--
architecture ARCH00586 of E00000 is
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
variable correct : boolean := true ;
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00586" ,
"Attribute declarations - composite dynamic subtypes"
& " with dynamic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
end p2 ;
begin
process
begin
p2 ;
wait ;
end process ;
end ARCH00586 ;
--
entity ENT00586_Test_Bench is
end ENT00586_Test_Bench ;
--
architecture ARCH00586_Test_Bench of ENT00586_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00586 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00586_Test_Bench ;
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/oneshot/oneshot.vhd | 1 | 2021 | -- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity oneshot is
generic (SIZE : positive := 12);
port(
CLK : in std_logic;
RESET : in std_logic;
ONESHOT_IN : in std_logic;
ONESHOT_OUT : out std_logic );
end oneshot;
architecture rtl of oneshot is
signal COUNTER : unsigned(SIZE-1 downto 0);
signal ONES : unsigned(SIZE-1 downto 0);
signal LOCK : std_logic;
begin
ONES <= (others=>'1');
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
LOCK <= '0';
COUNTER <= (others=>'0');
else
if ONESHOT_IN = '1' then
LOCK <= '1';
end if;
if LOCK = '1' then
if COUNTER /= ONES then
COUNTER <= COUNTER + 1;
else
LOCK <= '0';
COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
ONESHOT_OUT <= LOCK;
end rtl;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05600_good.vhd | 1 | 3378 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05600_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of combinational feedbacks: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity STD_05600_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_A : in std_logic; -- First Mux input
i_B : in std_logic; -- Second Mux input
i_Sel : in std_logic; -- Mux selector
o_O : out std_logic -- Mux output
);
end STD_05600_good;
architecture Behavioral of STD_05600_good is
signal Mux_Sel : std_logic; -- Combinational select
signal Mux_Sel_r : std_logic; -- Synchronized select
signal O : std_logic; -- Module output
begin
Mux_Sel <= i_Sel and O;
-- Synchronizes the Mux_Sel signal to avoid combinational feedback
DFF : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => Mux_Sel,
o_Q => Mux_Sel_r
);
-- Combinational Mux selecting A or B depending on Mux_Sel_r value
Mux1 : Mux
port map (
i_A => i_A,
i_B => i_B,
i_S => Mux_Sel_r,
o_O => O
);
o_O <= O;
end Behavioral;
--CODE
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/reg_bank.vhd | 1 | 16427 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--Uncomment following two lines for Xilinx RAM16X1D
library UNISIM; --Xilinx
use UNISIM.vcomponents.all; --Xilinx
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable tri_port_ram : ram_type;
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type;
variable dual_port_ram2 : ram_type;
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
begin
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end generate; --xilinx_16x1d
-- Option #4
-- Altera LPM_RAM_DP
-- Xilinx users may need to comment out this section!!!
altera_mem:
if memory_type = "ALTERA_LPM" generate
lpm_ram_dp_component1 : lpm_ram_dp
GENERIC MAP (
lpm_width => 32,
lpm_widthad => 5,
rden_used => "FALSE",
intended_device_family => "UNUSED",
lpm_indata => "REGISTERED",
lpm_wraddress_control => "REGISTERED",
lpm_rdaddress_control => "UNREGISTERED",
lpm_outdata => "UNREGISTERED",
use_eab => "ON",
lpm_type => "LPM_RAM_DP"
)
PORT MAP (
wren => write_enable,
wrclock => clk,
data => reg_dest_new,
rdaddress => addr_read1,
wraddress => addr_write,
q => data_out1
);
lpm_ram_dp_component2 : lpm_ram_dp
GENERIC MAP (
lpm_width => 32,
lpm_widthad => 5,
rden_used => "FALSE",
intended_device_family => "UNUSED",
lpm_indata => "REGISTERED",
lpm_wraddress_control => "REGISTERED",
lpm_rdaddress_control => "UNREGISTERED",
lpm_outdata => "UNREGISTERED",
use_eab => "ON",
lpm_type => "LPM_RAM_DP"
)
PORT MAP (
wren => write_enable,
wrclock => clk,
data => reg_dest_new,
rdaddress => addr_read2,
wraddress => addr_write,
q => data_out2
);
end generate; --altera_mem
-- Option #5
-- dual_port_mem_coregen:
-- if memory_type = "DUAL_PORT_XILINX" generate
-- reg_file_dp_ram_1: reg_file_dp_ram
-- port map (
-- addra => addr_read1,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out1,
-- web => write_enable);
--
-- reg_file_dp_ram_2: reg_file_dp_ram
-- port map (
-- addra => addr_read2,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out2,
-- web => write_enable);
-- end generate; --dual_port_mem
-- dual_port_mem_xc4000xla: if memory_type = "DUAL_PORT_XILINX_XC4000XLA" generate
-- reg_file_dp_ram_1: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read1,
-- SPO => open,
-- DPO => data_out1);
--
-- reg_file_dp_ram_2: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read2,
-- SPO => open,
-- DPO => data_out2);
-- end generate; --dual_port_mem
-- Option #6
-- Generic Two-Port Synchronous RAM
-- generic_tpram can be obtained from:
-- http://www.opencores.org/cvsweb.shtml/generic_memories/
-- Supports ASICs (Artisan, Avant, and Virage) and Xilinx FPGA
-- generic_mem:
-- if memory_type = "OPENCORES_MEM" generate
-- bank1 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read1,
-- di_a => ZERO,
-- do_a => data_out1,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
--
-- bank2 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read2,
-- di_a => ZERO,
-- do_a => data_out2,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
-- end generate; --generic_mem
-- Option #7
-- Xilinx mode using four 16x16 banks
-- xilinx_mem:
-- if memory_type = "XILINX" generate
-- bank1_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank1_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
-- end generate; --xilinx_mem
end; --architecture ram_block
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/vram/vram.vhd | 1 | 6064 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/alf/src/cpu/T80.vhd | 2 | 32378 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/cham_rom_synth.vhd | 1 | 6828 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY cham_rom_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE cham_rom_synth_ARCH OF cham_rom_synth IS
COMPONENT cham_rom_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: cham_rom_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/internalromram.vhd | 1 | 3597 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY internalromram IS
GENERIC
(
internal_rom : integer := 1;
internal_ram : integer := 16384
);
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
ROM_REQUEST_COMPLETE : out STD_LOGIC;
ROM_REQUEST : in std_logic;
ROM_DATA : out std_logic_vector(7 downto 0);
RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
RAM_WR_ENABLE : in std_logic;
RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RAM_REQUEST_COMPLETE : out STD_LOGIC;
RAM_REQUEST : in std_logic;
RAM_DATA : out std_logic_vector(7 downto 0)
);
END internalromram;
architecture vhdl of internalromram is
signal rom_request_reg : std_logic;
signal ram_request_reg : std_logic;
signal ROM16_DATA : std_logic_vector(7 downto 0);
signal ROM8_DATA : std_logic_vector(7 downto 0);
signal ROM2_DATA : std_logic_vector(7 downto 0);
signal BASIC_DATA : std_logic_vector(7 downto 0);
begin
process(clock,reset_n)
begin
if (reset_n ='0') then
rom_request_reg <= '0';
ram_request_reg <= '0';
elsif (clock'event and clock='1') then
rom_request_reg <= rom_request;
ram_request_reg <= ram_request;
end if;
end process;
gen_internal_os_b : if internal_rom=3 generate
-- d800 to dfff (2k)
rom2 : entity work.os2
PORT MAP(clock => clock,
address => rom_addr(10 downto 0),
q => ROM2_data
);
-- e000 to ffff (8k)
rom10 : entity work.os8
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => ROM8_data
);
process(rom_addr)
begin
case rom_addr(13 downto 11) is
when "011" =>
ROM_DATA <= ROM2_data;
when "100"|"101"|"110"|"111" =>
ROM_DATA <= ROM8_data;
when others=>
ROM_DATA <= x"ff";
end case;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os_loop : if internal_rom=2 generate
rom16a : entity work.os16_loop
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
ROM_DATA <= ROM16_DATA;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os : if internal_rom=1 generate
rom16a : entity work.os16
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
basic1 : entity work.basic
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => BASIC_data
);
process(rom16_data,basic_data, rom_addr(15 downto 0))
begin
ROM_DATA <= ROM16_DATA;
if (rom_addr(15)='1') then
ROM_DATA <= BASIC_DATA;
end if;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_no_internal_os : if internal_rom=0 generate
ROM16_data <= (others=>'0');
rom_request_complete <= '0';
end generate;
gen_internal_ram: if internal_ram>0 generate
ramint1 : entity work.generic_ram_infer
generic map
(
ADDRESS_WIDTH => 19,
SPACE => internal_ram,
DATA_WIDTH =>8
)
PORT MAP(clock => clock,
address => ram_addr,
data => ram_data_in(7 downto 0),
we => RAM_WR_ENABLE,
q => ram_data
);
ram_request_complete <= ram_request_reg;
end generate;
gen_no_internal_ram : if internal_ram=0 generate
ram_request_complete <='1';
ram_data <= (others=>'1');
end generate;
end vhdl;
| gpl-3.0 |
peteut/nvc | test/regress/issue349.vhd | 2 | 652 | entity issue349 is
end issue349;
architecture RTL of issue349 is
type WORD_TYPE is record
DATA : bit_vector(7 downto 0);
VAL : boolean;
end record;
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
VAL => TRUE);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
signal curr_queue : WORD_VECTOR(0 to 1);
begin
curr_queue <= (others => WORD_NULL);
process is
begin
wait for 1 ns;
assert curr_queue = (0 to 1 => WORD_NULL);
wait;
end process;
end RTL;
| gpl-3.0 |
peteut/nvc | test/sem/issue246.vhd | 2 | 134 | package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
| gpl-3.0 |
peteut/nvc | test/sem/issue197.vhd | 3 | 567 | entity entity_attr is
constant MIN_DELAY : NATURAL := 42;
attribute DELAY : NATURAL;
attribute DELAY of entity_attr : entity is MIN_DELAY;
end entity;
architecture foo of entity_attr is
begin
end architecture;
entity issue197 is
end entity;
architecture foe of issue197 is
constant fumble: natural := work.entity_attr'DELAY;
begin
alu_div_0:
entity work.entity_attr ;
MONITOR:
process
begin
assert fumble = 42;
assert work.entity_attr'DELAY = 42;
report '.' & 'A';
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/bounds/issue99.vhd | 5 | 321 | entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
| gpl-3.0 |
peteut/nvc | test/regress/slice2.vhd | 6 | 854 | entity slice2 is
end entity;
architecture test of slice2 is
procedure set_it(signal v : out bit_vector(7 downto 0);
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
procedure set_it2(signal v : out bit_vector;
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
signal vec : bit_vector(7 downto 0);
begin
process is
begin
set_it(vec, 3, 0, X"a");
wait for 1 ns;
assert vec = X"0a";
set_it(vec, 4, 1, X"f");
wait for 1 ns;
assert vec = X"1e";
set_it2(vec, 7, 4, X"f");
wait for 1 ns;
assert vec = X"fe";
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/elab/ifgen.vhd | 5 | 472 | entity sub is
generic (
foo : boolean := true );
port (
x : out integer );
end entity;
architecture test of sub is
begin
g: if foo = true generate
x <= 5;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity ifgen is
end entity;
architecture test of ifgen is
signal x : integer;
begin
sub_i: entity work.sub
port map ( x );
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/elab8.vhd | 5 | 1228 | entity sub is
port (
foo : out bit_vector(1 to 3) );
end entity;
architecture test of sub is
begin
process is
begin
foo <= "101";
wait for 10 ns;
foo <= "010";
wait for 10 ns;
foo <= "100";
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab8 is
end entity;
architecture test of elab8 is
signal bar : bit_vector(1 to 3);
signal a, b, c : bit;
begin
sub1_i: entity work.sub
port map (
foo(1) => bar(3),
foo(2) => bar(2),
foo(3) => bar(1) );
sub2_i: entity work.sub
port map (
foo(1) => a,
foo(2) => b,
foo(3) => c );
process is
begin
wait for 1 ns;
assert a = '1';
assert b = '0';
assert c = '1';
assert bar = "101";
wait for 10 ns;
assert a = '0';
assert b = '1';
assert c = '0';
assert bar = "010";
wait for 10 ns;
assert a = '1';
assert b = '0';
assert c = '0';
assert bar = "001";
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/case7.vhd | 2 | 867 | entity case7 is
end entity;
architecture test of case7 is
constant C1 : bit_vector(3 downto 0) := X"1";
constant C2 : bit_vector(3 downto 0) := X"2";
signal x : bit_vector(7 downto 0);
signal y : integer;
begin
process (x) is
begin
case x is
when C1 & X"0" =>
y <= 5;
when C1 & X"8" =>
y <= 6;
when C2 & X"0" =>
y <= 10;
when others =>
y <= 0;
end case;
end process;
process is
begin
x <= X"10";
wait for 1 ns;
assert y = 5;
x <= X"18";
wait for 1 ns;
assert y = 6;
x <= X"20";
wait for 1 ns;
assert y = 10;
x <= X"21";
wait for 1 ns;
assert y = 0;
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/elab/issue153.vhd | 5 | 290 | entity issue153 is
end entity;
architecture test of issue153 is
signal s, t : bit_vector(7 downto 0);
begin
g1: for i in s'range generate
s(i) <= s(i - 1);
end generate;
g2: for i in s'range generate
t(i - 1) <= s(i);
end generate;
end architecture;
| gpl-3.0 |
peteut/nvc | test/sem/const2.vhd | 4 | 229 | package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
| gpl-3.0 |
peteut/nvc | test/simp/issue345.vhd | 1 | 966 | package pkg is
function func (s : string) return natural;
function func2 (s : natural) return natural;
function func3(x : integer) return integer;
end package;
package body pkg is
function func(s : string) return natural is
function inner_func return natural is
begin
return s'length;
end;
begin
return inner_func;
end;
function func2(s : natural) return natural is
function inner_func return natural is
begin
return s;
end;
begin
return inner_func;
end;
function func3(x : integer) return integer is
function inner(n : integer) return integer is
begin
return x + n;
end function;
begin
return inner(2);
end function;
end;
use work.pkg.all;
entity bug is
end entity;
architecture a of bug is
begin
main : process
begin
assert func("") = 0;
assert func("abc") = 3;
assert func2(10) = 10;
assert func3(5) = 7;
wait;
end process;
end;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_M_AXI_GP1_ACLK_100M_0/proc_sys_reset_v5_0/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
dcsun88/ntpserver-fpga | vhd/hdl/io.vhd | 1 | 8386 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : io.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-21
-- Last update: 2016-08-17
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: GPIO tri-state buffer and clock domain transfer
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-21 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--
-- Address range: 0x412_0000 - 0x4120_0004
-- | 1 | 0 |
-- |5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
-- default T T T T T T T T 0 0 T 1 T T 1 1
--
-- 0x4120_0000 | gpio |d|a| |g| |l|p|o| Read/Write
-- | | | | | |
-- | | | | | OCXO enable (power) R/W
-- | | | | PLL reset bar R/W
-- | | | PLL Locked R
-- | | GPS enable (power) R/W
-- | DAC Controller enable R/W
-- Display controller enable R/W
--
-- 0x4120_0004 | | | Tri state control
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity io is
port (
fclk_rst_n : in std_logic;
fclk : in std_logic;
rst_n : in std_logic;
clk : in std_logic;
-- fclk
GPIO_tri_i : out std_logic_vector (15 downto 0);
GPIO_tri_o : in std_logic_vector (15 downto 0);
GPIO_tri_t : in std_logic_vector (15 downto 0);
-- clk
locked : in std_logic;
dac_ena : out std_logic;
dac_tri : out std_logic;
disp_ena : out std_logic;
-- fclk
pll_rst_n : out std_logic;
ocxo_ena : inout std_logic;
gps_ena : inout std_logic;
gps_tri : out std_logic;
gpio : inout std_logic_vector (7 DOWNTO 0)
);
end io;
architecture rtl of io is
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal gpio_o_d : std_logic_vector (15 downto 0);
signal gpio_t_d : std_logic_vector (15 downto 0);
signal reset_n : std_logic;
signal ocxo_ena_tri : std_logic;
signal ocxo_pwr_ena : std_logic;
signal ocxo_pwr_on : std_logic;
signal ocxo_on_ctr : std_logic_vector(12 downto 0); -- 25 us turn on
signal gps_ena_tri : std_logic;
signal gps_pwr_ena : std_logic;
signal gps_pwr_on : std_logic;
signal gps_on_ctr : std_logic_vector(12 downto 0);
attribute keep : string;
attribute keep of gps_pwr_ena : signal is "true";
begin
-- Generic gpio interface output register
io_oreg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o, gpio_o_d);
io_treg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_t, gpio_t_d);
-- gpio control interface
-- gpio(0)
ocxo_ena <= gpio_o_d(0) when gpio_t_d(0) = '0' else 'Z';
xtal_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, ocxo_ena, GPIO_tri_i(0));
xtal_pwr: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(0), ocxo_pwr_ena);
-- gpio(1)
reset_n <= gpio_o_d(1) and fclk_rst_n;
GPIO_tri_i(1) <= reset_n;
pll_rst_n <= reset_n;
-- gpio(2)
pll_lock: delay_sig generic map (2) port map (fclk_rst_n, fclk, locked, GPIO_tri_i(2));
-- gpio(3)
GPIO_tri_i(3) <= '0';
-- gpio(4)
gps_ena <= gpio_o_d(4) when gpio_t_d(4) = '0' else 'Z';
loc_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, gps_ena, GPIO_tri_i(4));
-- gpio(5)
GPIO_tri_i(5) <= '0';
-- gpio(6)
gpio_dac_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(6), dac_ena);
GPIO_tri_i(6) <= GPIO_tri_o(6);
-- gpio(7)
gpio_disp_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(7), disp_ena);
GPIO_tri_i(7) <= GPIO_tri_o(7);
-- gpio(15 downto 8)
io_tri: for i in 8 to 15 generate
begin
--io_tri_iobuf: component IOBUF
-- port map (
-- I => GPIO_tri_o(i),
-- IO => gpio(i),
-- O => GPIO_tri_i(i),
-- T => GPIO_tri_t(i)
-- );
gpio(i - 8) <= gpio_o_d(i) when gpio_t_d(i) = '0' else 'Z';
end generate;
io_ireg: delay_vec generic map (1) port map (fclk_rst_n, fclk, gpio, GPIO_tri_i(15 downto 8));
--gpio(0) <= gpio_o_d(8) when gpio_t_d(8) = '0' else 'Z';
--gpio(1) <= gpio_o_d(9) when gpio_t_d(9) = '0' else 'Z';
--gpio(2) <= gpio_o_d(10) when gpio_t_d(10) = '0' else 'Z';
--gpio(3) <= gpio_o_d(11) when gpio_t_d(11) = '0' else 'Z';
--gpio(4) <= gpio_o_d(12) when gpio_t_d(12) = '0' else 'Z';
--gpio(5) <= gpio_o_d(13) when gpio_t_d(13) = '0' else 'Z';
--gpio(6) <= gpio_o_d(14) when gpio_t_d(14) = '0' else 'Z';
--gpio(7) <= gpio_o_d(15) when gpio_t_d(15) = '0' else 'Z';
-- The ocxo dac 50 us tristate enable delay
ocxo_tristate:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
ocxo_pwr_on <= '0';
dac_tri <= '1';
elsif (clk'event and clk = '1') then
if (ocxo_pwr_ena = '0' or ocxo_pwr_on = '1') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
else
ocxo_on_ctr <= ocxo_on_ctr - 1;
end if;
if (ocxo_pwr_ena = '0') then
ocxo_pwr_on <= '0';
elsif (ocxo_on_ctr = 1) then
ocxo_pwr_on <= '1';
else
ocxo_pwr_on <= '0';
end if;
if (ocxo_pwr_ena = '0') then
dac_tri <= '1';
elsif (ocxo_pwr_on = '1') then
dac_tri <= '0';
end if;
end if;
end process;
--loc_pwr: delay_sig generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o(4), gps_pwr_ena);
-- Duplicate output buffer for enable
gps_ena_dup:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_pwr_ena <= '0';
elsif (fclk'event and fclk = '1') then
gps_pwr_ena <= GPIO_tri_o(4);
end if;
end process;
-- The gps rs232 tx 50 us tristate enable delay
gps_tristate:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
gps_pwr_on <= '0';
gps_tri <= '1';
elsif (fclk'event and fclk = '1') then
if (gps_pwr_ena = '0' or gps_pwr_on = '1') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
else
gps_on_ctr <= gps_on_ctr - 1;
end if;
if (gps_pwr_ena = '0') then
gps_pwr_on <= '0';
elsif (gps_on_ctr = 1) then
gps_pwr_on <= '1';
else
gps_pwr_on <= '0';
end if;
if (gps_pwr_ena = '0') then
gps_tri <= '1';
elsif (gps_pwr_on = '1') then
gps_tri <= '0';
end if;
end if;
end process;
end rtl;
| gpl-3.0 |
peteut/nvc | test/sem/issue368.vhd | 2 | 1052 | -- this package has mis-labeled "in" and "out" parameters in the procedure declaration
-- but no errors or warnings are generated.
package nvc_package_bug is
procedure in_through_the_out_door (
signal sig_in: out bit; --note this is labeled an "out" parameter but is really "in"
signal sig_out: in bit --note this is labeled an "in" parameter but is really "out"
);
procedure foo (x : in integer);
procedure bar (signal x : in integer);
function baz(x : integer) return integer;
end nvc_package_bug;
package body nvc_package_bug is
procedure in_through_the_out_door (
signal sig_in: in bit;
signal sig_out: out bit) is
begin
sig_out <= sig_in;
end procedure in_through_the_out_door;
procedure foo (y : in integer) is -- Error
begin
end procedure;
procedure bar (x : in integer) is -- Error
begin
end procedure;
function baz(y : integer) return integer is -- Error
begin
return 0;
end function;
end package body nvc_package_bug;
| gpl-3.0 |
peteut/nvc | test/bounds/issue247.vhd | 4 | 205 | package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
| gpl-3.0 |
peteut/nvc | test/sem/record.vhd | 3 | 2780 | package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2);
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2);
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9);
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4);
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2);
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
type int_file is file of integer;
type r7 is record
a : int_file;
end record;
end package body;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_gpio_0_0/axi_lite_ipif_v3_0/hdl/src/vhdl/axi_lite_ipif.vhd | 16 | 14520 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| gpl-3.0 |
peteut/nvc | test/sem/issue359a.vhd | 2 | 258 | -- this test program aborts during analysis
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
signal host_write : bit;
begin
process
procedure host_write is
begin
end host_write;
begin
host_write <= '1';
end process;
end behav;
| gpl-3.0 |
peteut/nvc | test/regress/concat4.vhd | 5 | 411 | entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
assert m = ( X"02", X"01", X"ff" );
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/signal13.vhd | 5 | 380 | entity signal13 is
end entity;
architecture test of signal13 is
function invert(signal x : in bit) return bit is
begin
return not x;
end function;
signal vec : bit_vector(1 to 3) := "101";
begin
process is
begin
assert invert(vec(1)) = '0';
assert invert(vec(2 to 3)(2)) = '1';
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/issue369.vhd | 2 | 402 | entity issue369 is
end entity;
architecture foo of issue369 is
begin
THIS_PROCESS:
process
type twovalue is ('0', '1');
subtype string4 is string(1 to 4);
attribute a: string4;
attribute a of '1' : literal is "TRUE";
begin
assert THIS_PROCESS.'1''a = "TRUE";
assert THIS_PROCESS.'1''a'RIGHT = 4;
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/elab15.vhd | 5 | 407 | entity sub is
port (
x : in bit;
y : out bit_vector(0 downto 0) );
end entity;
architecture test of sub is
begin
y(0) <= x after 1 ps;
end architecture;
-------------------------------------------------------------------------------
entity elab15 is
end entity;
architecture test of elab15 is
begin
sub_i: entity work.sub
port map ( x => '1' );
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/delay2.vhd | 5 | 846 | entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
| gpl-3.0 |
dcsun88/ntpserver-fpga | vhd/hdl/disp_sr.vhd | 1 | 4647 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_sr.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-15
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display shift register
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-15 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity disp_sr is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end disp_sr;
architecture rtl of disp_sr is
signal trig : std_logic;
signal trig_arm : std_logic;
SIGNAL bit_sr : std_logic_vector(255 downto 0);
SIGNAL bit_cnt : std_logic_vector(8 downto 0);
signal finish : std_logic;
signal lat : std_logic;
signal sclk : std_logic;
signal sin : std_logic;
begin
--
-- __
-- disp_lat ____| |_____________ ______________________
-- _______ _____ _____ _ __ _____ _____ _______
-- disp_sin _______X_____X_____X_ __X_____X_____X_______
-- __ __ __ __ __
-- disp_sclk __________| |__| |_ |__| |__| |_______
--
-- Bit 255 254 .. 1 0
--
-- Start triggering
disp_trig:
process (rst_n, clk) is
begin
if (rst_n = '0') then
trig <= '0';
trig_arm <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
trig_arm <= '1';
elsif (tsc_1ppus = '1') then
trig_arm <= '0';
end if;
if (tsc_1ppus = '1' and trig_arm = '1') then
trig <= '1';
elsif (finish = '1') then
trig <= '0';
end if;
end if;
end process;
-- bit counter
disp_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_cnt <= (others => '0');
finish <= '0';
elsif (clk'event and clk = '1') then
if (trig = '0') then
bit_cnt <= (others => '0');
elsif (tsc_1ppus = '1' and trig = '1') then
bit_cnt <= bit_cnt + 1;
end if;
if (tsc_1ppus = '1' and bit_cnt = 511) then
finish <= '1';
else
finish <= '0';
end if;
end if;
end process;
-- Generate DISP control signals
disp_shift:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_sr <= (others => '0');
bit_sr( 7 downto 0) <= x"1c";
bit_sr(15 downto 8) <= x"ce";
bit_sr(23 downto 16) <= x"bc";
lat <= '0';
sclk <= '0';
sin <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
bit_sr <= disp_data;
elsif (tsc_1ppus = '1' and bit_cnt(0) = '1') then
bit_sr <= bit_sr(bit_sr'left - 1 downto 0) & '0';
end if;
if (tsc_1ppus = '1') then
lat <= trig_arm;
sclk <= bit_cnt(0);
sin <= bit_sr(bit_sr'left);
end if;
end if;
end process;
-- Final output register
disp_olat: delay_sig generic map (1) port map (rst_n, clk, lat, disp_lat);
disp_osclk: delay_sig generic map (1) port map (rst_n, clk, sclk, disp_sclk);
disp_osin: delay_sig generic map (1) port map (rst_n, clk, sin, disp_sin);
end rtl;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/synth/cpu_axi_iic_0_0.vhd | 1 | 10035 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0;
USE axi_iic_v2_0.axi_iic;
ENTITY cpu_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_axi_iic_0_0;
ARCHITECTURE cpu_axi_iic_0_0_arch OF cpu_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_axi_iic_0_0_arch : ARCHITECTURE IS "cpu_axi_iic_0_0,axi_iic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "cpu_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=100000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END cpu_axi_iic_0_0_arch;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_proc_common_pkg.vhd | 1 | 18673 | -------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v3_00_a for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package cpu_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end cpu_xadc_wiz_0_0_proc_common_pkg;
package body cpu_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body cpu_xadc_wiz_0_0_proc_common_pkg;
| gpl-3.0 |
peteut/nvc | test/regress/bounds3.vhd | 5 | 220 | entity bounds3 is
end entity;
architecture test of bounds3 is
type int_vec is array (natural range <>) of integer;
signal s : int_vec(5 to 7);
signal k : integer;
begin
s(k) <= 61;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/access2.vhd | 5 | 774 | entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/func8.vhd | 2 | 627 | entity func8 is
end entity;
architecture test of func8 is
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
begin
process is
variable x : integer;
begin
x := 0;
wait for 0 ns;
assert lookup(x) = 0.62; -- Avoid constant folding
x := 2;
wait for 0 ns;
assert lookup(x) = 71.7;
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/bounds/issue54.vhd | 4 | 442 | entity issue54 is
begin
end entity issue54;
architecture a of issue54 is
begin
p : process
variable v : bit_vector(7 downto 0) := (others => '0');
begin
v(3 downto 0) := (7 downto 4 => '1'); -- OK
v(7 downto 4) := (3 downto 0 => '1'); -- OK
v(7 downto 4) := (3 downto 0 => '1', others => '0'); -- Error
assert (v = (7 downto 0 => '1'));
wait;
end process p;
end architecture a;
| gpl-3.0 |
peteut/nvc | test/sem/dwlau.vhd | 3 | 448 | entity dwl_lu is
port (
fs: in bit_vector (2 downto 1);
a, b: in bit_vector (3 downto 0);
lu_out: out bit_vector (3 downto 0);
carryout: out bit);
end dwl_lu;
architecture behavioral of dwl_lu is
begin
process (a, b)
begin
lu_out <= (not a);
carryout <= '0';
end process;
process is
begin
wait for 5 fs;
end process;
end behavioral;
| gpl-3.0 |
peteut/nvc | test/misc/ramb_test.vhd | 5 | 11365 | entity ramb_test is
end entity;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture test of ramb_test is
signal doa : std_logic_vector(31 downto 0);
signal dopa : std_logic_vector(3 downto 0);
signal dob : std_logic_vector(31 downto 0);
signal dopb : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(13 downto 0);
signal addrb : std_logic_vector(13 downto 0);
signal ena : std_logic := '1';
signal enb : std_logic := '1';
signal wea : std_logic_vector(3 downto 0) := X"0";
signal web : std_logic_vector(3 downto 0) := X"0";
signal clka : std_logic := '0';
signal dia : std_logic_vector(31 downto 0);
signal dipa : std_logic_vector(3 downto 0);
signal clkb : std_logic := '0';
signal rsta : std_logic := '0';
signal rstb : std_logic := '0';
signal regcea : std_logic := '1';
signal regceb : std_logic := '1';
signal dib : std_logic_vector(31 downto 0);
signal dipb : std_logic_vector(3 downto 0);
begin
RAMB16BWER_inst : entity work.RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INITP_00 to INITP_07: Initial memory contents.
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output Port A data
DOA => DOA,
-- 32-bit output A port data output
DOPA => DOPA,
-- 4-bit output A port parity output
-- Port B Data: 32-bit (each) output Port B data
DOB => DOB,
-- 32-bit output B port data output
DOPB => DOPB,
-- 4-bit output B port parity output
-- Port A Address/Control Signals: 14-bit (each) input Port A address and control signals
ADDRA => ADDRA,
-- 14-bit input A port address input
CLKA => CLKA,
-- 1-bit input A port clock input
ENA => ENA,
-- 1-bit input A port enable input
REGCEA => REGCEA, -- 1-bit input A port register clock enable input
RSTA => RSTA,
-- 1-bit input A port register set/reset input
WEA => WEA,
-- 4-bit input Port A byte-wide write enable input
-- Port A Data: 32-bit (each) input Port A data
DIA => DIA,
-- 32-bit input A port data input
DIPA => DIPA,
-- 4-bit input A port parity input
-- Port B Address/Control Signals: 14-bit (each) input Port B address and control signals
ADDRB => ADDRB,
-- 14-bit input B port address input
CLKB => CLKB,
-- 1-bit input B port clock input
ENB => ENB,
-- 1-bit input B port enable input
REGCEB => REGCEB, -- 1-bit input B port register clock enable input
RSTB => RSTB,
-- 1-bit input B port register set/reset input
WEB => WEB,
-- 4-bit input Port B byte-wide write enable input
-- Port B Data: 32-bit (each) input Port B data
DIB => DIB,
-- 32-bit input B port data input
DIPB => DIPB
-- 4-bit input B port parity input
);
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/issue187.vhd | 5 | 365 | entity issue187 is
end entity;
architecture a of issue187 is
function expensive_function_returning_false return boolean is
begin
report "This cost much";
return false;
end function;
begin
main : process
begin
assert (not (expensive_function_returning_false or expensive_function_returning_false));
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/parse/enum.vhd | 5 | 107 | package p is
type a is (x, y, z);
type b is ('x', 'y', Z);
type c is (FOO);
end package;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/shift8.vhd | 2 | 7262 | -------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: shift8.vhd
-- Version: v1.01.b
-- Description:
-- This file contains an 8 bit shift register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- System reset
-- Data_ld -- Shift register data load enable
-- Data_in -- Shift register data in
-- Shift_in -- Shift register serial data in
-- Shift_en -- Shift register shift enable
-- Shift_out -- Shift register serial data out
-- Data_out -- Shift register shift data out
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shift8 is
port(
Clk : in std_logic; -- Clock
Clr : in std_logic; -- Clear
Data_ld : in std_logic; -- Data load enable
Data_in : in std_logic_vector (7 downto 0);-- Data to load in
Shift_in : in std_logic; -- Serial data in
Shift_en : in std_logic; -- Shift enable
Shift_out : out std_logic; -- Shift serial data out
Data_out : out std_logic_vector (7 downto 0) -- Shifted data
);
end shift8;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of shift8 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal data_int : std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS: SHIFT_REG_GEN
-- purpose: generate shift register
----------------------------------------------------------------------------
SHIFT_REG_GEN : process(Clk)
begin
if Clk'event and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
data_int <= (others => '0');
elsif (Data_ld = '1') then -- Load data
data_int <= Data_in;
elsif Shift_en = '1' then -- If shift enable is high
data_int <= data_int(6 downto 0) & Shift_in; -- Shift the data
end if;
end if;
end process SHIFT_REG_GEN;
Shift_out <= data_int(7);
Data_out <= data_int;
end architecture RTL;
| gpl-3.0 |
peteut/nvc | test/parse/expr.vhd | 4 | 402 | architecture a of e is
begin
process is
begin
x := not y;
x := abs y;
x := y ** z;
x := f(4).z;
x := y sll 1;
x := y srl 1;
x := y sla 1;
x := y sra 1;
x := y rol 1;
x := y ror 1;
x := work.foo."and"(1, 2);
x(y'range) := y;
x := (1 => 1, x'range => 2);
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/sem/func.vhd | 4 | 6787 | package func is
function sum(x, y, z : in integer) return integer;
function invalid(x : out integer) return integer; -- Error
type uenum is (A, B, C);
type uenum_vector is array (integer range <>) of uenum;
function resolved(v : uenum_vector) return uenum;
subtype enum is resolved uenum;
subtype enum_ab is resolved uenum range A to B;
function resolved2(v : uenum) return uenum;
subtype enum_bad1 is resolved2 uenum; -- Error
function resolved3(v : uenum; x : integer) return uenum;
subtype enum_bad2 is resolved3 uenum; -- Error
subtype enum_bad3 is uenum uenum; -- Error
function default(x : in uenum := 6) return uenum; -- Error
function foo return integer is -- Error
begin
return 4;
end function;
end package;
package body bad is -- Error
end package body;
package body func is
function sum(x, y, z : in integer) return integer is
begin
return x + y; -- OK
end function;
function test1(x : integer) return integer is
begin
return A; -- Wrong return type
end function;
function test2(x : out integer) return integer is -- Invalid mode
begin
return 0;
end function;
function test3(x : integer) return integer is
begin
null; -- Missing return statement
end function;
function foo(x, y, z : in integer) return integer;
function foo(x, y, z : in integer) return integer; -- Duplicate
function test4(x : uenum_vector) return uenum is
begin
return x(x'low);
end function;
function test5(x, y : uenum) return uenum is
type uenum2d is array (uenum, uenum) of uenum;
constant table : uenum2d :=
( ( A, A, A ),
( A, B, C ),
( A, C, B ) );
begin
return table(x, y);
end function;
function test6(x : uenum_vector) return uenum_vector is
variable tmp : uenum_vector(1 to x'length);
begin
for i in tmp'range loop
tmp(i) := A;
end loop;
return tmp;
end function;
function test7(x : uenum_vector) return uenum_vector is
subtype rtype is uenum_vector(x'length downto 0);
variable r : rtype;
begin
return r;
end function;
function test8(x : uenum) return uenum_vector is
begin
return test7((1 to 3 => x));
end function;
function default2(y : in integer := 6) return integer is
begin
return y * 2;
end function;
function test9 return integer is
begin
return default2;
end function;
function test10(k : in integer) return integer is
variable v : integer;
variable u : uenum;
begin
v := sum(x => 4, 1); -- Error
v := sum(1, x => 4, x => 4); -- Error
v := sum(1, y => k, z => 4); -- OK
u := resolved3(A, x => 4); -- OK
u := resolved3(x => 3, v => B); -- OK
return v;
end function;
function test11(constant c : in bit) return bit; -- OK
function test12(variable v : in bit) return bit; -- Error
type ft is file of bit;
function test13(file f : ft) return bit; -- OK
function test14(signal s : bit) return bit; -- OK
procedure modify(variable b : inout bit) is
begin
b := '1';
end procedure;
function test15(file f : ft) return bit is
variable b : bit;
begin
read(f, b); -- OK
return b;
end function;
function test16(x : in bit) return bit is
begin
modify(x); -- Error
return x;
end function;
impure function test17(x : in bit) return bit is
begin
if now = 10 ns then
return '1';
else
return '0';
end if;
end function;
function test18(x : in bit) return bit is
begin
return not test17(x); -- Error, test18 not impure
end function;
type int_ptr is access integer;
function test19(x : in int_ptr) return integer; -- Error
function recur(x : in integer) return integer is
begin
if x = 0 then
return 1;
else
return x * recur(x - 1);
end if;
end function;
function test20(x : integer := 5; y : real) return integer is
variable k : integer;
begin
k := test20(6.5); -- Error
k := test20(5); -- Error
k := test20(y => 7); -- Error
return k;
end function;
function test21a(x : string) return integer;
function test21a(x : bit_vector) return integer;
function test21 return integer is
begin
return test21a(';' & LF); -- OK
end function;
function test22a(x : integer) return integer is
begin
return x + 1;
end function;
function test22a(x : integer) return real is
begin
return real(x) + 1.0;
end function;
function test22 return integer is
begin
assert test22a(1) = 2;
assert test22a(1) = 2.0;
return 1;
end function;
impure function test23 return integer is
variable x : integer;
impure function sub(y : in integer) return integer is
begin
return x + y;
end function;
begin
x := 5;
return sub(2);
end function;
function test24f(x : integer; r : real := 1.0) return integer;
function test24f(y : integer; b : boolean := true) return integer;
function test24 return integer is
begin
return test24f(x => 1) + test24f(y => 2);
end function;
end package body;
package func2 is
procedure test25(constant x : integer);
end package;
package body func2 is
procedure test25(variable x : integer) is -- Error
begin
end procedure;
function test26(signal x : integer) return integer;
function test26(x : integer) return integer is -- Error
begin
return 1;
end function;
end package body;
package func3 is
end package;
package body func3 is
-- default class should be treated identically to constant class
-- (ie, this should not produce an error)
function issue182(bitv : bit_vector) return integer is
function nested_fun return integer is
begin
return bitv'length;
end function;
begin
return nested_fun;
end function;
function issue123(signal x : integer) return integer is
function nested return integer is
begin
return x + 1; -- Error
end function;
begin
return nested;
end function;
end package body;
| gpl-3.0 |
peteut/nvc | test/regress/issue63.vhd | 5 | 257 | package pack0 is
constant v : bit_vector := "10";
end package;
entity issue63 is
end entity;
use work.all;
architecture test of issue63 is
begin
process is
begin
assert pack0.v = "10";
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/issue163.vhd | 5 | 1281 | package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/conv1.vhd | 5 | 416 | entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
| gpl-3.0 |
peteut/nvc | test/parse/issue360.vhd | 2 | 154 | entity bug is
end entity;
architecture a of bug is
begin
main : process is
begin
end;
end; -- Used to hang here
| gpl-3.0 |
peteut/nvc | test/lower/access_bug.vhd | 3 | 479 | entity access_bug is
end entity;
architecture test of access_bug is
type rec_t is record
foo: integer;
end record rec_t;
type rec_ptr_t is access rec_t;
type rec_arr_t is array (integer range <>) of rec_ptr_t;
type rec_arr_ptr_t is access rec_arr_t;
procedure bug_procedure is
variable rec_ptr: rec_arr_ptr_t;
begin
rec_ptr(0) := new rec_t'(foo => 42);
rec_ptr(0).all.foo := 2; -- this works
rec_ptr(0).foo := 2; -- <-- bug here
end;
begin
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/record11.vhd | 5 | 696 | entity record11 is
end entity;
architecture test of record11 is
type rec is record
x, y : bit;
end record;
signal r : rec;
signal a, b : bit;
begin
process is
begin
r <= ( '1', '0' );
wait for 0 ns;
assert r.x'event;
assert not r.y'event;
assert r.y'active;
assert r'event;
wait for 1 ns;
assert a'event;
assert not b'event;
assert b'active;
assert a = '1';
assert b = '0';
r.y <= '1';
wait for 1 ns;
assert b = '1';
wait;
end process;
update_a: a <= r.x after 1 ns;
update_b: b <= r.y after 1 ns;
end architecture;
| gpl-3.0 |
peteut/nvc | test/regress/record8.vhd | 5 | 761 | entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
process is
begin
assert r = ("000", integer'left, ( var => 0 ) );
r.vec <= "101";
wait for 1 ns;
assert r = ("101", integer'left, ( var => 0 ) );
assert r.vec = "101";
assert r.vec(3) = '1';
r.num <= 5;
wait for 1 ns;
assert r.num = 5;
r.sub.var <= 2;
wait for 1 ns;
assert r.sub.var = 2;
wait;
end process;
end architecture;
| gpl-3.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_processing_system7_0_100M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd | 23 | 17838 | -------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0;
--use lib_cdc_v1_0.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
| gpl-3.0 |
peteut/nvc | lib/synopsys/attributes.vhd | 5 | 7098 | ----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: ATTRIBUTES
--
-- Purpose: This package defines the attributes associated with
-- the Synopsys VHDL System Simulator and the HDL compiler.
-- The simulator specific attributes are built into the
-- the analyzer, so this source should not be analyzed on
-- the Synopsys VHDL System Simulator. It is provided for
-- reference and portability to other systems.
--
-- Author: JT, PH, GWH, RV
--
-- Modified. Added translate_off and translate_on pairs because
-- HDL compiler does not use/support the simulator specific attributes
-- in this package.
--
----------------------------------------------------------------------------
-- Simulator specific attributes
-----------------------------------------------------------------------
--
-- attributes for type conversion functions, SDF backannotation and
-- resolution functions
--
-----------------------------------------------------------------------
package ATTRIBUTES is
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF: boolean;
attribute PROPAGATE_VALUE: string;
attribute SDT_CONDITION: string;
attribute SDT_VALUE_NAME: string;
attribute SDT_VALUE: string;
attribute REFLEXIVE: boolean;
attribute COMMUTATIVE: boolean;
attribute ASSOCIATIVE: boolean;
attribute RESULT_INITIAL_VALUE: integer;
attribute TABLE_NAME: string;
attribute REAL_NAME: string;
attribute PRIVATE: boolean;
attribute UNPRIVATE: boolean;
attribute ASIC_CELL: boolean;
attribute DIVERT_MESSAGES: boolean;
-- Note: type BUILTIN_TYPE and attributes BUILTIN and EXTRA_SPACE
-- will be phased out after Elroy. This is to move towards
-- the upcoming '92 standard.
type BUILTIN_TYPE is (VHDL_SYSTEM_PRIMITIVE, LMSI, C_BEHAVIOR,
VHDL_SYSTEM_PRIMITIVE_STD_LOGIC);
attribute BUILTIN: BUILTIN_TYPE;
attribute EXTRA_SPACE: positive;
-- Note: ### For the '92 standard, attribute FOREIGN must be
-- moved to package STANDARD.
attribute FOREIGN : STRING;
-- CLI (C Language Interface) attributes
type CLI_PIN_SENSITIVITY is (CLI_PASSIVE, CLI_EVENT, CLI_ACTIVE);
attribute CLI_ELABORATE : STRING; -- components only
attribute CLI_EVALUATE : STRING; -- components only
attribute CLI_ERROR : STRING; -- components only
attribute CLI_CLOSE : STRING; -- components only
attribute CLI_PIN : CLI_PIN_SENSITIVITY; -- components only
attribute CLI_FUNCTION : STRING; -- functions only
attribute CLI_PROCEDURE : STRING; -- procedures only
attribute CLI_POSTPONED : BOOLEAN; -- components only
-- Logic Modeling Corporation (LMC) interface attributes:
type LMSI_DELAY_TYPE_TYPE is (TYPICAL, MINIMUM, MAXIMUM);
attribute LMSI_DELAY_TYPE : LMSI_DELAY_TYPE_TYPE;
type LMSI_TIMING_MEASUREMENT_TYPE is (DISABLED, ENABLED);
attribute LMSI_TIMING_MEASUREMENT: LMSI_TIMING_MEASUREMENT_TYPE;
type LMSI_LOG_TYPE is (DISABLED, ENABLED);
attribute LMSI_LOG: LMSI_LOG_TYPE;
type LMSI_DELAY_ED_TYPE is (ENABLED, DISABLED);
attribute LMSI_DELAY: LMSI_DELAY_ED_TYPE;
type LMSI_TIMING_VIOLATIONS_TYPE is (ENABLED, DISABLED);
attribute LMSI_TIMING_VIOLATIONS: LMSI_TIMING_VIOLATIONS_TYPE;
type LMSI_XPROP_TYPE is (DISABLED, ENABLED);
attribute LMSI_XPROP: LMSI_XPROP_TYPE;
type LMSI_XPROP_METHOD_TYPE is (PREVIOUS, HIGH, LOW, FLOAT);
attribute LMSI_XPROP_METHOD: LMSI_XPROP_METHOD_TYPE;
-- Zycad XP interface attributes:
type BACKPLANE_TYPE is (XP, VERILOG, VIP);
attribute BACKPLANE: BACKPLANE_TYPE;
-- Attribute to instantiate a Model Bank component in the Zycad
-- XP box.
type ENCRYPTION_TYPE is (MODELBANK);
attribute ENCRYPTION: ENCRYPTION_TYPE;
-- Attribute to specify the EDIF file for an architecture. This
-- attribute can be specified in architecture(s) where the structural
-- information is in EDIF and we want to use it. This should be used
-- in conjunction with BACKPLANE attribute.
attribute EDIF_FILE_FOR_THIS_ARCHITECTURE: string;
attribute VERILOG_FILES_FOR_THIS_ARCHITECTURE: string;
-- The following two attributes are used to specify the physical
-- filename of the EDIF file containing the definitions of cell(s) or
-- entity(s) from a package and the EDIF library name used in the
-- above EDIF file.
attribute EDIF_LIBRARY_FILENAME: string;
attribute EDIF_LIBRARY_NAME: string;
-- XPMSW
-- XP attribute for a component which is described by a ZYCAD
-- CBMOD.
attribute ZYCAD_XP_CBMOD : BOOLEAN;
-- This attribute is used to specify the initialization file for
-- RAM(s) and ROM(s).
attribute MVL7_MEM_INITFILE: string;
-- attributes for the function units bus (funbus)
type FUNBUS_TYPE is (LAI,CBMOD);
attribute FUNBUS : FUNBUS_TYPE;
attribute CHANGE_SIMPLE_NAME : string;
attribute CHECKOUT_LICENSE : string;
attribute COMPILED_SYSTEM : boolean;
attribute USE_FULL_NAME : boolean;
attribute USE_SIMPLE_NAME : boolean;
--synopsys synthesis_on
--------------------------------------------------------------------
-- HDL compiler specific Attributes
attribute async_set_reset : string;
attribute sync_set_reset : string;
attribute async_set_reset_local : string;
attribute sync_set_reset_local : string;
attribute async_set_reset_local_all : string;
attribute sync_set_reset_local_all : string;
attribute one_hot : string;
attribute one_cold : string;
attribute infer_mux : string;
--------------------------------------------------------------------
-- design compiler constraints and attributes
attribute ARRIVAL : REAL;
attribute DONT_TOUCH : BOOLEAN;
attribute DONT_TOUCH_NETWORK : BOOLEAN;
attribute DRIVE_STRENGTH : REAL;
attribute EQUAL : BOOLEAN;
attribute FALL_ARRIVAL : REAL;
attribute FALL_DRIVE : REAL;
attribute LOAD : REAL;
attribute LOGIC_ONE : BOOLEAN;
attribute LOGIC_ZERO : BOOLEAN;
attribute MAX_AREA : REAL;
attribute MAX_DELAY : REAL;
attribute MAX_FALL_DELAY : REAL;
attribute MAX_RISE_DELAY : REAL;
attribute MAX_TRANSITION : REAL;
attribute MIN_DELAY : REAL;
attribute MIN_FALL_DELAY : REAL;
attribute MIN_RISE_DELAY : REAL;
attribute OPPOSITE : BOOLEAN;
attribute RISE_ARRIVAL : REAL;
attribute RISE_DRIVE : REAL;
attribute UNCONNECTED : BOOLEAN;
-- state machine attributes
attribute STATE_VECTOR : STRING;
-- resource sharing attributes
subtype resource is integer;
attribute ADD_OPS : STRING;
attribute DONT_MERGE_WITH : STRING;
attribute MAP_TO_MODULE : STRING;
attribute IMPLEMENTATION : STRING;
attribute MAY_MERGE_WITH : STRING;
attribute OPS : STRING;
-- general attributes
attribute ENUM_ENCODING : STRING;
-- optimization attributes
attribute TRANSFORM_CONST_MULT : boolean;
--
end ATTRIBUTES;
| gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/simulation/random.vhd | 101 | 4108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/raw2rgb/onchip_fifo.vhd | 2 | 6420 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: test_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.2 Build 222 07/20/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY onchip_fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END onchip_fifo;
ARCHITECTURE SYN OF onchip_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone V",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 12,
lpm_widthu => 11,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "12"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "12"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/simulation/instructionMemory_tb.vhd | 1 | 4409 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: instructionMemory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY instructionMemory_tb IS
END ENTITY;
ARCHITECTURE instructionMemory_tb_ARCH OF instructionMemory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
instructionMemory_synth_inst:ENTITY work.instructionMemory_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 |
alphaFred/Sejits4Fpgas | sejits4fpgas/hw/user/dsp_sreg_block.vhd | 1 | 2619 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/29/2015 12:03:12 PM
-- Design Name:
-- Module Name: dsp_sreg_block - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dsp_sreg_block is
Generic (
WIDTH : natural;
LENGTH : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
end dsp_sreg_block;
architecture Behavioral of dsp_sreg_block is
TYPE iBus is array(LENGTH-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal sRegBus : iBus;
COMPONENT dsp_dff_block
Generic (
WIDTH : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END COMPONENT;
begin
shiftReg: for i in 1 to LENGTH generate
begin
dffLeft: if i = 1 generate
begin
dff: component dsp_dff_block
generic map (
WIDTH => WIDTH
)
port map (
D => D,
CLK => CLK,
RST => RST,
Q => sRegBus(i)
);
end generate dffLeft;
--
dffOthers: if (i > 1 AND i < LENGTH) generate
begin
dff: component dsp_dff_block
generic map (
WIDTH => WIDTH)
port map (
D => sRegBus(i-1),
CLK => CLK,
RST => RST,
Q => sRegBus(i)
);
end generate dffOthers;
--
dffRight: if i = LENGTH generate
begin
dff: component dsp_dff_block
generic map (
WIDTH => WIDTH)
port map (
D => sRegBus(i-1),
CLK => CLK,
RST => RST,
Q => Q
);
end generate dffRight;
end generate shiftReg;
end architecture Behavioral;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/atc18/pads_atc18.vhd | 1 | 10146 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gsi/ssram/core_burst.vhd | 1 | 21019 | -- Copyright © 2006. GSI Technology
-- Jeff Daugherty
-- [email protected]
-- Version: 3.2
--
-- FileName: core.vhd
-- Unified Sram Core Model for Sync Burst/NBT Sram
--
-- Revision History:
-- 04/23/02 1.0 1) Created VHDL Core.VHD from Verilog Core.V
-- 06/05/02 1.1 1) added new signals, DELAY and tKQX. These signals will
-- be used to setup the Clock to Data Invalid spec.
-- 07/17/02 1.2 1) Fixed the JTAG State machine
-- 2) changed the SR register to shift out the MSB and shift
-- in the LSB
-- 09/25/02 1.3 1) Removed all nPE pin features
-- 2) Max number of Core addresses is now dynamic
-- 3) Max width of Core data is now dynamic
-- 4) Removed alll reference of JTAG from core, seperate JTAG
-- model file: GSI_JTAG
-- 01/10/03 1.4 1) Created a Write_Array process to remove race conditions
-- 2) Created a Read_Array proccess to remove race conditions
-- 02/20/03 1.5 1) Added We and Waddr to Read_Array sensitivity list.
-- 2) Changed the Read_Array process to look at the last
-- write's byte write setting and determine where to pull the
-- read data from, either coherency(byte write on) or the
-- array(byte write off).
-- 3) Added signal Iscd to fix SCD to the right state for NBT
-- 04/03/03 1.6 1) Added a write clock W_k to trigger the Write_Array function
-- 07/09/03 1.7 1) changed NBT write clock to clock off of we2.
-- 2) Delayed the internal clock by 1ns to control the write
-- 3) changed ce to take into account NBT mode
-- 07/23/03 1.8 1) Changed W_K to ignore the byte writes
-- 08/12/03 1.9 1) updated state machine to include seperate read and write
-- burst states
-- 2) Changed internal bytewrite signal to ignore nW
-- 10/29/03 2.0 1) updated the state machine, changed reference to suspend
-- to deselect.
-- 2) added timing functions to core
-- 03/25/04 2.1 1) Updated state machine. Added deselect and suspend states
-- 2) Fixed other issues with the state machine
-- 04/28/04 2.2 1) Rearranged state that determins Deselect, Burst and Suspend
--
-- 11/01/05 3.0 1) Created BurstRAM only Model
-- 06/21/06 3.1 1) Added Qswitch to control when the IOs turn on or off
-- 2) Delayed the Qxi inteernal data busses instead of the DQx
-- external Data busses.
-- 3) Added CLK_i2 to control the setting of Qswitch
-- 4) All these changes removed Negative time issue for some simulations
--07/18/06 3.2 1) Initialized ce and re to 0 so that Qswitch is not
-- undfined which can cause bus contention on startup.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdio.all;
ENTITY VHDL_BURST_CORE IS
GENERIC (
CONSTANT bank_size : integer ;-- *16M /4 bytes in parallel
CONSTANT A_size : integer;
CONSTANT DQ_size : integer;
fname : string := "ram.dat"; -- File to read from
index : integer := 0); -- Index
PORT (
SIGNAL A : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte A data
SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte B data
SIGNAL DQc : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte C data
SIGNAL DQd : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte D data
SIGNAL DQe : inout std_logic_vector(DQ_size DOWNTO 1);-- byte E data
SIGNAL DQf : inout std_logic_vector(DQ_size DOWNTO 1);-- byte F data
SIGNAL DQg : inout std_logic_vector(DQ_size DOWNTO 1);-- byte G data
SIGNAL DQh : inout std_logic_vector(DQ_size DOWNTO 1);-- byte H data
SIGNAL nBa : IN std_logic;-- bank A write enable
SIGNAL nBb : IN std_logic;-- bank B write enable
SIGNAL nBc : IN std_logic;-- bank C write enable
SIGNAL nBd : IN std_logic;-- bank D write enable
SIGNAL nBe : IN std_logic;-- bank E write enable
SIGNAL nBf : IN std_logic;-- bank F write enable
SIGNAL nBg : IN std_logic;-- bank G write enable
SIGNAL nBh : IN std_logic;-- bank H write enable
SIGNAL CK : IN std_logic;-- clock
SIGNAL nBW : IN std_logic;-- byte write enable
SIGNAL nGW : IN std_logic;-- Global write enable
SIGNAL nE1 : IN std_logic;-- chip enable 1
SIGNAL E2 : IN std_logic;-- chip enable 2
SIGNAL nE3 : IN std_logic;-- chip enable 3
SIGNAL nG : IN std_logic;-- output enable
SIGNAL nADV : IN std_logic;-- Advance not / load
SIGNAL nADSC : IN std_logic;
SIGNAL nADSP : IN std_logic;
SIGNAL ZZ : IN std_logic;-- power down
SIGNAL nFT : IN std_logic;-- Pipeline / Flow through
SIGNAL nLBO : IN std_logic;-- Linear Burst Order
SIGNAL SCD : IN std_logic;
SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
SIGNAL tKQ : time;
SIGNAL tKQX : time);
END VHDL_BURST_CORE;
LIBRARY GSI;
LIBRARY Std;
ARCHITECTURE GSI_BURST_CORE OF VHDL_BURST_CORE IS
USE GSI.FUNCTIONS.ALL;
USE Std.textio.ALL;
TYPE MEMORY_0 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_1 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_2 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_3 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_4 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_5 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_6 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_7 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
-- ******** Define Sram Operation Mode **********************
shared variable bank0 : MEMORY_0 ;
shared variable bank1 : MEMORY_1 ;
shared variable bank2 : MEMORY_2 ;
shared variable bank3 : MEMORY_3 ;
shared variable bank4 : MEMORY_4 ;
shared variable bank5 : MEMORY_5 ;
shared variable bank6 : MEMORY_6 ;
shared variable bank7 : MEMORY_7 ;
-- ---------------------------------------------------------------
-- Gated SRAM Clock
-- ---------------------------------------------------------------
SIGNAL clk_i : std_logic;
SIGNAL clk_i2 : std_logic;
-- ---------------------------------------------------------------
-- Combinatorial Logic
-- ---------------------------------------------------------------
SIGNAL E : std_logic;-- internal chip enable
SIGNAL ADV : std_logic;-- internal address advance
SIGNAL ADS : std_logic;
SIGNAL ADSP : std_logic;
SIGNAL ADSC : std_logic;
SIGNAL W : std_logic;
SIGNAL R : std_logic;
SIGNAL W_k : std_logic;
SIGNAL R_k : std_logic;
SIGNAL BW : std_logic_vector(7 DOWNTO 0);-- internal byte write enable
SIGNAL Qai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Qbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qdi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Dai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL Dbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Ddi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL bwi : std_logic_vector(7 DOWNTO 0);
SIGNAL addr0 : std_logic_vector(A_size - 1 DOWNTO 0);-- saved address
SIGNAL addr1 : std_logic_vector(A_size - 1 DOWNTO 0);-- address buffer 1
SIGNAL baddr : std_logic_vector(A_size - 1 DOWNTO 0);-- burst memory address
SIGNAL waddr : std_logic_vector(A_size - 1 DOWNTO 0);-- write memory address
SIGNAL raddr : std_logic_vector(A_size - 1 DOWNTO 0);-- read memory address
SIGNAL bcnt : std_logic_vector(1 DOWNTO 0) := to_stdlogicvector(0, 2);-- burst counter
SIGNAL we0 : std_logic := '0';
SIGNAL re0 : std_logic := '0';
SIGNAL re1 : std_logic := '0';
SIGNAL re2 : std_logic := '0';
SIGNAL ce0 : std_logic := '0';
SIGNAL ce1 : std_logic := '0';
SIGNAL ce : std_logic := '0';
SIGNAL re : std_logic := '0';
SIGNAL oe : std_logic;
SIGNAL we : std_logic;
SIGNAL Qswitch: std_logic ;
SIGNAL state : string (9 DOWNTO 1) := "IDLE ";
SIGNAL Check_Time : time := 1 ns;
SIGNAL DELAY : time := 1 ns;
SIGNAL GUARD : boolean:= TRUE;
-- TIMING FUNCTIONS
function POSEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '0') OR (s = '1')));
end;
function NEGEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '1') OR (s = '0')) );
end;
-- END TIMING FUNCTIONS
PROCEDURE shiftnow (SIGNAL addr1 : INOUT std_logic_vector(A_size - 1 DOWNTO 0);
SIGNAL re2 : INOUT std_logic;
SIGNAL re1 : INOUT std_logic;
SIGNAL ce1 : INOUT std_logic;
SIGNAL Dai : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dbi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dci : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Ddi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dei : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dfi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dgi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dhi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0))
IS
BEGIN
addr1 <= baddr;
re2 <= re1;
re1 <= re0;
ce1 <= ce0;
Dai <= DQa;
Dbi <= DQb;
Dci <= DQc;
Ddi <= DQd;
Dei <= DQe;
Dfi <= DQf;
Dgi <= DQg;
Dhi <= DQh;
END;
BEGIN
PROCESS
BEGIN
WAIT UNTIL POSEDGE(CK);
clk_i <= NOT ZZ after 100 ps;
clk_i2 <= NOT ZZ after 200 ps;
WAIT UNTIL NEGEDGE(CK);
clk_i <= '0' after 100 ps;
clk_i2 <= '0' after 200 ps;
END PROCESS;
-- ---------------------------------------------------------------
-- State Machine
-- ---------------------------------------------------------------
st : PROCESS
variable tstate : string(9 DOWNTO 1) :="DESELECT ";
variable twe0 : std_logic := '0';
variable tre0 : std_logic := '0';
variable tce0 : std_logic := '0';
BEGIN
WAIT UNTIL POSEDGE(CK);
CASE state IS
WHEN "DESELECT " =>
if (E = '1') then
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
END IF;
-- Checking for Deselect
if ((E /= '1' and ADSC = '1') or (nADSP and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
END IF;
-- **************************************************
WHEN "NEWCYCLE " | "BURST " | "SUSPBR " | "LATEWRITE" =>
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
-- Checking for Deselect
if ((E /= '1' and nADSC = '0') or (nADSP = '0' and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
end if;
-- Checking for Burst Start
if (ADSC = '0' and ADSP = '0' AND ADV = '1') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "BURST ";
if we0 = '1' then
twe0 := W;
tre0 := '0';
bwi <= BW;
end if;
if re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
bcnt <= to_stdlogicvector(bcnt + "01", 2);
end if;
-- Checking for a Suspended Burst
if (ADSC = '0' and ADSP = '0' AND ADV = '0') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "SUSPBR ";
if we0 = '1' or W = '1' then
twe0 := W;
tre0 := '0';
re1 <= '0';
bwi <= BW;
elsif re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
end if;
WHEN OTHERS =>
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
bcnt <= to_stdlogicvector(0, 2);
END CASE;
state <= tstate;
we0 <= twe0;
re0 <= tre0;
ce0 <= tce0;
END PROCESS;
RAMINIT : process
-- variable MEMA : MEM;
variable L1 : line;
-- variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if fname /= "" then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 20) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
-- if index = 6 then
-- ai := to_integer(recaddr);
-- for i in 0 to 15 loop
-- MEMA(ai+i) := recdata((i*8) to (i*8+7));
-- end loop;
-- elsif (index = 4) or (index = 5) then
ai := to_integer(recaddr)/4;
for i in 0 to 3 loop
bank0(ai+i) := '0' & recdata((i*32+index*16) to (i*32+index*16+7));
bank1(ai+i) := '0' & recdata((i*32+index*16+8) to (i*32+index*16+15));
end loop;
-- else
-- ai := conv_integer(recaddr)/4;
-- for i in 0 to 3 loop
-- MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
-- end loop;
-- end if;
end if;
end if;
end if;
end loop;
end if;
wait;
end process;
-- ---------------------------------------------------------------
-- Data IO Logic
-- ---------------------------------------------------------------
Write_Array: process (W_k)
begin -- process Write_Array
IF (POSEDGE(W_k)) THEN
IF (we = '1') THEN
IF bwi(0) = '1' THEN
bank0(to_integer(waddr)) := Dai;
END IF;
IF bwi(1) = '1' THEN
bank1(to_integer(waddr)) := Dbi;
END IF;
IF bwi(2) = '1' THEN
bank2(to_integer(waddr)) := Dci;
END IF;
IF bwi(3) = '1' THEN
bank3(to_integer(waddr)) := Ddi;
END IF;
IF bwi(4) = '1' THEN
bank4(to_integer(waddr)) := Dei;
END IF;
IF bwi(5) = '1' THEN
bank5(to_integer(waddr)) := Dfi;
END IF;
IF bwi(6) = '1' THEN
bank6(to_integer(waddr)) := Dgi;
END IF;
IF bwi(7) = '1' THEN
bank7(to_integer(waddr)) := Dhi;
END IF;
END IF;
END IF;
end process Write_Array;
Read_Array: process (r_k)
begin -- process Read_Array
IF (we = '0') then
Qai <= transport bank0(to_integer(raddr)) after DELAY - 200 ps;
Qbi <= transport bank1(to_integer(raddr)) after DELAY - 200 ps;
Qci <= transport bank2(to_integer(raddr)) after DELAY - 200 ps;
Qdi <= transport bank3(to_integer(raddr)) after DELAY - 200 ps;
Qei <= transport bank4(to_integer(raddr)) after DELAY - 200 ps;
Qfi <= transport bank5(to_integer(raddr)) after DELAY - 200 ps;
Qgi <= transport bank6(to_integer(raddr)) after DELAY - 200 ps;
Qhi <= transport bank7(to_integer(raddr)) after DELAY - 200 ps;
END IF;
end process Read_Array;
-- check it -t option is active and set correctly
time_ck : process (CLK_i)
begin
check_time <= CK'last_event;
assert check_time /= 0 ns report "Resolution needs to be set to 100ps for modelSIM use vsim -t 100ps <>" severity FAILURE;
end process time_ck;
ADS_SET : process (CLK_i)
begin
if posedge(clk_i) then
ADS <= ADSP OR ADSC;
end if;
end process ADS_SET;
q_switch : process (CLK_i2)
begin --read clock controls outputs
Qswitch <= transport re and ce after DELAY - 200 ps;
end process q_switch;
E <= (NOT nE1 AND E2 AND NOT nE3);
ADV <= not nADV;
ADSP <= NOT nADSP AND ( E2 or NOT nE3);
ADSC <= NOT nADSC AND ( not nE1 or E2 or NOT nE3);
W <= (NOT nGW OR NOT nBW );
W_k <=((NOT ADSP or not ADSC) AND (NOT nGW OR NOT nBW )) and clk_i after 100 ps;
R <= nGW and nBW;
R_k <= (TERNARY((ADS or ADV) and not W, TERNARY( nFT, re1, re0), '0') and clk_i) after 100 ps;
BW(0) <= not nGW or (NOT nBa and not nBW);
BW(1) <= not nGW or (NOT nBb and not nBW);
BW(2) <= not nGW or (NOT nBc and not nBW);
BW(3) <= not nGW or (NOT nBd and not nBW);
BW(4) <= not nGW or (NOT nBe and not nBW);
BW(5) <= not nGW or (NOT nBf and not nBW);
BW(6) <= not nGW or (NOT nBg and not nBW);
BW(7) <= not nGW or (NOT nBh and not nBW);
baddr <= to_stdlogicvector(TERNARY(nLBO, addr0(A_size - 1 DOWNTO 2) & (bcnt(1) XOR addr0(1)) &
(bcnt(0) XOR addr0(0)), addr0(A_size - 1 DOWNTO 2) & (addr0(1 DOWNTO 0) + bcnt)), A_size);
waddr <= to_stdlogicvector(TERNARY(not ADV, addr0, baddr), A_size);
raddr <= to_stdlogicvector(TERNARY(nFT, addr1, baddr), A_size);
we <= we0;
re <= TERNARY(nFT, re1, re0);
ce <= (TERNARY(not SCD AND re2 = '1', ce1, ce0));
oe <= re AND ce;
DELAY <= TERNARY(nG OR not ((we and re) or oe) OR ZZ, tKQ, tKQX);
DQa <= GUARDED TERNARY(Qswitch, Qai, HighZ);
DQb <= GUARDED TERNARY(Qswitch, Qbi, HighZ);
DQc <= GUARDED TERNARY(Qswitch, Qci, HighZ);
DQd <= GUARDED TERNARY(Qswitch, Qdi, HighZ);
DQe <= GUARDED TERNARY(Qswitch, Qei, HighZ);
DQf <= GUARDED TERNARY(Qswitch, Qfi, HighZ);
DQg <= GUARDED TERNARY(Qswitch, Qgi, HighZ);
DQh <= GUARDED TERNARY(Qswitch, Qhi, HighZ);
END GSI_BURST_CORE;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/ringosc.vhd | 1 | 2533 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_ut130hbd
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_rhs65
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
ut130r : if tech = ut130 generate
ut130rx : ringosc_ut130hbd port map (roen, roout);
end generate;
rhs65r : if tech = rhs65 generate
rhs65rx : ringosc_rhs65 port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc and tech /= ut130 and tech /= rhs65 generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl;
| gpl-3.0 |
EliasLuiz/TCC | Teste/MemoTableTInputWay.vhd | 1 | 10350 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTInput.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any Input files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTInputWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTInputEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTInputEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0)
);
END MemoTableTInputWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTInputWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTInputEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToInput(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= InputToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTInputEntryWidth,
width_b => MemoTableTInputEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Input_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Input_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Input_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Input_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTInputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 Input NODEFVAL "q[MemoTableTInputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/usb/grusb.vhd | 1 | 24363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: grusb
-- File: grusb.vhd
-- Author: Marko Isomaki, Jonas Ekergarn
-- Description: Package for GRUSBHC, GRUSBDC, and GRUSB_DCL
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package grusb is
-----------------------------------------------------------------------------
-- USB in/out types
-----------------------------------------------------------------------------
type grusb_in_type is record
datain : std_logic_vector(15 downto 0);
rxactive : std_ulogic;
rxvalid : std_ulogic;
rxvalidh : std_ulogic;
rxerror : std_ulogic;
txready : std_ulogic;
linestate : std_logic_vector(1 downto 0);
nxt : std_ulogic;
dir : std_ulogic;
vbusvalid : std_ulogic;
hostdisconnect : std_ulogic;
functesten : std_ulogic;
urstdrive : std_ulogic;
end record;
constant grusb_in_none : grusb_in_type :=
((others => '0'), '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', '0');
type grusb_out_type is record
dataout : std_logic_vector(15 downto 0);
txvalid : std_ulogic;
txvalidh : std_ulogic;
opmode : std_logic_vector(1 downto 0);
xcvrselect : std_logic_vector(1 downto 0);
termselect : std_ulogic;
suspendm : std_ulogic;
reset : std_ulogic;
stp : std_ulogic;
oen : std_ulogic;
databus16_8 : std_ulogic;
dppulldown : std_ulogic;
dmpulldown : std_ulogic;
idpullup : std_ulogic;
drvvbus : std_ulogic;
dischrgvbus : std_ulogic;
chrgvbus : std_ulogic;
txbitstuffenable : std_ulogic;
txbitstuffenableh : std_ulogic;
fslsserialmode : std_ulogic;
tx_enable_n : std_ulogic;
tx_dat : std_ulogic;
tx_se0 : std_ulogic;
end record;
constant grusb_out_none : grusb_out_type :=
((others => '0'), '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
type grusb_in_vector is array (natural range <>) of grusb_in_type;
type grusb_out_vector is array (natural range <>) of grusb_out_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
o : out grusb_out_vector((nports-1) downto 0);
i : in grusb_in_vector((nports-1) downto 0));
end component;
component grusbdc is
generic (
hsindex : integer range 0 to NAHBSLV-1 := 0;
hirq : integer range 0 to NAHBIRQ-1 := 0;
haddr : integer := 0;
hmask : integer := 16#FFF#;
hmindex : integer range 0 to NAHBMST-1 := 0;
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
irqi : integer range 0 to NAHBIRQ-1 := 1;
irqo : integer range 0 to NAHBIRQ-1 := 2;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component grusb_dcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
burstlength: integer range 1 to 512 := 8;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1
);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component grusb_dcl;
component grusbhc_gen is
generic (
tech : integer := 0;
memtech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC APB slave input signals
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC APB slave output signals
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_irq : out std_ulogic;
-- EHC/UHC(s) AHB master input signals
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC(s) AHB slave input signals
uhc_ahbsi_hsel : in std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC AHB master output signals
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC(s) AHB master output signals
uhc_ahbmo_hbusreq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hlock : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_htrans : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbmo_haddr : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbmo_hwrite : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hsize : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hburst : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hprot : out std_logic_vector(((n_cc*4)-1)*uhcgen downto 0);
uhc_ahbmo_hwdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
-- UHC(s) AHB slave output signals
uhc_ahbso_hready : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbso_hresp : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbso_hrdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbso_hsplit : out std_logic_vector(((n_cc*NAHBMST)-1)*uhcgen downto 0);
uhc_irq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
-- ULPI/UTMI+ output signals
xcvrselect : out std_logic_vector(((nports*2)-1) downto 0);
termselect : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataout : out std_logic_vector(((nports*16)-1) downto 0);
txvalidh : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
reset : out std_logic_vector((nports-1) downto 0);
oen : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- ULPI/UTMI+ input signals
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datain : in std_logic_vector(((nports*16)-1) downto 0);
rxvalidh : in std_logic_vector((nports-1) downto 0);
hostdisconnect : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component grusbdc_gen is
generic (
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
-- usb clock
uclk : in std_ulogic;
--usb in signals
datain : in std_logic_vector(15 downto 0);
rxactive : in std_ulogic;
rxvalid : in std_ulogic;
rxvalidh : in std_ulogic;
rxerror : in std_ulogic;
txready : in std_ulogic;
linestate : in std_logic_vector(1 downto 0);
nxt : in std_ulogic;
dir : in std_ulogic;
vbusvalid : in std_ulogic;
urstdrive : in std_ulogic;
--usb out signals
dataout : out std_logic_vector(15 downto 0);
txvalid : out std_ulogic;
txvalidh : out std_ulogic;
opmode : out std_logic_vector(1 downto 0);
xcvrselect : out std_logic_vector(1 downto 0);
termselect : out std_ulogic;
suspendm : out std_ulogic;
reset : out std_ulogic;
stp : out std_ulogic;
oen : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
drvvbus : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- amba clock/rst
hclk : in std_ulogic;
hrst : in std_ulogic;
--ahb master in signals
ahbmi_hgrant : in std_ulogic;
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
--ahb master out signals
ahbmo_hbusreq : out std_ulogic;
ahbmo_hlock : out std_ulogic;
ahbmo_htrans : out std_logic_vector(1 downto 0);
ahbmo_haddr : out std_logic_vector(31 downto 0);
ahbmo_hwrite : out std_ulogic;
ahbmo_hsize : out std_logic_vector(2 downto 0);
ahbmo_hburst : out std_logic_vector(2 downto 0);
ahbmo_hprot : out std_logic_vector(3 downto 0);
ahbmo_hwdata : out std_logic_vector(31 downto 0);
--ahb slave in signals
ahbsi_hsel : in std_ulogic;
ahbsi_haddr : in std_logic_vector(31 downto 0);
ahbsi_hwrite : in std_ulogic;
ahbsi_htrans : in std_logic_vector(1 downto 0);
ahbsi_hsize : in std_logic_vector(2 downto 0);
ahbsi_hburst : in std_logic_vector(2 downto 0);
ahbsi_hwdata : in std_logic_vector(31 downto 0);
ahbsi_hprot : in std_logic_vector(3 downto 0);
ahbsi_hready : in std_ulogic;
ahbsi_hmaster : in std_logic_vector(3 downto 0);
ahbsi_hmastlock : in std_ulogic;
--ahb slave out signals
ahbso_hready : out std_ulogic;
ahbso_hresp : out std_logic_vector(1 downto 0);
ahbso_hrdata : out std_logic_vector(31 downto 0);
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0);
-- misc
irq : out std_logic_vector(2*sepirq downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
end grusb;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/grgpreg.vhd | 1 | 4712 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpreg
-- File: grgpreg.vhd
-- Author: Kristoffer Glembo - Aeroflex Gaisler
-- Description: General purpose register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end;
architecture rtl of grgpreg is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPREG, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, resval)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
v := r;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
readdata := r.reg(31 downto 0);
else
readdata(nbits-1 downto 0) := r.reg;
end if;
when "001" =>
if nbits > 32 then
readdata(nbits-33 downto 0) := r.reg(nbits-1 downto 32);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
v.reg(31 downto 0) := apbi.pwdata;
else
v.reg := apbi.pwdata(nbits-1 downto 0);
end if;
when "001" =>
if nbits > 32 then
v.reg(nbits-1 downto 32) := apbi.pwdata(nbits-33 downto 0);
end if;
when others =>
end case;
end if;
if rst = '0' then
if extrst = 0 then
v.reg := conv_std_logic_vector(rstval, nbits);
if nbits > 32 then
v.reg(nbits-1 downto 32) := conv_std_logic_vector(rstval2, nbits-32);
end if;
else
v.reg := resval;
end if;
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
end process;
gprego <= r.reg;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpreg" & tost(pindex) &
": " & tost(nbits) & "-bit GPREG Unit rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xup/leon3mp.vhd | 1 | 22639 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_2.in.vhd | 1 | 300 | -- Secondary GR1553B
constant CFG_GR1553B_ENABLE2 : integer := CONFIG_GR1553B_ENABLE2;
constant CFG_GR1553B_RTEN2 : integer := CONFIG_GR1553B_RTEN2;
constant CFG_GR1553B_BCEN2 : integer := CONFIG_GR1553B_BCEN2;
constant CFG_GR1553B_BMEN2 : integer := CONFIG_GR1553B_BMEN2;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkand.vhd | 1 | 3937 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
struct : if has_clkand(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
rhl : if (tech = rhlib18t) generate
clkgate : clkand_rh_lib18t port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut13 : if (tech = ut130) generate
clkgate : clkand_ut130hbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut09 : if (tech = ut90) generate
clkgate : clkand_ut90nhbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
n2x : if (tech = easic45) generate
clkgate : clkand_n2x port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
saed : if (tech = saed32) generate
clkgate : clkand_saed32 port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
rhs : if (tech = rhs65) generate
clkgate : clkand_rhs65 port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
dar : if (tech = dare) generate
clkgate : clkand_dare port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and (eni or tsten);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkrand is
signal eni : std_ulogic;
begin
ut13 : if (tech = ut130) generate
eni <= en or tsten;
clkgate : clkrand_ut130hbd port map(I => i, en => en, O => o);
end generate;
nonut13 : if (tech /= ut130) generate
clkgate : clkand generic map (tech, 1)
port map (i, en, o, tsten);
end generate;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/pllsim.vhd | 1 | 1486 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25-eek/serializer.vhd | 1 | 2713 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: serializer
-- File: serializer.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: Takes in three vectors and serializes them into one
-- output vector. Intended to be used to serialize
-- RGB VGA data.
--
library ieee;
use ieee.std_logic_1164.all;
entity serializer is
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end entity serializer;
architecture rtl of serializer is
type state_type is (vec0, vec1, vec2);
type sreg_type is record
state : state_type;
sync : std_logic_vector(1 downto 0);
end record;
signal r, rin : sreg_type;
begin -- rtl
comb: process (r, clk, sync, ivec0, ivec1, ivec2)
variable v : sreg_type;
begin -- process comb
v := r;
v.sync := r.sync(0) & sync;
case r.state is
when vec0 =>
ovec <= ivec0;
v.state := vec1;
when vec1 =>
ovec <= ivec1;
v.state := vec2;
when vec2 =>
ovec <= ivec2;
v.state := vec0;
end case;
if (r.sync(0) xor sync) = '1' then
v.state := vec1;
end if;
rin <= v;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
end rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libfpu.vhd | 1 | 4767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
end;
| gpl-3.0 |
hoglet67/CoPro6502 | src/CPU65C02/core.vhd | 1 | 14958 | -- VHDL Entity r65c02_tc.core.symbol
--
-- Created:
-- by - jens.Domain Users (ENTW-7HPZ200)
-- at - 11:09:21 08/01/13
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end core ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.8 2013/08/01 11:00:00 jens
-- - Change Block names to lower case
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder.
--
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:00:34 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--library r65c02_tc;
architecture struct of core is
-- Architecture declarations
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_alu_prio_o_i : std_logic_vector(7 downto 0);
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal rst_nmi_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
signal var_shift_data_o_i : std_logic_vector(7 downto 0);
-- Component Declarations
component fsm_execution_unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_alu_prio_i : in std_logic_vector (7 downto 0);
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
rst_nmi_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component fsm_intnmi
port (
clk_clk_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_nmi_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
end component;
component reg_pc
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component reg_sp
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
component regbank_axy
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit;
for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi;
for all : reg_pc use entity r65c02_tc.reg_pc;
for all : reg_sp use entity r65c02_tc.reg_sp;
for all : regbank_axy use entity r65c02_tc.regbank_axy;
-- pragma synthesis_on
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
var_shift_data_o_i <= x"01";
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & ch_a_o_i;
temp_din1 := '0' & ch_b_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
reg_0flag_o_i <= temp_sum(8) ;
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.12) for instance 'U_5' of 'lshift'
u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i)
variable temp_shift : std_logic_vector (3 downto 0);
variable temp_dout : std_logic_vector (7 downto 0);
variable temp_din : std_logic_vector (7 downto 0);
begin
temp_din := (others=> 'X');
temp_shift := ch_a_o_i(3 downto 0);
temp_din := var_shift_data_o_i;
for i in 0 to 3 loop
if (i < 3) then
if (temp_shift(i) = '1') then
temp_dout := (others => '0');
temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0);
elsif (temp_shift(i) = '0') then
temp_dout := temp_din;
else
temp_dout := (others => 'X');
end if;
else
if (temp_shift(i) = '1') then
temp_dout := (others => '0');
elsif (temp_shift(i) = '0') then
temp_dout := temp_din;
else
temp_dout := (others => 'X');
end if;
end if;
temp_din := temp_dout;
end loop;
d_alu_prio_o_i <= temp_dout;
end process u_5combo_proc;
-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- Instance port mappings.
U_4 : fsm_execution_unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_alu_prio_i => d_alu_prio_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
rst_nmi_o => rst_nmi_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_3 : fsm_intnmi
port map (
clk_clk_i => clk_clk_i,
nmi_n_i => nmi_n_i,
rst_nmi_i => rst_nmi_o_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_0 : reg_pc
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : reg_sp
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
U_2 : regbank_axy
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
end struct;
| gpl-3.0 |
ARC-Lab-UF/UAA | src/uaa_tb_all.vhd | 1 | 2906 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- Greg Stitt
-- University of Florida
-- Description:
-- This file instantiates the uaa's testbench for each of the
-- architectures and verifies their correctness in a simple case
library ieee;
use ieee.std_logic_1164.all;
use work.uaa_pkg.all;
entity uaa_tb_all is
end uaa_tb_all;
architecture DEFAULT of uaa_tb_all is
begin
UUT_FCBT : entity work.uaa_tb
generic map(
test_name => "FCBT",
arch => UAA_FCBT,
parallel_inputs => 4,
add_core_name => "virtex7_latency",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
UUT_DSA : entity work.uaa_tb
generic map(
test_name => "DSA",
arch => UAA_DSA,
parallel_inputs => 4,
add_core_name => "virtex7_speed",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
UUT_SGA : entity work.uaa_tb
generic map(
test_name => "SGA",
arch => UAA_SGA,
parallel_inputs => 4,
add_core_name => "virtex7_speed",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
end DEFAULT;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/dsu3x.vhd | 1 | 40314 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 2;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type tregtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
tforce : std_logic; -- Force AHB trace
timeren : std_logic; -- Keep timer enabled
sample : std_logic; -- Force sample
end record;
constant TRES : tregtype := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0',
tforce => '0',
timeren => '0',
sample => '0'
);
type tfregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
pf : std_ulogic; -- Filter perf outputs
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
bpfilt : std_logic_vector(1 downto 0);
end record;
type pregtype is record
stat : dsu_astat_type;
split : std_ulogic;
splmst : std_logic_vector(3 downto 0);
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
end record;
constant PRES : pregtype := (
stat => dsu_astat_none, split => '0', splmst => "0000", hready => '1', hresp => "00");
constant TFRES : tfregtype :=
(shsel => (others => '0'), pf => '0', af => '0', fr => '0', fw => '0',
smask => (others => '0'), mmask => (others => '0'),
bpfilt => (others => '0'));
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
constant FILTEN : boolean := TRACEN and (ahbpf > 0);
constant PERFEN : boolean := (ahbpf > 1);
function ahb_filt_hit (
tr : tregtype;
tfr : tfregtype) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((tfr.fw and tr.hwrite) or (tfr.fr and not tr.hwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) /= zero32(29 downto 0)) then
if tfr.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in tfr.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(tr.hmaster) and tfr.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in tfr.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (tfr.shsel(i) and tfr.smask(i)) /= '0' then
hit := true;
end if;
end loop;
return hit;
end function ahb_filt_hit;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal pr, prin : pregtype;
signal tfr, tfrin : tfregtype;
signal tr, trin : tregtype;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2, tahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x, tfr, pr)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : tregtype;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable rdata, wdata : std_logic_vector(127 downto 0);
variable bphit : std_logic_vector(1 to 2);
variable vh : hclk_reg_type;
variable atact : std_ulogic; -- ahb trace active
variable tfv : tfregtype;
variable pv : pregtype;
variable slvhaddr : std_logic_vector(2 downto 0);
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata; hwdata := ahbreadword(ahbsi2.hwdata, r.slv.haddr(4 downto 2));
wdata := (others => '0'); rdata := (others => '0');
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0'; tv.sample := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
tfv := tfr; pv := pr;
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
atact := tr.enable and ((not r.act) or tr.tforce);
-- check for AHB watchpoints
bphit := (others => '0');
if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit(1) := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit(2) := '1'; end if;
end if;
-- generate AHB buffer inputs
vabufi.write := (others => '0');
if TRACEN then
wdata(AHBDW-1 downto 0) := tahbsi2.hwdata;
rdata(AHBDW-1 downto 0) := ahbmi.hrdata;
if atact = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := orv(bphit);
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := (others => '0'); --ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+3 downto 4); --tr.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+4 downto 5); --tr.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data(255 downto 0) := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- filter and write trace buffer
if atact = '1' then
if ((tr.ahbactive and tahbsi2.hready) or tr.sample) = '1' then
if not (FILTEN and ahb_filt_hit(tr, tfr)) then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := (others => '1');
elsif FILTEN then
for i in 1 to 2 loop
if tfr.bpfilt(i-1) = '1' then bphit(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- trigger AHB break/watchpoints
if orv(bphit) = '1' then
if (atact = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0'; tv.bphit := tr.break; end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- AHB statistics
if PERFEN then
pv.hready := tahbsi2.hready;
pv.hresp := ahbmi.hresp;
pv.stat := dsu_astat_none;
if pr.hready = '1' then
case tr.htrans is
when HTRANS_IDLE => pv.stat.idle := '1';
when HTRANS_BUSY => pv.stat.busy := '1';
when HTRANS_NONSEQ => pv.stat.nseq := '1';
when others => pv.stat.seq := '1';
end case;
if tr.ahbactive = '1' then
pv.stat.read := not tr.hwrite;
pv.stat.write := tr.hwrite;
case tr.hsize is
when HSIZE_BYTE => pv.stat.hsize(0) := '1';
when HSIZE_HWORD => pv.stat.hsize(1) := '1';
when HSIZE_WORD => pv.stat.hsize(2) := '1';
when HSIZE_DWORD => pv.stat.hsize(3) := '1';
when HSIZE_4WORD => pv.stat.hsize(4) := '1';
when others => pv.stat.hsize(5) := '1';
end case;
end if;
pv.stat.hmaster := tr.hmaster;
end if;
if pr.hresp = HRESP_OKAY then
pv.stat.ws := not pr.hready;
end if;
-- It may also be interesting to count the maximum grant latency. That
-- is; the delay between asserting hbusreq and receiving hgrant. This
-- would require that all bus request signals were present in this
-- entity. This has been left as a possible future extension.
if pr.hready = '1' then
if pr.hresp = HRESP_SPLIT then
pv.stat.split := '1';
pv.split := '1';
if pr.split = '0' then
pv.splmst := tr.hmaster;
end if;
end if;
if pr.hresp = HRESP_RETRY then
pv.stat.retry := '1';
end if;
end if;
pv.stat.locked := tr.hmastlock;
if tfr.pf = '1' and ahb_filt_hit(tr, tfr) then
pv.stat := dsu_astat_none;
pv.split := pr.split; pv.splmst := pr.splmst;
end if;
-- Count cycles where master is in SPLIT
if pr.split = '1' then
for i in ahbmi.hgrant'range loop
if i = conv_integer(pr.splmst) and ahbmi.hgrant(i) = '1' then
pv.split := '0';
end if;
end loop;
pv.stat.spdel := pv.split;
end if;
end if;
-- save AHB transfer parameters
if (tahbsi2.hready or tr.sample) = '1' then
tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans;
tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst;
tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock;
tv.ahbactive := tahbsi2.htrans(1);
if FILTEN then tfv.shsel := tahbsi2.hsel; end if;
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if ((r.dsuen(2) and not tstop) or tr.timeren) = '1' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := hwdata(0);
v.be(index) := hwdata(1);
v.bw(index) := hwdata(2);
v.bs(index) := hwdata(3);
v.bx(index) := hwdata(4);
v.bz(index) := hwdata(5);
v.reset(index) := hwdata(9);
v.halt(index) := hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := hwdata(NCPU-1 downto 0);
v.ss := hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(6 downto 5) := tr.timeren & tr.tforce;
hrdata(4 downto 0) := conv_std_logic_vector(log2(bwidth/32), 2) & tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := hwdata((TBUFABITS+ 15) downto 16);
tv.sample := hwdata(7);
tv.timeren := hwdata(6);
tv.tforce := hwdata(5);
tv.break := hwdata(2);
tv.dcnten := hwdata(1);
tv.enable := hwdata(0);
else
tv.delaycnt := tr.delaycnt;
tv.sample := tr.sample; tv.timeren := tr.timeren;
tv.tforce := tr.tforce; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10010" =>
if FILTEN then
hrdata(9 downto 8) := tfr.bpfilt;
hrdata(3 downto 0) := tfr.pf & tfr.af & tfr.fr & tfr.fw;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.bpfilt := hwdata(9 downto 8);
tfv.pf := hwdata(3);
tfv.af := hwdata(2);
tfv.fr := hwdata(1);
tfv.fw := hwdata(0);
else
tfv.bpfilt := tfr.bpfilt;
tfv.pf := tfr.pf;
tfv.af := tfr.af;
tfv.fr := tfr.fr;
tfv.fw := tfr.fw;
end if;
end if;
end if;
when "10011" =>
if FILTEN then
hrdata := tfr.smask & tfr.mmask;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.smask := hwdata(31 downto 16);
tfv.mmask := hwdata(15 downto 0);
else
tfv.smask := tfr.smask;
tfv.mmask := tfr.mmask;
end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := hwdata(31 downto 2);
tv.tbreg1.read := hwdata(1);
tv.tbreg1.write := hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := hwdata(31 downto 2);
tv.tbreg2.read := hwdata(1);
tv.tbreg2.write := hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not atact;
slvhaddr := r.slv.haddr(4 downto 2);
case slvhaddr is
when "000" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "001" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "010" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when "011" =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
when "100" =>
if bwidth > 32 then
hrdata := tbo.data(159 downto 128);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(7) := vabufi.enable and v.slv.hready;
end if;
else
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(223 downto 192);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(6) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(191 downto 160);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(5) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
end if;
when others =>
if bwidth > 32 then
hrdata := zero32;
else
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0';
tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
if FILTEN then
tfv.pf := '0'; tfv.af := '0'; tfv.fr := '0'; tfv.fw := '0';
tfv.smask := (others => '0'); tfv.mmask := (others => '0');
tfv.bpfilt := (others => '0');
end if;
if PERFEN then
pv.split := '0'; pv.splmst := (others => '0');
end if;
end if;
rin <= v; trin <= tv; tbi <= vabufi; tfrin <= tfv; prin <= pv;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
if PERFEN then dsuo.astat <= pr.stat; else dsuo.astat <= dsu_astat_none; end if;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
-- register i/f
gen0 : for i in ahbsi.hsel'range generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen1 : for i in ahbsi.haddr'range generate
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
gen3 : for i in ahbsi.htrans'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen4 : for i in ahbsi.hwdata'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
-- not used by register i/f:
ahbsi2.hsize <= (others => '0');
ahbsi2.hburst <= (others => '0');
ahbsi2.hprot <= (others => '0');
ahbsi2.hmaster <= (others => '0');
ahbsi2.hmastlock <= '0';
ahbsi2.hmbsel <= (others => '0');
ahbsi2.hirq <= (others => '0');
ahbsi2.testen <= '0';
ahbsi2.testrst <= '0';
ahbsi2.scanen <= '0';
ahbsi2.testoen <= '0';
-- trace buffer:
gen6 : for i in tahbsi.haddr'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i));
end generate;
ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite);
gen8 : for i in tahbsi.htrans'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i));
end generate;
gen9 : for i in tahbsi.hsize'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i));
end generate;
gen10 : for i in tahbsi.hburst'range generate
a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i));
end generate;
gen11 : for i in tahbsi.hwdata'range generate
ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i));
end generate;
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready);
gen12 : for i in tahbsi.hmaster'range generate
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i));
end generate;
ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock);
gen14 : for i in tahbsi.hsel'range generate
ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i));
end generate;
-- not used by trace buffer:
tahbsi2.hprot <= (others => '0');
tahbsi2.hmbsel <= (others => '0');
tahbsi2.hirq <= (others => '0');
tahbsi2.testen <= '0';
tahbsi2.testrst <= '0';
tahbsi2.scanen <= '0';
tahbsi2.testoen <= '0';
gen15 : for i in hrdata2x'range generate
ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
tahbsi2 <= tahbsi;
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
tpf : if FILTEN generate
pfreg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tfr <= tfrin;
if RESET_ALL and (rst = '0') then tfr <= TFRES; end if;
end if;
end process;
end generate;
perf : if PERFEN generate
preg : process(cpuclk)
begin
if rising_edge(cpuclk) then
pr <= prin;
if RESET_ALL and (rst = '0') then pr <= PRES; end if;
end if;
end process;
end generate;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, dwidth => bwidth, testen => testen)
port map (cpuclk, tbi, tbo, ahbsi.testin
);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
tbo.data <= (others => '0');
tr <= TRES;
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
notpf : if not FILTEN generate
tfr.shsel <= (others => '0');
tfr.pf <= '0';
tfr.af <= '0';
tfr.fr <= '0';
tfr.fw <= '0';
tfr.smask <= (others => '0');
tfr.mmask <= (others => '0');
tfr.bpfilt <= (others => '0');
end generate;
noperf : if not PERFEN generate
pr.stat <= dsu_astat_none;
pr.split <= '0';
pr.splmst <= (others => '0');
pr.hready <= '0';
pr.hresp <= (others => '0');
end generate;
end;
| gpl-3.0 |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Add.vhd | 1 | 6569 | -- megafunction wizard: %PARALLEL_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: parallel_add
-- ============================================================
-- File Name: Add.vhd
-- Megafunction Name(s):
-- parallel_add
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY Add IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Add;
ARCHITECTURE SYN OF add IS
-- type ALTERA_MF_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire2 : ALTERA_MF_LOGIC_2D (1 DOWNTO 0, 31 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
sub_wire3 <= data0x(31 DOWNTO 0);
result <= sub_wire0(31 DOWNTO 0);
sub_wire1 <= data1x(31 DOWNTO 0);
sub_wire2(1, 0) <= sub_wire1(0);
sub_wire2(1, 1) <= sub_wire1(1);
sub_wire2(1, 2) <= sub_wire1(2);
sub_wire2(1, 3) <= sub_wire1(3);
sub_wire2(1, 4) <= sub_wire1(4);
sub_wire2(1, 5) <= sub_wire1(5);
sub_wire2(1, 6) <= sub_wire1(6);
sub_wire2(1, 7) <= sub_wire1(7);
sub_wire2(1, 8) <= sub_wire1(8);
sub_wire2(1, 9) <= sub_wire1(9);
sub_wire2(1, 10) <= sub_wire1(10);
sub_wire2(1, 11) <= sub_wire1(11);
sub_wire2(1, 12) <= sub_wire1(12);
sub_wire2(1, 13) <= sub_wire1(13);
sub_wire2(1, 14) <= sub_wire1(14);
sub_wire2(1, 15) <= sub_wire1(15);
sub_wire2(1, 16) <= sub_wire1(16);
sub_wire2(1, 17) <= sub_wire1(17);
sub_wire2(1, 18) <= sub_wire1(18);
sub_wire2(1, 19) <= sub_wire1(19);
sub_wire2(1, 20) <= sub_wire1(20);
sub_wire2(1, 21) <= sub_wire1(21);
sub_wire2(1, 22) <= sub_wire1(22);
sub_wire2(1, 23) <= sub_wire1(23);
sub_wire2(1, 24) <= sub_wire1(24);
sub_wire2(1, 25) <= sub_wire1(25);
sub_wire2(1, 26) <= sub_wire1(26);
sub_wire2(1, 27) <= sub_wire1(27);
sub_wire2(1, 28) <= sub_wire1(28);
sub_wire2(1, 29) <= sub_wire1(29);
sub_wire2(1, 30) <= sub_wire1(30);
sub_wire2(1, 31) <= sub_wire1(31);
sub_wire2(0, 0) <= sub_wire3(0);
sub_wire2(0, 1) <= sub_wire3(1);
sub_wire2(0, 2) <= sub_wire3(2);
sub_wire2(0, 3) <= sub_wire3(3);
sub_wire2(0, 4) <= sub_wire3(4);
sub_wire2(0, 5) <= sub_wire3(5);
sub_wire2(0, 6) <= sub_wire3(6);
sub_wire2(0, 7) <= sub_wire3(7);
sub_wire2(0, 8) <= sub_wire3(8);
sub_wire2(0, 9) <= sub_wire3(9);
sub_wire2(0, 10) <= sub_wire3(10);
sub_wire2(0, 11) <= sub_wire3(11);
sub_wire2(0, 12) <= sub_wire3(12);
sub_wire2(0, 13) <= sub_wire3(13);
sub_wire2(0, 14) <= sub_wire3(14);
sub_wire2(0, 15) <= sub_wire3(15);
sub_wire2(0, 16) <= sub_wire3(16);
sub_wire2(0, 17) <= sub_wire3(17);
sub_wire2(0, 18) <= sub_wire3(18);
sub_wire2(0, 19) <= sub_wire3(19);
sub_wire2(0, 20) <= sub_wire3(20);
sub_wire2(0, 21) <= sub_wire3(21);
sub_wire2(0, 22) <= sub_wire3(22);
sub_wire2(0, 23) <= sub_wire3(23);
sub_wire2(0, 24) <= sub_wire3(24);
sub_wire2(0, 25) <= sub_wire3(25);
sub_wire2(0, 26) <= sub_wire3(26);
sub_wire2(0, 27) <= sub_wire3(27);
sub_wire2(0, 28) <= sub_wire3(28);
sub_wire2(0, 29) <= sub_wire3(29);
sub_wire2(0, 30) <= sub_wire3(30);
sub_wire2(0, 31) <= sub_wire3(31);
parallel_add_component : parallel_add
GENERIC MAP (
msw_subtract => "NO",
pipeline => 0,
representation => "UNSIGNED",
result_alignment => "LSB",
shift => 0,
size => 2,
width => 32,
widthr => 32,
lpm_type => "parallel_add"
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
-- Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
-- Retrieval info: CONSTANT: SHIFT NUMERIC "0"
-- Retrieval info: CONSTANT: SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTHR NUMERIC "32"
-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM.vhd | 1 | 6221 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAM.vhd when simulating
-- the core, RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END RAM;
ARCHITECTURE RAM_a OF RAM IS
-- synthesis translate_off
COMPONENT wrapped_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan3a"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END RAM_a;
| gpl-3.0 |
hoglet67/CoPro6502 | src/DCM/dcm_32_8.vhd | 1 | 2061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_8 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_8;
architecture BEHAVIORAL of dcm_32_8 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 8.000 = 32.000 * 5/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-111/leon3mp.vhd | 1 | 16651 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.11",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 |
hoglet67/CoPro6502 | src/T6502/T65_ALU.vhd | 1 | 8522 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 ost(ML) July 2014
-- ALU opcodes to vhdl types
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
variable CT : std_logic;
begin
CT:='0';
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
Op=ALU_OP_ADC or --"0011"
Op=ALU_OP_EQ2 or --"0101"
Op=ALU_OP_SBC or --"0111"
Op=ALU_OP_ROL or --"1001"
Op=ALU_OP_ROR or --"1011"
Op=ALU_OP_EQ3 or --"1101"
Op=ALU_OP_INC --"1111"
) then
CT:='1';
end if;
C := P_In(Flag_C) or not CT;--was: or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;
when ALU_OP_AND=>
Q_t := BusA and BusB;
when ALU_OP_EOR=>
Q_t := BusA xor BusB;
when ALU_OP_ADC=>
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when ALU_OP_EQ2|ALU_OP_EQ3=>
-- LDA
when ALU_OP_CMP=>
P_Out(Flag_C) <= SBC_C;
when ALU_OP_SBC=>
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when ALU_OP_ASL=>
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when ALU_OP_ROL=>
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when ALU_OP_LSR=>
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ROR=>
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_BIT=>
P_Out(Flag_V) <= BusB(6);
when ALU_OP_DEC=>
Q_t := std_logic_vector(unsigned(BusA) - 1);
when ALU_OP_INC=>
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
--EQ1,EQ2,EQ3 passes BusA to Q_t
end case;
case Op is
when ALU_OP_ADC=>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when ALU_OP_CMP|ALU_OP_SBC=>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when ALU_OP_EQ1=>
when ALU_OP_BIT=>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libiu.vhd | 1 | 9104 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
constant cctrl_none : cctrltype := (
burst => '0', dfrz => '0', ifrz => '0', dsnoop => '0',
dcs => (others => '0'), ics => (others => '0')
);
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
fline : std_logic_vector(31 downto 3); -- flush line offset
nobpmiss : std_ulogic; -- Predicted instruction, block hold
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
cstat : l3_cstat_type;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
mmucacheclr : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
hit : std_ulogic;
cstat : l3_cstat_type;
wbhold : std_ulogic;
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15 := 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
end component;
end;
| gpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.