repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/win_1/win_stub.vhdl | 2 | 1344 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:35:24 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/win_1/win_stub.vhdl
-- Design : win
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity win is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end win;
architecture stub of win is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| gpl-3.0 |
algebrato/eldig | Lez12/num.vhd | 1 | 3849 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:31 04/21/2016
-- Design Name:
-- Module Name: num - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--Tutto quello che entra in SEZIONE LOGICA CONCORRENTE -- e` tutto in parallelo (non conta l'ordine)
--non ho un prima o un dopo (solo logica combinatoria -> le uscite al tempo t sono una funzione al tempo t).
--Ma posso aver bisogno di un ordine (logica sequenziale) out(t)=f(I(t))_{t<=t_0} quindi gli ingressi dipenderanno anche
--da quello che e` successo nel passato. Uguale a scrivere a out(t_0) = g(I(t_0), stati(t_0)), gli stati sono informazioni
--interne alal scatola.
--Un contatore e` un oggetto di logica sequenziale. L'ingresso e` un segnale di tipo "enable" se passo da 0 a 1 allora incrementa di 1
--passo da uno stato all'altro da una certa regola
entity num is
Port ( SW : in STD_LOGIC_VECTOR(7 downto 0);
N_OUT : out UNSIGNED(3 downto 0);
SEG : out STD_LOGIC_VECTOR(0 to 6)
);
end num;
architecture Behavioral of num is
signal N: UNSIGNED(2 downto 0);
begin
--flipflop di tipo D
contatore_3bit:process(enable)
begin
if rising_edge(enable) then
--N <= N+1; --sfrutto algebra di bool (perdo il riporto)
--oppure, in modo diverso
if N=7 then N<= "000";
else N<=N+1
end if
end if
end process contatore_3bit;
--possibili rappresentazioni della stessa cosa (porta AND)
C <= A and B;
C <= '1' when A='1' and B='1' else '0';
porta_and:process(A,B)
begin
if A='1' and B='1' then
C <='1';
else
C <= '0';
end if;
end process porta_and;
--possibili interpretazioni del multiplexer
with sel select
C <= A when '1',
B when '0';
--implementazione della porta AND col multiplexer
with sel select
C <= '1' when '11',
'0' when others;
--N_OUT(0)<='0' when SW(0)='1' else '1';
--N_OUT(1)<='0' when SW(1)='1' else '1';
--N_OUT(2)<='0' when SW(2)='1' else '1';
--N_OUT(3)<='0' when SW(3)='1' else '1';
--N<=UNSIGNED(SW(7 downto 4));
--SEG(0)<='0' when N=0 or N=2 or N=3 or N>4 else '1';
--SEG(1)<='0' when N=0 or N=1 or N=2 or N=3 or N=4 or N=7 or N=8 or N=9 else '1';
--SEG(2)<='0' when N=0 or N=1 or N=3 or N=4 or N=5 or N=6 or N=7 or N=8 or N=9 else '1';
--SEG(3)<='0' when N=0 or N=2 or N=3 or N=5 or N=6 or N=8 or N>9 else '1';
--SEG(4)<='0' when N=0 or N=2 or N=6 or N=8 or N>9 else '1';
--SEG(5)<='0' when N=0 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
--SEG(6)<='0' when N=2 or N=3 or N=4 or N=5 or N=6 or N=8 or N>8 else '1';
--processi--
--P1:process(A,B,C) --sensivity list
--parte dichiarativa
--parte implementativa --dentro una entity posso avere tanti processi quanti ne voglio
--la struttura del processo, come blocco, sono all'interno della sezione concorrente.
--stanno tutte parallelamente nella entity. I processi, sono tra loro concorrenti (agiscono in modo indipendente)
--ma all'interno di un processo c'e` un "prima" e un "dopo" c'e` una certa idea di sequenzialita`
--i processi parlano tra loro tramite i segnali! Oppure posso usare le VARIABILI. Sono piu` astratte
--end process P1;
end Behavioral;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/pikachu_down_pixel/pikachu_down_pixel_stub.vhdl | 2 | 1449 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_stub.vhdl
-- Design : pikachu_down_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pikachu_down_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end pikachu_down_pixel;
architecture stub of pikachu_down_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_pixel/bg_pixel_sim_netlist.vhdl | 1 | 608016 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Dec 23 11:06:46 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pixel/bg_pixel_sim_netlist.vhdl
-- Design : bg_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 14 downto 0 );
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_bindec : entity is "bindec";
end bg_pixel_bindec;
architecture STRUCTURE of bg_pixel_bindec is
begin
ENOUT: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(0),
I3 => addra(1),
I4 => addra(2),
O => ena_array(0)
);
\ENOUT__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(0),
I3 => addra(1),
I4 => addra(2),
O => ena_array(1)
);
\ENOUT__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(1),
I3 => addra(0),
I4 => addra(2),
O => ena_array(2)
);
\ENOUT__10\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(4),
I1 => addra(1),
I2 => addra(0),
I3 => addra(2),
I4 => addra(3),
O => ena_array(11)
);
\ENOUT__11\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addra(4),
I1 => addra(1),
I2 => addra(3),
I3 => addra(0),
I4 => addra(2),
O => ena_array(12)
);
\ENOUT__12\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addra(4),
I1 => addra(0),
I2 => addra(3),
I3 => addra(1),
I4 => addra(2),
O => ena_array(13)
);
\ENOUT__13\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => addra(4),
I1 => addra(3),
I2 => addra(2),
I3 => addra(0),
I4 => addra(1),
O => ena_array(14)
);
\ENOUT__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(2),
I3 => addra(0),
I4 => addra(1),
O => ena_array(3)
);
\ENOUT__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(2),
I3 => addra(0),
I4 => addra(1),
O => ena_array(4)
);
\ENOUT__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(1),
I3 => addra(0),
I4 => addra(2),
O => ena_array(5)
);
\ENOUT__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(3),
I1 => addra(4),
I2 => addra(0),
I3 => addra(1),
I4 => addra(2),
O => ena_array(6)
);
\ENOUT__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(4),
I1 => addra(2),
I2 => addra(3),
I3 => addra(0),
I4 => addra(1),
O => ena_array(7)
);
\ENOUT__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(4),
I1 => addra(2),
I2 => addra(1),
I3 => addra(0),
I4 => addra(3),
O => ena_array(8)
);
\ENOUT__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(4),
I1 => addra(2),
I2 => addra(0),
I3 => addra(1),
I4 => addra(3),
O => ena_array(9)
);
\ENOUT__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addra(4),
I1 => addra(2),
I2 => addra(3),
I3 => addra(0),
I4 => addra(1),
O => ena_array(10)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_mux is
port (
\^douta\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
clka : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 0 to 0 );
DOUTA : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_31\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_32\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_33\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_34\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_35\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_pixel_blk_mem_gen_mux;
architecture STRUCTURE of bg_pixel_blk_mem_gen_mux is
signal \douta[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0),
I2 => sel_pipe_d1(3),
I3 => sel_pipe_d1(4),
I4 => DOUTA(0),
O => \^douta\(0)
);
\douta[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[10]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[10]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[10]_INST_0_i_3_n_0\,
O => \^douta\(10)
);
\douta[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(7),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I5 => sel_pipe_d1(2),
O => \douta[10]_INST_0_i_1_n_0\
);
\douta[10]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[10]_INST_0_i_4_n_0\,
I1 => \douta[10]_INST_0_i_5_n_0\,
O => \douta[10]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[10]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[10]_INST_0_i_6_n_0\,
I1 => \douta[10]_INST_0_i_7_n_0\,
O => \douta[10]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[10]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(7),
O => \douta[10]_INST_0_i_4_n_0\
);
\douta[10]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(7),
O => \douta[10]_INST_0_i_5_n_0\
);
\douta[10]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(7),
O => \douta[10]_INST_0_i_6_n_0\
);
\douta[10]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(7),
O => \douta[10]_INST_0_i_7_n_0\
);
\douta[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[11]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[11]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[11]_INST_0_i_3_n_0\,
O => \^douta\(11)
);
\douta[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOPADOP(0),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I5 => sel_pipe_d1(2),
O => \douta[11]_INST_0_i_1_n_0\
);
\douta[11]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[11]_INST_0_i_4_n_0\,
I1 => \douta[11]_INST_0_i_5_n_0\,
O => \douta[11]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[11]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[11]_INST_0_i_6_n_0\,
I1 => \douta[11]_INST_0_i_7_n_0\,
O => \douta[11]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[11]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_30\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_31\(0),
O => \douta[11]_INST_0_i_4_n_0\
);
\douta[11]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_32\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_33\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_34\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_35\(0),
O => \douta[11]_INST_0_i_5_n_0\
);
\douta[11]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(0),
O => \douta[11]_INST_0_i_6_n_0\
);
\douta[11]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(0),
O => \douta[11]_INST_0_i_7_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0),
I2 => sel_pipe_d1(3),
I3 => sel_pipe_d1(4),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\(0),
O => \^douta\(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1),
I2 => sel_pipe_d1(3),
I3 => sel_pipe_d1(4),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_0\(0),
O => \^douta\(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[3]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[3]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[3]_INST_0_i_3_n_0\,
O => \^douta\(3)
);
\douta[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(0),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I5 => sel_pipe_d1(2),
O => \douta[3]_INST_0_i_1_n_0\
);
\douta[3]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_4_n_0\,
I1 => \douta[3]_INST_0_i_5_n_0\,
O => \douta[3]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[3]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[3]_INST_0_i_6_n_0\,
I1 => \douta[3]_INST_0_i_7_n_0\,
O => \douta[3]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[3]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(0),
O => \douta[3]_INST_0_i_4_n_0\
);
\douta[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(0),
O => \douta[3]_INST_0_i_5_n_0\
);
\douta[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(0),
O => \douta[3]_INST_0_i_6_n_0\
);
\douta[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(0),
O => \douta[3]_INST_0_i_7_n_0\
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[4]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[4]_INST_0_i_3_n_0\,
O => \^douta\(4)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(1),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I5 => sel_pipe_d1(2),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_4_n_0\,
I1 => \douta[4]_INST_0_i_5_n_0\,
O => \douta[4]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_6_n_0\,
I1 => \douta[4]_INST_0_i_7_n_0\,
O => \douta[4]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(1),
O => \douta[4]_INST_0_i_4_n_0\
);
\douta[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(1),
O => \douta[4]_INST_0_i_5_n_0\
);
\douta[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(1),
O => \douta[4]_INST_0_i_6_n_0\
);
\douta[4]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(1),
O => \douta[4]_INST_0_i_7_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[5]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[5]_INST_0_i_3_n_0\,
O => \^douta\(5)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(2),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I5 => sel_pipe_d1(2),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_4_n_0\,
I1 => \douta[5]_INST_0_i_5_n_0\,
O => \douta[5]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_6_n_0\,
I1 => \douta[5]_INST_0_i_7_n_0\,
O => \douta[5]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(2),
O => \douta[5]_INST_0_i_4_n_0\
);
\douta[5]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(2),
O => \douta[5]_INST_0_i_5_n_0\
);
\douta[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(2),
O => \douta[5]_INST_0_i_6_n_0\
);
\douta[5]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(2),
O => \douta[5]_INST_0_i_7_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[6]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[6]_INST_0_i_3_n_0\,
O => \^douta\(6)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(3),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I5 => sel_pipe_d1(2),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_4_n_0\,
I1 => \douta[6]_INST_0_i_5_n_0\,
O => \douta[6]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_6_n_0\,
I1 => \douta[6]_INST_0_i_7_n_0\,
O => \douta[6]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(3),
O => \douta[6]_INST_0_i_4_n_0\
);
\douta[6]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(3),
O => \douta[6]_INST_0_i_5_n_0\
);
\douta[6]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(3),
O => \douta[6]_INST_0_i_6_n_0\
);
\douta[6]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(3),
O => \douta[6]_INST_0_i_7_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[7]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[7]_INST_0_i_3_n_0\,
O => \^douta\(7)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(4),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I5 => sel_pipe_d1(2),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_4_n_0\,
I1 => \douta[7]_INST_0_i_5_n_0\,
O => \douta[7]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_6_n_0\,
I1 => \douta[7]_INST_0_i_7_n_0\,
O => \douta[7]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(4),
O => \douta[7]_INST_0_i_4_n_0\
);
\douta[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(4),
O => \douta[7]_INST_0_i_5_n_0\
);
\douta[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(4),
O => \douta[7]_INST_0_i_6_n_0\
);
\douta[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(4),
O => \douta[7]_INST_0_i_7_n_0\
);
\douta[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[8]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[8]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[8]_INST_0_i_3_n_0\,
O => \^douta\(8)
);
\douta[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(5),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I5 => sel_pipe_d1(2),
O => \douta[8]_INST_0_i_1_n_0\
);
\douta[8]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_4_n_0\,
I1 => \douta[8]_INST_0_i_5_n_0\,
O => \douta[8]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_6_n_0\,
I1 => \douta[8]_INST_0_i_7_n_0\,
O => \douta[8]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(5),
O => \douta[8]_INST_0_i_4_n_0\
);
\douta[8]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(5),
O => \douta[8]_INST_0_i_5_n_0\
);
\douta[8]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(5),
O => \douta[8]_INST_0_i_6_n_0\
);
\douta[8]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(5),
O => \douta[8]_INST_0_i_7_n_0\
);
\douta[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \douta[9]_INST_0_i_1_n_0\,
I1 => sel_pipe_d1(4),
I2 => \douta[9]_INST_0_i_2_n_0\,
I3 => sel_pipe_d1(3),
I4 => \douta[9]_INST_0_i_3_n_0\,
O => \^douta\(9)
);
\douta[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => DOADO(6),
I1 => sel_pipe_d1(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I5 => sel_pipe_d1(2),
O => \douta[9]_INST_0_i_1_n_0\
);
\douta[9]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_4_n_0\,
I1 => \douta[9]_INST_0_i_5_n_0\,
O => \douta[9]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_6_n_0\,
I1 => \douta[9]_INST_0_i_7_n_0\,
O => \douta[9]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(6),
O => \douta[9]_INST_0_i_4_n_0\
);
\douta[9]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(6),
O => \douta[9]_INST_0_i_5_n_0\
);
\douta[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(6),
O => \douta[9]_INST_0_i_6_n_0\
);
\douta[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(6),
O => \douta[9]_INST_0_i_7_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(3),
Q => sel_pipe_d1(3),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(4),
Q => sel_pipe_d1(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(3),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(4),
Q => sel_pipe(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_prim_wrapper_init is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_pixel_blk_mem_gen_prim_wrapper_init is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "COMMON";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FACF2D00A6CAFEAC6743641DA5F24F259F59E5C514F95ED69FF2DBEEA49E49E6",
INIT_01 => X"A25EE7EC6741761D38D3A3932C12DD45F9E78BEE8EE82E433493C935CE927924",
INIT_02 => X"4EC82B21BFE76F33F6EBDC84658BCA7E11DD07CA7A0BB0E9CE9ECD3D6196682F",
INIT_03 => X"1B0325882EF23D415E907D4F8AD21FABF24394A4FF3B69D4E9EEF99F3C5A43F4",
INIT_04 => X"65DE80F93CAF501E2F6581E6222680D80CA5B0C37795EA0345E847057C44701B",
INIT_05 => X"61CABCE21039789EE9AF129128921880AC3E57F533F52F13E1FA0FF125104350",
INIT_06 => X"F58F5AE4A8CA9F80F04B04BA5A80A1AB6C828E41951953F04486002B0090C405",
INIT_07 => X"B0A712317EB46E94E6CAEAB5990E3521B2A3287E0654EC0F824FFFDFEF854D59",
INIT_08 => X"2344AA9BF7F44189E121C6A42B2CB8D48592FEBEF72750267E66741CC8619D1F",
INIT_09 => X"DEE71872359C621E46C9B94FFFCA23ABDE08EC3BFEA28C46C8D03A9994AFD474",
INIT_0A => X"6861FFDF5FECAF01E11B993CDDEC4CCF4D78DDAEE97E15E017BBF43D5B9D899A",
INIT_0B => X"4F62A6B92F9A4BF5FFFD2ED9C5887A8E9F01A31225F3497F1B53B3334F627662",
INIT_0C => X"35175B3E96EE68D5851881838C36862864B2692FFC925FAFFE1EFEE239E3D47C",
INIT_0D => X"777AC1CA6D61C683458ED0C507B18A192F989EA0D01B47AC42F0FD0461F63141",
INIT_0E => X"2C8C38D17D91877AAFF99EE0F07F4E0AE05233534B32348F552B36A247A46D89",
INIT_0F => X"FA43FEDB7FE15BECD7F8413E8ECAF3B65FF2DBEEFB832BFC4ED87C71DDC95E36",
INIT_10 => X"B1BB0FB6FA3DE39E39E78BEEBE3BA33356B8DA6EAB47BC73AAB9ADC7DE573DB0",
INIT_11 => X"F6EBDC84E92E88DC14AD5E91BB3963F59B68E78E71EF1CF1CDC3FFECB1A91D99",
INIT_12 => X"051E83BBFD38F10160E72D7FAE1CE5AFB47BFFFEFDA847CDAED2677639C31CA7",
INIT_13 => X"C0A39E622E1452CAC5A4FAD057A848CB3847C64AA9C28A595B0325889DBD0415",
INIT_14 => X"0FFFFFFFFFF5A3022D1241EBF7BCE44621FA0FF17306B462816D2739B2FF9C82",
INIT_15 => X"BD23505A03A4B0C96C828E41C51A35F292C32CABD8709699EF9D73907DF7AA33",
INIT_16 => X"A6CAEAB5A9F5891D8726E02E79A91F81F80E12DB2D01C65B6499E7EE7001AD9A",
INIT_17 => X"F430550B14E76BC0333D23A12A47A47526471F84160C68EDA5DF5E9C6D48F48E",
INIT_18 => X"9ED86D381DDA08A30202CF841F8201D0E2ACBAA8A73B5C052344AA9B9524417A",
INIT_19 => X"BDD674D3A77F311854BA6962D02FD4B2D7BBF43D766FE6232F0F601F6F896A87",
INIT_1A => X"BA2DA0570454C1F81F01A3123867C575E09E457D448B983FBBF12D95E97EA596",
INIT_1B => X"0518818300B080C17D8B5E3596C5E605DD107B07C2A60FC0F80DA251C93E2BA2",
INIT_1C => X"3007F9D3C6E5AF8E38DCBE81313B95502086803005840201651314B32E2F30AA",
INIT_1D => X"B65E95F5C86BD3ABBB929001C501A783D5156A1B850D7C75777AC1CA292434F3",
INIT_1E => X"76C3EA4C1844662E16C16BF55F5975278ED87C7181888C44020A37FF7FEBAEA4",
INIT_1F => X"DBAA53E653872B6FD6B8DA6EE3C2837600E4BE07BE70ED6DB67D71E49ACFAA3C",
INIT_20 => X"14AD5E9125528561FFB00FCBE9EA9621D94E59BDBF394B7EB7C6D3771F1423B8",
INIT_21 => X"2C0E84409C875DAAA4BD52C53AB7A858A52AF48F2A942B00D42954B12F54B50A",
INIT_22 => X"9D90E2B541F23C5628E41D98D42F973071839291643A659AC51E83BB1A04F2E7",
INIT_23 => X"4F6939D9B0AFB492AC9DAD827F0BE6CB816D27393E1D769A3DE14C0EF7E97CD9",
INIT_24 => X"AE6AA313B913953452C32CAB8E9879DD4D689793C7227AA460FD33DA381F365C",
INIT_25 => X"0726E02E76E42FA2EE56CC74AE3CB4026CE54D54899CA9AA9219655E75C3CEE4",
INIT_26 => X"2A2CA982957106E8814B96C0CE2970C839370171B7237615D858B3C115C5AE19",
INIT_27 => X"C12FA0DD0C65FC0BA1A6281B8CC33CBFB29FB2D04988BF017430550B275C6517",
INIT_28 => X"797B04FB875334EB76B1D30421F285FBAF0F601F66E866DCE3D2BC30F53FD01F",
INIT_29 => X"84C54C37CFF9E910A09E457D53DD3D9A1600F003B8DF3D22BCA1FAC3EF942FDD",
INIT_2A => X"FD8B5E35D6D9EFBC6C8E4A8503E377FB3F1B66A07BCB68850CD24B6A9EA9ECDE",
INIT_2B => X"41818E10ACB4515AE6FC6EFF78DFAFCFEC5AD1AE36EB6DFDFAFF2DF31F1BFDF8",
INIT_2C => X"43968E2A0470D1CDC03E86B4AC8FB0D24901D488A5AE8A517007F9D39791761B",
INIT_2D => X"1051B7FABA8BAF6DEB9832C42CFE2DE2020A37FF575A77EDBB836125019FC510",
INIT_2E => X"1420F00F44F854CC40E4BE07E0660C2BDFF03B0AE4BD1A9945B3F8A202B17F10",
INIT_2F => X"7FB00FCBF9F34C6E0F07A030256056FFBF17235027C2E66A0725F07F03706146",
INIT_30 => X"F6A01E489805C1D0882C4A9FF1058F53FD025E0FCFD8637D52C396EA0B22B5FA",
INIT_31 => X"7A01B82B0150350560740142414A32800C768140C02A0680AC0E8440D029C610",
INIT_32 => X"CF2A60BF647C90667802256278A68A167DE14C0EEC8F93D1FFD3EB7A3F144153",
INIT_33 => X"BD21D5457741ECDBCD6897937B71A5C996435CF38EE8359A59E2893A65345123",
INIT_34 => X"2E56CC749B6DAEB3D3CDFDDDA522407C3137D5E51A1F20DE6944BC9BD98D378E",
INIT_35 => X"4EE95C5E2C85119CCF3CB1494C94190972B66324FA6D5069F6E39689299283E1",
INIT_36 => X"EB3325E931E0845FF0450C1561264DF56ECA64FD262C9CC3AA2CA982AC24C07A",
INIT_37 => X"0F95E1851D4173DAD3745C0DA4CA544F23D2BC30A3A1885DE8B88B819499CA89",
INIT_38 => X"B77BCC7DA67A8762D600F003B1553F62F6BAF98EF48F50EC77A2E06D2652A279",
INIT_39 => X"AC8E4A850974B6F00F816B0ED165B718AEDA63E533D43B56B14F801D8AE86FF0",
INIT_3A => X"A9268D28BE92F543F05E47AC7949C6CD6472D4204B85587EBA51D8778B2938C0",
INIT_3B => X"48A71A3CA4FC50D60C2CF0C67051BD3D469A6347F4978A1A41818E10CC0A96D0",
INIT_3C => X"D41B8961D29B21F386BE7A97CC715FE8FB8361253A5351D899780F5AFB8E2BFD",
INIT_3D => X"B3A8A987FCD359759FF03B0AFC6C4D9F575B9730FE926B2F5E03D4BE638A3B47",
INIT_3E => X"CF07A030472E59D1F9F75D68AA26302F76F54C1CC2FAC9ACFFC9D85DE362D1FF",
INIT_3F => X"DDE1625C49D377FFF5D7DA2308A819CA78BD01823833F7D9480AFB4471318139",
INIT_40 => X"F4EC95027125EDDFF500724F495353DF973392E04E22BDFAB6A01E48A92397EA",
INIT_41 => X"FEFF7BF55731630AF7FFF71F95DFD9BDFFD3EB7AAA417FDDE6767EE3B2BBFB37",
INIT_42 => X"F0C6512F3BD2B97256435CF3C31075CB4A70CE25E572572E99A1A8F8AEEACDEC",
INIT_43 => X"A5A243243F5246FB10CCACA1BD6804C9FB878979D795CB92B31AE78659D3AC1F",
INIT_44 => X"9E473B75377AE58AB2119A6FDAB5201B2D129121FAA7AA82CF35400DEB50260B",
INIT_45 => X"92DA902DD6DD6B9A292438C50174052CEC419709BBDB2C524574871AA02918FC",
INIT_46 => X"66B63142952B523E6244C6E9C0FA54AF2CD6862856AACFCF0D65C117BC1F481D",
INIT_47 => X"DE91A3D3C5404E5CE4EE6F8FF0CD5FFFD7F08A4A248C2BCB13DA842E47F0FD70",
INIT_48 => X"2F3A74BD616297690863B432ECCE5EF2DF97D9E1281232EF26737C7F867875D5",
INIT_49 => X"F14F0A2147F44E26B7CBBFE303B3BDE1699385EB1AA836E8696FD5BDA27677B8",
INIT_4A => X"B7FFBFF8A51B896B9130E00389AF20FB535F2BBFE6A2713072E41C0175264F32",
INIT_4B => X"E9B68E73CF3590503D7F3BEEEE6EE0CD2D36D1CE79640EFB5E445B8DDDC9D818",
INIT_4C => X"08EBD496F99D85DB627335B37F86B4DC080827437113B49FCF9126F533772669",
INIT_4D => X"0A3077F93117C974BC9B0C682A5B14A4BFFABE500CCC6ED313992D9BFD3F6036",
INIT_4E => X"61B7A416A8DD1D10F7D2FF69B0C16E5A1183BEC998BC68AFDBCDF664A298A56B",
INIT_4F => X"E9F91EC11263F474E3F6B11D28B1154A75F1F93D72CCFA87BD7E5243A316A105",
INIT_50 => X"FACF2CA0A6CAFEAC681F9C1D69F24F259F59E5C514F95ED68EE868C3A49E49E6",
INIT_51 => X"BEFFFFE77741761D38D3A3932C12DD45F54BDCEC8EE82E433FBE8DB2AE927924",
INIT_52 => X"4EC82B21BFE76F339DBD5F32E58BCA7EFFFFCE283A0BB0E9CE9C68916196682F",
INIT_53 => X"4054B498AEF23D419F57825DEAD21FABF241F30DFF3B69D4F0CED252C85A43F4",
INIT_54 => X"3E4708853CAF501E2F62302BA22680D8009E64A13F95EA0345E847057C44701B",
INIT_55 => X"61F6BFA99FB9789EE95DF6BE78921880AC3E57F533F52F13DD35E25025104350",
INIT_56 => X"F685BAC908CA9F80F04B04BA5A80A1AB3EB1EB58951953F0FBFFB6C94090C405",
INIT_57 => X"B0A712317EB46E94CFCCCA83990E3521927BC4096654EC0F825825D2D5054D59",
INIT_58 => X"3BC59DA777F441893132D20A0B2CB8D485B89183DDA750267F2ACA1CA8619D1F",
INIT_59 => X"61A1334FB59C621E46A1D4CCC55A23ABDE00983BFEA28C46C8D03A9994AFD474",
INIT_5A => X"6BC66D775B74AF01E119493CDDEC4CCF4D78DDAEE97E15E03E227B2FDB9D899A",
INIT_5B => X"4F62A6B92F9A4BF5FFFD2ED9C5887A8EC1CC54DF25F3497F0092C9E6EF627662",
INIT_5C => X"35175B3E96EE68D5C87E18A08C368628780D31D17C925FAFFEE9768E2C43D47C",
INIT_5D => X"640A063BED61C6835783E82307B18A1928BAD9F4A77347AC42F0FD0461F63141",
INIT_5E => X"22919A1A5D91877AAD1D975219074E0AE05233534B32348F552B36A247A46D89",
INIT_5F => X"FB36FF75DC395BECD7F8413E8ECAF3B65FF2DBEEFB832BFDDAAEDA07D5C95E36",
INIT_60 => X"B1BB0FB6FA3DE39E39E78BEEBE3BA333361761F4DF47BC73BFC22B781E573DB0",
INIT_61 => X"F6EBDC84E92E88DDA5DACCEE873963F58CD87D87D1EF1CF1CF3C5F45F1DD1D99",
INIT_62 => X"0F8C38A95538F10176972BB3CE1CE5AFB7DAE46F497447CDAED2677639C31CA7",
INIT_63 => X"C03E3076AE1452CAC4192E0AAD4848CB3847C64AA9C28A595B0325889DBD0415",
INIT_64 => X"0F907F8B9835A3022D1241EBF7BCE44621FA0FF17306B46045A3C87D7EFF9C82",
INIT_65 => X"BD23505A03A4B0C96C828E41C51A35F3C7A4E40B40709699E0968F07BDF7AA33",
INIT_66 => X"A6CAEAB5A9F5891D3EB9FAD28DA91F81E91A92900D01C65B6416510628C1AD9A",
INIT_67 => X"1855375D34E76BC036FAF4E36A47A475265765AD5FEC68EDA5DF5E9C6D48F48E",
INIT_68 => X"8465D4853DDA08A3020176DDED2201D0E2ACBAA8A73B5C052344AA9B9524417A",
INIT_69 => X"BDCB81EBB27F311854BA6962D02FD4B2D7BBF43D766FE6238ED74D225F896A87",
INIT_6A => X"BA2DA0570454C1F81F01A3123867C5745744B408E88B983FA47B5F16897EA596",
INIT_6B => X"0518818300B080C02CAA66DC66C5E605D15D02B822A60FC0F80D9891C93E2BA2",
INIT_6C => X"6BA02D4232E5AF8E2098A599713B955020868C1005840201651314B32E2F30AA",
INIT_6D => X"A0AE10FC086BD3ABBB92C241C501A783D5156A1B850D7C75777AC1CA292434F0",
INIT_6E => X"7606404C1844662E16C16BF55F5975278ED87C7181888C45C2DA2C7EBBEBAEA4",
INIT_6F => X"DBAA53E653872B6FD6B8DA6EE3C283771B054AADCA70ED6DB60B5FA3FACFAA3C",
INIT_70 => X"14AD5E91255285601A8D2A9E25EA9621DD4A1F3A9F394B7EB63CEB631F1423B8",
INIT_71 => X"8630F2506C875DAAA16AA5897AB7A858A5269FDD2A942B00D42954B12F54B50A",
INIT_72 => X"8C1CD6CBC1F23C5628DF56EED42F973071839291643A659AC51E83BB1A04F2E7",
INIT_73 => X"533FAD3750AFB492AC9DAD827F0BE6CB816D27393E1D769B1597B4B007E97CD9",
INIT_74 => X"AE6AA313B913953452C32CAB8E9879DC95CE746277227AA464FD7C13F81F365C",
INIT_75 => X"0726E02E76E42FA0BB0B066B023CB4027357189D899CA9AAAADF0A5795C3CEE4",
INIT_76 => X"BE53725A097106E882C53E19AE2970C83987E88757237615D858B3C115C5AE19",
INIT_77 => X"D4F994826C65FC0BF2F3F47B8CC33CBFB29FB2D04988BF017430550B275C6515",
INIT_78 => X"523FB86B475334EB76B1D30421F285FBAF0F601F66E866DD6EE61861A53FD01F",
INIT_79 => X"84C54C37CFF9E910A09E457D53DD3D9BD098A996F8DF3D22B5AF98210F942FDD",
INIT_7A => X"FD8B5E35D6D9EFBFBF5FE53E27E377FB266A60BE7BCB6885051FBFBABEA9ECDE",
INIT_7B => X"4921399914B4515AF6FD7F98F8DFAFCFEB7D968076EB6DFDFAFF2DF31F1BFDF8",
INIT_7C => X"492EA4C42470D1CDC09DF673AC8FB0D24901D488A5AE8A517007F9D39791761A",
INIT_7D => X"1200887B3A8BAF6DEB9832C42CFE2DE2020A37FF575A77EDB1611458A59FC510",
INIT_7E => X"B118F00F44F854CC40E4BE07E0660C28C2C41E01E8BD1A9954C1866162B17F10",
INIT_7F => X"7FB00FCBF9F34C6F2A4C529C416056FFA307807A27C2E66A0691547A03716FCB",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AD8E50485005C1D0962C354271058F53FD180E0FCFDA3542710796EA0B22B5FA",
INIT_01 => X"63B40846215035056072E142414A084621508140C02A0680AC0E8440D029C610",
INIT_02 => X"CF2A60BF647D0B138534256278A68A167DE14C0EEC8F93D01500C4AD4F144153",
INIT_03 => X"BA1FD5457741ECDBCD6897937B71A5C918963AA88EE8359A40510B1385345123",
INIT_04 => X"2E56CC749B6DAEB3CF3C72512522407C250E086BBA1F20DE6944BC9BD98C086B",
INIT_05 => X"4EE95C5E2C85119CCF3CB1494C94190972B66324FA6CB1494C979689299283E1",
INIT_06 => X"EB3325E931E0845FF0450C15612725E931E064FD262C9CC3AA2CA982AC24C07A",
INIT_07 => X"0F95E1851D40E06D26525C0DA4CA544F23D2BC30A3A1885DE8B88B819499CA89",
INIT_08 => X"33D7CC7DA67A8762D600F003B1553F62F6BAF98EF48F50EC17A2E06D2652A279",
INIT_09 => X"AC8E4A850974B6FE0F816B0ED165B71802DA63E533D43B56B14F801D8AE863E5",
INIT_0A => X"29268D28BE92F543BC5E47AC7949C6CD6472D4204B8647AC7949D8778B2938C0",
INIT_0B => X"AF271A3CA4FC50D60C2CF0C670551A3CA4FC6347F4978A1A41818E10CC0A96D2",
INIT_0C => X"D41B88B1D29BD4BE63887A97CC715FE8FB8361253A536EB7A9780F5AFB8E2BFD",
INIT_0D => X"C2F8A987FCD359759FF03B0AFC6C5A0DAD5B9730FE926B2F2D6A54BE638A3B47",
INIT_0E => X"CF07A030472E65A557F75D68AA26302F1F674C1CC2FAC9ACFFC87CF9E3634C1C",
INIT_0F => X"BBD1625C49D377FFFF675A2308A819CA78BF8C2C3833DA2308A8FB4471318139",
INIT_10 => X"F7F755027125EDDFF50729A201529502712792E04E22BDFAB6A01E48A922656F",
INIT_11 => X"FEE07C7ECB31A8F8AEE9F71F95DFD9BDFFD3EB7AAA4620264E6A7EE3B2BBFB37",
INIT_12 => X"D796712F3BD2B97256435CF3C31AE3364E64CE25E572572E8F99C0F8AEEACDEC",
INIT_13 => X"A5A243243F54F00C39E6ACA1BD6804C997FBB979D795CB92B319F2BFFDD38979",
INIT_14 => X"9DAF3B75377AE58ACAA9FA6FDAB5201B2D3A3AD4F8A70A6FDAB7650DEB50260B",
INIT_15 => X"ACC191CDD6DD6B9A299ABEA8DFF4BDCDD6DDD7A9BBDB2C524574871AA02C1879",
INIT_16 => X"67A61D21942B45CE47F228BDC0FA54AF2CD6862856AE36514E55C117BC1F481D",
INIT_17 => X"2810525125404E5CE4EE6F8FF0C469DF01A88A4A248C2BCBEB722DCE47F0FD70",
INIT_18 => X"2F3A74BD61753A3ECE47B432ECCE5EF2EFFE7A09281232EF27813EAB65F8B209",
INIT_19 => X"EF530A2147F44E26E1283EB303B3BDE169D37CC356290EB303B2A197627677B8",
INIT_1A => X"FCDCA440A51B896B91167F78B22E8C40A51A518816A2713072E41C017546FDEF",
INIT_1B => X"E98BEFDB2334617F3376DC6EEE6EE0CD2D36D1CE7945771FFF945B8DDDC9D818",
INIT_1C => X"0CCDAA13899D85DB627335B37D48333B73C827437113B49FA8D3097F33772669",
INIT_1D => X"0A3077F9302E3C1F33CB0C682A5B14A4E7FBE89D0CCC6ED3139DCEB8833F509D",
INIT_1E => X"ADB7A416A8DD1D10E8784C02B0C16E5A1188324980BD1C02B0C063C15698A56B",
INIT_1F => X"EC03479A1263F474E3F1543D24B0079A126280B346CCFA87BD7E5243A2947D59",
INIT_20 => X"FACF3FA0A6CB20E3AE91641DA5F24F259F59E5C51294FDDCE5A868C3A49E49E6",
INIT_21 => X"3A0AE7EC6741761D38D3A3932C813ED7CCBBDCEC8EE82E43E6DBF0E3AE927924",
INIT_22 => X"4EC82B21BFE7FCE014CD5F32E58BCA7E56D16F633A0BB0E9CE9C689161972F63",
INIT_23 => X"7FC4B498AEF23D410E76F4F8EAD21FABF241F30DFF3AF4F8EAD0F99F3C5A43F4",
INIT_24 => X"2529C6133CAF501E2F62302BA225C6133CAFB0C37795EA0345E847057EF7FFF8",
INIT_25 => X"61F6BFA99FB896894091129128921880AC3E57F532B5F7ABA165E25025104350",
INIT_26 => X"66575AE4A8CA9F80F04B04BA5AD9CFCCA131EB58951953F04D7896894090C405",
INIT_27 => X"B0A712317EF6B7F7BF8CCA83990E3521AC7AD7AD6654EC0F825825D2D504D7AD",
INIT_28 => X"01C59DA777F44189F33BB1660B2CB8D485B89183DDA7B1660B2C741CC8619D1F",
INIT_29 => X"D04732DFB59C621E46A1D4CCC55B32DFB59EEC3BFEA28C46C8D03A99948E8B18",
INIT_2A => X"6BC66D775B74C9E6EF63993CDDEC4CCF4D78DDAEE963F3F033A27B2FDB9D899A",
INIT_2B => X"7C92A6B92F9A4BF5FFFD2ED9C588340EC1CC54DF25F3497F00DCC9E6EF627662",
INIT_2C => X"35175B3E96EEC055C87E18A08C3686287B1531D17C925FAFFEE9768E2C4331D1",
INIT_2D => X"640A063BED61C6835783E82307B18A1928BAD9F4A773E82307B0FD0461F63141",
INIT_2E => X"22919A1A5D91877AAD1D975219079A1A5D9033534B32348F552B36A247A45609",
INIT_2F => X"FB36FF75DC382B781E5641398ECAF3B65FF2DBEEFB832BFDDAAEDA07D5C95E36",
INIT_30 => X"D1EF0FB9FA3DE39E39E78BEEBE3BA333361761F4DF47BC73BFC22B781E573DB0",
INIT_31 => X"F6EBDC84E92E88DDA5DACCEE873963F58CD87D87D1EF1CF1CF3C5F45F1DC7D87",
INIT_32 => X"0F8C38A95538F10176972BB3CE1CE5AFB7DAE46F49752BB3CE1C676AB9C31CA7",
INIT_33 => X"C03E3076AE1452CAC4192E0AAD483076AE15C65AE9C28A595B0325889DBD0415",
INIT_34 => X"0F907F8B9835A3022D1241E8B7BCE44621FA0FF17306B46045A3C87D7EFF9C82",
INIT_35 => X"BD23505F83A4B0C96C828E41C51A35F3C7A4E40B40709699E0968F07BDF7AA33",
INIT_36 => X"A6CAEAB5A9F5891D3EB9FAD28DA91F81E91A92900D01C65B6416510628C1AD9A",
INIT_37 => X"1855375D34E76BC036FAF4E36A47A475265765AD5FEC68EDA5DF5E862D48F48E",
INIT_38 => X"8465D4853DDA08A3020176DDED2201D0E2ACBAA4273B5C052344AA9B9524417A",
INIT_39 => X"BDCB81EBB27F311854BA6963502FD4B2D7BBF43D766FE6238ED74D225F896A87",
INIT_3A => X"BA2DA0530454C1F81F01A3123867C5745744B408E88B983FA47B5F16897EA596",
INIT_3B => X"69A037A1AE7458891676354D4C9A8412D15D02B822A60FC0F80D9891C93E2BA2",
INIT_3C => X"4B902EB1915DA35510F0A14510A8AECE549D7FB6473E5F1E85C6D4B14FCF02A4",
INIT_3D => X"3DE8D6804198448CE5EC5689844DBF4620A9B209956BD3C84D16DC0E8B2AFAAB",
INIT_3E => X"235A66882DFB153E26354653684310266F83D1E04B13C2E51E7EAA18A992EFA0",
INIT_3F => X"767C032349C94A60735BBB802AE6075B0849EC0717C647E00E0E18B874B68FF1",
INIT_40 => X"E192FE038F79C953AC04272B2E7CFD55C04828C3A4EA49A1AC0957C5C8505525",
INIT_41 => X"642C027BD7FB32592089ABF347A30ACD088026DB28DC992E810FB1AB969E0A0C",
INIT_42 => X"4FA6961A3700D48A23AD465EA1ECF76C25A7B943C68ECA63C3AFFFCC5088898B",
INIT_43 => X"0A961CA8BCD053D636DDAC5375E380FD3074FFFAE68E0BE207FDF8A42DDB3ACA",
INIT_44 => X"3B4682F1AEB3D874D005DCFD2745178301CD7CFCF7911E7F2BB2EA3743BD21F9",
INIT_45 => X"54F2F553EBB3919AA2A6D460E87E0DE56E429A1B8E579333D343D2CFB0DF60D5",
INIT_46 => X"A9F5A3DF376CC0C9FFA77689D9B857FF5FCF5935AFF7B2B948DEEE93E8BCC19B",
INIT_47 => X"FFD7E7F5265FEFFEBFF3F3DCFBB78D95F62BFFD10DFF443429FF0BA99376A02B",
INIT_48 => X"EE73F5BFF9BBC8E9FF77DDF39BBFF8B0FEB1B47D99D823292280577F9D2DB906",
INIT_49 => X"9CE5F883C2FFB7349261303F95A0F687435D83FFB02092E8FFEA89B899BD1FFF",
INIT_4A => X"B2CB7AAF07E86618D70F3C1370A1516EFFFD9A858F87FFFFFF17AD181AD04072",
INIT_4B => X"8DC017BCC494B6A3BFFFF694329FFFFFFF8A41FE9C8BB77A3F27BFC3C9FFE9ED",
INIT_4C => X"7FFFC908F9EFFFFFFFFDFFF8AA472A3FAF59F3E1BE3FFEA5DBADA629991EA64B",
INIT_4D => X"FFDA3EEB5ED84D3F0F87D3F1CADBDE095445EBBDC04A998C4E183513353122EB",
INIT_4E => X"BFDBF011A1264B3C1874858FE974E21219547A0F448C2FDA5FFFF77EC7BFFFFF",
INIT_4F => X"56193CD6DD743180F1EFA949458D172B1FFF0EA33FE3FFF1525F7F904C8F4EAF",
INIT_50 => X"11F840B78976949221FFA4D1AD0DFFE6FDBB1D8012616FBA7DB4F343A53D77E1",
INIT_51 => X"AA7DB6C1E5FDFFFDE841AF35CC6D107E97BA9353BE8F0886F4AF4C5E7B4E8824",
INIT_52 => X"7E2F8C0D990B6057EF35355BCEEF64611846F7883F343E436D272BE5607B3437",
INIT_53 => X"FFE4D1318DEFD311D037B106ED2703B39FF2B5377BFFBA17FA1E78757AB73FA4",
INIT_54 => X"40354AD5E02BE576971F34135529D2178EDDC950B6D8BA05926DDFBEA4D0212F",
INIT_55 => X"A18250897612A857F3E507DA779BD7EE1C33EC94083A1031FEF5097999762B4D",
INIT_56 => X"249D2AF4DCED2CC39D62CBC04D47C756BB1DD87287FA660B890D552719C95B3E",
INIT_57 => X"27BD2EBA753C55B2EE2B39F3EEA0420A7FF490CA489ABDB99016ED8977061E6B",
INIT_58 => X"838D9BD3D63783339296660F45A22EADBFE72E209C5CB986956962DD475868C3",
INIT_59 => X"8B6623FD24119ED1CE49A78495BA691266CAD773517CE72C16C64A3C94DA3D32",
INIT_5A => X"EE8CE2D93E2CB1C651300DFD914CDD36EF9FCD0AB53F0C17097317FBCB865CCB",
INIT_5B => X"97E8F9C0D9CB09DC16B630FE49E916F9FDFC6AF247F1583B4C1721AFC9A5BD59",
INIT_5C => X"FA8ECF8B2B4E4277DCC1DDD1BC21CF84C39D05C5DC877E8960BB7EA73BD53D2A",
INIT_5D => X"7F4D76811DEE284B79F58AFB8FF67D0085535FD6A663CAB7422F09EFFFBEE14D",
INIT_5E => X"418A24327DC920823CFC6333BEAF1D648DCE461252381E35AF8E7F9C898940C9",
INIT_5F => X"FA953033B90E227281525337DCD164AA06F0D40A766FC071DC408449400822D6",
INIT_60 => X"8D3F9A7291E7B71114F719D0FC239B7EF61A6B9A7E9F4E3493610F205B6A4615",
INIT_61 => X"6D989BA22E317BC2A194D53B499FB32FADA21B48CB8FBF5F20D2AB91BF83297D",
INIT_62 => X"A8D1BFA35CE333F6D6FBED478D87B6E9C6968F1BC1B5B58B2545E91CF29E682A",
INIT_63 => X"E3F79C475B787656442301FFE1D26D9722FCE8F51419B17D2F2E7F5D92DA9793",
INIT_64 => X"7A33342B215C76214F67EC3FE4BAE50C47F9ED6C6E382F2F7624976921C0A301",
INIT_65 => X"1AC035BB59B43BC7602C3BF467DCC973E27B76A15DFE7906A17AADB6B9393B97",
INIT_66 => X"BB9217BAB0421EFCE7CEB95B79D3101DA177DB71685036626F973FFB17B8399C",
INIT_67 => X"A34993CB7BB3D7872F3EB9FD356E9D6F56A855B3E2573646CEBCCDC8653CE70C",
INIT_68 => X"E60AAFB1959CF3EB29A55BC9FDEB9A7503EAF2953C45247AF80ED5B2836D79A2",
INIT_69 => X"B7A31482EC24504127D658F190CC6168181640EACF5FB4C8D71A634B61773D27",
INIT_6A => X"299C40D0B51DC93A3A4DE1B0B767B17257A96F336ADDEE217A4FBF9BAF5E48FE",
INIT_6B => X"70B18716378FA23B14E1BFEB39C49447875F9E15E2BCE8C20F25A9F115CB5C25",
INIT_6C => X"B849CD010B015615700ED0153CFA00AFB54BC61A6E5FECF937AAD4D594A44F54",
INIT_6D => X"7133255F74F8269CAFFF61803698C12FD64C366EE7A0415603DDAFBA69D5C36E",
INIT_6E => X"892040BE6400B4A8F06701757996F12632D3F6931FF4F8A0ED853CBB16F1E54A",
INIT_6F => X"713F4EFBFFF7685F1E98762B7E6F44C656BF3AD914DCDD80B9ED4DBCAA9F018C",
INIT_70 => X"3A91F447A2DAD7B1C1D62ACB1E2CFA2D59F7E28F8DFC6775EECFDD1111B1FDF8",
INIT_71 => X"C75FF9836187B0F150C4081A4993D8F69A9D62E552DE499171B9BD3449B7CFB7",
INIT_72 => X"8A395DB4E0D74B38AE8C49ABD63329DE017BE2CD39F25E715FBAB868D44265AF",
INIT_73 => X"BA8452DBBCB2301B0AD5E5A84B46C8A78EAE9F15B6B49F9F3322DFEB7CDB46DD",
INIT_74 => X"4EF7E113A7EF7F60BD71E89DADE3F099EF9A91212B00853154C569264C4D5CD2",
INIT_75 => X"427B5BF05F3EA3F6E27CFA216B3B435CB094A7BAB388EB2A4E906FA46262DD40",
INIT_76 => X"0645BE197EBBFEEF3103EFDFFEA8E054A02B47D764B14B9FF7F59937762F89E5",
INIT_77 => X"C806AD80838100248417007FFDFE7F3FB0056ADA05D92F07AAB2BC9C97FDE486",
INIT_78 => X"FFFFFFFFFFFFFFFF75304544502088192008EF3662E84544502088632AD80E4C",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"924A4924924C9349249248D36D2449249249259B684925B6DB6DB6DB69A49A49",
INIT_7B => X"592593F977FF90524D24D27FFF34934975FF7FFFFEFFEFD2DB64934924924924",
INIT_7C => X"FFFFFEFFF7FFBFFBFFBFFBFFBFFBFFFF6DD7FDD2592590524D24B00A49A7FDD2",
INIT_7D => X"FFFFFFFFAFFAFFAFEFFF7FFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFF17FDFFFFF",
INIT_7E => X"FFFF5FFDFEDFEFFFFFFFFDFFFFFF5FFDFEDFEFF27FD7EFFFFFFFFFDFF7FFFFFF",
INIT_7F => X"F5DFBBBBFEBDD9DCDDCDDE332776DDDFF5DE59E9DFD6796F8770674FFCEECEE6",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"020060C3688461065068069A2141A01B09949AD10D101100FC1DD9DCDDCDDDDF",
INIT_01 => X"CDA0DA2D9F36836B3EB6C96CF6CF7A956422002002006106506A0C20CA020020",
INIT_02 => X"FFFFFFFFFFFFFFFFADF9EB52B5292E92CDA1259359B1EB52B5292F63367BAE92",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"BBDB7FB7F77EEFEEFECBED79B7FD6DBFBBDAFDFDFEFF6BF7FF76FFAFF6FF2F7F",
INIT_05 => X"965B5179D7D5D3F4DFF3ED75FD7BCFB5FBCBBEAFEABABB3CDCFEEFEEFECBEDBF",
INIT_06 => X"FFFBFFBFFEFFEFFEFEFFEFFFFFBEF9EFF3EF5767965B53F4DFF36A7E8BDF5767",
INIT_07 => X"FFFFFFFFFFFFFA00FBFFDF3DF3DF3FFFFFFBE7FFFFF7DF3DF3DF3DF1FDFF3FFF",
INIT_08 => X"C03FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"0000000000000000000000030000000000000000000000000000000000000BA0",
INIT_0A => X"67A7F4DBFDEDF6E727FFE7BB7CDFFD9DBFFFBC9BFFBDB6BF5340000000000000",
INIT_0B => X"B6FB6FF7FEDBEDBFBFDBFDBFFFFFFE1F9D0FB6FB67A7F6E727FCFEDDE4FFB6FB",
INIT_0C => X"00000000000002DBFEFFFFFFF7FF7FFFB6FBEFFFF6DFFFFFF7FF7DF1FFFFFFFF",
INIT_0D => X"0300000000000000000000000000000000000001000000000000000000000000",
INIT_0E => X"0080000000120060000000030100000000800C004002003002001002002008C0",
INIT_0F => X"0040040300180400200200400280080100100100100301BC0E02006000000000",
INIT_10 => X"6496924491949A010492482482492CAC1C006006004004002002008004006006",
INIT_11 => X"5A02185C80705A5C1D116006096DA6996497A4D92C916006096DA72312492699",
INIT_12 => X"4CC20B40891A01241A835A2483520B40891A03630BC201241A804902D00A4334",
INIT_13 => X"4B171E4A296F6EF4870CF0F34BDB725D4B15E3127F2CC5BDB75FE79FFF7B72A0",
INIT_14 => X"DD68D1191175D0870C76D9445036DB66BA6AB822822EB8EE255F6EF4870CF25D",
INIT_15 => X"0800800C002002002002006006006084A3CDD75EDD68D0870C750A10E1BDD75E",
INIT_16 => X"FFFFFFFFFFFFFFFF91C00C00C00800800801001001000C00C008030BB0030080",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"32C26465C27004234A2321689005A03232C10C35004706006C1211AC1200A10A",
INIT_19 => X"4208B1205644310B1C20101D907000D00D04406C08D8898200A004234A232032",
INIT_1A => X"0012030508804A0CA0CA08280A85A81A401300304208B10B1C23962063830030",
INIT_1B => X"E1883841483861023280A51951910211001020022400A51951910144142D0211",
INIT_1C => X"73079C20059C21071443842083879C20059C200A41C221071441050820718014",
INIT_1D => X"1AE300320251897995981244216211901AE13A09784A843C4EC4084B842C418C",
INIT_1E => X"F218508520425107346BD28810F52F4058859250A408D89FB131897995981190",
INIT_1F => X"8678A5951019621289AB9CA8DB8910C121611F03F2185107346A0A28F6A11F03",
INIT_20 => X"00318300118000314AA1241021087AE786790F54F0C1241021087906DC48FAE7",
INIT_21 => X"0C00400600400660E40E008C1C8040060040068084008660E40E406003901081",
INIT_22 => X"1091102100110691218A92B4212C01481051CB22D802017D56C86C5218251488",
INIT_23 => X"2C35B5E403DCB5DB52C3A934934E0763E6D4A857B87B86C8A2190691218A9145",
INIT_24 => X"AA3A5E7C71A3E984379DB90756F5EF94B51916C92C35B5DF52831EAF6A7116C9",
INIT_25 => X"AE30B38FB2FDBFF978C3BDF21F35726BEA672ED7FD13BDF21F35713FFFAFF66F",
INIT_26 => X"FFA840FD4641FC8EE46FADCBF86FD0EC9FB7CBDFEFE99F9ADC3F33991F4DF7BD",
INIT_27 => X"31442ACA812F00EDA3188FE95CAD64A1D995944F57A5F134BFB501CA5A94EC94",
INIT_28 => X"CC6D74CB60E44B0E6254B7A570379F2CDD2F0231C9AC897018C6534EEDE707A6",
INIT_29 => X"C5E0B70F1A8928C98604D277A3BFA95BE3549C5B080AD865C3503B3BC1B8D98F",
INIT_2A => X"82B05C80DEBFDC017AF018C19824D6A41FA27129D40D46958E7C65981DDDCADF",
INIT_2B => X"1B76403B2A4C447802B6F364323285EEF369B5836DFEC00D84CE43780406D8F7",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[0]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "COMMON";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"6F9678019219B199959849A41E69E69F2DF2CF24B263373336A16E9593CD3CD3",
INIT_01 => X"0C7445464D61D61F71F7175871A70E18D2BD3AD1CBAC3AC3B279A79B724F34F1",
INIT_02 => X"B017511619AD89D48C24F06793182140697587586B0EB0FB8FBBED838C38F2C7",
INIT_03 => X"E55C511E18691492D04200280E08500500BBBC87CD6C4EA5DA7DC39C98C10A01",
INIT_04 => X"030D27825A6524F1499057C4748F48248268FE1EC34CA49E293283A83E914904",
INIT_05 => X"94981C006F6C5CC48C494CB4CB4CA56A52913913D9BD8B9889008048196B94AD",
INIT_06 => X"4704705601E01F08F8CF8CFACFACF2CE7FA7B81AC03C03E163297A94BA652B52",
INIT_07 => X"0B4CB4CA590411810C34C35474C54A162807827C2F00F84FC662FEC08067D670",
INIT_08 => X"89BE05E052572F739E98A942D1D395285A16FE00F7648808D08D9AEBA63A70A0",
INIT_09 => X"6A5AE5ED754BDCADAE37F901FF8B40F48BDDBFBAD2B97B94B5CF4F7EF6E9E81F",
INIT_0A => X"105E7F83199184DB5DB053043A62A623623239009309B09B70C5895AC74C54C4",
INIT_0B => X"658658668268B6DB2D905806806C26CB5C599699504D16DBE8E9889893153113",
INIT_0C => X"4A74A700500104232B02B02212AD6AD62A0DA2DB7345B6D96C86BE8019E93652",
INIT_0D => X"DA79259410EC8E419255AD5AC94AB5AAD5F8CF82D0FC201A11B59958952956B7",
INIT_0E => X"931D91C83E63B2790699CFC2F0957F15D5D94B94A74C720F20E2CA75ABDE2BE2",
INIT_0F => X"B1F8BEC7FFD21D39BB8BAE696296376B76A16E95EC1AC327789388F68442C6ED",
INIT_10 => X"BA6BB6B96B96B92B92BD3AD1AD9AD9253FF3FF1CF572D725D588DADDB4B11B5B",
INIT_11 => X"0C24F06707707535C044004419C20C00C5AE4AE4BCB5C95C9460FEE06F6ECD24",
INIT_12 => X"7E83E867BBB91959D4384081108708106078FFFCBAF3A8B21B29B0CB0E106102",
INIT_13 => X"5273A3292E4E54652758FE7F77FE6EA4CADCEF9C9DC9CA8CA55C511E19F5C9D4",
INIT_14 => X"481FFFE68606682E9BE9BE16C16D80D8090080480C90CD042536530ED825B013",
INIT_15 => X"717F97997B97B3FB7FA7B81A81AE3EE2E416417C4F76F6FF4B4436024B6C86C0",
INIT_16 => X"4C34C354376C72C6182D02D05C14405485EEDEDFECBDDFDBFD9BEFED9FC1F71F",
INIT_17 => X"8E746144716D14170882885B8510510A718EFFFBFF93B6304304300A00A20A21",
INIT_18 => X"BA2D2282FF45A5545DCF7FF806198988D48F58EF8B68A0BB89BE05E042153132",
INIT_19 => X"8639DADDA8DE51C4196EB6EB6BB43B0430C5895AB4ABCA3B494C846010760761",
INIT_1A => X"B269269B699619C59C59969968D6CD674EACEED68133C338CD0EC02C35A1D821",
INIT_1B => X"AB02B0221221A89910490610513093598DA670670CB0CE2CE2CC510B4CB66B26",
INIT_1C => X"1A1DF1762CAF4BF44026122AAC24C2455055A038910D40D44844814811849A48",
INIT_1D => X"8297E97E8AD2FD3ED3CD3CB2EA3A213393118954B55A5FA7DA7925945C434427",
INIT_1E => X"C49C4FB47BC75E15B15B1312B1271201389388F68FF8EB417D39C6846A24E240",
INIT_1F => X"3F932871EE5EE7FB7FF3FF1CF4CBE2BDA96E36A32DCBD4FF99C4984809389309",
INIT_20 => X"00440044880880C27FFB6F3480008800F7B97E9FF0F72FDBFD9FF8E7A65F25F9",
INIT_21 => X"EA4EE00E1A72267D110011000020002002200220404406006022020440044004",
INIT_22 => X"944E4CCFBC89C999F41F433D32D3E93F917995F913913B233E83E867A6DA7D24",
INIT_23 => X"2DB298618F2CD2E4CA4C8698CB80AA0E6536530E39E59A544E3E61E709701541",
INIT_24 => X"25521510592596596416417C53E5BE4B0978D78D8324B2C9522E02A93C455073",
INIT_25 => X"982D02D0090190F910A122123147D33421659659282CB2CB24B20BE09E2DF257",
INIT_26 => X"940F40F444A44A1CFFA4FA6611F49D4CC1681680480C84C87C86DE27EA3E93A9",
INIT_27 => X"889409438912813873870A20AA1AF3265345B41A252250A70E74614415C75EE5",
INIT_28 => X"4A642703B8D08D08C88EB0E31F217894894C8460611A11A00C04C05532E52F12",
INIT_29 => X"31B31B53BDBF4FF2CEACEED6E96E96E184A5CA586F97E9FE585EA522590BC4A4",
INIT_2A => X"904906106482480483E42E02901A09209EF2FC3BE9FE5F967D6756374B74B70B",
INIT_2B => X"BC4346345B38B184040341240680482482483083243240240660E60FA0D00904",
INIT_2C => X"536712308E6CE24690EF8BB8BA0EE08F48D4C95C99CD8C20DA1DF1761541DC13",
INIT_2D => X"E9CE3C22022020151D15D15415E91E91BD39C684404406010390F1040EBD237E",
INIT_2E => X"15117117157D4ED4E96E36A36A26AA2B3F12B122768DA9DAF057A46FCA08F48D",
INIT_2F => X"FFFB6F34F64B65AC74EC1E818FDB7DFFBE51B53A4BEA36A74B71B51B51355155",
INIT_30 => X"76EB6EB7A49DC954A6FB6FBFFEDF6FF7FF5B79B7B25B2D79B69B69F5BEDBEDFE",
INIT_31 => X"5B12B92A8772552552772370070E56A06A74E30E84EE4AA4AA4EE00E18E1CAD7",
INIT_32 => X"51D30F38B281E79DF9F91BD19F99F9A38E3E61E716503C204A04A00EBBF32F34",
INIT_33 => X"1FBC47D45F416C92C978D78D7A95BB1B50F73FF2CBE82592967E64E69CCFCC9C",
INIT_34 => X"50A1221271270A189D19519519699681617691791A0B209649C6BC6BD6ADD720",
INIT_35 => X"0890A9C3FD1E5320620660665E65A65285091093893868600FD0CCACCBCCB40A",
INIT_36 => X"642A42BF47B4695C015A07A1DA1DADF00EF54817E8F68923940F40F43B43B419",
INIT_37 => X"712602A82B93A7C8137FB0B30B20A2E24C04C055057B77F65F61F6164164945C",
INIT_38 => X"137FF25E4464864A44A5CA5805E876B66BE6BE4AC88C90C9D97D859859051712",
INIT_39 => X"43E42E02C108118FD9341241459C48C6F9AF92FA23243252252652C02F002EF2",
INIT_3A => X"04D45D45B05B09B84D049049471631321F21F0160861F13C3A18920B2CE2C636",
INIT_3B => X"3413517D16C36E25E21A31A33206F03C0E94EA2F82D86DC43C43463466406000",
INIT_3C => X"14878868C20EE1FB47F9C95CF0C684294390F10418419F6F7B12B9239C18D085",
INIT_3D => X"9511319339B79B79BF12B1225627DC40166BA6326736F36EC4AE4AE78634614A",
INIT_3E => X"F4EC1E81E83491C01DF1010D14FDCFD8BAE98C98C99CDBCDF8DD8918B13FD9D9",
INIT_3F => X"1DCB7DBFB7FB7DFF0C40C3443E53F637A760F40F40E4B7D9FF70186887EE7EC6",
INIT_40 => X"B6DB6DFDFEDF6DF7F75B75B736D32FBF8BFB6DFFBFDBEDFEB6EB6EB7A6DA77E0",
INIT_41 => X"50650050056465D91B7CA00AC08E08A0CA04A00E000FDF98267014011811C114",
INIT_42 => X"D8A4D5051051010910F73FF2FB0E35CC027A9A60A20220211100105204604504",
INIT_43 => X"097887887C8FC7F8505C07CB1BF13D12EBB098288288084886B9FF9FD97DBB94",
INIT_44 => X"1E5B519599711735331100C67C6F44F44BC4BC43E40E417F03E00058DF89E896",
INIT_45 => X"C38000065465C450D5095893813801A498C0B82CCB8CB9AA1AB12B127027C0FC",
INIT_46 => X"95690EB0EA0CA040447FE0388D32992A92AD61D6194D87DE8FFA8C886DA65125",
INIT_47 => X"4C018002257C578C79C7BD5BDDA9C7FF9EDA8FCA7CAF88F1C3801BEA29B69954",
INIT_48 => X"F057007A27A34727EB71AFD35B552540DF801DC729F2BC63CE3DEADEED6EC4FE",
INIT_49 => X"DFB23262C70C50C43F403FF6C56D501F82F823D13D13517416EFC03DFAADAA07",
INIT_4A => X"3F743FF98B1C31121B21C01488588D81DD1F203FE962862643A438029119CF33",
INIT_4B => X"07287386386A84A15F3F306EF031011010E50E70C70C7FFBDBF6966162022023",
INIT_4C => X"4CEBD806F8B15B15899D8B58B58B8DFB601C86C968B62B42F798267881880880",
INIT_4D => X"38E38A76AF6ED6EF29CA0360D6D4DC4119F0766F25AAD8AC4CECDAC5AC5AC4AC",
INIT_4E => X"1671D15D1456C7ED3FF07E7393335371871C53B57B7756154F8FF0A432E6E24E",
INIT_4F => X"01F80ECF3491DB1FB56B5487407619399F81F83D6E923F6AD6AD6E90EC0E4203",
INIT_50 => X"6F9679259219B199960FBD1FF669E69F2DF2CF24B263373330B3093493CD3CD3",
INIT_51 => X"1F8FFF3E7561D61F71F7175871A70E18E08E88B8CBAC3AC31F9D8FFF724F34F1",
INIT_52 => X"B017511619AD89D4BBCF3873931821401FFFCDFF6B0EB0FB8FB8FACB8C38F2C7",
INIT_53 => X"D0CD1FC398691492DE4FABD2CE08500500BA8AB0CD6C4EA5C0EE4FD3FCC10A01",
INIT_54 => X"3E4777FA1A6524F149941D41F48F4824879E66FFCB4CA49E293283A83E914904",
INIT_55 => X"9489C89ECDEC5CC48FBFF7B3EB4CA56A52913913D9BD8B9891892996996B94AD",
INIT_56 => X"441BF64001E01F08F8CF8CFACFACF2CE08E08E0AC03C03E11FFF8F7E5A652B52",
INIT_57 => X"0B4CB4CA590411811A11B75D74C54A1651F681F82F00F84FC67C67D67D67D670",
INIT_58 => X"917FB7F752572F73FEF639F571D395285A65A652E0248808D17DFDE8663A70A0",
INIT_59 => X"529BFFD6D54BDCADAE5A7BF7B76B40F48BD9A9BAD2B97B94B5CF4F7EF6E9E81F",
INIT_5A => X"1191C804884984DB5DB0FB043A62A623623239009309B09B69B60A60C74C54C4",
INIT_5B => X"658658668268B6DB2D905806806C26CB0CB0CB04D04D16DBED749821D3153113",
INIT_5C => X"4A74A700500104234236B12B12AD6AD62822C32C1345B6D96D82C03403613652",
INIT_5D => X"B2BB296390EC8E418DA8CAC4A94AB5AAD3A538028008201A11B59958952956B7",
INIT_5E => X"8ECA5CA53E63B279071673AD7AD57F15D5D94B94A74C720F20E2CA75ABDE2BE2",
INIT_5F => X"B5AB54AF60F61D39BB8BAE696296376B76A16E95EC1AC3273770F5CD2C42C6ED",
INIT_60 => X"BA6BB6B96B96B92B92BD3AD1AD9AD924976D76D72D72D725DC5D53C734B11B5B",
INIT_61 => X"0C24F067077075365365B61921C20C00D25DB5DB5CB5C95C95E9D69D6CD6CD24",
INIT_62 => X"B9DF1DF393B91959D94D965870870810612783783B83A8B21B29B0CB0E106102",
INIT_63 => X"56E77CE7CE4E546526E28AB08F0E6EA4CADCEF9C9DC9CA8CA55C511E19F5C9D4",
INIT_64 => X"480402406486682E9BE9BE16C16D80D8090080480C90CD05D37C3782D825B013",
INIT_65 => X"717F97997B97B3FB7FA7B81A81AE3EE37E2F72F32F76F6FF574DF0FE0B6C86C0",
INIT_66 => X"4C34C354376C72C688609601401440548BFCBCCBCCBDDFDBFD3FC3DC0D61F71F",
INIT_67 => X"1E91CB15D16D1417182180500510510A71A61AA1AB23B6304304300A00A20A21",
INIT_68 => X"A47AC77C5F45A5545DD40F0250A98988D48F58EF8B68A0BB89BE05E042153131",
INIT_69 => X"86386AD5A55E51C4196EB6EB6BB43B0430C5895AB4ABCA38076DD6D568760761",
INIT_6A => X"B269269B699619C59C59969968D6CD64D64D24D36D33C338CA5DB75B55A1D821",
INIT_6B => X"AB02B0221221A89A8900902301309359935934DB4CB0CE2CE2CC34CB4CB66B26",
INIT_6C => X"6362B12A94AF4BF44A240A408C24C24550558118910D40D44844814811849A48",
INIT_6D => X"988D0A85AAD2FD3ED3CD04B2EA3A213393118954B55A5FA7DA7925945C434426",
INIT_6E => X"C4FFFB347BC75E15B15B1312B1271201389388F68FF8EB42B62B63624624E240",
INIT_6F => X"3F932871EE5EE7FB7FF3FF1CF4CBE2BF27D265DE3DCBD4FF8AD8989D89389309",
INIT_70 => X"00440044880880C00C04404088008800FC99438770F72FDBFC3201D7A65F25F9",
INIT_71 => X"F22FB2BF2272267D0130102200200020028600FF404406006022020440044004",
INIT_72 => X"8BCCAFC8FC89C999F6DF00EF32D3E93F917995F913913B233E83E867A6DA7D26",
INIT_73 => X"327E8137CF2CD2E4CA4C8698CB80AA0E6536530E39E59A54994D91D311701541",
INIT_74 => X"25521510592596596416417C53E5BE4AE4AA62A20B24B2C9526434C65C455073",
INIT_75 => X"982D02D0090190F90F90CBD4FD47D3342A92A882882CB2CB2ACF2017BE2DF257",
INIT_76 => X"8A68368344A44A1CE436512F51F49D4CBF13C283C80C84C87C86DE27EA3E93A9",
INIT_77 => X"9A29A0D1091281380F03E0FB6A1AF3265345B41A252250A70E74614415C75EE6",
INIT_78 => X"4E1F347FB8D08D08C88EB0E31F217894894C8460611A11A11921D61C42E52F12",
INIT_79 => X"31B31B53BDBF4FF2CEACEED6E96E96E16636637A7797E9FE44748718F90BC4A4",
INIT_7A => X"904906106482480480CC1C41B01A09208D98DB9DE9FE5F967D9D9D512B74B70B",
INIT_7B => X"E91A99239338B1841203307D06804824837D9FF7A43240240660E60FA0D00904",
INIT_7C => X"47A64A64CE6CE24696FBF5BF3A0EE08F48D4C95C99CD8C20DA1DF1761541DC11",
INIT_7D => X"EA7DB7B3822020151D15D15415E91E91BD39C68440440602ABA2A82A82BD237E",
INIT_7E => X"99A97117157D4ED4E96E36A36A26AA2AA2E22E22E28DA9DAE8AE8AA0AA08F48D",
INIT_7F => X"FFFB6F34F64B65AFB6D36D7FB7DB7DFFAA8B88B8ABEA36A74A79651051342FC2",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"A94E1C01D89DC954B4DB4DBDFEDF6FF7FF4FC9B7B25B4DBDFEDF69F5BEDBEDFE",
INIT_01 => X"53A71874077255255275C370070F18740770E30E84EE4AA4AA4EE00E18E1CAD4",
INIT_02 => X"51D30F38B280FE8CFCCF1BD19F99F9A38E3E61E716503C23E23FA37B33F32F34",
INIT_03 => X"FA0A47D45F416C92C978D78D7A95BB1BB1BF88FA8BE825928F88FE8CFCCFCC9C",
INIT_04 => X"50A1221271270A1881881995996996816FE2BEA2FA0B209649C6BC6BD6ACBEA2",
INIT_05 => X"0890A9C3FD1E5320620660665E65A65285091093893860665E64CCACCBCCB40A",
INIT_06 => X"642A42BF47B4695C015A07A1DA1C42BF47B74817E8F68923940F40F43B43B419",
INIT_07 => X"712602A82B9385985905B0B30B20A2E24C04C055057B77F65F61F6164164945C",
INIT_08 => X"2325F25E4464864A44A5CA5805E876B66BE6BE4AC88C90C9657D859859051712",
INIT_09 => X"43E42E02C108119159341241459C48C601AF92FA23243252252652C02F0392FA",
INIT_0A => X"04D45D45B05B09B85F849049471631321F21F016086090494714920B2CE2C636",
INIT_0B => X"8693517D16C36E25E21A31A33203517D16C2EA2F82D86DC43C4346346640600D",
INIT_0C => X"14878848C20C4AE78635C95CF0C684294390F104184184910B12B9239C18D085",
INIT_0D => X"C99D319339B79B79BF12B1225627EAFEAA6BA6326736F36E04594AE78634614A",
INIT_0E => X"F4EC1E81E834830B3031010D14FDCFD800008C98C99CDBCDF8DD5F88B13F8C98",
INIT_0F => X"B6DB7DBFB7FB7DFFE00803443E53F637A763B21B40E4C3443E52186887EE7EC6",
INIT_10 => X"00F7ADFDFEDF6DF7F758180006D36DFDFEDF6DFFBFDBEDFEB6EB6EB7A6DA6DAF",
INIT_11 => X"507E7C03396510520460A00AC08E08A0CA04A00E000C80C4484414011811C114",
INIT_12 => X"8288D3051051010910F73FF2FB0F20AA6B269A60A20220218199F85204604504",
INIT_13 => X"097887887C81C805807C07CB1BF13D128399C0288288084886ADF207FC7C9828",
INIT_14 => X"9319519599711735A089F0C67C6F44F44BCBFA04DC8FF0C67C6E3E58DF89E896",
INIT_15 => X"87C07D665465C450D5FA3C81DE38656654668CACCB8CB9AA1AB12B1270260949",
INIT_16 => X"947C4F09868C223A29B444434D32992A92AD61D61945BC02F4888C886DA65125",
INIT_17 => X"29F07E53E57C578C79C7BD5BDDAE380201FC8FCA7CAF88F1C072563A29B69954",
INIT_18 => X"F057007A27943800EE7DAFD35B552540E77FD61F29F2BC63CE703C99FF6FF21F",
INIT_19 => X"EEA63262C70C50C4E0FEF2DEC56D501F82F87CC9FE93F6DEC56F7E9ADAADAA07",
INIT_1A => X"FDBAF8A18B1C31121B5E7EF5BF5898A18B1F93143162862643A43802915EFC01",
INIT_1B => X"071BEFFEFE6B1A588188B30B1031011010E50E70C733F303FF86966162022023",
INIT_1C => X"25A8364344B15B15899D8B58B5E3330373AC86C968B62B426FFFFA5881880880",
INIT_1D => X"38E38A76AF0F3C4173EA0360D6D4DC41EE860A1B25AAD8AC4CEFAE607C5BB21B",
INIT_1E => X"A3D1D15D1456C7EDEF9FE83D933353718717FE6A7D76D83D93301B06B2E6E24E",
INIT_1F => X"B80E87453491DB1FB56A2F274477574534932AE8A2923F6AD6AD6E90EFF0EF07",
INIT_20 => X"6F9640A592184D24724E49A41E69E69F2DF2CF24B7F0EF82E3D3093493CD3CD3",
INIT_21 => X"6B0C45464D61D61F71F7175877603CC6FFEE88B8CBAC3AC3B529CD24724F34F1",
INIT_22 => X"B01751161860FCE3BFDF387393182140E3853A326B0EB0FB8FB8FACB8C383A32",
INIT_23 => X"B7DD1FC398691492C2EF3CE5CE08500500BA8AB0CD6D3CE5CE09C39C98C10A01",
INIT_24 => X"3343B0FE1A6524F149941D41F48FB0FE1A66FE1EC34CA49E293283A83C70FFFB",
INIT_25 => X"9489C89ECDEC65A65A674CB4CB4CA56A52913913D915FE27FB892996996B94AD",
INIT_26 => X"2F00705601E01F08F8CF8CFACF97EFC37EA08E0AC03C03E1624A65A65A652B52",
INIT_27 => X"0B4CB4CA5979EFFE72D1B75D74C54A16382382382F00F84FC67C67D67D678238",
INIT_28 => X"1E3FB7F752572F73846CC6DD71D395285A65A652E024C6DD71D39AEBA63A70A0",
INIT_29 => X"7EEDFED6D54BDCADAE5A7BF7B76BFED6D54BBFBAD2B97B94B5CF4F7EF6CB5F38",
INIT_2A => X"1191C80488489821D31453043A62A62362323900931C9F836CB60A60C74C54C4",
INIT_2B => X"134658668268B6DB2D905806806C8F8B0CB0CB04D04D16DBED829821D3153113",
INIT_2C => X"4A74A7005001FF834236B12B12AD6AD62C32C32C1345B6D96D82C0340360C32C",
INIT_2D => X"B2BB296390EC8E418DA8CAC4A94AB5AAD3A538028008CAC4A9499958952956B7",
INIT_2E => X"8ECA5CA53E63B279071673AD7AD45CA53E614B94A74C720F20E2CA75ABDE39E2",
INIT_2F => X"B5AB54AF60F753C734B3AE6F6296376B76A16E95EC1AC3273770F5CD2C42C6ED",
INIT_30 => X"5CB7B6B86B96B92B92BD3AD1AD9AD924976D76D72D72D725DC5D53C734B11B5B",
INIT_31 => X"0C24F067077075365365B61921C20C00D25DB5DB5CB5C95C95E9D69D6CD7B5DB",
INIT_32 => X"B9DF1DF393B91959D94D965870870810612783783B8396587087B0D70E106102",
INIT_33 => X"56E77CE7CE4E546526E28AB08F0F7CE7CE4CEF8E9DC9CA8CA55C511E19F5C9D4",
INIT_34 => X"480402406486682E9BE9BE18816D80D8090080480C90CD05D37C3782D825B013",
INIT_35 => X"717F978FBB97B3FB7FA7B81A81AE3EE37E2F72F32F76F6FF574DF0FE0B6C86C0",
INIT_36 => X"4C34C354376C72C688609601401440548BFCBCCBCCBDDFDBFD3FC3DC0D61F71F",
INIT_37 => X"1E91CB15D16D1417182180500510510A71A61AA1AB23B6304304300C80A20A21",
INIT_38 => X"A47AC77C5F45A5545DD40F0250A98988D48F58E10B68A0BB89BE05E042153131",
INIT_39 => X"86386AD5A55E51C4196EB6E36BB43B0430C5895AB4ABCA38076DD6D568760761",
INIT_3A => X"B269269B699619C59C59969968D6CD64D64D24D36D33C338CA5DB75B55A1D821",
INIT_3B => X"45774976D1A2466473AC793E1A614240935934DB4CB0CE2CE2CC34CB4CB66B26",
INIT_3C => X"9C305039AD0DE3022E18E81B8253D0030266052F8A03407DFC0CD941583063BB",
INIT_3D => X"7B8A6A06339C7406E9FF0604A55E7085754AE5F975FEAF070A9CED9CCAD93930",
INIT_3E => X"15A90AB063204758B0EA79A112386C8B937F115F916A360A0D25817EC040B208",
INIT_3F => X"E2EC9EBB0059447886D0EF0C2D4184C0EDFDB60700DD54B875517DCE584F2048",
INIT_40 => X"9349FE3C604620C25648B2EF007992616B8918DF286130D5870FD4A38A7627F5",
INIT_41 => X"DF173FFBC0FB91B33E12400B1870ECAC2E885932439BB77B0A84A03B500926E6",
INIT_42 => X"219FBC82C6513A24F9F6790499E9E7B9E86B55CB2BD67FE32FA9FF9B3398C579",
INIT_43 => X"FD41B31D91E1F980030AD86B6A19641AC7CFFFFD8DC656C850008FE40193D980",
INIT_44 => X"2E06D80902CCAFB023FFFFFED2D68302491E4ED8C090C0558B80A19E3522BFA6",
INIT_45 => X"F617FEFE3B0887005B19D900E0FEC9C0A74EB96B67E309EF9A51C45EF1EFDF23",
INIT_46 => X"D7FFA60F777FFC61FFEC02223FF3FFFCFE5CF60066FFEDE46D15B47177FF4FEE",
INIT_47 => X"FFBE677ED6FFFFFF3DF36DF79AF7B3FFFEDFFFF157FFABF968C1F45E7DCB4CB0",
INIT_48 => X"FEDAFFFFF76C7F3FEB4DFFF37FFF6F5AB35E6B867E02985EFFDDAF1F9CCEC8A4",
INIT_49 => X"7FBFFFF33FFFCCCB6DDF4E407A08BC54C956A77F113796A3FFFFD6089EFCFFFF",
INIT_4A => X"4F96CD717C6D5923DAC369FF767B660AFFFF16AFA4BFFFFFFFFFB4FFE5EDFFF9",
INIT_4B => X"F65BA87FF2CF7859FFFEE9AE9E3FFFFFFFFA5FFF752DDDFDBFF7F7F373FFE737",
INIT_4C => X"BFFFDFF37FFFFFFFFFFFFFFF7F69F5FFEFFFFFF15DFFE105E29DBA168499791D",
INIT_4D => X"FFFFFFFEF3FFBFFF1FFFFFF13DA7EDF6EAEFCCC001D27C9B10C82055B3AEFF80",
INIT_4E => X"FFEFFFF17EDFBCC1E51D8DD002A12A098D800A61E2B544C3FFFFB1BD7FDFFFFF",
INIT_4F => X"2CF6D3A6019F4C2F16F9DFB29362FF00FFFFFFDBFF9FFFFFFFFFFFFFBF79B7FF",
INIT_50 => X"5F5667EDDFD37F1CFFFFDE1EFFFFFFF712FEEFDBFDACF1FFBF61FDF35A53FF69",
INIT_51 => X"79FFAFD70D7FFFFFAD34FF639569F7FF7F6FFB1327AEFA9E19994F9113CE41FD",
INIT_52 => X"13F952FE8AEF96BDFFFAD7CB76F3FDBBE26A7BFA530FD92E9682313B3EBBC068",
INIT_53 => X"FFFB9EC17AC8F40E2D5B401B12A9484750AA13B78438D79E01A9DFDFEFCBEFFB",
INIT_54 => X"A9F33F08AA1E08AA9B90685CCC4AC700212A6FFF5D7F55FB6FB223740190FFDF",
INIT_55 => X"BFFE6DF793EA3B2C9CE3F37AAFAF7F146FB6374E9FA777CFFFFEF7E956738532",
INIT_56 => X"F5BCB9AF3DD5BBBDF517EDD9F8557767FEAF0CA17BDEFFEF9B6BC9665CC66364",
INIT_57 => X"D8B1777DEA836FFDFF57DD337DB7BF26763BFC6AF14B927C92D9B664FD5ACDD8",
INIT_58 => X"7EEA2F232F427F18EDBB9EACD461380120ADFE7B51846056A3DB5DC4B683E737",
INIT_59 => X"3C5DC9709B4ACB4FC7FACE6BBA47202D402D359CC3C011D7FDA997F05C3C295D",
INIT_5A => X"E2FF4FE6AFDD6F9DF9A373773FD31DFD61A9FFBCB1E6B2EF6FDA0ACB7DBDA9A5",
INIT_5B => X"E24D1DDBA77AB3DFC6F2EAFFD7806BB9FFBF4C436E783373A60BED74D7BB250B",
INIT_5C => X"FB565F235FA6775652D66B014902121E42BA3830A0C93DF11FD9805CC75A5081",
INIT_5D => X"005144890FE3EF4E013FFE5920412928D717169B25A9EC4B214AF63D5B6DB9DF",
INIT_5E => X"B6C0228C9EC608A3FE0694C460D36C811231BBFDAF2D94E0D6FEF81FFDD6B6BD",
INIT_5F => X"DCCD792CD7C5D87C92AE65F6495A09E5A39687FF2DC08FAF7BCFF9F12FF35DAB",
INIT_60 => X"03906BB8B9EB3DFC73B8613803FC3011CCCBCE036D40A5C9EDB6763B504FFD9D",
INIT_61 => X"9383767F95CB06058D582A531F428C285219E6BBA75269A2D65B30BE8F31EB40",
INIT_62 => X"A4E412B31073EE31121054BFF03CB347B6865580253F9702506B3FBF8EF3EF7B",
INIT_63 => X"6D289251E66D497BB2D8CE00168D6700559D0012D810900FD44CAC07DC63482F",
INIT_64 => X"32DC57386C980C3204FB0F046B24A292D036849981CFDDC093D299C17205D8F2",
INIT_65 => X"84F14F7E91159FAE16FD423F206082E8A32A1C213034B0BA480D934B220739F4",
INIT_66 => X"3F49F4582F9D11971C14B0816FB5B6B21826BB1B62CB48C6BD78820008434420",
INIT_67 => X"411F60835F63DBF1AFBDF47DD4393C5B5F2D96FF4327F31C928533639A77C8C0",
INIT_68 => X"880144A68A2F8514F276067E800056D8CFA6C7DE5EF8D0BDA65DF00814936B74",
INIT_69 => X"265B90989A186F00987FA40000C04017A4E8DE371924B14129F18A931FC64A22",
INIT_6A => X"B54C013BDBEEF7E91930036A55E400C00836D8330F6410228224F600616DA167",
INIT_6B => X"486DF01849C29DC4691C86130EBDC95A09A0E99C3C0277A5E3E2F1440030BFC2",
INIT_6C => X"B0C7ACB1419ABCC3D8C879AB8EEB4D68F97F48018F6681806030E06E6F5BC494",
INIT_6D => X"086078182C84900C98049800904A2C40035BF0719A6AE7D3395A6D6F128F8154",
INIT_6E => X"A1A12BA230B14D43A878FA80564AEEC9C85C962801130313183259C163259228",
INIT_6F => X"CF50F0204080AB003360001C0238403C0D8D8C014C04154069A0C0402926ECC3",
INIT_70 => X"C16853B85305BA42C10A54D3404401C92C0404000081908A2A156170CB201104",
INIT_71 => X"735A158365DCB753EB4E5D8B46829F747D3D148721EAD7581C6E8142251DB0D5",
INIT_72 => X"04249460090E30C7417DC21CC4BDD8A03E1DDBC8904E1AE1D1D1F028644A86A4",
INIT_73 => X"3A21D240892218E6A78941902DF1A710C81A6060A5691252A581903309460282",
INIT_74 => X"FD0C3A4A6CB18A72C3A308060728B34262603801691AA502480291A72216C208",
INIT_75 => X"9888B64BE054804B4D2884D153A68FE043353A684D2C174307041F8068094A5C",
INIT_76 => X"32EFC321272F999AB14A6699ECB8D3C6ABC7936C2C821FC508B2724628F4B21E",
INIT_77 => X"000000000000000000000000020180C08273DD3B362B5682996B75A59350F470",
INIT_78 => X"FFFFFFFFFFFFFFFF000000000000000000000000000000000000000300000000",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF37FFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"924A4924924C9349249248D36D2449249249259B684925B6DB6DB6DB69A49A49",
INIT_7B => X"824824010000268920920900008248248200000000000024DB64934924924924",
INIT_7C => X"FFFFFEFFF7FFBFFBFFBFFBFFBFFBFFFF9208002482482689209106D124100024",
INIT_7D => X"FFBFFBFFAFFAFFAFEFFF7FFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFF97FDFFFFF",
INIT_7E => X"EFFF5FFDFEDFEFFEFFEFFDFFDFFF5FFDFEDFEFF97FD7EFFEFFEFFEDFF7FFBFFB",
INIT_7F => X"C7DDFF9FF8FFDBFDFFDFFEFB2FF6FCFFC7DD7DEBFF1F75F75EF5EF5FFDFEDFEF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"8008008000000000000000000010010010010010000000000000000000000000",
INITP_06 => X"0200000000000000000000000000000400400400000000000000000000000800",
INITP_07 => X"0000000000000100000000000000000010010000000000000000000000000000",
INITP_08 => X"0000000000004004004000000000000000000000000008008000000000000000",
INITP_09 => X"0010010010010000000000000000000000020020020000000000000000000000",
INITP_0A => X"0000000400400000000000000000000000000000800000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000020020000000000000000000000",
INITP_0C => X"2202202202202202000000000000000800000000000000000000000000000001",
INITP_0D => X"8088088088088088088080180180100110110110110110110110300300300220",
INITP_0E => X"00007C0000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B10BADEFCF55AF69453393D1B109AFEFCF55AD8B453375F19127D1EFD1558DAD",
INIT_01 => X"CD93B3458B11F175D10F69F1CD93B1456911D193D10D8BEFCF75B1676713B3B1",
INIT_02 => X"91CF7191AFCF918B91EF8DCF91AF7191AFCF8F6D91EF8FCFB1B171B1B1CF8F6F",
INIT_03 => X"CFB1918971F18BB191CF9191CFAF918B91F18BB191CF7191CFCF918B91EF8DCF",
INIT_04 => X"71B1AB93AFCF9171CF91AF8B71D18993AFCF9191CFB1B18971D189B1B1CF9191",
INIT_05 => X"CFB19171B191CF8D6F91CD91CFAF9171AF91CF8D6FB1AB93CFCF9171CF91CF8B",
INIT_06 => X"91CFCF918B91EF8DCF91AF7191AFCF916D91EF8FCFB1B171B1B1CF8F6D91CD91",
INIT_07 => X"8971F189B191CF9191CFAF918991F18BB191CF7191CFAF918B91EF8BCF91CF71",
INIT_08 => X"93CFCF9171CF91AF8B71D18B93AFCF9191CF91B18971D189B3B1CF9191CFB1B1",
INIT_09 => X"71B1B1CF8F6F91CD91CFAF9171AF91CF8D6FB1AB93CFAF9171CF91CF8B6FB1AB",
INIT_0A => X"918B91EF8DCF91AF7191AFCF918D91EF8FCF91B17191B1CF8F6D91CD91CFB1B1",
INIT_0B => X"89B1B1CF9191CFB1918971F18BB191CF7191CFAF918B91EF8BCF91CF7191CFCF",
INIT_0C => X"F173D1EF2933F171EF312D33D193D1CD2B33D191F12F3133D1B1D1CD2F33B1B1",
INIT_0D => X"2333D153F1532537D155F1EF2533D153EF532735F155F1EF2733F173EF312B35",
INIT_0E => X"D1B127397155F1EF45339153D19125399155F1EF2533B153D1732537B135F1EF",
INIT_0F => X"33B1D1D1AB2F53B1B1F12B355193F1D189315191D1D129375173F1D167337173",
INIT_10 => X"EF2933F171EF312D33F193D1CD2B33D191F12F2F33D1B3D1CD2D33D191F12F33",
INIT_11 => X"53D1732537D155F1EF2533D153F1532735F155F1EF2733F153EF332935F173D1",
INIT_12 => X"397155F1EF45339153D1B127399155F1EF4533B153D1912537B135F1EF2333D1",
INIT_13 => X"D1AB2F33B1B1F12D355193D1D189315191B1D12B375173F1D167337173D1B127",
INIT_14 => X"F173EF312B33F193D1EF2B33D171F1312F33D1B3D1CD2D33D191F12F3333B1D1",
INIT_15 => X"2537D135F1EF2533D153F1532737D155F1EF2533F153EF532935F173D1EF2733",
INIT_16 => X"CCCD2F030DADEF6C03CF09CDCCAD0F0509CFEF4E03AF07EFCDAB0F0707EFEF2E",
INIT_17 => X"1147F1AC0BCD0D67CCEF4B031169F18C07CF0D89CCCF2D030F8BEF8C05CF0BAD",
INIT_18 => X"0F472F03EFEF69090F23F1AC0D692F25CFEF6B071125F1AC0BAB0F45CDEF6B05",
INIT_19 => X"EFCDAB0F0705F1EF2F238F03EFCF890D0B03F1CD0F454F03EFEF890B0D03F1CD",
INIT_1A => X"030DADEF6C05D109CDCCCD2F030BCFEF4E03AF07CFCDAB0F0507EFEF4E03AF05",
INIT_1B => X"AC0BAD0D47CDEF4B031167F18C09CD0D89CCCF4D030F8BEF8C07CF0BABCCCD2F",
INIT_1C => X"03EFEF690B0F03F1CD0D672F23CFEF69071125F1AC0D8B0F45CDEF6B051145F1",
INIT_1D => X"0F0705F1EF2E238F05EFCF890D0903F1CF2F256F03EFEF890B0D03F1CD0F452F",
INIT_1E => X"EF6C05D109CDCCCD2F030BCDEF6E03CF07CFCDAB0F0509EFEF4E03AF05EFCDAB",
INIT_1F => X"0D47CDEF4B051167F18C09CD0D69CCCF4D030F89EF8C07CF0BABCCCF2D030DAD",
INIT_20 => X"052DADF1F3D10F8953EFCDEF072BAFF1F1D10D8B53EFCFEF0729D1F1F1B10DAD",
INIT_21 => X"F5CF2F4791D1CDEF273169F1F3CF0F6773F1CDEF052F8BF1F3CF0F6973EFCDEF",
INIT_22 => X"B173CDCF8B2F45F1F3EF7147B191CDCF693147F1F5EF5147B1B1CDCF473167F1",
INIT_23 => X"EF0927D1F1EFB12BAF53EFCFCD0B25D1F3EFB129AF73EFCFAD2D25D1F3EF9127",
INIT_24 => X"F1F3D10F6953EFCDEF072BAFF1F1D10D8B53EFCFEF0729CFF1F1D10DAD53EFCF",
INIT_25 => X"4591D1CDEF273169F1F3CF2F6791F1CDEF052F8BF1F3CF0F6773EFCDEF052FAD",
INIT_26 => X"CFAB2F45D1F3EF7147B191CDCF8B3145F1F5EF5147B1B1CDCF493167F1F5CF2F",
INIT_27 => X"D1F1EFB10BAF53EFCFCF0B25D1F3EFB129AF53EFCFCD2D25D1F3EF9129B173CD",
INIT_28 => X"0F6953EFCDEF052DAFF1F1D10D8B53EFCFEF072BAFF1F1D10DAD53EFCFEF0927",
INIT_29 => X"CDCF273169F1F3CF2F4791D1CDEF25318BF1F3CF0F6773F1CDEF052F8DF1F3D1",
INIT_2A => X"91CDB10B8FB12FF3F1714EF1B1ABB10D6DB351D1F1516EF1B1ABB32D6BB371B1",
INIT_2B => X"938B3133B1910CD1B1EF8D0D918D0F13D1912CD191CD8F0D918F0F13D1712EF1",
INIT_2C => X"91D10FB1D1F169717169711391B10CB1D1EF894F738B511391B10CD1B1EF8B2D",
INIT_2D => X"F1B189932F699391B1F12F8FF1D189934F6993B191D12FB1F1D16971716973F3",
INIT_2E => X"0B8FB12FF3F1714EF191ABB10D8DB32FD3F1516EF1B1ABB32D6BB351B1F1518E",
INIT_2F => X"33B1910CD1B1EF8D2D918D2F13B1912CD191EF8F0D918F0F13D1712EF191CDB1",
INIT_30 => X"B1D1F16971716971F391B10FB1D1F1694F7389511391B10CD1B1EF8B2D938B31",
INIT_31 => X"B32D6B9371B1F1518FF1D189934F6993B191F12FB1F1D16991516973D391D10F",
INIT_32 => X"0FF3F1714EF191CDB10D8DB12FD3F1514EF1B1ABB32D6DB351B1F1516EF1B189",
INIT_33 => X"0CD1B1EF8D2D938D3113B1910CD191EF8D0D918F0F13D1712EF191CD910B8FB1",
INIT_34 => X"F173EFD191D1B19145D18B2FD171EFD16FF1B1B145D1692FD191EFD14F1191D1",
INIT_35 => X"F151D153ABADAF29D155CDD1D191D15389AFAF2BF155EFD1B1B1D17367D1AD2D",
INIT_36 => X"EF67D1258F55CDEFF131F153CD69D1278F55CDD1F151F153CD8DD127CF55CDD1",
INIT_37 => X"4FB3AFEFF12F1191D145D1474F93AFEFF12FF171CF47D1456F75CDEFF111F153",
INIT_38 => X"D1B1D1B17145D18B2DF171EFD191F1B19145D1692FD191EFD14FF191B145D167",
INIT_39 => X"53ABADB129CF55CDD1D171D15389AFAF2BF155EFD1D1B1D17367D1AD2DF173EF",
INIT_3A => X"256F75CDEFF131F153CD69D1258F55CDD1F131F153CD8BD127AF55CDD1F151D1",
INIT_3B => X"EFD12F1191D145D1474FB3AFEFF12F1171CF47D1456F93CDEFF111F173EF67D1",
INIT_3C => X"B17167D18D2DF173EFD191F1B19145D18B2FD191EFD16FF1B1B145D1694FB3AF",
INIT_3D => X"D129CF55CDD1F171D15389AFAF29D155EFD1D191D17389CFAF2BF173EFD1B1D1",
INIT_3E => X"23ABCD37F133EF95D1D116F52389CD37F133F177D1D116134547EF55F133F159",
INIT_3F => X"EFB1D1D177EF177445CF6737EF91D1D395F117B423ADAB37EF53F1B3B3F117F4",
INIT_40 => X"3BEF5536ADCD2393D1D173F139EF373689CF4575F1B1B1F159EF175467CF4555",
INIT_41 => X"134745F175F133F139EF9316F16923D193F153F139EF7516EFAB23B3B3F153F1",
INIT_42 => X"37F153EF95D1F116F52389CD37F133EF77D1D116134567EF55F133F157EFB316",
INIT_43 => X"D157EF177445CF6737EF91D1D375F117B423CD8937EF73F1B3B3F117D423ABCD",
INIT_44 => X"16CDAD23B3D1D173F139EF3736ABCD2373F1D191F159EF175467CF4555F1B1D1",
INIT_45 => X"F175F133F139EF9316116723D193F133F139EF7516EF8B23B1B3F153F13BEF55",
INIT_46 => X"EFB5B1F116F42389CD37F133EF95D1D116132567CF55F133F157EFB316134545",
INIT_47 => X"177445CF6755EF91D1D175EF179423CD8937EF73F1B393F117D423ABAB37F153",
INIT_48 => X"F19573F12DAFD1714555ED25F1B553D12BAFD1914573EF05D3D553D129D1B18E",
INIT_49 => X"3169EF558933EA6BCF55B3D1316BEF556733EB49EF7593F12F8DEF536755ED27",
INIT_4A => X"AA2BCCB1695513915345D155AA2DEAAF8B55F3B15347F1558931EA8DAD55D3D1",
INIT_4B => X"05B3F353B127D1B3AC2791D1259313539125D193AC29AFD1477513717325D175",
INIT_4C => X"F12DAFCF734555ED27F1B553D12BAFD1714553EF05D1D553D129D1B18F4573CF",
INIT_4D => X"558933EA6DCD55D3D13169EF558933EB6BEF7593F12F8BEF536755EB27F19573",
INIT_4E => X"B1477513715345D155AA2DCAAF895513915347F155AB2FEA8DAD55F3D13167EF",
INIT_4F => X"53B127D1B1AE2791D125B313539125D193AC27AFD1279313737325D175AA29CC",
INIT_50 => X"EF734555ED27F19553F12BAFD1714553ED05D1D553D129D1D18F4573CF05D3F3",
INIT_51 => X"EA8DCD55D3D13169EF558933EA6BEF55B3F12F8BEF536735EB49F17573F12FAD",
INIT_52 => X"119191F1B3B371B19389D115F1B171F1B39371919389B315F1D171D1D1939191",
INIT_53 => X"73D171F17169F153F371B1F193D171F17369F133F391B1F193B371D17369D135",
INIT_54 => X"518FCD737391F1B193F173F1518DEF739371D1B193F171F1716BEF73D371D1D1",
INIT_55 => X"15D1D171D1F193917193AB9333D1F191B3F193B17191CD9353B1F19193F173D1",
INIT_56 => X"F1B3B371B19389D11511B191F1B39371B19389B315F1D171D1D193919193ABB3",
INIT_57 => X"F1716BF153F371B1F193D171F17369F153F391B1F193B371D17369D135119191",
INIT_58 => X"937391F1B193F173D1518FEF739391F1B193F171F1716DEF73B371D1D193D171",
INIT_59 => X"71D1D193917193ABB333D1F171B3F193B17191CD9353B1F191B3F173D1518FCD",
INIT_5A => X"71D19389D11511B191F1B39371B19389D115F1B171D1D19391919389B315F1D1",
INIT_5B => X"F153D371D1D193D171F17169F153F391B1F193B371D17369F135119191F1B3B3",
INIT_5C => X"CD8FAFCDCF5125CFD12DEFD1CD8FAFCDCF5327CFD12DEFD1CD6DD1CFCF3147CF",
INIT_5D => X"D18F07EFAF2DEFF1CDAF6DCDD18F07EFD10DEFF1CDAF8FCDD17105EFD10DEFD1",
INIT_5E => X"AF8FCFF1CFCF4BCFD1AD0DCDAF6FCFF1CFD14DCFD1AF09EFAF4FEFF1CFD16DCD",
INIT_5F => X"D1CF4DD1CFCD3169CFB16FF1D1CF4DCFCFCD2F8BAF8F8FF1D1CF4BCFD1CD2FAD",
INIT_60 => X"CDCF5105EFD12DEFD1CD8FAFCDCF5127CFD12DEFD1CD6DD1CFCF3147CFB14D11",
INIT_61 => X"EFAF2DEFF1CDB16DCDD18F07EFAF2DEFF1CDAF8FCDD17105EFD10DEFD1CD8FAF",
INIT_62 => X"F1CFCF4BCFD1AD0DCDAF6FCFF1CFD14DCFD1AF0BEFAF4FEFF1CFD16DCDD18F07",
INIT_63 => X"D1CFCD3169CFB16FF1D1CF4DD1CFCD318BAFAF8FF1D1CF4BCFCFCD2FADAF8FAF",
INIT_64 => X"05EFD10DEFD1CD8FAFCDCF5125CFD12DEFD1CD6DB1CDCF3147CFB14D11D1CF4D",
INIT_65 => X"EFF1CDB16DCDD18F07EFAF2DEFF1CDAF8FCDD17105EFD10DEFD1CDAF8FCDD151",
INIT_66 => X"1147EF37B1D1338F17EF11CD1169F13571D1336F17EF11AC0FABF15553F1114F",
INIT_67 => X"F15333EF13D111EF3323EF37D17133CF13D111CD1345EF37B1B133AF15F111CD",
INIT_68 => X"1155F1EF6E05EF93D13311111173F1EF7103EF75D15311F111B311EF5103EF55",
INIT_69 => X"AC0DADF17533F1112F37EF11AC0BCDD1933311113155F1EF8E07EFB3B3331111",
INIT_6A => X"37B1B133AF15EF11CD1167F13791D1336F17EF11CC0F89F15553F1334F17EF11",
INIT_6B => X"EE13B111EF3123EF35D17333CF13D111CD1323EF37D19133AF15F111CD1345EF",
INIT_6C => X"EF8E05EFB3D13311111175F1EF6F03EF73D13311F11193F1EF5103EF55F15333",
INIT_6D => X"F17553F1112F37EF11AC0BCDD19333F111220000000409EFD1B33311111155F1",
INIT_6E => X"33AF15EF11CD1167F13791D1338F17EF11CC0F89F15573F1336F17EF11AC0DAB",
INIT_6F => X"11EF3123EF35F17333CF13D111EF3323EF37D19133CF15F111CD1345EF37B1B1",
INIT_70 => X"EF91AFD1CFF1356945EF2EB1EF91AFD1CFF1338B45CF2ED1EF73CDCFD1F131AD",
INIT_71 => X"CCD17505ABCD2C71F1AF71D1CCF1552789EF2C91F1AF91D1CFF1354767EF2CB1",
INIT_72 => X"EF676D51F1CD55CFCCD1B307CD894D51F1CD55CFCCD19305CDAB2D71F1CD73CF",
INIT_73 => X"D1EF55CDCFD1F10FCD45AF2ED1EF55CDCFD1D10BEF678F2FD1CD55CDCDD1B309",
INIT_74 => X"D1CFF1356945EF2EB1EF91AFD1CFF1338B45CF2EB1EF73CDCFCFF131AD45AF2E",
INIT_75 => X"05ABCD2C71F1AD73D1CCF1552589CF2C91F1AF91D1CDF1354767EF2C91EF8FAF",
INIT_76 => X"51D1CD55CFCDD1B307EF894D51F1CD55CFCCD19307CDAB4D51F1CD73CFCCD175",
INIT_77 => X"CDCFD1F12FCD45AF0C4444444466CD442255335555112244CDCFD1D109EF676D",
INIT_78 => X"354967EF2CB1EF91AFD1CFF1336945CF2EB1EF73ADCFCFF131AB45CF2ED1EF53",
INIT_79 => X"2C71F1AD73CFCCF15525ABCD2C71F1AF91D1CDF1552789EF2C91EF8F8FD1CFF1",
INIT_7A => X"718D8B1393D1712971EF6D93718D8B3373D1514971CD6F936F6F895355F14F69",
INIT_7B => X"F15391098DF16975738B6D13D17391096DF16B93718B8D13B1B371296FEF6B93",
INIT_7C => X"89B18975938B714DD135D10B8BB18975738B712FD135B1098BD1697573896F31",
INIT_7D => X"936F6F6B7335F14F6991CD73938D716B9135F12D6991AB73938D716DB115D10B",
INIT_7E => X"13B3D1712971EF6D93718D8B3393D1514971EF6F936F6F8B5353F14F6971CD71",
INIT_7F => X"098DD16975738B6F11D17391098DF16993738B8D13D19371296FEF6B93718B8B",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal ena_array : STD_LOGIC_VECTOR ( 7 to 7 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000079FF0000000000",
INITP_01 => X"0000000000000000000000000000000000FFFF80000000000000000000000000",
INITP_02 => X"000000000000000003FFFFFE0000000000000000000000000000000000000000",
INITP_03 => X"07FFFFFF00000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"00000000000001001001100100000000000000000000000007FFFFFF80000000",
INITP_06 => X"000000000000000000400440040000001FFFFFFFC00000008008800800800000",
INITP_07 => X"00000000000000003FFFFFFFC000000000000000000000000200200000000000",
INITP_08 => X"1FFFFFFFC0000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000400400000000200200200000000000800800800000000000000000000",
INITP_0A => X"00000000000000000000000000000000000000200200000007FFFFFF90000000",
INITP_0B => X"0000000000000200000000000000000007FFFFFF800000000000000000000000",
INITP_0C => X"000000000000800803FFFFFF0000000000000000000010010010010000000000",
INITP_0D => X"11DFF80C01000000000000000000000002002002002000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000007E00000000000",
INIT_00 => X"75938B714DD135D10B8BB18975938B714FD135B1098BD1697573896F31F15391",
INIT_01 => X"895335F14F6991CD8999777799EFCC997799BB99BB997777AC460A662800AA89",
INIT_02 => X"71296FEF6D93718D8B3393D1714971EF6F93716F8B3373F14F4971CD71936F6F",
INIT_03 => X"697573896F11F17391098DF16993738B8D13D19371296FEF6B93718B8B13B1B1",
INIT_04 => X"D1CF51D1CFCDD18FB1EFCFCDD1CF51CFCFCDCF6FD1EFCFCDCFCF51CFCFCDCF4F",
INIT_05 => X"CDCFCFAD71F1CDCFD1CD91B1CDCFD1AD91EFCDCFD1CD71D1CDCFD1AD91EFCFCD",
INIT_06 => X"51D1CDD1CFCDB171CDD1CFCD51F1CDD1CFCDB191CDCFCFCD51F1CDD1CFCD91B1",
INIT_07 => X"CDCFCF51CFCFCDCF4FD1EFD1CDCFD151CFD1CDCF4FD1EFD1CDCFD171CDD1CFCD",
INIT_08 => X"D1CFCDD18DB1EFCFCDD1CF51D1CFCDCF6FB1EFCFCDCFCF51CFCFCDCF6FD1EFD1",
INIT_09 => X"AD71F1CDCFCFCD91B1CDCFD1AD71F1CDCFD1CD71B1CDCFD1AD91EFCFCFD1CF51",
INIT_0A => X"D1CFCDB171CDD1CFCD51F1CDD1CFCDB191CDCFCFCD51F1CDD1CFCDB191CDCFCF",
INIT_0B => X"51CFCFCDCF4F02883399BB9999777799BB9999BBBBBBBBBB77EECCCDEEEEAAAA",
INIT_0C => X"D18DB1EFCFCDD1CF51D1CFCDD18FB1EFCFCDCFCF51CFCFCDCF6FD1EFD1CDCFCF",
INIT_0D => X"CDCFCFCD91B1CDCFCFAD71F1CDCFD1CD71B1CDCFD1AD91EFCFCFD1CD71D1CFCD",
INIT_0E => X"F175F1EF0713F173EF110D15D193F1CD0B13D191F10F1113B1B3F1AB0D13B1B1",
INIT_0F => X"0313D133F1530519D137F1EF0313D133EF330717D155F1EF0513F153EF130915",
INIT_10 => X"F1B1051B7335F1F123137133F19103199137F1EF2313B133F1730319B137F1EF",
INIT_11 => X"33B3D1F1AB0F3391D1D10B173393D1F167113373D1D109195355F1F145135353",
INIT_12 => X"EF0713F173EF110B15D175F1CD0B13D191F10F0F15D1B3F1AB0D13B1B1F10D15",
INIT_13 => X"33F1530319D137F1EF0313D133F1330517D135F1EF0513F153EF130915F155F1",
INIT_14 => X"1B7355F1F123137333F191051B9137F1EF23139133F1730319B137F1EF0313D1",
INIT_15 => X"F1AB0F33B1043311777799777777777799BB99BB99BBBB997777777777777744",
INIT_16 => X"F153EF110B15F175F1CD0913D171F1110F15D193F1CD0D13D1B1F10F1313B3D1",
INIT_17 => X"0319D137F1EF0313D133F1330517D135F1EF0513F153EF130717F155F1EF0713",
INIT_18 => X"8BAD2D452DCDCF6C07EE2BCDAB8B2F472BEFCF4C05CE29EFAB8B2F4929EFAD4E",
INIT_19 => X"3367D18A2BCD2F89ABAF4B273189CF8A09CF2DABABAF4D252FABCF6A07EF2BCD",
INIT_1A => X"2F496E45CDCF672B5145EFAB2D694F45CDCF49293145EF8B2DAB2F67ABCF4927",
INIT_1B => X"EFAD692F4B27EFAD4F25AE25EFAD692D4D25EFAD2F278E25EFAF672D4F25EFAB",
INIT_1C => X"452DCDCF6C07EE2BCDAB8D2F472BEFCF6C05CE29EFAB8B2F4929EFAF4E05AE27",
INIT_1D => X"8A2BCD2F89ABCF4B273189CF8A0BCF2DABABAF4B252FABCF6A09EF2DCD8BAD4D",
INIT_1E => X"2244CF672B5145EFAB2F694F45CDCF49295145EF8B2D8B4F67ABCF49273367D1",
INIT_1F => X"2F4927CC8911773399557733777777BB7799BB99BBBB99779999777799777777",
INIT_20 => X"CF6A07EE2BCD8BAD2F472DCDCF6C05CE29EFAB8B2F4729EFAF4C05CE27EFAB89",
INIT_21 => X"2F67ABCF4B273189CF8A0BCF2D89ABAF4B2531ABCF8A09EF2DABABAD4D452FCD",
INIT_22 => X"0B8F6F8BB3910FAF91EF6BEF0D8D718BD3712F9191CD6BEF2D8B718DD1714F91",
INIT_23 => X"95D10FCD71F169AF2B918D8BB5B10FCF91EF69CF0B8F6F8BB5910FAF91EF69CF",
INIT_24 => X"73B1898F8F71896F93CF31AD73D1898F6D718B8D95CF31AD73D1698F4D918B8B",
INIT_25 => X"EF2D8B718FD1714F9191CD6DCF4F8B718FEF516D71B1AB6DAF4F896F93EF518D",
INIT_26 => X"8BB3910FAF91EF69EF0B8D718BB3912FAF91EF6BEF2D8D718DD1712F9191CD6D",
INIT_27 => X"CD71F167AF2D918D8B95B10FCF71F169AF2B8F6F8BB5B10FAF91EF69CF0B8F6F",
INIT_28 => X"55AB6C896F93EF51AD73D1898F8D718B8D95CF31AD73D1698F4D918B8B95D10F",
INIT_29 => X"718D6A89EE335555775533557777777799997799BB99BB999955777799777777",
INIT_2A => X"0FAF91EF69EF0B8D718BB3912FAF91EF6BEF0D8D718DD1712F9191CD6BEF2D8B",
INIT_2B => X"67AF2D918D8B95B10FCD71F169AF2B916D8BB5B10FAF91EF69CF0B8F6F8BB391",
INIT_2C => X"D1ABD1118DD12FF1EF3372F1D189D13169F12FD1EF3392F1D167F33167F351CF",
INIT_2D => X"B1693111CF5332F1D1EF8B31AF8B3111CF533211D1CDAD11ADAF0FF1EF335211",
INIT_2E => X"AFB112F3F1F14593B14591F1CF9112F1F1EF4771B1677111CF7312F1D1EF6951",
INIT_2F => X"F1D167F35147F371CFF112D3F1F145D37145D3B1CFD112F3F1F145B39145B3D1",
INIT_30 => X"118DD10FF1EF337211D1ABD1318BD12FF1EF3392F1D189F33169F351CFF133B2",
INIT_31 => X"11CF7312F1D1EF8B31AF8B3111CF533211D1CDAD11AFAD0FF1EF335211D1ABCF",
INIT_32 => X"5533444593B14593F1AFB112F1F1EF4771B14771F1CF9112F1D1EF6951B16951",
INIT_33 => X"F30DEE3377335577BB7777557755777777777799BB9977777777779999BB3333",
INIT_34 => X"0FF1EF337211D1ABD1118BD12FF1EF3392F1D189F33169F351D1F133B2F1D167",
INIT_35 => X"12F1D1EF8931AF8B3111CF5332F1D1CD8D31AFAD3111EF335211D1CDCF118DCF",
INIT_36 => X"F155EFF191D1D17323F1890DD173EFF171F1D19123F1670FB1B3EFF153F1B1D1",
INIT_37 => X"F151F133ABCDCF07CF37EFEFD191F13367CFCD09F155EFF1B1B1F15345EFAB0D",
INIT_38 => X"EF47F1036F55EFEFF133F133CD69F1038F37EFEFF133F133ABABEF05AF37EFEF",
INIT_39 => X"2FB3B1EFF1331191D123F1232F93D1EFF1331173CF45F1234F75EFEFF113F153",
INIT_3A => X"F1B1D1D17345F18B0DD173EFF191D1D19123F1670FD193EFF151F1B1B123F145",
INIT_3B => X"33ABADCF07CF37EFEFD171F13389CFCD09D135EFEFD191F15367EFAB0BF155EF",
INIT_3C => X"333344EFEFF133F133CD67F1038F37EFEFF133F133CD8BEF05AF37EFEFF153F1",
INIT_3D => X"EF8A333355557755BBBBBBBB77777777777777BB99BB77773377777777997777",
INIT_3E => X"D17345F18B0DF175EFF191D1D19123F1690FD193EFF171F1B1B123F1450FB3B1",
INIT_3F => X"EF07CF37EFEFF171F13389CDCD09D135EFEFD191F15367EFAD0BF155EFF1B1D1",
INIT_40 => X"458DAD55CF51F195AFB334D1458BAF55CF53F175AFB334EF4769B175CD53F157",
INIT_41 => X"D18FD1B375D1359245AF8955D18FF1B373D135B245AF8B55CF71F19391D135D1",
INIT_42 => X"37CF5554ABAF4593B1AD91D157CF555489AF4773B1AFB1D155CF357467B16955",
INIT_43 => X"EF6967B175CD53F157CD9336CD6B47B193CD53F137CD7334CD8D45B393CD73D1",
INIT_44 => X"55CF51F195AFB334D1458BAF55CF53F175AFB334F14769B155CF53F157CD9334",
INIT_45 => X"B375D1359245AF6955D18FD1B373D1359245AF8B55CF71F1B391D135D1458DAD",
INIT_46 => X"5511444593B1AD91D137CF555489AF4773B1AFB1D155CF357467B16775D18FD1",
INIT_47 => X"B1752233555577999999BB777777777755777777BB3377777777335577553377",
INIT_48 => X"F195AFB134D1458BAF55CF53F175AFB334F14769AF55CF53F177CDB334EF6767",
INIT_49 => X"357467B16955D18FD1B373D1359245AF8B55CF71F1B391D135B345ADAD55CF51",
INIT_4A => X"13B3B1F18F71CFB1AB93D10B13D391F18D73CFAFABB1B10BF3F391D18B73CFAD",
INIT_4B => X"918DCF93AB91ED4FF193D1F1918FCF93AB93EF2D11B3B1F18F71CF91AB93CF0B",
INIT_4C => X"AAADEF736D9311B1B18BB193AA8FED538D93F1D1918BB193AA91ED51CF93F1D1",
INIT_4D => X"09F3F191D18B93B1ACADD1932BD31191D18B93B1ACADCF734BB311B1B18993B3",
INIT_4E => X"F18F71CFB1AB93CF0B13D391F18D73CFAFABB3B10BF3D391F18B73CFAFABB193",
INIT_4F => X"93AB91ED4FF193D1F1918FCF93AB93ED2FF193D1F18F6FCF91AB93CF2D11B3B1",
INIT_50 => X"33EF6611B1B18B9193AA8FED738D93F1D1918BB193AA91ED51AF93F1D1918DCF",
INIT_51 => X"91D18B0CCC773377559999777777557777995577775555555555555511773355",
INIT_52 => X"CF91AB93CF0B13B391F18D73CFAFABB3B10BF3D391F18D73CFAFABB19309F3F1",
INIT_53 => X"ED51CF93D1F1918DCF93AB93ED2FF193D1F18F6FCF91AB93CF2D11B3B1F18F71",
INIT_54 => X"F17153F193D153B13345F135F19153D1B3D151913367F115D1B153D1D1D17151",
INIT_55 => X"55F153F13327F173D153B1D155F153D13325F155F15371F175D133D13345F135",
INIT_56 => X"332FCDB37553F19155F191D1332BEFB39353D1B155F173F13329EF93B353B1D1",
INIT_57 => X"15B1D153B3D1B191513189D13591D15393F1B1B13331ABD15573F17175F191D1",
INIT_58 => X"F175D133B13345F135F19153D193D151913345F115D1B153D1B3D171713367D1",
INIT_59 => X"F13327F173D153B1D155F153D13325F175F15391F175F133D13345F135F17173",
INIT_5A => X"116651F17155F191D1332DCDB39353D19155F171F13329EF93B353D1D155F153",
INIT_5B => X"53B3D1B10A113377777777777777777777997777337755557755553355555555",
INIT_5C => X"33B13345F135F19153F193D151913345F115D1B153D1B3D151713367D115D1D1",
INIT_5D => X"F193D353B1D155F153F13327F173F15391F155F133D13325F155F17171F175D1",
INIT_5E => X"CCAFAFCCEF3323EFEF2FEFF1CC8DCFCDCF3325EFEF2F11F1CC4DEFCDCD1345EF",
INIT_5F => X"F18E05EFEF2FEFF1CDCF6DCCEF6F03EFEF2FEFF1CCAF8DCCEF5103EFEF0FEFF1",
INIT_60 => X"CF8FCFF1EFEE2BCEEFAC0BCDCF6FCFF1CFEE2BCCEF8C09EFCF4FEFF1CDEF4DCC",
INIT_61 => X"F1CC4BEECDCD1167CFCF6F11EFCE2BEECFCC0F89CFAF8F11EFEE2BEEEFAC0DAD",
INIT_62 => X"CCEF3103EFEF2FEFF1CC8DCFCCCF3323EFEF2F11F1CC6DEFCDCD1345EFF14F11",
INIT_63 => X"EFCF2FEFF1CDCF6DCCEF6F05EFEF2FEFF1CCCF8DCCEF5103EFEF0FEFF1CCAFAF",
INIT_64 => X"22EFEE2BCEEFAC0BCDCF8FCFF1CFEE2BCEEF8C09EFCF4FEFF1CDEF4DCCF18E05",
INIT_65 => X"EECDCD1147441133335555773355557777777777773355555533777755557777",
INIT_66 => X"03EFEF0FEFF1CC8DCFCCCF3323EFEF2F11F1CC6DCFCDCD1345EFEF4F11F1CC4B",
INIT_67 => X"EFF1CDCF6DCCEF6E05EFEF2FEFF1CCCF8DCCEF5103EFEF0FEFF1CCAFAFCCEF31",
INIT_68 => X"3169F155B1D1F38F13EFCFCC316BF15591F1F36F13EFCFCC2F8DF17571F1F36F",
INIT_69 => X"EE73F3AD31D1CFCF5145F155CF91F3AD13F1CFCF5147F155D1B1F5AD13EFCFCD",
INIT_6A => X"3153CFCF8F27D1B3D15313CF3171CFCF7125D193CF73F3CD31B1CFCF7125D175",
INIT_6B => X"AC2DAFF1735311F15133EFCFAC2BAFD1935311F15133EFCFAE29D1D1B15311CF",
INIT_6C => X"55B1D1F38F13EFCFCC3169F15591F1F38F13EFCFCC2F8BF17571F1F36F13EFCF",
INIT_6D => X"AD31D1CFCF5145F155CF91F3AD31D1CFCF5147F155D1B1F5AD13F1CFCD3167F1",
INIT_6E => X"048F27D1B3D15313CF3171CFCF8F25D193D153F3CD3191CFCF7125D175CE73F3",
INIT_6F => X"F1737311F14F22111133EF11555577557777335533CC2204222222EE3311EEEE",
INIT_70 => X"F58F13EFCFCD3169F15591D1F38F13EFCFCC2F8BF17571F1F36F13EFCFCC2FAD",
INIT_71 => X"CFCF5145F155CF91F3AD31D1CFCF5145F155CFB1F5AD13F1CFCD3167F155B1D1",
INIT_72 => X"EF6B6B71B1F1732B89EF8F73EF6D6991B1F1714989EF8F73CD8F699193F15169",
INIT_73 => X"CEB3B30B89EF8F91F1698D71CFB3930B89EF8F73F16B6D71CFD1932B89EF8F73",
INIT_74 => X"89ABAF91B389936BCF93D10D89CD8F91B389916DCE93B30B89CD8F91D1698F6F",
INIT_75 => X"73CD91699193F14F6989CF8F93AB9169B193F12F89ABAF9193AB936BCF93D12D",
INIT_76 => X"71B1D1732B89EF8F73EF6D6991B1F1714989EF8F73CD8F699193F1716989CF8F",
INIT_77 => X"894DCD8FAF93CF6D8971D1938B4BCD8F73F1696D71CFD1932B89EF8F73EF6B6B",
INIT_78 => X"91B389936BCF93D10D89CDAF91B3892BAB4FF1938B6F898FAFB3EF4D8971D193",
INIT_79 => X"699193F151698989880C4466CC333377555555AA882CAB936BAF73882A018889",
INIT_7A => X"932B89EF8F73EF6D6991B1F1734B89EF8F73EF8F699191F1714989CF8F73CD91",
INIT_7B => X"8F91D1698F6FCEB3B30B89EF8F93F1696D71CFD1932B89EF8F73EF6B6B71B1D1",
INIT_7C => X"538FAF1391D1314751EF2BB3538FAD3373D12F6953CD2FB35171AD5353F12F8B",
INIT_7D => X"F15373058FD1257553AD7133D173532571F1279353AF8F13B1B1332771EF29B3",
INIT_7E => X"CD73675593AF536FD135B107AD91455573AD5151D1339105AFB1257573AD7133",
INIT_7F => X"D17151AD7333F10DAB53AB33B17153AF9135D10BAD738935B38F538FB115B107",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(7),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addra(15),
I1 => addra(16),
I2 => addra(14),
I3 => addra(12),
I4 => addra(13),
O => ena_array(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000100100100000000000000000000000000000000000000000000",
INITP_05 => X"1100100100124124004000000000000000000000000000000000000000000000",
INITP_06 => X"4004004004004904900008008008004004008008008209201200010010010010",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"4000002002000000000008008008008000000000000000000000000000000000",
INITP_0A => X"0000000000000000C00200200200200200000100100000200200400400400400",
INITP_0B => X"FF00000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0080080000000000080000000100100100100100000000000000000000200200",
INITP_0D => X"000000000000000000000000000000000000000000000000FF00000008008008",
INITP_0E => X"00000000000000000000000000000000FF800000000000000000000000000000",
INITP_0F => X"0000000000000000FFFF000000000000000065F4000000000000000000000000",
INIT_00 => X"13B1D1314751EF2BB3538FAD3393D1316953CD2FB35171AD5353F12F8B53AB31",
INIT_01 => X"314751EF2BB3538FAF3393D13169EF279353AF8F13D191332771EF2993538FAF",
INIT_02 => X"5593AF536FD135B107AD91455593ADAF8F13D193532771EF299353AF8F13B1B1",
INIT_03 => X"AD5333F12DAB53AB33B1712FAB2222444422664535B18F538FB115D109AD7367",
INIT_04 => X"314751EF2BB3538FAF3393D1316953CD2DB35171AD3373F12F8953CD31B17151",
INIT_05 => X"257553AD7133F17353058FD1277553AF8F13D193532771EF299353AF8F13B1B1",
INIT_06 => X"EFCC4FEECDCDF18FD1EFEFCCEFCE2FEECFCCEF6FD1EFEFCCEFEE2FEEEFCCEF4F",
INIT_07 => X"CCEFEECF71F1EFCEEFCC91D1CCCFEECF91EFEFCCEFCC71EFCDCDEFAFB1EFEFCC",
INIT_08 => X"2FF1EFEECDCDD171CCEFCCEF2FF1EFEECFCCD191CCEFCEEF51F1EFEEEFCCB1B1",
INIT_09 => X"CCEFEE2FCEEFCCEF2FF1EFF1CCCFEE2FCEEFCCEF2FF1EFF1CDCDEF51CCEFCCEF",
INIT_0A => X"EECDCDF18FD1EFEFCCEFCC2FEECFCCEF6FD1EFEFCCEFCE2FEEEFCCEF4FF1EFF1",
INIT_0B => X"F1AFB1EFEFCCEFCC2FEECFCCEF8FCFEFCEEFCC71CFCDCDEEAFB1EFEFCCEFCC4F",
INIT_0C => X"EFCDCDD171CCEFCCEF2FF1EFEECFCCCC71D1CDCDEEAF91EFEFCCEFCC51EECDCD",
INIT_0D => X"2FEEEFCCEF2FF1EFF1CCCFEE2FCCEFCCEE2EEFEFF1CDCDEE4FCCEFCCEF2FF1EF",
INIT_0E => X"F1AFB1EFEFCCEFCC2FEECFCCEF8FD1EFEFCCEFCE2FEEEFCCEF4FF1EFEFCCEFEE",
INIT_0F => X"EFEEEFCC91D1CCCFEECF71EFEFCEEFCC71D1CDCDEEAF91EFEFCCEFCC51EECDCD",
INIT_10 => X"EF73CFAB0933F171CD310B33D193CFAB0B33D191CD2F0F33D1B1CF8B0D53B1B1",
INIT_11 => X"0511D133CF510515CF55CFCD0511F151CF510715CF55CFCD0733F151CD310933",
INIT_12 => X"CF8F07177155EFCF25119151CF8F05159155EFCF0511B133CF710515B155CFCD",
INIT_13 => X"53B1B1CF690D53B1B1AD0B135393CFCF690F5391B1AF09157373CFCF270F7351",
INIT_14 => X"AB0933F171CD310B33D193CFAB0933D171CD2F0F33D1B1CF8B0B33D191CD2F11",
INIT_15 => X"F171CD310B33D173CFAB0933D171530715CF55CFCD0731F151CD310935CF73CF",
INIT_16 => X"177175EFCF25119151CF8F0715915555CFCD0711F151CF310935CF75CFAD0733",
INIT_17 => X"CF890D53B1B1AD0D135393CFCF690F5391B1AF0B157373CFCF470F7371CF8F07",
INIT_18 => X"F171CD310B33D173CFAB0933D171CD310D33D191CF8B0B33D191CD2F1153B1B1",
INIT_19 => X"0515D155CFCD0511D133CF510715CF55CFCD0711F151CF310935CF75CFAD0733",
INIT_1A => X"474D6DAB8FEF6F690BEE8DEF474B8FAD8DEF6D6B0BEE8BEF49498FAD8BEF6D6D",
INIT_1B => X"B3AB8F474FCF8FAB677149ABB1AB8F674DCF8FCD676F6BABB1CD6F692DEF8DEF",
INIT_1C => X"8F4DAE89AB6F458DB389AF476F6D8FABAB7147ADB389AF476FAF8FAB897147AD",
INIT_1D => X"EF69478FAF8BEF6B8D2BCE8BEF6B458FAF89EF698F2DAE89CD6D458FB189CF49",
INIT_1E => X"AB8FEF6F690DEE8DEF474B6DAD8DEF6F6B0BEE8BEF49498FAD8BEF6D6D0BCE8B",
INIT_1F => X"6F692DEE8DEF474D6DAD8FEF6F6BEE8FCD676F6BABB1CD6F692DEF8DCD476D6D",
INIT_20 => X"89CD6F458FB389CF476F6D8FABAB716F6BABB1CD8F672DEF8FCD676D6DAB91CD",
INIT_21 => X"8FAF8BEF6B8D2BCE8BEF6B478FAF89EF6B8F2DAE89CD6D458FB189CF498F4DAE",
INIT_22 => X"6F692DEE8DEF474D6DAD8FEF6F6B0BEE8DEF49498FAD8DEF6D6D0BCE8BEF6947",
INIT_23 => X"8FAB677149ADB3AB8F474DCF8FCD676F6BABB1CD8F672DEF8FCD676D6DAB91CD",
INIT_24 => X"11CF514795532FD3B1EF27CF31CF5147B3534FB3B1CD29EF31CF3149D1336F73",
INIT_25 => X"57B10F1373F1258E2FD18F2755910F1391EF25AE0FCF712575710FF391EF27CE",
INIT_26 => X"53D1674C8FB1AD2D53D111F353F1454C6FB1AF2B55D1111353F1256C4FD18F27",
INIT_27 => X"EF51CD314BD1339173D1AB2BCF71CD314FD133B153D1892DAF91CD2F51EF31F1",
INIT_28 => X"4595732FD3B1EF27CE11CF514793532FB3B1CD29EF31CF3149B3334F93D1AB2B",
INIT_29 => X"0FD3B1EF27CE11CF514793532FB3F1258E2FCF712775910FF391EF27CE11CF51",
INIT_2A => X"4CAF91AD2D53F111F353F1454C8FB1CF712775910FF391EF25AE11CF71457573",
INIT_2B => X"314BD1337173D1AB2BCF51CD314DD133B153D1892BCF71CD2F51F131D153D167",
INIT_2C => X"0FD3B1EF27CE11CF514793532FB3B1CD29EF31CF5349B3334F93D1CD29EF51CD",
INIT_2D => X"256C2FD18F2757B10F1373F1258E2FCF712775910FF391EF25AE11CF71457573",
INIT_2E => X"F1ABEF138BEF2FEFEF159411F189113369112FEFEF15B411F1671353451351EF",
INIT_2F => X"CF675111EF533613F1CD8933CD8B31EFEF335611F1CDAD33ADCD11EFEF137411",
INIT_30 => X"CFB11633F1EF23B3D123B3D1CF911633F1EF4593D14571F1EF731633F1EF6753",
INIT_31 => X"F1F1451351251371CFD114F5F1F123F39123F391CFD11413F1F123D3B123D3D1",
INIT_32 => X"13ABEF0FEFEF157411F189F13389112FEFEF15B411F167135347134FEFF114F4",
INIT_33 => X"0FEFEF157411F189F13389F12FEF333611F1CDAB33ADAD31EFEF135411F1ABEF",
INIT_34 => X"33F1F123B3B123B3D1CF911633F1EFCDAB33CDAB31EFEF135411F1ABCF13ABEF",
INIT_35 => X"1353451371CFF114F5F1F123F37123F391CFD11413F1F123D39123D3B1CFB114",
INIT_36 => X"0FEFEF157411F189F13389F12FEFEF15B411F167133367134FEFF114D411F145",
INIT_37 => X"1613F1EF6953CF8931F1EF333611F1CDAB33CDAB31EFEF135411F1ABCF13ABEF",
INIT_38 => X"AD73EFD1B1B1F17347F16B2FAF71EFD191B1D19345F1494FAF91EFD173D1B1B3",
INIT_39 => X"F173F1538DCDB109AD55CDD1D173F1536BEFAF2BAD55CDD1D191F17367EF8D2D",
INIT_3A => X"B167D1076F55CDCFF153F153AF89D1078F55CDD1F153F153AFABD109AD55CDD1",
INIT_3B => X"5191AFEFF153D1B1B345F1275191AFEFF153D191B167F1076F73CDCFF153D173",
INIT_3C => X"D1B1B1F17347F16D2FAF71EFD191B1D19345F14B2FAF91EFD173D1D19345F129",
INIT_3D => X"F17347F16D2FAD73EFD1B1B1D173F1AF2BAD55CDD1D191F15369EF8D2DAD73EF",
INIT_3E => X"056F55CDCFF153F153B189D1078F5555CDD1D191F15369EF8F2DAD73CDD1B1B1",
INIT_3F => X"EFD173D1B1B345F1275191AFEFF153D191B345F1076F73CDCFF153D173B167D1",
INIT_40 => X"F17347F16D2FAD73EFD1B1B1D17345F16B2FAF91EFD191D1D19345F129518FAF",
INIT_41 => X"AB058C13CDCCF173F1538BCDAF2BAD55CDD1D191F15369EF8F2DAD73CDD1B1B1",
INIT_42 => X"899191936D8FF1736973918B8B8F71936D91F173697391898B8F71936B91D173",
INIT_43 => X"716BF1756F718E8F89738F93716DF1756D73908D89938F936F8FF1756B73908B",
INIT_44 => X"736B91938971AB737369D193716D91918973AD937169D175716F8E9189738D93",
INIT_45 => X"898DAD73936991D173697393898FAD737369B1B3736B91938971AB737369B193",
INIT_46 => X"936F8FF1736973918B8B9171936D91F173697391898B8F71936B91D173697393",
INIT_47 => X"F1736973918B8B9171936D91F17375908D89938F936F8DF1756B73908D899191",
INIT_48 => X"938971AB737369B193716D91918973738F936F8DF1756B73908D89918F936F8F",
INIT_49 => X"73936991D173697393898FAD739369B1B373699193896FAB737369B193736B91",
INIT_4A => X"F1736973918B8B9171936D91F1736973918B8B8F71936B91D173697393898DAD",
INIT_4B => X"000000000000716BF1756D738E8F89738F936F8DF1756B73908D89918F936F8F",
INIT_4C => X"33D1CFF1CF55CDCFEFD1B30F13D1CFF1CF55CDCFEFD1930D13F1AFF1CD55CFCD",
INIT_4D => X"D191AFD1CCD1EF13F1D1F1EFD191AFD1EFD1D11113D1CFEFCF73CDCFEFD1B10F",
INIT_4E => X"CCF1EF356FD111CFD1AF71D1CCF1EF35B1D1F1CFD1AF91D1CCD1EF33D1B1F1EF",
INIT_4F => X"0D13F1AFF1CD55CFCCF1F1552DF1F1CFF1CD55CFCCF1EF554FD111CFD1CD73D1",
INIT_50 => X"F1CF55CDCFEFD1B10F33D1CFF1CF55CDCFEFD1930D13F1AFF1CF55CFCDEFD175",
INIT_51 => X"CDCFEFD1B10F33D1CFF1CF55CDCFD1CF1113D1CFEFCF73CDD1EFD1D10F33D1CF",
INIT_52 => X"356FD111CFD1AD73D1CCF1EF358FD1D1CFEFCF73ADD1EFD1D11113D1CFF1CF53",
INIT_53 => X"AFF1CD55CFCCF1F1552DF1F1CFF1CD55CFCCF1EF554FF111CFD1CD73D1CCF1EF",
INIT_54 => X"CDCFEFD1B10F33D1CFF1CF55CDCFEFD1930F13F1AFF1CF55CFCDEFD1730D13F1",
INIT_55 => X"3311EFEEEEEE0200AAD1CDD1CF1113D1CFEFCF73ADD1EFD1D11113D1CFF1CF53",
INIT_56 => X"F17353F175F133911323F137D19133D193F133711345F117D1B133B3B3F15353",
INIT_57 => X"37F153F11305EF93D13391D137F133D11303F175F15373F155F133B11303F135",
INIT_58 => X"130DCDD17553F17337F191D1130BCDD19333D19137F173F11307EFB3B333B1D1",
INIT_59 => X"17B1D133B3D1D173331167F13791D13395F1D191330FABF15573F15355F1B1D1",
INIT_5A => X"F175F133B11323F137F17333D193F133711345F137D1B133D3B3F153531345F1",
INIT_5B => X"33B11323F137F17333D175F1339103F175D13373F155F133B11303F155F15353",
INIT_5C => X"D15553F17355F191D1130BCDD193333371D155F133D11303F155F15353F155F1",
INIT_5D => X"33B3D1D173331167F13791D13393D1D191330F89F13573F15375F1B1B1130DCD",
INIT_5E => X"33B11323F137F17333D175F133911323F137D19133D1B3F153531345F117B1D1",
INIT_5F => X"7777BB99BB77553344D11305F173D13371D155F133D11303F155F15353F155F1",
INIT_60 => X"8C8DCFAECF5145CFD14F11EFAC8DEFAFCF5367CFD16F11EFAC6BEFAFAF3167CF",
INIT_61 => X"EF6F27EFAF51EFEFADAD8DAEEF7147EFD151EFEFACADAFAEEF5145EFD14FEFEF",
INIT_62 => X"AF91CFEFCFCD4BCFEF8E2DCDAF91EFEFCFCD4DCFEF8E29EFAF71EFEFAFAD6DAE",
INIT_63 => X"EFAC4BEFCFAF3189CFB18F11EFAD4BEFCFAC2FABAFB1AF11CFAD4BEFEF8E2FCD",
INIT_64 => X"AECF5145EFD14F11EFAC8DCFAFCF5367CFD14F11EFAC6BEFAFAF3367CFD16F11",
INIT_65 => X"45EFD14F11EF8C8DCFAFCF5345CF4FEFEFACADADAEEF5145EFD151EFEF8C8DCF",
INIT_66 => X"EFCFCD4BCFEF8E2DCDAF91CFEFCFCDAD8DAEEF5145EFD151EFEFAC8DCFAECF51",
INIT_67 => X"EFAFAF3189CFB18F11EFAD4BEFCFAC31ABAFB1AF11CFAD09AAAB8A0DCDAF91CF",
INIT_68 => X"45EFD14F11EF8C8DCFAFCF5345CFD14F11EFAC6BEFAFCF3367CFD16F11EFAC4B",
INIT_69 => X"9999BB99BB77775588CCAB2CCCCDAAAA8DAEEF5145EFD151EFEFAC8DCFAECF51",
INIT_6A => X"918DD193AFF1958B2DEF6FCE918FF193AFF1938D0BCF6FCE8F71F1B1B1F191AF",
INIT_6B => X"CEB1B5696FCF6FAF918BB3B3CED195694FCF6FAF918BD193CFD1958B2DEF6FCF",
INIT_6C => X"B14D8F6FCF8B93D1CF91D369916D8F8FB18B93B3CEB1B36991AF6F8FB189B3B3",
INIT_6D => X"CE8F71F1B191F18FB12BAF6FCF8D73F1B191F16DB12DAF6FCF8B73D1CF91D16B",
INIT_6E => X"93CFF1958B2DEF6FCE918FF193AFF1938D0BEF6FCE8F6FF1B3B1F1918F0BCF6F",
INIT_6F => X"958B2DEF6FCF918DF193AFF1938DF16FAF918BD193CFD1958B2DEF6FCF918DD1",
INIT_70 => X"6FCF8B93D1CF91D36B916D8F8FAF8B8BB393CFD195894DEF6FAF918DD193CFF1",
INIT_71 => X"F1B1B1F191AF2BCF6FCE8D73F1B1916688060A6A6F4602CC88AAAAAA66064D8F",
INIT_72 => X"958B2DEF6FCF918DF193AFF1938D0BEF6FCE8F6FF1B3B1F1938F0BCF6FCE8F71",
INIT_73 => X"999999BBBBBBBBBB99AAAA8889AAAAAA8893CFD195894DEF6FAF918DD193CFF1",
INIT_74 => X"EF694753B1D1B10BABEFCF55CD6B455393F1B129CDEFCF55CD8D257175F19127",
INIT_75 => X"EF75D10F67EFCF93D1458B31D193D10D89EFCF73F1476931D1B3D10DABEFCF55",
INIT_76 => X"45CDCFB19345AF29CF55F13145EFCFB19345AF2DCF75F10F67EFCF91D1458D2F",
INIT_77 => X"55ABAF257155F17127CDEFCF5589AF279155F15125CDEFD17567B127B155F131",
INIT_78 => X"53B1D1B10BABEFCF55EF69455393F1B129ABEFCF55CD8B257373F19127CDEFCF",
INIT_79 => X"B10BABEFCF55EF69475393D1B12BEFCF73F1476931D1B3D10D89EFCF75EF6747",
INIT_7A => X"B17567B129D155F13145EFCFB19345456931D1B3D10D89EFCF75EF676753B1D1",
INIT_7B => X"257175F17127CDEFCF55ABAF259144EEEE1111460233EF777799BB55EF1144CF",
INIT_7C => X"B10BABEFCF55EF69475393D1B12BABEFCF55CD8B457373F19129CDEFCF55ABAD",
INIT_7D => X"777777BBBBBBBBBB99333311113333338831D1B3D10D89EFCF75EF676753B1D1",
INIT_7E => X"33B1B11391D1116733CD0BD13391CF3373D10F8933CD0FD15353CF5353F10DAB",
INIT_7F => X"F153530391D1037533CF7133D173332371D1059333B19113B1B1134553EF09B3",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFF8000000000000001FFFE0000000000000000000000000000000000000000",
INITP_01 => X"0003FFFFF0000000000000000000000000000000000000000000000000000000",
INITP_02 => X"000000000000000000000000000000000000000000000000FFFFC00000000000",
INITP_03 => X"00000000000000000000000000000000FFFFF00000000000000FFFFFF8000000",
INITP_04 => X"1001001000000000FFFFF00000000000001FFFFFFC0000000000000000000000",
INITP_05 => X"FFFFF00000000000003FFFFFFE800400000000800000000000000001001001F0",
INITP_06 => X"90FFFFFFFF0000000000000000120120120000000003E7FE0000000000024024",
INITP_07 => X"0000000000000000000000000007FFFF0000000000000000FFFFF80000000900",
INITP_08 => X"00000000000FFFFF0000000000000000FFFFF80000000000007FFFFFFF000000",
INITP_09 => X"FF00080880880880FFFFF80000000000003FFFFFFF0000000000000000000000",
INITP_0A => X"FFFFF22022022022021FFFFFFE200220220040440440440440440400400FFFFF",
INITP_0B => X"000FFFFFFC000000000000000000000000000000003FFFFFFF80000000000000",
INITP_0C => X"080100100100100100100000003FFFFFFF80200200200200FFFFF00000000000",
INITP_0D => X"0000000000FFFFFFFFC0000000000000FFFFE080080080080087FFF07C000080",
INITP_0E => X"FFE0000000000000FFFFC0000000000000003FC0000000000000000000000000",
INITP_0F => X"FC0FC0000000000000001F800000000000000000000000000000000003FFFFFF",
INIT_00 => X"CF73453791D13391D1339105CF91233773CF3371D1337303B1B1035553CF5333",
INIT_01 => X"D15353CF7333F10BCD338913D17133D19133D109CF536715B1B133B1B113B105",
INIT_02 => X"13B1D1114733EF0BD13391D13393D1118933CD0DD15371CF5353F10FAB33AB11",
INIT_03 => X"134753EF09D13391D13391D11169EF059333D19133D191134553EF07B333B1B1",
INIT_04 => X"0000000006D1339105CF73233793CFD19133D191332571EF07B333B1B113B1B1",
INIT_05 => X"CF5333F10DCD338913D17133D10ACDBB9999BB55779999BBBB99BB9999993300",
INIT_06 => X"134753EF09D13391D13391D1116933CD0DD13371CF3373F10FAB33AB11D15353",
INIT_07 => X"BBBBBBBB99BBBBBB77777777777777775522D191332571EF07B333B1B113B1B1",
INIT_08 => X"EFAF6FEEADAFF191D1D1CFAEEFCF4FEEADACF171F1CFD1ACEFCF4FEEAFACF151",
INIT_09 => X"8BAFEFB18FD1CDB1EFAEAFCFABAFEFB1B1D1CDAEEFAE8FEFABAFEFB1D1D1CFAE",
INIT_0A => X"4FF1CDD1CFAFEF8FABD1CFD14FF1CDD1CFAFCFAFABD1CFD16FD1CDB1EFAEAFCF",
INIT_0B => X"ACCFEF4FCCCFACF151F1CFD1ADCFEF4FCCCFAEF151F1CFD1AFAFEF6FAAD1AED1",
INIT_0C => X"EEADAFF191D1D1CFAEEFCF4FEEADAEF171F1CFCFAEEFCF4FEEAFACF171F1CFD1",
INIT_0D => X"F191D1D1CFAEEFCF4FEEADAFF191B1CDAEEFAE8FEFABAFEFB1B1D1CFAEEFAE6F",
INIT_0E => X"11335555EE88D1CED14FF1CDD1CFAFAE8FEFABAFEFB1B1D1CFAEEFAE6FEFABAF",
INIT_0F => X"4FCCCFACF151F1CFD1ACCFCC22AA5599997777777777999999BBBBBBBBBB7755",
INIT_10 => X"F191D1D1CFAEEFCF4FEEADAFF191F1CFCFAEEFCF4FEEAFACF171F1CFD1ACCFEF",
INIT_11 => X"77999999BBBBBB77779999777799997777774422ACB1B1D1CFAEEFAE6FEFABAF",
INIT_12 => X"CE918F670B6FEF6F69710B71CFAF6F470971EF6F696F0B91CFAF6F490991CF6F",
INIT_13 => X"0B2DF16F6D8F092FCF938D690B4DF16F6B91094FCE918F670B4FF16F69910B71",
INIT_14 => X"6F6B2B0DB193AD6D0B0BD18F6F6D0B0DAF93AD6B0B2BD1086628000A8C93AD69",
INIT_15 => X"91CFAD6F490991CF6F694D0D91B1AD6F2909B1AF6F692D0DB1B1AD6D2909B18F",
INIT_16 => X"670B6FF16F69710B71CEAF6F670B71EF6F696F0B91CFAF6F490991CF6F694F0B",
INIT_17 => X"F16F69710B71CEB18F670B71EF6F91094FCE918F690B4FF16F6B910971CE918F",
INIT_18 => X"7777777777EE086B8F6F6B0B0DAF93938D690B4DF16F6B910951CE918F670B6F",
INIT_19 => X"6F490991CF6F694D0B916C8A551199777777777799997799BB99BBBBBB777777",
INIT_1A => X"F16F69710B71CEB18F670B71EF6F69710B71CFAF6F490991CF6F696F0B91CFAD",
INIT_1B => X"779999BB99BB777777BBBB777799BB7777553311026F6B910951CE918F670B6F",
INIT_1C => X"232DADF1F1EF2F692FEECFEF252BADF1CFEF2D8B0FEECFEF2727CFF1CDEF2BAD",
INIT_1D => X"F3CD6F236FCFCFEF453169F1F3CD4F456FEFCFEF252F8BF1F1EF2F472FEFCFEF",
INIT_1E => X"AF4FCECDAB2F23EFF3ABAF25AF6FCFCD893125EFF3CD8F0000000000013147EF",
INIT_1F => X"EF2925CFF1CDEF2BAD2FEECDCD2B25CFF3ADCF29AF2FCECDCD2D23CFF3ABAF25",
INIT_20 => X"F1F1EF2F672FEECFEF252BADF1CFEF2D690FEECFEF2729CFF1CFEF2D8B0FEECD",
INIT_21 => X"2F672FEECFEF252BADF1CFEF2D69EECFEF452F69F1F1EF4F454FEFCFEF232D8D",
INIT_22 => X"7777BB777755EF8923AF6FCFCD89312F69F1F3CD4F454FEFCFEF252F8BF1F1EF",
INIT_23 => X"CFF1CDEF2BAD2FEECD22AA33551177555511777777997799BBBB99BB99779999",
INIT_24 => X"2F672FEECFEF252BADF1CFEF2D692FEECFEF2529AFF1CFEF2D8B0FEECDEF2727",
INIT_25 => X"77779999BB99BB9977995577779999777777775500454FEFCFEF252F8BF1F1EF",
INIT_26 => X"13EF530375332FD5D1CD05CE33EF330593334FB5D1CD07EE53EF1307B3137175",
INIT_27 => X"37B10F5773F1036C33EF910537910F3791EF038E33EF710355730F15B1EF05CE",
INIT_28 => X"33F1452C91B1CF0B13D1113533F1220000000001150000555511333344000001",
INIT_29 => X"F151EF1109D1139155F1890AD171EF110DD113D333F1670AB191EF0F11F11115",
INIT_2A => X"0375532FF5D1EF05CE33EF330593334FB5D1CD07CE33EF1307B3137175F1AB09",
INIT_2B => X"2FF5B1EF05CE13EF330575332FB5D1038E33EF710355730F15B1EF05AE13EF53",
INIT_2C => X"77779977777777AA3333F1232C91D1EF710357730F1791EF03AE13EF53035553",
INIT_2D => X"1309D1139155F18900EF551177777777557777777777BB773399BB99BB999933",
INIT_2E => X"2FF5B1EF05CE13EF330575332FB5D1CD07CE33EF3307B3137195F1AB09F153EF",
INIT_2F => X"7777BB99BB77BB3377777777999999BB33335577EF0491EF03AE13EF53035553",
INIT_30 => X"F18DEF538BEF51CFCD3392D1F18B1153691151CFCD33B3D1F1691373471371EF",
INIT_31 => X"AA452CCCAB2E32EFF1AFAB53CF8B51D1CD5354F1F1AFCD53ADCD51D1CD3374D1",
INIT_32 => X"EF8F34EFF1D145D3D127B1B189223355559911884477339999BB99BB999933AA",
INIT_33 => X"D1F1471391271371EFAD34D1D1F145F39125F391EFAF34F1D1D145F3D105F3B1",
INIT_34 => X"53ABEF51CFCD3392D1F18B11538B1151CFCD33B2D1F1691173491371CFCD34D1",
INIT_35 => X"51CFCD3392D1F18BEF538BF151CF5354F1F1AFCD53CDAD51D1CD3374D1F18DEF",
INIT_36 => X"779999BB3355555522EF8F34EFF1D1AFAB53CDAD51D1CD3374D1F18DEF53ADEF",
INIT_37 => X"1373271371EFAD0A335577555577BB9999557755777755779999BB9955777777",
INIT_38 => X"51CFCD3392D1F18BEF538BF151CFCD3392D1F1691173691151CFCD34D1D1F147",
INIT_39 => X"7777BB99BB9999557777777799997799335533551122CD3374D1F18DEF53ADEF",
INIT_3A => X"698FCD93D173F1938BF13191698DCF93D173F1758BD12FB16B6BEF93B173D175",
INIT_3B => X"000000000000004E6991AB93F191F1938FEF53716991CD93F173F1938DF15391",
INIT_3C => X"75AB930C8D9189B1F191B1912211BB9999BB7755779999BBBBBB99BBBBBB77BB",
INIT_3D => X"B16B6BEFB3B191D17589D10FB16D69D1B39191B175ABB30CAF8F69D1D191B1B1",
INIT_3E => X"73D173F1938BF15191698DCD93D173F1758BF131916B6DEF93B173D17589D10F",
INIT_3F => X"F1938BF15191698FCD93D173F195F1534F6991AB93F173F1938DEF5371698FCD",
INIT_40 => X"55777755557733332275CD930E8D9191AB93F171F1938FEF5371698FCD93D173",
INIT_41 => X"EFB3B191D175898F8A555555999999BB99997777777755777799997777775577",
INIT_42 => X"F1938BF15191698FCD93D173F1958BF13191696DEF93B173F17589D12FB16B6B",
INIT_43 => X"777777999955777755777777777777555577333333048FEF5371698FCD93D173",
INIT_44 => X"AD7573B12DADF1534555CF47AF9353B12BAFD1732553CF45AFB353B329D1B371",
INIT_45 => X"EEEECCCDEEEEEE04AB55B1B13169F1556933CC69AD7591B12F8DF1554735CC67",
INIT_46 => X"8F29ACB16755F17353458A22113399BB999977777799BB999999BBBBBBBBBB99",
INIT_47 => X"4591D1539327D1B3912571D14591D1537325D1938F278FD16773F1737325D175",
INIT_48 => X"D12DADF1534555CD47AF9353B12BAFD1732555CF45AFB353B329D1D1712573D1",
INIT_49 => X"F1534755CD47AD9353B12BAFD17355CC8BAB5591B12F8BF1554735CC69AD7573",
INIT_4A => X"1177557711337733228D2BACAF89555591B12F8BF1554735CC69AD7573B12FAD",
INIT_4B => X"539327D1B3912571CD6655775599BBBB99777777777777777777997733773377",
INIT_4C => X"F1534755CD47AD9353B12BAFD1734555CF45AFB353B129CFD1712573CF458FD1",
INIT_4D => X"777777997777775533557733775555551155775511224735CC69AD7573B12FAD",
INIT_4E => X"33EFEFEFEF35CCCF11F1931133EFCFEFEF37CDCD33F1750F33EFCFF1EF37CDCD",
INIT_4F => X"777777777777773344CFEFEFEF93ACEFEFF1D11313EFEFEFEF55ACEF11F1B311",
INIT_50 => X"CC13EF1771EFEFEFF1CC88EF5577779977777777777799BBBBBBBB99BBBBBB77",
INIT_51 => X"0F11EFCFF1EF37CDCC33F1372F11EFCFF1EF35CFCC33EF1751F1EFEFF1EF53EF",
INIT_52 => X"EFEF55CCCF11F1931133EFCFEFEF37CDCF33F1751133EFCFEFEF37CDCD33F155",
INIT_53 => X"CCEF11F1B31133EFCFEFEF37CCCFEED11313CFEFEFEF75ACEF11F1B11133EFEF",
INIT_54 => X"77331177555511AACDCC11EF1791EFCFEFEFEF73ACEF11F1D11333EFEFEFEF55",
INIT_55 => X"CFF1EF37CDCD33F1370C88771177119999777777117777BB1177773355557755",
INIT_56 => X"CCEF11F1B31133EFCFEFEF37CCCF11F1931133EFCFEFEF37CDCD33F1550F13EF",
INIT_57 => X"7777777777777733113355117733557711337755EF2211F1D11333EFEFEFEF55",
INIT_58 => X"EF7153CF73D12FB13325EF55CF7153D193D12F913327EF55D19153B1B1B14F73",
INIT_59 => X"7777777777777777770008CF55EF31D13305EF93D15371CF75D10FD13305EF75",
INIT_5A => X"332DCDF17353AF915522555511BB55775577777799BB7777999999BBBBBB7777",
INIT_5B => X"55B1AF53B1D1B16F533169F15591AF5393D1B18F532F8BF17571AF7375EF91AF",
INIT_5C => X"EF73D10FB13325EF55CF7153D193D12F913325EF55D19153D1B1D14F713147EF",
INIT_5D => X"0FB13305EF55CF7153D193D12F9105EF93D15371CF75D111D13305EF75EF7153",
INIT_5E => X"555577555555EE08CF330BCDD193535371CF55D111D13305EF75CF7171EF75D1",
INIT_5F => X"53B1D1B16F533169EF5589CC3377777777777777777777777777337755557733",
INIT_60 => X"0FB13305EF55CF7153D193D12F913325EF55D19153D1B3D14F713347EF55B1AF",
INIT_61 => X"BB7755775555335577775577331111775555111122D13305EF75CF7171EF75D1",
INIT_62 => X"4F69EF73B191ABAF738F11EF4F6BEF73B191CDAF73AF11CF4D8BF1919191CD8F",
INIT_63 => X"997777779999777777AA8851F171ADEF719111EF6F69CF73D171ABCF739111EF",
INIT_64 => X"6F73EFEFAF698D6666EE55333399555533777777999977779999BBBBBB997777",
INIT_65 => X"CF6D8BF1917191CD8F73CF11CF6B8DF1B17191CD6F73CFEFAF6B8DD1D1518FEF",
INIT_66 => X"73D191ABCF738F11EF4F69EF73B191ABAF73AF11CF4F8BEF919191CD8F73AF11",
INIT_67 => X"ABCF738F11EF4F69EF73B191ABAF8F11EF6F69CF73D171ABCF739111EF4F69EF",
INIT_68 => X"AA5555555555028FEF6F73EFEF8F6969CF73D171ABCF739111EF4F69CF73D171",
INIT_69 => X"F1917191CD8F73AF11CF6D888855555533335555777777775555771188888888",
INIT_6A => X"ABCF738F11EF4F69EF73B191ABAF73AF11CF4F8BEF719191CD8F73AF11CF4D8B",
INIT_6B => X"7777777733777733773333333355773333333388ABCF739111EF4F69CF73D171",
INIT_6C => X"D191D1D1CFF1358927EE2FCED191F1D1CFF133AD27CE2FEFCF73F1D1CFF131CF",
INIT_6D => X"99337777999977777777AAAFCCF155476BCF2DAFD1AFB3D1CDF1556749EF2DCF",
INIT_6E => X"F1496C4FEFCD44EF11773377777777337777777777779999779999BBBBBBBB77",
INIT_6F => X"EFCF55F1CFCFF12FD127AE2FEFCF55F1CFD1D12BF1278C2FEFCF55F1CFD1D329",
INIT_70 => X"D1CFF1358927EE2FCED191D1D1CFF1338B27CE2FCFCF73F1D1CFF131CF05AE2F",
INIT_71 => X"356929EE2DCFD191D1D1CFF1338BF12D8FD1AFB3D1CDF1556749EF2DAFD18FD1",
INIT_72 => X"0A4444444444CDB327D1694C4FEFCDAF93D1CDF155676BEF2DAFD18FD1D1CFF1",
INIT_73 => X"F1CFCFF12FCF27AE2FEFCF55AA44444422EF7777335577775577442805EF452A",
INIT_74 => X"356929EE2DCFD191D1D1CFF1338B27CE2FCECF73F1D1CFF131AD07CE2FEFCF53",
INIT_75 => X"777777775555335555333377775555555577448855676BEF2DAFD18FD1D1CFF1",
INIT_76 => X"EF474533B3D1D10BCDF1EF37CD69233373F1B109CDF1EF37ABAB035355F1B105",
INIT_77 => X"77777799BBBB331133553322D193F10F89EFEF75F1456713B1B3F10DABF1EF55",
INIT_78 => X"23EFEFD1754477557755337799BB9977557711557777557777BB99BBBBBB3377",
INIT_79 => X"37ABAD037355F19105EFEFF13789CD059137F17103EFEFF15567CF07B137F133",
INIT_7A => X"33B3D1D10DCDF1EF37CD67233393D1D109CDF1EF37CD8B035375F1B107EFEFEF",
INIT_7B => X"D10DABF1EF35EF67233393D1D10BCDEF73D1256711D1B3F10FABF1EF55EF4545",
INIT_7C => X"D15523CD07AE37F13323EFEFD19323236911D193F10F89EFEF55EF454513B3D1",
INIT_7D => X"037355F19105EFEFEF3789CD037135EF7102441133773355110015EF5323EFEF",
INIT_7E => X"D10DABF1EF35EF67233393D1D10BCDF1EF37CD89235375F1B107EFEFEF37ABAD",
INIT_7F => X"7755335577330000000000005555773355330089F10F89EFEF55EF454513B3D1",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000000000000000000000000000000003FFFFFFFFE0000000000000",
INITP_01 => X"00000000000000000000000001FFFFFFFFE0000000000000F806000000000000",
INITP_02 => X"0000000000FFFFFFFFE0000000000000C0000000000000000000000000000000",
INITP_03 => X"FFE8018018010010000000000000000000000000000000000000000000000000",
INITP_04 => X"0600600600600400400400C00C00600600600C00C00C00800800801800FFFFFF",
INITP_05 => X"0000000000800400000000800000000000000001007FFFFFFFC1001000000000",
INITP_06 => X"000000000000002002000000001FFFFFFF800000000000040040040000000000",
INITP_07 => X"00000000001FFFFFFF8000000000000000000000000001009001000000000000",
INITP_08 => X"1F80000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"00000000000000000000010010000000000000000000000000020020021FFFF0",
INITP_0A => X"000000000000002002004004004004004000000000007FE00000080080080080",
INITP_0B => X"00000000000000000000000000003F8000000000000000000002002002002002",
INITP_0C => X"0010000000000000020020020020020000000000000000000000000000000000",
INITP_0D => X"0000000000000000800800800800800800800000000000800801001001001001",
INITP_0E => X"0000000000000000000040040040000000020000000000000000080080000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53B1B153B1D1316953EF2BD15391B15391CF2F8B53CD2FCF7371B17371EF2FAD",
INIT_01 => X"7777779999BB551155555522CF91534571F127B353D19153D1B1336773EF29D1",
INIT_02 => X"D1736755B10477557755557799BB9999777711557777557777BB99BBBBBB3377",
INIT_03 => X"EF7173B17153CF2DAD53AB33CF9153B19153D12BAF738935D1B153B1B153B127",
INIT_04 => X"53B1D1316953EF2BD15391B15391CF318B53CD2FD17371B17371CF2F8D53AB31",
INIT_05 => X"316753EF2BD153B1B15391CF3169EF279353D19153D1B1534773EF29B153B1B1",
INIT_06 => X"55B1D15391D153B127B191455591CFCF9153D1B1534771EF29B153B19153B1D1",
INIT_07 => X"D17173CF2DAD53AB33CF9153B19153CF2BAF2F222222222206B153B129AF7367",
INIT_08 => X"316753EF2BD153B1B15391CF316953CD2DD15391B17371CF2F8B53CD31EF7173",
INIT_09 => X"7755335511EE222222220222EE1133EEEEEE22AB534771EF29B153B19153B1D1",
INIT_0A => X"F191B1EF6B51F171F1716F51F1B191CD6D51F191F16F7171D1D191CD6F71D191",
INIT_0B => X"7777555577775555773333224771F171CF916B73F171B1EF4971F171CF716D51",
INIT_0C => X"91D16975912CCC5533555599999999BB99997777777755777777999977777755",
INIT_0D => X"71D1D18FAB6F71D191F16D7371B1F1AFAB7171B191D16B759191F1AF89719191",
INIT_0E => X"EF6951F171F1716D51F1B1B1EF6B51F191F16F6F51D1B191CD6D71D191F16F73",
INIT_0F => X"F171EF716D51F191B1EF6B51F191716B73F173B1EF4971F171CF716B53F191B1",
INIT_10 => X"759171F1AF6771919191D16975B17373D1EF4971F171CF716B73F191B1EF6951",
INIT_11 => X"91CD6F71D191F16D7371B1F1AFAB7171B191F16B757191F1AF8971919191D16B",
INIT_12 => X"F171EF716D51F191B1EF6B51F191F1716F51D1B191CD6D71D191F16F7171D1D1",
INIT_13 => X"5577CCAA89884771D171D191030C680C89884971F171CF716B73F191B1EF6951",
INIT_14 => X"CCAF4F250BAFEF6E25B109AFCCAD4F2509AFEF4F258F09AFCFAD2F2707D1CF4F",
INIT_15 => X"5555117755771111557733220F6BF18C29AF0B6DCCCF4D250D8DEF6E27B10B8D",
INIT_16 => X"2F672D07CFD166AA3377779999BBBBBB77777777777777777777779977773333",
INIT_17 => X"D1CFAB2F2907D1CF4F456F07D1CF8B2D0905D1CF2F474F07CFCF8B2D0D05D1AF",
INIT_18 => X"250B8DEF6E25B109AFCCAF4F250BAFEF6F25AF09AFCDAD2F2709D1EF4F258F07",
INIT_19 => X"EF6E27B10BAFCCAF4F250BAFEF6FB10B6BCCCF6D250D6BEF6E27AF0B8DCCAF4F",
INIT_1A => X"07CFD18B2B0D05F1AF2F692D27CFD1D16D250D6BF18E29AF0B8DCCAF4F250D8D",
INIT_1B => X"2F2707D1CF4F456F07D1CFAB2D0905D1CF2F474F07CFCF8B2D0B05D1AF2F672D",
INIT_1C => X"EF6E27B10BAFCCAF4F250BAFEF6F25AF09AFCDAD2F2709CFEF4F258F07D1CFAB",
INIT_1D => X"444488CD6D250F49F18C2BAF0B6BCCD16D250D6BF18E29AF0B8DCCAF4F250D8D",
INIT_1E => X"030DAD3311EF0F6733EEEFEF030BCD33F1EF0D8933EEEFEF0507EF33EFEF0BAD",
INIT_1F => X"55551177337711113377332233EF2F2371F1EFEF230F893313EF0F4553F1EFEF",
INIT_20 => X"D151EEEFAB0F01883377777799BBBBBB77777777777777777777777777773333",
INIT_21 => X"EF0705F133EFEF09CD33EEEFCD0B03F133EFCF07CF33EEEFAB0D031133CDAF05",
INIT_22 => X"3311EF0F6733EEEFEF030BCD3311EF0D8933EEEFEF0507EF33EFEF0BAB13EEEF",
INIT_23 => X"0F4733EEEFEF030BCD3311EF0D69EEEFEF230F893313EF0F4551F1EFEF030DAB",
INIT_24 => X"EFAB0F031133CD8F03D171EFEF891111893313EF2F4551F1EFEF030FAB3311EF",
INIT_25 => X"F133EFEF0BCD33EEEFCD0903F133EFCF07CF33EEEFCD0D031133CDAF05CF51EE",
INIT_26 => X"0F4733EEEFEF030BCD3311EF0D6933EEEFEF0509CF33EFEF0BAB13EEEFEF0705",
INIT_27 => X"00000111673333EF2F2391D1EFEF2311893313EF2F4551F1EFEF030FAB3311EF",
INIT_28 => X"53EF730573532FF5D1AF09CF53EF5307915351B5F18F2BEF73CD53098F337173",
INIT_29 => X"77557733115555775511AA0555910F3591D107AF53EF710553710F15B1CF07CF",
INIT_2A => X"53F1274CB1D1AD2C221155557711777777777777337777BB9933775533337777",
INIT_2B => X"F173CD330BAF339173F16B2CD191CD310DAF33D353F1494CD1B1CD2F31AD3315",
INIT_2C => X"0573732FF5D1AF09CF53EF530771534FD5F1AF29EF73CD530991537193F18D2B",
INIT_2D => X"2FF5D1AF09CF53EF530771532FD5B107AF53EF710755710F15B1D107CF53EF73",
INIT_2E => X"4CB1D1AD2D33AD313553F1274C91F1EF910755710F15B1D107AF53EF71057373",
INIT_2F => X"330BAF339173F16B2AF191CD310DAF33B353F14B4CD1B1CD2F31AD33F353F127",
INIT_30 => X"2FF5D1AF09CF53EF530771532FD5F1AF29EF53EF530991535193F18D2BF173CD",
INIT_31 => X"058E73EF8F07558F0F3591D1078F53EF910755710F15B1D107AF53EF71057373",
INIT_32 => X"F171EF918FF191B189938F6FF16FEFB16DF191B169938D6FD18DF1B14D1191CF",
INIT_33 => X"33557755555555335588CCB1CF8FB191AB91918DF171CD91AFAF91918991916F",
INIT_34 => X"EF6B9389AF9389D1F10ACD553355557777553377777777777777775555335555",
INIT_35 => X"8FD18BF1B12D1191CF69938B8FB38BF1D12BF171EF69938B8FB389F1D10BF171",
INIT_36 => X"91AFD191B189918F6FF16FEF918DF191B189938D6FD18DF1B14D1191D169938B",
INIT_37 => X"919189918F6FF16FEF918DF191B191918DF171CD91CFAF91918991916DF171EF",
INIT_38 => X"89AF9389D1F12BF171CD6B938BAF9373CD91CFAF9191AB91916DF171EF91AFD1",
INIT_39 => X"11B12D1191CF69938B8FD18BF1D12B1171CF69938B8FB389F1D10BF171EF6B93",
INIT_3A => X"919189918F6FF16FEF918DF191B189938D6FF18DF1B16D1191D169938D6FD18B",
INIT_3B => X"938BCF73ABB1EF6DB191AB91918DF173CD91CFAF9191AB91916DF171EF91AFD1",
INIT_3C => X"458DCD55F153F195AFF115D3458BCD55F153F175AFD114F34769EF75D153F157",
INIT_3D => X"335577773333773377008955F191F1B393EF359245AFAB55F173F1B391F135B2",
INIT_3E => X"59CD7512ADAF45B3D1AE66331133335577551155557777777777777711117733",
INIT_3F => X"F16947F193D153F157CDB312D16B45D193D153F159CD9312CF8D45B1D1D173D1",
INIT_40 => X"55F153F195AFF115D3458BCD55F153F175AFD114F34769EF75D153F177CDB312",
INIT_41 => X"F193AFF135D3458BCD55F153F195F1359245AFAB55F173F1B391F135B2458DCD",
INIT_42 => X"12ADAF45B3D1B191D157EF55328BAFAF8955F173F1B391F135B2458DAB55F153",
INIT_43 => X"F175D153F157CDB312F16945D193D153F159CD9312CF8B45D1B3D173D159CD75",
INIT_44 => X"F193AFF135D3458BCD55F153F195AFD114D34769CF75F153F177CDD114F16747",
INIT_45 => X"375267B16755F191D1B373EF357245AF8955F173F1B391F135B2458DAB55F153",
INIT_46 => X"CF7553D10DCDF1532335ED23D19533D109CFD1710355ED23B1D533B107EFB38E",
INIT_47 => X"00000055555555333322B3D11169F1354715EA67CF5773D10FABF1354515EA45",
INIT_48 => X"AA09ACCF67351373332388117733771133337755775577775533557766000000",
INIT_49 => X"23B3F5339105F1938E0571EF239313337303F1758C078EEF455513535303F155",
INIT_4A => X"D10DADF1532335ED25D19533D10BCFD1712335ED23B1B533B107EFB38F0353EF",
INIT_4B => X"F1532337EB45D19553D10BCDD17335EA69CD5793D10F8BF1354515EA45CF7753",
INIT_4C => X"EF675513733323F1378A0BCACD67375793D10F89F1354515EA47CF7773D10DAD",
INIT_4D => X"33B105F1B38E0371EF2393F3339303F1958C058EEF457513535303F155AC09AC",
INIT_4E => X"F1532337EB45D19553D10BCDD1732335ED23D1B533B109EFD3710353EF23B1F5",
INIT_4F => X"E8ABAB37B3D11167F1376713EA89CD5793D10F89F1354515EA47CF7773D10DAD",
INIT_50 => X"33CFCFF1D155ACCFF3CDB31313CFCFF1F155AFCFF3CD931113EFAFF1F135AFAF",
INIT_51 => X"D1B38E220400220222AFCFEFD1938EEFD1CDD11313CFCFEFD1758EEFF3CDB313",
INIT_52 => X"AEF1EF3573D1EFCFD1F1734404022222683333551155557777333322CFAFEFEF",
INIT_53 => X"1111EFAFF1F155CFAFF3EF5531F1EFCFF1F155CFACF3EF3551D1EFCFD1F153EF",
INIT_54 => X"F1D175ACCFF3CDB31333CFCFF1F155AFCFF3CD931313EFAFF1F155AFAFF3CD75",
INIT_55 => X"ACCFF3CDB31333CFCFF1F155ADCFCDD11313CFCFEFD1938EEFD1CDD11333CFCF",
INIT_56 => X"3573D1EFCFD1F153EFAEF1EF3593CFCFCFEFD1938EEFD1CDD11313CFCFF1D175",
INIT_57 => X"AFF1F135CFAFF3EF5531F1EFCFF1F155CFACF3EF5551F1EFCFD1F153EFAEF1EF",
INIT_58 => X"ACCFF3CDB31333CFCFF1F155ADCFF3CD931313CFAFF1F155AFAFF3CD751111EF",
INIT_59 => X"F135F3AFEFEFD1B38EEFD1CDD11313CFCFEFD1938EEFD1CDD11313CFCFF1D175",
INIT_5A => X"CF8F91CFB19129D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714B91",
INIT_5B => X"93AF0BF1910BEFD1CF916FCF93AF0BF1910BEFB3CF918FCFB39109D19109EFB3",
INIT_5C => X"714FCFF1B1916DB193CF2DCF714DCFF14800331133773333558800D1CF916FCF",
INIT_5D => X"93CF6D91B1CF716B91716DF193AF6D91B1CF518D916F8DF1B3B16DB1B1CF4FAF",
INIT_5E => X"CFB19109D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714BB1914BEF",
INIT_5F => X"09D19109EFB3CF8F91CFB1912BB10BEFD1CF918FCFB39109D19109EFB3CF9191",
INIT_60 => X"F1B1916DB193CF4FCF714DCFF1B191918FCF93B10BF19109EFB3CF9191CFB191",
INIT_61 => X"91CFCF716B91716BF193AF6D91B1CF518D916F8DF1B3B16DB1B1CF4FAD914FAF",
INIT_62 => X"09D19109EFB3CF8F91CFB1912BB1912BEF93CF6F91CFB1714BB1914BEF93CF6F",
INIT_63 => X"EFD1CF916FCF93AF0BF1910BEFD1CF918FCF93B10BF19109EFB3CF9191CFB191",
INIT_64 => X"3167EF35B1B1EFAF35CF11CD2F69EF5591B1EF8F35CF11CD2F8BF17371D1EF6F",
INIT_65 => X"F171F1EF33B111EF5145EF55D171F1CF33B111EF3145EF55D191F1CF35D111CD",
INIT_66 => X"3175F1EF8F27CFB3D133F1EF3173F1EF6E0344222244222244AACDEF5125CF55",
INIT_67 => X"AD2DADF17351D1EF4F55EF11AD2BADD19353D1EF4F55EFEFAF29CFD1B133D1EF",
INIT_68 => X"35B1B1EFAF35CF11CD3169EF5591B1EF8F35CF11CD2F8BF15571D1EF6F35CF11",
INIT_69 => X"EFAF35CF11CD3169EF5591B1EF8FAF11EF3145EF55D191F1CF33D111CD3167EF",
INIT_6A => X"EF8F27CFB3D133F1EF3173F1EF6F2545EF55D191F1CF33D111CD3167EF35B1B1",
INIT_6B => X"F17351D1EF4F55EF11AD2BADD19351D1EF4F55EFEFAF29CFD1B133D1EF3175F1",
INIT_6C => X"EFAF35CF11CD3169EF5591B1EF8F35CF11CD2F89F15571D1EF6F35CF11CD2DAB",
INIT_6D => X"11EF5145EF55F171F1EF33B111EF3145EF55D191F1CF33D111CD3167EF35B1B1",
INIT_6E => X"F1B3D1F1CDF1158925CE0CCFF193D1EFCFF113AB23CE0EEFEF55F1EFEFF111EF",
INIT_6F => X"CCF15523ADCD0C6FF1D175F1CCF1374589CF0C8FF1B1B3F1CDF1176747EF0CAE",
INIT_70 => X"13474C2FEFEF37F1CCF19305F1692C2FF1EF35EFAAEF5303CDAB0C4FF1EF55F1",
INIT_71 => X"EFEF55EFEFEFF10FF1238E0FEFEF37F1CFEFD10B11256C0FEFEF37F1CDF1B307",
INIT_72 => X"F1CDF1156945EE0CCFF193D1EFCFF113AB23CE0EEFEF75F1EFEFF111CF03AE0E",
INIT_73 => X"156745EE0CCEF193D1EFCFF1138B110C8FF1D193F1CDF1374567EF0CAFF1B1D1",
INIT_74 => X"2FEFEF37F1CDF1930511672C2FEFEFD193F1CDF1374569EF0CAFF1B1B3F1CDF1",
INIT_75 => X"EFEFEFF10FEF238E0FEFEF37F1CFEFD10B11256C0FEFEF37F1CDF1B30711454C",
INIT_76 => X"156745EE0CCEF193D1EFCFF1138B25CE0ECFF173F1EFEFF111CD03AE0EEFEF55",
INIT_77 => X"0C6FF1D175F1CCF13723ABCD0C8FF1D193F1CDF1374569EF0CAFF1B1B3F1CDF1",
INIT_78 => X"AF69471393D1B10BAFEFCF55AF69453373F1B109AFEFCF55AD8D255355F19127",
INIT_79 => X"F155D10F69F1CD93B1458B11D173D10D8BF1CD75B1476913B1B3D10D8DEFCF55",
INIT_7A => X"45D1CDB37547AF0BD137F12F45F1CDB39345AD0DD135F10F47F1CDB393458D0F",
INIT_7B => X"558BAD257335F17125D1EFD1558BAF279137F15125D1EFD15567AF29B117F131",
INIT_7C => X"13B3D1B10BADEFCF55AF69453393D1B109AFEFCF55AD8B255355F19127D1EFD1",
INIT_7D => X"B10BADEFCF55AF69453393D1B109EFCD75B1476913D193D10D8DEFCF75AC4523",
INIT_7E => X"B17547AF29D137F13145F1CDB37345456911D193D10D8BEFCF75B1676713B3B1",
INIT_7F => X"255335F17125D1EFD1558BAF257137F17125D1EFD15569AF27B117F13125D1CD",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000700000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000F80000000",
INITP_03 => X"000000000000000000000000000000000000000F800000000000000000000000",
INITP_04 => X"00000000000000000000000F8000000000000000000000000000000000000000",
INITP_05 => X"8008008F80000000000000000010010010010010000000000000000000000000",
INITP_06 => X"0200000000000000000000000000000400400400000000000000000000000800",
INITP_07 => X"0000000000000100000000000000000010010000000000000000000700000000",
INITP_08 => X"0000000000004004004000000000000000000007000008008000000000000000",
INITP_09 => X"0010010010010000000000070000000000020020020000000000000000000000",
INITP_0A => X"0000000700400000000000000000000000000000800000000000000000000000",
INITP_0B => X"0000000401000000080000000000000000000020020000000000000000000000",
INITP_0C => X"000000007C000000000010000000000000001000000000000008020700000040",
INITP_0D => X"0000000000000000004000000000040000000007000010000000020000000000",
INITP_0E => X"000000000000000000000047000000000009FE80008000000000007FFF800000",
INITP_0F => X"00000007000000000087FF0000000000000000FFFFC600000000000000000000",
INIT_00 => X"B10BADEFCF55AF69453393D1B109AFEFCF55AD8B453375F19127D1EFD1558DAD",
INIT_01 => X"CD93B3458B11F175D10F69F1CD93B1456911D193D10D8BEFCF75B1676713B3B1",
INIT_02 => X"91CF7191AFCF918B91EF8DCF91AF7191AFCF8F6D91EF8FCFB1B171B1B1CF8F6F",
INIT_03 => X"CFB1918971F18BB191CF9191CFAF918B91F18BB191CF7191CFCF918B91EF8DCF",
INIT_04 => X"71B1AB93AFCF9171CF91AF8B71D18993AFCF9191CFB1B18971D189B1B1CF9191",
INIT_05 => X"CFB19171B191CF8D6F91CD91CFAF9171AF91CF8D6FB1AB93CFCF9171CF91CF8B",
INIT_06 => X"08CFCF918B91EF8DCF91AF7191AFCF916D91EF8FCFB1B171B1B1CF8F6D91CD91",
INIT_07 => X"918B91EF8DCF91AF7191AFCF918DEF8BB191CF7191CFAF918B91EF8B6A111110",
INIT_08 => X"93CFCF9171CF91AF8B71D18B93AFCFCF7191CFAF918B91EF8BCF91CF7191CFCF",
INIT_09 => X"71B1B1CF8F6F91CD91CFAF9171AF91CF8D6FB1AB93CFAF9171CF91CF8B6FB1AB",
INIT_0A => X"918B91EF8DCF91AF7191AFCF918D91EF8FCF91B17191B1CF8F6D91CD91CFB1B1",
INIT_0B => X"89B1B1CF9191CFB1918971F18BB191CF7191CFAF918B91EF8BCF91CF7191CFCF",
INIT_0C => X"F173D1EF2933F171EF312D33D193D1CD2B33D191F12F3133D1B1D1CD2F33B1B1",
INIT_0D => X"2333D153F1532537D155F1EF2533D153EF532735F155F1EF2733F173EF312B35",
INIT_0E => X"D1B127397155F1EF45339153D19125399155F1EF2533B153D1732537B135F1EF",
INIT_0F => X"33B1D1D1AB2F53B1B1F12B355193F1D189315191D1D129375173F1D167337173",
INIT_10 => X"762833F171EF312D33F193D1CD2B33D191F12F2F33D1B3D1CD2D33D191F12F33",
INIT_11 => X"F173EF312B33F193D1EF2B33D171532735F155F1EF2733F153EF334333FD26D8",
INIT_12 => X"397155F1EF45339153D1B12739915555F1EF2533F153EF532935F173D1EF2733",
INIT_13 => X"D1AB2F33B1B1F12D355193D1D189315191B1D12B375173F1D167337173D1B127",
INIT_14 => X"F173EF312B33F193D1EF2B33D171F1312F33D1B3D1CD2D33D191F12F3333B1D1",
INIT_15 => X"2537D135F1EF2533D153F1532737D155F1EF2533F153EF532935F173D1EF2733",
INIT_16 => X"CCCD2F030DADEF6C03CF09CDCCAD0F0509CFEF4E03AF07EFCDAB0F0707EFEF2E",
INIT_17 => X"1147F1AC0BCD0D67CCEF4B031169F18C07CF0D89CCCF2D030F8BEF8C05CF0BAD",
INIT_18 => X"0F472F03EFEF69090F23F1AC0D692F25CFEF6B071125F1AC0BAB0F45CDEF6B05",
INIT_19 => X"EFCDAB0F0705F1EF2F238F03EFCF890D0B03F1CD0F454F03EFEF890B0D03F1CD",
INIT_1A => X"DC00ADEF6C05D109CDCCCD2F030BCFEF4E03AF07CFCDAB0F0507EFEF4E03AF05",
INIT_1B => X"EF6C05D109CDCCCD2F030BCDEF6ED10D89CCCF4D030F8BEF8C07CF0A7724FF48",
INIT_1C => X"03EFEF690B0F03F1CD0D672F23CFEFCF4D030F89EF8C07CF0BABCCCF2D030DAD",
INIT_1D => X"0F0705F1EF2E238F05EFCF890D0903F1CF2F256F03EFEF890B0D03F1CD0F452F",
INIT_1E => X"EF6C05D109CDCCCD2F030BCDEF6E03CF07CFCDAB0F0509EFEF4E03AF05EFCDAB",
INIT_1F => X"0D47CDEF4B051167F18C09CD0D69CCCF4D030F89EF8C07CF0BABCCCF2D030DAD",
INIT_20 => X"052DADF1F3D10F8953EFCDEF072BAFF1F1D10D8B53EFCFEF0729D1F1F1B10DAD",
INIT_21 => X"F5CF2F4791D1CDEF273169F1F3CF0F6773F1CDEF052F8BF1F3CF0F6973EFCDEF",
INIT_22 => X"B173CDCF8B2F45F1F3EF7147B191CDCF693147F1F5EF5147B1B1CDCF473167F1",
INIT_23 => X"EF0927D1F1EFB12BAF53EFCFCD0B25D1F3EFB129AF73EFCFAD2D25D1F3EF9127",
INIT_24 => X"DC44D10F6953EFCDEF072BAFF1F1D10D8B53EFCFEF0729CFF1F1D10DAD53EFCF",
INIT_25 => X"4591D1CDEF273169F1F3CF2F6791F1CDEF052F8BF1F3CF0F6773EF887748D94A",
INIT_26 => X"CFAB2F45D1F3EF7147B191CDCF8B3145F1F5EF5147B1B1CDCF493167F1F5CF2F",
INIT_27 => X"D1F1EFB10BAF53EFCFCF0B25D1F3EFB129AF53EFCFCD2D25D1F3EF9129B173CD",
INIT_28 => X"0F6953EFCDEF052DAFF1F1D10D8B53EFCFEF072BAFF1F1D10DAD53EFCFEF0927",
INIT_29 => X"CDCF273169F1F3CF2F4791D1CDEF25318BF1F3CF0F6773F1CDEF052F8DF1F3D1",
INIT_2A => X"91CDB10B8FB12FF3F1714EF1B1ABB10D6DB351D1F1516EF1B1ABB32D6BB371B1",
INIT_2B => X"938B3133B1910CD1B1EF8D0D918D0F13D1912CD191CD8F0D918F0F13D1712EF1",
INIT_2C => X"91D10FB1D1F169717169711391B10CB1D1EF894F738B511391B10CD1B1EF8B2D",
INIT_2D => X"F1B189932F699391B1F12F8FF1D189934F6993B191D12FB1F1D16971716973F3",
INIT_2E => X"DC22B12FF3F1714EF191ABB10D8DB32FD3F1516EF1B1ABB32D6BB351B1F1518E",
INIT_2F => X"33B1910CD1B1EF8D2D918D2F13B1912CD191EF8F0D918F0F13D1710877FF90FC",
INIT_30 => X"B1D1F16971716971F391B10FB1D1F1694F7389511391B10CD1B1EF8B2D938B31",
INIT_31 => X"B32D6B9371B1F1518FF1D189934F6993B191F12FB1F1D16991516973D391D10F",
INIT_32 => X"0FF3F1714EF191CDB10D8DB12FD3F1514EF1B1ABB32D6DB351B1F1516EF1B189",
INIT_33 => X"0CD1B1EF8D2D938D3113B1910CD191EF8D0D918F0F13D1712EF191CD910B8FB1",
INIT_34 => X"F173EFD191D1B19145D18B2FD171EFD16FF1B1B145D1692FD191EFD14F1191D1",
INIT_35 => X"F151D153ABADAF29D155CDD1D191D15389AFAF2BF155EFD1B1B1D17367D1AD2D",
INIT_36 => X"EF67D1258F55CDEFF131F153CD69D1278F55CDD1F151F153CD8DD127CF55CDD1",
INIT_37 => X"4FB3AFEFF12F1191D145D1474F93AFEFF12FF171CF47D1456F75CDEFF111F153",
INIT_38 => X"668DD1B17145D18B2DF171EFD191F1B19145D1692FD191EFD14FF191B145D167",
INIT_39 => X"53ABADB129CF55CDD1D171D15389AFAF2BF155EFD1D1B1D17367D18D44FFFFFF",
INIT_3A => X"256F75CDEFF131F153CD69D1258F55CDD1F131F153CD8BD127AF55CDD1F151D1",
INIT_3B => X"EFD12F1191D145D1474FB3AFEFF12F1171CF47D1456F93CDEFF111F173EF67D1",
INIT_3C => X"B17167D18D2DF173EFD191F1B19145D18B2FD191EFD16FF1B1B145D1694FB3AF",
INIT_3D => X"D129CF55CDD1F171D15389AFAF29D155EFD1D191D17389CFAF2BF173EFD1B1D1",
INIT_3E => X"23ABCD37F133EF95D1D116F52389CD37F133F177D1D116134547EF55F133F159",
INIT_3F => X"EFB1D1D177EF177445CF6737EF91D1D395F117B423ADAB37EF53F1B3B3F117F4",
INIT_40 => X"3BEF5536ADCD2393D1D173F139EF373689CF4575F1B1B1F159EF175467CF4555",
INIT_41 => X"134745F175F133F139EF9316F16923D193F153F139EF7516EFAB23B3B3F153F1",
INIT_42 => X"00F153EF95D1F116F52389CD37F133EF77D1D116134567EF55F133F157EFB316",
INIT_43 => X"D157EF177445CF6737EF91D1D375F117B423CD8937EF73F1B3B3F117062251B7",
INIT_44 => X"16CDAD23B3D1D173F139EF3736ABCD2373F1D191F159EF175467CF4555F1B1D1",
INIT_45 => X"F175F133F139EF9316116723D193F133F139EF7516EF8B23B1B3F153F13BEF55",
INIT_46 => X"EFB5B1F116F42389CD37F133EF95D1D116132567CF55F133F157EFB316134545",
INIT_47 => X"177445CF6755EF91D1D175EF179423CD8937EF73F1B393F117D423ABAB37F153",
INIT_48 => X"F19573F12DAFD1714555ED25F1B553D12BAFD1914573EF05D3D553D129D1B18E",
INIT_49 => X"3169EF558933EA6BCF55B3D1316BEF556733EB49EF7593F12F8DEF536755ED27",
INIT_4A => X"AA2BCCB1695513915345D155AA2DEAAF8B55F3B15347F1558931EA8DAD55D3D1",
INIT_4B => X"05B3F353B127D1B3AC2791D1259313539125D193AC29AFD1477513717325D175",
INIT_4C => X"002DAFCF734555ED27F1B553D12BAFD1714553EF05D1D553D129D1B18F4573CF",
INIT_4D => X"558933EA6DCD55D3D13169EF558933EB6BEF7593F12F8BEF536755EB24209077",
INIT_4E => X"B1477513715345D155AA2DCAAF895513915347F155AB2FEA8DAD55F3D13167EF",
INIT_4F => X"53B127D1B1AE2791D125B313539125D193AC27AFD1279313737325D175AA29CC",
INIT_50 => X"EF734555ED27F19553F12BAFD1714553ED05D1D553D129D1D18F4573CF05D3F3",
INIT_51 => X"EA8DCD55D3D13169EF558933EA6BEF55B3F12F8BEF536735EB49F17573F12FAD",
INIT_52 => X"119191F1B3B371B19389D115F1B171F1B39371919389B315F1D171D1D1939191",
INIT_53 => X"73D171F17169F153F371B1F193D171F17369F133F391B1F193B371D17369D135",
INIT_54 => X"518FCD737391F1B193F173F1518DEF739371D1B193F171F1716BEF73D371D1D1",
INIT_55 => X"15D1D171D1F193917193AB9333D1F191B3F193B17191CD9353B1F19193F173D1",
INIT_56 => X"20B3B371B19389D11511B191F1B39371B19389B315F1D171D1D193919193ABB3",
INIT_57 => X"F1716BF153F371B1F193D171F17369F153F391B1F193B371D17369D12420B297",
INIT_58 => X"937391F1B193F173D1518FEF739391F1B193F171F1716DEF73B371D1D193D171",
INIT_59 => X"71D1D193917193ABB333D1F171B3F193B17191CD9353B1F191B3F173D1518FCD",
INIT_5A => X"71D19389D11511B191F1B39371B19389D115F1B171D1D19391919389B315F1D1",
INIT_5B => X"F153D371D1D193D171F17169F153F391B1F193B371D17369F135119191F1B3B3",
INIT_5C => X"57F3D1F18DCDB151D12FEFD151CF132793539191AFAFB0D1CD73C5CF2FF191B1",
INIT_5D => X"D1CD33CC11EDEE8BCD05CFCD3389AFF1D1034ECFF1138F536FB1ACAC2ACDEFAF",
INIT_5E => X"17B3D155D1D1F113D1EF8BCDAF71D1F1F137548BAF6775F19391F139B1058FB1",
INIT_5F => X"11F155D19133F1F133AF67F18F73F1AF8B53F1CFF3079155B393F1D1F333F1F1",
INIT_60 => X"00D17536ADAFABB3B3CF6F33D17353D16DB1AF2B1553F1D1470955D1D113AB67",
INIT_61 => X"CC8D8B55F1473191D1B12B13110BAD51CF53CFCE3327110551D1ABCD0200D177",
INIT_62 => X"EF09B155CFD1F173F1D17133D17135F1F1D1AF935327CF314773B1958B17EF55",
INIT_63 => X"D1B18FF191B133ABCD2793D1AF69EF537113F11145576931B171EF71F18E0DAB",
INIT_64 => X"D1F131AD9337F1F127EF7133B17333AD8ED1D19333F169EF5373AF0DCDB1F1F1",
INIT_65 => X"EFF1F1D193D1D1EF3353F32555F155AF69CF3711055151CDD19355D1D1F153CC",
INIT_66 => X"F11111335555EFEE2FCD6733CCE92D2E4EACEE51D131EF171191EF13AF134C45",
INIT_67 => X"33B1B1018C15CF7133D17337EF7311D17333CD6733F1CDEFEFF10353EFEFEFEE",
INIT_68 => X"F1EF55CF6755EE13053391D115ADF1110DCACD8937B1911323EF37CC53CF53F1",
INIT_69 => X"D10F891567F1239305EF6FAC3389CD5195D1D19B255711F1F1CDFD677623B1D1",
INIT_6A => X"0009ACCF6735F1713323EF88F1EF23CD89EF2C11CCCCCC035371CF4551ACB350",
INIT_6B => X"F17357F1B116EFEFEF2391D123EFF1CD89ACD193F1EF7592F50913B104209177",
INIT_6C => X"177445CF6755EFCD37CD67F1CCF1F13371AC33F1CF3373CFF3B1EFB1AFEF07B1",
INIT_6D => X"035345EF71F1EFEF351147EF37EF338C91F1AF13CFAD89F1F147EFCD55F1EFEF",
INIT_6E => X"EF13B1F1916BF16F33D173F1AE73F15189AA35CDEF4571F1EFEFEFEFEFEF4F55",
INIT_6F => X"2FB38E37EEEF1167F1F191CFCD0BD1D19137F1730CEFF1EF4551CF455103F155",
INIT_70 => X"5555BB99BB997733335391CFB18FEFCF69AF118B054F716ACD6931CF73ADB131",
INIT_71 => X"AD71EFF371EFCD69D1458BAF256EEFEF6EB1F171F18B8F55CD33557777131B77",
INIT_72 => X"558FB1F171EFD1CF0F53EFD1CD2B8EF1CFEF35B3CFEFEFD1D193EFAF690DD1D1",
INIT_73 => X"EFD167D1B1D153AFF13995D133B5F113111135115535115711F1CDF3D1F1F3CD",
INIT_74 => X"40F1EF3573D1EFEFD1F17155536FB151CF45AD2D07CD2DD1D191EF71EFCD2FAD",
INIT_75 => X"53CFCC3189D1276F55CDF147332D11D1B155AB8B512991CF270F53CF44209397",
INIT_76 => X"CD8DF055D3D13189D1D1714FB16FD1D1EFEFCF4FB155EFEE55EF33AD2FEF7167",
INIT_77 => X"EFD173D1CD33F173F125B351AA6BF1CDF151CD6931D135CF5373F17327EF2F31",
INIT_78 => X"F1D1CDAA89D1EFEFEF53F153D18933F171B1EF6FF15171F14F73CF75D14DD1D1",
INIT_79 => X"D1ABCDCFB18EF133AFD18931D171EF71CFCC318BEF0D8F55EFCF2553EFF331EF",
INIT_7A => X"999999BB99BBBBBB7711D1EFD333338F7171CF716FD1AF91CD6DCC498F05CFCF",
INIT_7B => X"CDCF696FF16F0BD1B3F1B19389AFCF6F679169AF712D6DEF3355999999777777",
INIT_7C => X"F1B18EF173CF918D93EFAD9393AF91CF4DEFF1D16F71AD93D12BEF916FAB6D6F",
INIT_7D => X"ACB39191B193F15113EFAFB59315355977BD9FBB997D3355F3D1ABB3AF49F52D",
INIT_7E => X"204DCFF1B38F71AD93EFCD7369B191738DF1916B9175D19193B1CF6FAD0B6BF1",
INIT_7F => X"73CFCF716D71D36D738B7393CF93918FB1F1AD71EF91CD913593F1AF44206E97",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0097FFE0000000000000007FFFFF000000000000000000000000000000000000",
INITP_01 => X"8001FF7FFFFF8100000000000000000000000000003DE0000000000700028000",
INITP_02 => X"000000010000000000002000806EFF000000000700280000001FFFFF00000000",
INITP_03 => X"CC000000007FFFC0000000070012EF400CFFFFFFE00000000401FFFFFFFFF000",
INITP_04 => X"0001CE273FFE5FFC0CFFFFFFFC000000000FFFFFFFFFF08033800000000019F1",
INITP_05 => X"BFFFFFFFFE20004004AFFBFFFFFFD600FFC00000000C37FC4200000100FFFFC0",
INITP_06 => X"FE9FF7FFFFFFFE00FFC0004000072FFF73F3800007FFFFC00003FFF77FFF17FC",
INITP_07 => X"FFE4000010867FFFFF9418A467FFFFF1F077FFF77FFF9FFF3FFFFFFFFFEC0008",
INITP_08 => X"FF764FFFFFFFFFFCF87FFFF77FFFFFFFFFFFFFFFFFFC021B1FFAFFFFFFFFFC00",
INITP_09 => X"7F7FFFF77FFFFFFFFFFFFFFFFFFD007F7FBA7FFFFFFFF880FFFA001004DFFFFF",
INITP_0A => X"FFFFFFFFFFFEF7B4FFEFCFFFFFFFF800FFFE0900817FFFFFFFF71FFFFFFFFFFD",
INITP_0B => X"FFBFBFFFFFFFFE00FFFF484C1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_0C => X"FFFFE93B7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFEFFFFFFFFDFECE",
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFF7DBAFFFFBFFEFFBDD20",
INITP_0E => X"FFFFFFF77FFFFFFFFFFFFBFFFFFFFFF7E9FFFCFFFFFFFF80FFFFF4E7FFFFFFFF",
INITP_0F => X"FFFFFFFFFFFFFEDF6B7FF7FFFBFF7F80FFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_00 => X"F153D371ADEF93CD8FEFCFF1B1CD93AFCF71B3AB8FAE9167EF91CF936B71AFD1",
INIT_01 => X"F1AF9191AFCF93B173F1B191F19173AB71CF0F736991B35391AF93EF8F71D16B",
INIT_02 => X"73937369B3B1F1B191F191EF71B191EFD191676D71CF8F7169CF73D173CF9391",
INIT_03 => X"936BF18DB18FEFEFAD918F69718DCFB38F6973D18FAD93F1514EF1B189B32D6B",
INIT_04 => X"9999BB99BBBBBB999977773377557733F1EF336EEF51CC332FCE558F91CD71EE",
INIT_05 => X"23B3AF35B1D0F129D14FB1D12F91D131F5EFD1B3D1D1F1F1F959779977337777",
INIT_06 => X"F1D1EF35CF55F133AF5593D1D1CFF1D193F1EF7125AF73F153EFEF2F8FEF7573",
INIT_07 => X"35B1B1F1F1D1F17511F1FD35F377BBDDFFFFFFFFFFFFDD99771733D1F1D137B1",
INIT_08 => X"0275F1EF8F25D1B3D1312FAFF1F311F11155F1F1F1D1F1F1AD8953AF758C4FCD",
INIT_09 => X"B129D1AFF1EF318DF1F1F1CFEFD1CDCFD155AE91EF8F8FF1B38F55D106208E77",
INIT_0A => X"EFF1CDB16FCDD1EF554511333311EF11113711EFD5F1F1F1D5D153F1CF13F1F1",
INIT_0B => X"AD73D1AD73F127EFAFF191B1CD89D1CF71F1D1D1CD33F1D1CDEFD17371D1CF2D",
INIT_0C => X"D1B1B1F1F157F173D153EFEFEFF1D1CD8955D191ACF1F1AFD191D1CDF1EE2F31",
INIT_0D => X"CF4F75F1F145EFB1D1AD73CD33F1EF07912FD191D1F15125D1692FB18FEFAF0D",
INIT_0E => X"777799BB99BBBBBB77777777777777773331F1EF2FB10913CFCD034E450FAB0F",
INIT_0F => X"1351EFF1EF310C73EFEF91D1CD69F1111377553333117733F133777777777777",
INIT_10 => X"37AFF1ACEFF1EFCDEFD171F12B91D113892C29F1EF55F1CCF17503EFF1EF89EF",
INIT_11 => X"6A55EF1509D137F133F1F17711BBBBFFFFFFFFFFFFFFFFFFFFBB99BB33BB3511",
INIT_12 => X"20474C29EFEF37CDCCF11139359DD137F5F1F593F115EC235375F1EFEFEFABCD",
INIT_13 => X"EFEF53EF0BCDD17531D16F37D19137D193F1EF67CF55F1EFABEFF15144207677",
INIT_14 => X"11CD3123EF35EF71F15719D7113B79FD17111D99791F151DF3F3F1B117CF4F55",
INIT_15 => X"23D38C23B3D1338911EFCC2333B5D133F137117513B113AC5575F1F1F123B3B1",
INIT_16 => X"F151F13B918EEF8951EF71D113AB31D191EF45EE035375EF454713B10713EFF1",
INIT_17 => X"EFB3B309733333EE2EEF7315D16E35EFEFEF45CCEF53CDEFD377EF4545F17711",
INIT_18 => X"99999999BBBB997777BB7777BB99777755113311ACEF918C2E8DD1D191F173D1",
INIT_19 => X"4FB3AF316911CFB3B145F153D1914F1155BBBB99775555337755335577779999",
INIT_1A => X"33111157AD33D1518C45F1D1CDF153D1F1D1D17145AF2DF155CF53D1334FB191",
INIT_1B => X"05B3B3CD1133D1EF133399BB9957BBDDFFFFFFFFFFFFFFFFFFFFFFFFFFDDBB55",
INIT_1C => X"00D1F1F19567EF4BD1359113F3F111F3131111F557337757F311F1736FEF6CCD",
INIT_1D => X"55AFCFEF91CFEFCFCD51CFEFAC89AB4FEF4BD1B355678F2FD1CC45CD2420CE97",
INIT_1E => X"2C71F1F151CFF1D3F11357BB999999DDDD5FBB3BBD99BB331155D7F1EFD1CFEF",
INIT_1F => X"1511F1551111F175F15391B1CF9125CDEFCD53F1F1ADEFEF49AFEF6D71F531CD",
INIT_20 => X"D1B1B3AC9153F173EF55EFEFD193F1CD93F1531115F3D3131357151BF3F38911",
INIT_21 => X"F1891111F1EF13111155F1F1AFF1F1330BD15393ADCF712553CF05F4D353AF27",
INIT_22 => X"777755BB99BBBB55777777779999775555553333B3F1D18F114B91CF91EF6F91",
INIT_23 => X"F19193F1B1F18FEFB173D1931155555555775577555539797777557777557777",
INIT_24 => X"BB99BB775933CF7593F1D1930D8DCD917191EF8FF1936DEF718D6FCD6DF191B1",
INIT_25 => X"91EF91CD151393F13BBB997D3537BBFFFFFFDDFFFFFFDDDDFFFFFFFFFFFFBB99",
INIT_26 => X"02B7153317191137177759553B3539B3F5137315193559777B7711551111D10F",
INIT_27 => X"716BD1516D8F8BAFAD71AFCF91EFAB113355F7B5351133F1B9B7118F2820B177",
INIT_28 => X"F175F189D191F9B5571F9D9B7FFF9FFFDDFFBBDD7DDDDD7D7715F7D3CF936FCF",
INIT_29 => X"9713F7F5D1F711F3F1F1B19389CD91AD8FEFF12DEF718DEF4DB1F171CD0EAE11",
INIT_2A => X"93CDB3EFAFEF71D1CFF1B3F31113F1B1D3F13317B577999FBDBD9F793B5BF7F9",
INIT_2B => X"5BBB3999577717117711D3F19371F1757371CFD18991AF9389B315F1CF91D1F1",
INIT_2C => X"77777799BB99997733777777777777775555F533F7111155CCCE53EF71EF9131",
INIT_2D => X"F1D1D1F1D74F359311D111D133551B557777777713F9355599BBBB9999777777",
INIT_2E => X"BBBBFFDDDD7733F3F1551147F36FF145EF55CD93F1F1F155D111AFEFF1EFF171",
INIT_2F => X"11EF1113391B9999BBBBBB3599BBFFDDFFFFFFFFDDFFDDBBDDFFDDFFDDDDFFBB",
INIT_30 => X"4219111D3B7D99BDDFDDFFFFFFDDBD77B5F1B513F399DDFFFFDD99591511F9D1",
INIT_31 => X"D1EF53D1EFD1AF9367D18FCE57FB573D5DBBDF9BBB9D5B771515111944209397",
INIT_32 => X"458D2FF1951115993FDFFFFFBDFFDFFF9FBDFFBB9DDDBB9B5535F3EFEF45CFEF",
INIT_33 => X"F9151511FBF511331B111333AF9311111355F1ADEF47F1EFD1D153D1EFCF91D1",
INIT_34 => X"F171752571EFD1ABF153F1F1D5171135D5F11DF599FFFFFFFFFFFFFFDFDF9B9B",
INIT_35 => X"FFFFDFFFFFFFDDBB3D99EFCD45D1EFD1F1D1EF75F151EFD14D11D1CD71D1CFCD",
INIT_36 => X"7733777799337777777777557777555577113533353311F1138EEF4DCD2FEFEE",
INIT_37 => X"11333333111133F133F1F777555511331177771BF11377BBBBBB99BB77777777",
INIT_38 => X"BBDDDDFFDDDDBB55111155FB111137F393F1EF6711CD0DF1D1B1F1D915F155F1",
INIT_39 => X"EFEF3377579999BB333FBBBBBBBBBBFFDDDDDDDDBBDDBBBBBBDDBBDDFFDD9D7B",
INIT_3A => X"405577BDBBFFDDFFFFFFFFFFFFFFFFFF33FDF13755BBDDDDDDDDFFFFBBBB7955",
INIT_3B => X"11193311F3F1F1F7F3331111F1351FFFFFFFFFFFFFFFFFFFFFFFBB3388409177",
INIT_3C => X"F13D1DF1FF591F5BDFDDFFFF99FFFF3FFF999D7DBBBBDD3FBB77BB11FBF1F71B",
INIT_3D => X"BB993F1D111D1D1133D37911D71337D193F1573311FBD5F1337915F3F311FBFB",
INIT_3E => X"F1F1F133F155CCF713F1F3F1F1111DFFF51D33BBFFFFFFFFFFFFFFFFFFFFFFDD",
INIT_3F => X"FFFFFFFFFFFFFFFFFFBB7DF3F117F133730555F1EFADAB37EF67AC0FABF15553",
INIT_40 => X"77997777777755353355557733553311555511353311F52565D1CCB1CF8C6FCF",
INIT_41 => X"F5B3F513191177333333331333CF11F5351B33333377557777BBBB7777777777",
INIT_42 => X"BBDDDDFFFFDDDDBBBBBB99BB5533D1EFCFD1D1D3F17511F1F175F11133F13333",
INIT_43 => X"3333331399BB1D35BB9955339D7D9B595599359B99BBBBBBDDBBBBBBBBFFDDBB",
INIT_44 => X"00353D33FFDDFFFFFFDDFFFFFFFFFFDF5B11115755DD7DBDBBDDBBFFDD99DD99",
INIT_45 => X"33131B5719D5F5F5F51B175BBD9FBBFFFFFFDDFFFFFFDDFFFFFFFFFF88204E97",
INIT_46 => X"3313131B3333BD5D99DDDFBBFFDDBBBBBB559DDD3FBDBD9DBBBB5F99131BF3F3",
INIT_47 => X"FFFFFFDDFF5533177D111533F31713F9F133F3F9131313111D351D33331D3333",
INIT_48 => X"4BD1AF55EF11B133131BF11D153F799977DDDDFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFDD33F537EFEF53CD8FF1739525CF2FD111758BCFD1",
INIT_4A => X"339955777777333777333733131755351317131513B5B3F10F8FEF8F8F91AF8F",
INIT_4B => X"933355173333111313F5111533F33393D3333315135533555577777777777777",
INIT_4C => X"BBDDDDFFDDBBDDBBBB7777997755D733F393F1D3F3EFF3F1F333333311151133",
INIT_4D => X"BB9D575B7B35993735197B777D9977179977BB7B77BB7799799DBBBBBBBB55BB",
INIT_4E => X"429B57DDDDDDFFDDFFFFFFFFFFFFFFFFFF779B9BDD9FBBBBBB99BBBBDDBBDDDD",
INIT_4F => X"F55977997B777D55B713377DDDFFDDFFFFFFDFDFFFDDDDDDFFDDDDDD88207277",
INIT_50 => X"BD5D3D5537559955775F9DBB777777BD597F7D99BBBD9D7DBDBFFFFF7D13B711",
INIT_51 => X"FFFFFFFFFFFFFFBF77571919F5371757F7F9F73519373D557B7BDDFFFFDDDD7D",
INIT_52 => X"11EF71F1B3F5B315F71979DD7DFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF7B3BEFAFF7F1F311F1F111F1F193EFEF8BB7D5",
INIT_54 => X"77777777775511773D335755333555773335331911D1F1334D73F1EFCEEFEECD",
INIT_55 => X"3333771337133333113533F7111177331111F5F1331315553355557755337777",
INIT_56 => X"99DDDDDDDDFFBBBBBB1F1777331577F733331135F133133333F5111DF31DD3F5",
INIT_57 => X"BBBDBBBB3599333B119B399BBB553D557733BBBB33BB993D5779FFDDBBBB7755",
INIT_58 => X"227FBBDDBB99DDFFFFFFFFFFFFFFFFFFFFFFFF99BBBDDD33BBBB335DBBFFDDFF",
INIT_59 => X"1399DDFFFFFFFF9F9B1179DD99FFFFFFFFDDFFDF9B5FFFFFFFFFDDDD8820B097",
INIT_5A => X"BB997B3D991D793B99797D791D5B9B35BD9DBB5DBD5FBB3FDDFFFFFF5F113519",
INIT_5B => X"FFFFFFFFFFFFFFFF5FBB5B9D1D791D797779773B9DBBBDFFFFFFFFFFFFFFFFBD",
INIT_5C => X"F1D5D11115111D779B9DDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFDDFFFFFFFFFFFFFFFFFFFFFFFFDF55F159F1D311D5F5F1F113F1F51911AF33",
INIT_5E => X"77773355331D33333311331D5555331339333311113311F1EFF133ABABEF45EE",
INIT_5F => X"111535555511333935F11735113333553BF11133333333353D33113333775555",
INIT_60 => X"779999BBBBDD99BB557717791119F13519131155331339311D11F1F1113511F7",
INIT_61 => X"FFFFDDBBBB9911551D9955FB1117791317771F7DBB1B55777777BBDDBBBD3DBB",
INIT_62 => X"22BDBBFFFF3FBBDDDDDDFFFFFFFFFFFFFFFFFFBBBBBBBBBBBB99BB9999FF99FF",
INIT_63 => X"1D333F99FFFFFFFFDDFF7DDFFFDDDDFFFFFFFFFFDDBDFFFFFFFFFFDD8C00D177",
INIT_64 => X"BBBB33BD19991F77773F7777BD9BBBDF7DBD3FBDBBBDBBBDDDDDFFFFFFFFFF33",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDF9FFF3FFFFFFFFFFFFFFFFFFFFFDDDDDD",
INIT_66 => X"EF11111D179DBD7FFFDF7FDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"DDBBFFFFFFFFFFFFFFFFFFFFFFFFFFFF551D59F511F3F311F3F3331111D73313",
INIT_68 => X"557777FD173311555577771111F93533331177335515D53333B111F173F1B327",
INIT_69 => X"11F555F1151D131311333313353977997777773913D5131133111D3557555533",
INIT_6A => X"BBBB999977777755995533331B33335733331D155733331B3333F91115713333",
INIT_6B => X"BDFFDDBB9D593D39BD1155773357131B551D9933777955991533BBBBBBBB99BB",
INIT_6C => X"22BBDDDDFFDDBB7DDFBBBBBBBBDDFFFFFFFFDDBB3FDD993D99799955779DDDBB",
INIT_6D => X"999999DDFFFFFFFFFFDD77BBDDFFFFFFFFFFDDFFDDDDFFFFFFFF5FFF88209177",
INIT_6E => X"BD5FBD3FBBBB33BDFF357DDDFFDDDDBDDDBBDDDD5FFFBDFFDDDDFFFFFFFFDF5F",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFDDFFFFDDFFDDDDDDFFFFFFFFFFDDFFFFFFDD7FBD5FBB",
INIT_70 => X"1D159DDDDDFFFFFFFFDDBBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"DDFFDDFFFFFFFFFFFFFFFFFFFFFFFFFF57551113D555D5F11B131BD5D5351513",
INIT_72 => X"3B33553333113515553355173333333515333315335533314FB5F1D1CFF1B1B5",
INIT_73 => X"333333F33797F713331315393333779977553B115533F3F13355331133393757",
INIT_74 => X"BBBBBB997777353B5733553B33373315331917113313173313351113F5791333",
INIT_75 => X"7DDDDDBBBB77795B33555757351977331733353D35F5371317337777BBBBBBBB",
INIT_76 => X"62DDFFDDDDDD7DBB5D77773B3B3757BB99BBDDDD77779999573D557B575B99DD",
INIT_77 => X"7FBDDF7FFFFFFFFFFFFFDDBBFFDD7FFFFFFFFFFFDDDDBDDDBDBDDDFF88209197",
INIT_78 => X"5DBB7DBD5B5DBD5D9B7D9977577BBB39DDBBDDDDBBDFDFDDFFDDFFDDFFDFBFFF",
INIT_79 => X"DDFFDDFFDDDDFFDDDDFFDDFFFFFF9FFFDDFFFFFFFFFFFF7FDFBDDDBFBDDDDDDD",
INIT_7A => X"3B99FFFFFFFFFFFF7F5B7BBDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDDDFF",
INIT_7B => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFF9D77353519F7F7351713553933391117",
INIT_7C => X"35111B1115FB11331B115557113333119535331333151D110FD1F1EF73F1B1B3",
INIT_7D => X"F91111D511F53311F53355117755197777551333773333331313113311135513",
INIT_7E => X"BBBB99BB55BB77591B573B131135111B771315171D1313F95533F91133133333",
INIT_7F => X"99BBDDBB7D35BB793D995B355535333D3511551355113511195533779933FF99",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"9F17F1E5DFFFFFC0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFEFDFFFFFFF7FF",
INITP_02 => X"FFFFFFFFFC73FFFFFFFFFFF77FFFFFFFFFFFFF7FFFFFFFA6F7F7CEFFFFFFD6DF",
INITP_03 => X"FFFFFFF77FFFFFEFFFFFFECFFF7FFFFBFEEFEFFBDFFFFF61FFFFFFFFFFFFFFFF",
INITP_04 => X"FFFFFFCFFFFFFBFEBFFD9CDBEFFFFF41FFFFFFFFFFFFFFFFFFFFFFFFB24FFFFF",
INITP_05 => X"DFDED7FFFFFFFD20FFFFFFFFFFFFFFFFFFFFFFFCF409FFFFFFFFEFF77FFFFE3F",
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFD8580FFFFFFFDBFF77FFFFF2FFFFE7FF7FFFFF47E",
INITP_07 => X"FFFFFFFD6001BFFFFFFFFFF77FF7C157FFBDF7BFFFFFDFF8FFFD4957FDFEFF7F",
INITP_08 => X"FFFDC9F77FDFB447FFFD95DFFFFDCFB7FFF9F431F777FF6BEBFFFEFFFFDFBFFF",
INITP_09 => X"FFFBB2B3DFEFFDDFFFF9F5813FD7FFFFFFFFFFFAFFEEBFFFFFFFFFFE00005FFF",
INITP_0A => X"FFF7BDE4E5FFDF81FFFFFFFED7EAAFFFFFFFFFF8A00029FFFFFFAAF77FD6B207",
INITP_0B => X"FFFFFFFFEF5231FFFFBFFFFC0000FBFDFFFFBE475FFE9150F3787E073FD7D7FF",
INITP_0C => X"FFFFFFF80000000BFFE029071825400F00A78467FFFFFFFFFFDFC71FFFAFFDDE",
INITP_0D => X"14A9A3670000002088D0491DFFFFFFFFFFFC78C1BDCB3C14FFFFFFFFFFC16BCF",
INITP_0E => X"00190B07FFFFFFFBFFFC06FDD57D7FD5FFFFFFFFFF9129A7DFFFFF8000000000",
INITP_0F => X"E77DE3975EE5FE57FFFFFFE7FFB90823FFFFF800000000000000000700000000",
INIT_00 => X"22DDBBDDDDBB9DBB799B5B157979993FBB335F7F9B3D1933551313793577593F",
INIT_01 => X"9DBBFFDFFFFFDDFFBBBD7FBB99BB79DDFFFFFFFFDDDDBB3399BBDDDD88204E97",
INIT_02 => X"9D9999339B9D3B79995955999B5D7999553D55DDBBBBBBFF5FDD5FFFFFDDFFDD",
INIT_03 => X"BBBBBB55BBBBDDBBFFDDFFFFFFDDDFBBDDDDDDBBFFDF9DDFFFDD99DDDD999D9D",
INIT_04 => X"15DD5FDDFFFFBD3B9B9B57BD5FFFDDFFFFFFFFFFFFFFFFFFFFFFFFDD99335FDD",
INIT_05 => X"DDDDFFDDDDDDDDFFFFFFFFFFFFFFFFFF9FBDBB99131335795B5977177B113B9B",
INIT_06 => X"7733F1557735557755353B777755115533331155557735333311F153F133F1EF",
INIT_07 => X"11D5D11133111F19F1F1F533FB33111119133311F1F3F333773377BDF511F733",
INIT_08 => X"99BBBB115B797777357733777917337755555733EF7777351133115533111B11",
INIT_09 => X"BBBBBB133DBB793D1399559911551DF1331F77771135F5333311771B55BB5599",
INIT_0A => X"2299FFBBBBFF33771D773577131911BB55BB99771179337733331D111B113599",
INIT_0B => X"BB7D9DFFDDFFDF5FBBBB55BB1D5511DDFFDDDD55BB77191F77BB99FF88408E77",
INIT_0C => X"1F5B79BB3B33773377131977115577137DBDBB5577DDDDDDDDFFFFFFFFFFBF9D",
INIT_0D => X"1F551D99999999DD99BB7DBD99DD99BB7FBDFFDD3FFFFFFF99DD1FBB99BBBD33",
INIT_0E => X"BB5B5B997D157755BB137F3FFF9FBDFFFFFF5FFFFFFFFFFFFFFFFFFFFFFFBD33",
INIT_0F => X"BBDDFFDDFF99BBDDDDFFFFFFFFFFDDFF57773FBBBBFFDDDDFF5F793D79BB7911",
INIT_10 => X"1D115733111B337733BB7777777777773535F933F71111571933551115113311",
INIT_11 => X"55131135F533331311773357EF1333553311D5F7111133F73335133333331335",
INIT_12 => X"99775577555577797955353D1135111B57331555771B351157F53557F73511D5",
INIT_13 => X"997999BBBB993D77771F3B773D3313773B13131D15551933D5331B3377593577",
INIT_14 => X"42BF9DDD7B35DF7911135D1B99993F157D1D339B991117131B13331333775555",
INIT_15 => X"FFFFFFDDFFFFFFFFDDDDFF5599BB995977995755793D9B33991979BB66207477",
INIT_16 => X"115755551137F1F5FB11331BF1F559113359557999999B99DDBBDDDFDDFFBBFF",
INIT_17 => X"999B9B335B5B3F9B9BBD7DDD5FBBBBFFBBDD99DDBBBBDD99DDBBBB7B371B3399",
INIT_18 => X"99131B59359B3F771B9B99BBBBBBFF5FDDDDFFBBFFDFFFFFDFDDFF9D9DBBBB99",
INIT_19 => X"BBBBBBBBBB99BBDDDD99DDBBDDBBBBBB773377571B9D7B9D99BB791335135D35",
INIT_1A => X"3515F51B177799579B55777755553339375755773335154FB51511EFB3F1D113",
INIT_1B => X"33151355333311F3151315F333351333371311D3131335111115171313F51313",
INIT_1C => X"5B55553B55553B35F53359773337131715351715333315193337133315F33333",
INIT_1D => X"559B5D99555B99597955771957391717113B1133173535F51313F1F5335B3755",
INIT_1E => X"229DBDBB599B7D7B1397531917335B7937195515193B1513131313D313353999",
INIT_1F => X"FFFFFFFFFFFFFFFFFF7FFFDD777B777D373539173535359977775B9B6A20D197",
INIT_20 => X"55F71313F3B311D1F113F3B511111733333933593B777B57BDBDBBBDBFFFFFFF",
INIT_21 => X"9B595B99375D5579779977BBBBBBDDBBBBBBDDBBBBBB995D5577551799115555",
INIT_22 => X"5537551735579959551137557799DD7DBBDD995B9B7DBBDD7DDDDDDDDD997739",
INIT_23 => X"BB997799BBBBBB999999999B1977BBBB9B577779195B55175B557D19353D3B3B",
INIT_24 => X"351355F31377775599995577131D35137777795B77557731D111F173EF53EF11",
INIT_25 => X"33F53377591D7755135713331B15F11113F1F7131113F3D51119EF3311F13333",
INIT_26 => X"135915797B7913777777151335173313171D331711D5333533111D1B111B3375",
INIT_27 => X"3D777B793B79795D33BD391377551B5733351339111B11351111D5F1191D7799",
INIT_28 => X"22BD99337933BD5B771D1157795B159935795517151313F1F5F511331357133B",
INIT_29 => X"FFFFFFFFFFFF5FDDFFDFFF5F9B13BB77353313F75533553377333DBB68209177",
INIT_2A => X"11133335951153F1F155D1D111F3F13317131B17593355999979BBBBDDDDDDFF",
INIT_2B => X"995555BBBD359977BB797D3F77775FBBBBBBDD77BB1B779D995D77571B11F7F5",
INIT_2C => X"33551B55553D131911551557355B3F155B359B5DBB35373DBBBBBB5DBB33BB79",
INIT_2D => X"3355551D5533BB5B131D11777999BB5577999919595719115719BB1319591355",
INIT_2E => X"331133115173115555555B35331311D1337777351177F735EF7333F155F1B3D1",
INIT_2F => X"1111F733331313193333F535113577FD1777F133331111113311333333351B33",
INIT_30 => X"7733777777117755117713771D35551D33111113F11197F1F9331111331137F5",
INIT_31 => X"119999BB5599BB5599133D77133911F1F3111D13333519111D331111F1113377",
INIT_32 => X"62DD33BB3DBB1D55331155111D3511995D131D3333331935F3F3335533331515",
INIT_33 => X"FFDDFFFFFFDDFFBBDD99DDBB335DF1135BFB57551F1317779D5B115544207395",
INIT_34 => X"35775133F111F11111F1F1F1B791F157133313337713171F995FBDBB99FFFFDD",
INIT_35 => X"FFBBBB1FBBDD795D99BB559B795B13991913BB9911DDBB1F151577333377F111",
INIT_36 => X"1D151511191177331D1D13111D11773355773333115577BB33BBBB333DBBBBFF",
INIT_37 => X"351F1335177977331177331F131977BB3B793F3311795B351B5511BB33113D33",
INIT_38 => X"557733773577F93557113335133359D73933775577773355F113111133111111",
INIT_39 => X"3355777799995517135513333333F113EF33F3B333F5B333F1194511F1331119",
INIT_3A => X"11351B335959793B1D13191133131511331D75111B1133351119773315F1F1F1",
INIT_3B => X"5515151D7B131D5B59F915331113F71119351333F11333551395153315571933",
INIT_3C => X"40333D33151355331B77391DF3351B333555F5F5F9F1F311D533F133F5133377",
INIT_3D => X"FFFFFFBDFF5FFFDD999B993D55111B7735135715351115115757131944208E77",
INIT_3E => X"F11113EFB3D153B3D1B19331CFB1D113135513331B133B111B791D55BD99BBDD",
INIT_3F => X"DDDDBBBDBD77BB9B3D795F33BB99993D999B157DBB555799557711573511F533",
INIT_40 => X"33571B337715131B131DF75513171B1333FB11171533339977573DBB99BB3D35",
INIT_41 => X"115153F155D513171B1311331377331D7713573B331333F9113B797959133357",
INIT_42 => X"33131155F3193337F3131517F51117135955775519131533F11313D533B53333",
INIT_43 => X"55175599775B99331533131335D5F31733331711F533B3F1F3EF1111B3F1B511",
INIT_44 => X"3517333B33551915113335131313B3351571F9F51139111713F91311D5553515",
INIT_45 => X"1933335533335519571315173313EF3513F5F315F513B3133733F31317111313",
INIT_46 => X"021B1399333911391735F7351713553337F11717F113F7F59117F3D1D1171139",
INIT_47 => X"BB9DBD7DDDDD7FBB77773B791733F7133717F1F315F1F7111717333548206E97",
INIT_48 => X"F3D193EFD1F171AB9191D191F1B393F1D311F315111737117715553B39779BBD",
INIT_49 => X"5599BB577B999B5977BB79775D599977775B7959995719573333113917131391",
INIT_4A => X"3315173517393519171115D5131533F713F53B17173535199B359955995D797D",
INIT_4B => X"3B393339555513153319337D17153577575B77157717571155995B3333F535F5",
INIT_4C => X"57F13377331333113333F133F9333333131133333533131D1911111333151133",
INIT_4D => X"77577799995733333533151357F3F11D17331311F133F311119333D1F3F1D133",
INIT_4E => X"3333D513391533171D1133D533331B11113157353313F5115515D71155133B77",
INIT_4F => X"37331B3355111D150F57131315B5331133F11113F175135711953333F5F11513",
INIT_50 => X"4013791D151555135955F11BF91711F711F71113FBEF17F3F5F5F1F1F1331157",
INIT_51 => X"993535993B99BD9999335535151D375739D533D511D511F91119111346207477",
INIT_52 => X"13751355F1F1D1B3B1EF69EF45F155D1D35535F555F1F5573B19551333331B13",
INIT_53 => X"775D5F775B7BBB555F99BBBB159BBB3D171333353D1135333B771B1335FB9355",
INIT_54 => X"1B15F533F5131B131B1B17F355F311F913F135F133331313333B331999135799",
INIT_55 => X"35793D337B797779337717595717993D99339D7BBB993B115519131955111DF3",
INIT_56 => X"353311FF7933D75511333311331177553B35D71B1133331111D5F1F3F3F1D511",
INIT_57 => X"11777799BBBB77331D333533F115111113D7113333339735333333F1F133D5D3",
INIT_58 => X"F1F71133133313191157F511F93355113377F711FB3333771D11115511773377",
INIT_59 => X"33111177F3F33317F31D331D33D5F1D99B153333331111F1D5F1F155F1111133",
INIT_5A => X"021FF37733111F551D131911351157F117EFF911EFD7F333EF333733D5F10DCD",
INIT_5B => X"11191B115533BB17131D17131D11331111F11D3311351137D511FBF34840CE95",
INIT_5C => X"EF6ED1F1B3D133EFEE3393D133EFF1F11335111B35F9775511551F333377F559",
INIT_5D => X"BB3379BB79131F7713FB111D77551179359B1D5555773377151511331111F1EF",
INIT_5E => X"111111FB11111319F133F53537F133D1F3D7135BEFD5F71133117715151D3333",
INIT_5F => X"113355BB79BB11BBBB779999335D799D5BBBBB551D55791D3335773333773355",
INIT_60 => X"351511135511331513F733D533111B1B331111113313F5353511D111331111F5",
INIT_61 => X"775557553B131F3B3311F335333571111311F3F553111311D3F5CD1515111111",
INIT_62 => X"3313111B1355797777337777333555373913155513771913331911111B775519",
INIT_63 => X"F1F7F1F9F1F1D7F333EF33554819131B11D7F3FBF11B55F1F11135EFD51B3319",
INIT_64 => X"00F1F11D15F5CFB5D1F113D1D11755339313F1B5F3F3CE53F3D1F17511331535",
INIT_65 => X"3519335913111B33571135F3F1FB51D5F5F311F35937B555F5F3F3F74600B177",
INIT_66 => X"6BEFEFCCEECCEEEECCF1F1EFD12D33D313CE4C8C8ECCF0D051CD0FF215573319",
INIT_67 => X"13191913177711175733773355191577551199353D15175933111D1933D1F7EE",
INIT_68 => X"1F195515191933155711F3F1F1F1F713931133F533751133131555EF1177131B",
INIT_69 => X"99BB33999999BB5599999B773FBBFFBBDDDDBDBDBB9999BBBBBB3F991B335B15",
INIT_6A => X"11D311173517F5333311D3F113B51311CD9533151135D3F7F3EF9311B311F3D1",
INIT_6B => X"5515173355173B3333193315331591F7B713131333F1F3931153ADD5B3CDB533",
INIT_6C => X"55373B7757555B555B5515357737553B11391733171315551315351913331733",
INIT_6D => X"11F3F39313B191EF1119F513F5D3F5F3D315F3D311B3D313B3B3F3331113F355",
INIT_6E => X"20D1F193EE8ECCEE6ED28E906CB0CE8EAECC8ECE8E8C90CE90AE1191906FF2B3",
INIT_6F => X"EFEFF339F31391EF17F115D51393F11115B111EFF7F11311F41117D124209197",
INIT_70 => X"6ED08CCC8E8C92CEEECE92D0ACD2D4B290ACD4D098CED452CE6E96D26ECE928E",
INIT_71 => X"5717F5331155113717353733191917793D9977577733333913D191EEEE6ED0D0",
INIT_72 => X"3379795B553B111717939313F1D17311B1F133D313D1D13313F311F5B3131739",
INIT_73 => X"BB9999559999559BBB559D77BBBBBBDDDDBBBD9D7DBB99BBDD99BB555B55993B",
INIT_74 => X"3333D533EF13F111753313331115F713D5153313333313113311EF11D111F113",
INIT_75 => X"3535773333353533111337133315F1F1F1457395F13311F3111111111155F311",
INIT_76 => X"3355577777773355137777771D33331517771D153333331D1313111557EF3533",
INIT_77 => X"2C6EAC8CAEB08C8E2CD0F11133F15311D151CE9111F1331173F1F1F3F3111317",
INIT_78 => X"408A30B16C52D66CAC7252D4D2D0CCB0743AACD24C50B0D66E90528A8E8C70CC",
INIT_79 => X"32766C4E6CAE8C6CCC4EB1F1CCCCD48CAED46C8C4CAE8E4CCC70AC4C22209177",
INIT_7A => X"8EACCEB2B2CEB8AE4CF0B490B4B0AEAC92AE8E908ED2CEB4CC4A32B0AED4D2D0",
INIT_7B => X"117913571D131135135533117935BB7957571133116ED0CCAEB08C30CED4EED4",
INIT_7C => X"771579BB557977357BD157111331B111F1F1519311F1F15173F133F1F1F11113",
INIT_7D => X"33999999999999BB339955BBDDDDFF99993399777933335533115575F1331157",
INIT_7E => X"3711F1111133159535113337EF11F11135113333111111FDD5113733EF331111",
INIT_7F => X"11331BF1F7333519D733331D3311F111333333F1F1D5331151911733D5331133",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFB200DEC8482A3FF7800000000020000000070000080000000143FFFFFBFA",
INITP_01 => X"05F8000000000000000000070000000004000001FFFFEEDAF9EE967CFBB2D9E0",
INITP_02 => X"0000000700000000000000007FFFFDFB7DE844AB5EC06F9EFFFE90020A404800",
INITP_03 => X"000000001FFDBD9D176D9E883A7BDB81FFFA5000024048000040000000000000",
INITP_04 => X"E1D9B23827F2C800FFE800000000400000000000000000000000000700000000",
INITP_05 => X"7FC0080000000000000088000000000000000007000000000000200001FFF771",
INITP_06 => X"0000000000000000000000070000080000000000800FF84FBE6C2000985CFF00",
INITP_07 => X"0000000700000000000000000002F7B1EFD4A00081B252001F20008000400000",
INITP_08 => X"00000000000026AB8FD621C2626EFB4000020000000000000000000000000000",
INITP_09 => X"6C7800201039FF00000000200000000000000000000000000000000700000000",
INITP_0A => X"00082000000000000000000000000000000400070000000000000000000000F3",
INITP_0B => X"000000000000000000000007000000000000000000000008E88800009F90F040",
INITP_0C => X"0000000700000000000000000000000000A000001030FE400002000000000000",
INITP_0D => X"00000000000000000382000224387D9000000000000000000000000000000000",
INITP_0E => X"0000000005F07E00000000004000000000000000000000000000000700000000",
INITP_0F => X"8000000000000000000000000000000000000007000000000000000000400000",
INIT_00 => X"795F99775B79BB3D77775577115B79113511113535571135111B771111FD11F7",
INIT_01 => X"D0585AACD42C32EEAC32EE2C6E6CACAC90ACAEB032CEAE33F11137B159F15513",
INIT_02 => X"004EEEB28ED032CC3CCC904CB4B2B6EECE2C944A0AEE4CACCC58ACB2B4D6ECCE",
INIT_03 => X"F0EEB0B4D4EEB68ED4AC92AE0E688EB44C6E308EEECC6E168A6B12AE02204E95",
INIT_04 => X"ACB6B2AAA8B2CCB0B6CC908CD6D236D44CC82C78AC90B0AC90B42AF032ACACD0",
INIT_05 => X"F1771B11331D3333111D1713F933553311CCD4AED6EE8EEE2EB0D6F8AC128E8E",
INIT_06 => X"1133F911777777F5133389131171D1377357F3F533CD0FD111D3357711331557",
INIT_07 => X"BB999999BBBBBB55BB99BBFFBBBBBBBB33F9111123551133D3B337ABABFF5359",
INIT_08 => X"331113333377331111D53333F1EF33F11333D51333F5F133113333D1F3F191F1",
INIT_09 => X"3333113333F3F311113313D31113555517EF7533D11113F1791511331111F5D1",
INIT_0A => X"55331599BB3377553D3379333D55111B355535F7113511F73313511D39F115F3",
INIT_0B => X"EECE4CB44A0CD2AEB6ECB2EE5894B0B48C32CEB4AC5272AEB08ECCD0CEF1D131",
INIT_0C => X"00B2AC6E72CED0728EB26CCEAC6A72AA74AAAED2D63872B44C906C8E50B2B2B4",
INIT_0D => X"AE549084AC50688E6ED04ECE306E964CAC2CCCB2CE308E8A686C2A6820209077",
INIT_0E => X"D490AED03AAEB4D0CCCCB4AED49032EAD0D0F06AAA4C70AEB6AA90B4D0CC6C58",
INIT_0F => X"F191D1F5F111D1551355131333F1D0ACAC54AE788C9090B4B24E70AC76F0CED0",
INIT_10 => X"53B3B3EF13F111F35333B5AFD19355CDF111F39113F571F1757111D1EFD1ADAD",
INIT_11 => X"99997799999979BB993F7777339933F313F1733337CD93F153CFF175750711D1",
INIT_12 => X"F511B311333313B33333D3F1F3D375F1F31133D51311151111B1F133113311D3",
INIT_13 => X"F51333331515F711151313F513F1F5F5AB33F1D19311D3F113D111B111891111",
INIT_14 => X"92101555779977555577353B33593533353317353337D5351313312F15F31111",
INIT_15 => X"AA6E6C74D0B2728CAEB070CEAE70B06CD2964C928A768EB45250CE568CEE4EAE",
INIT_16 => X"2072708E8C8C10AE8A72AE72908E7274AC8E72902EEEB04CAEB4346E6CAEA654",
INIT_17 => X"B0F0B0988EAC4E906ED26EAE6E8C8E506E906A4A2E6C8C6C4C4C862E0620B297",
INIT_18 => X"76CE9274CED4B08EB274D2B04E8CF4D46E9490AE56B0B0B0B28CD0B256CECE70",
INIT_19 => X"758FEF732DCEB3D3F711F3F5CEB2B48ECED0B0B08E92D0B28C70906CCCD49072",
INIT_1A => X"6F93B171939313D39311D19193B1F10F7113B3B313F19173D1D10D8FCD1591CE",
INIT_1B => X"7777BB7799775B9D57BB775557D511B3D31393119193D191AF5171CFD1937191",
INIT_1C => X"D1733311117511F37711131133F151333333F51111D5331111F1F173EF53EF11",
INIT_1D => X"F1F3F333F1113517F13333F1334FF1131173F1113311115311F1F1F333D9D3D3",
INIT_1E => X"B02ED03311551155777755153313D53717FB1B113311F3331195452E51139533",
INIT_1F => X"3ACECE8E4E30EED090A252AE4C8E38CEB28E8C70AAAE5490AC4C888E2EF050A8",
INIT_20 => X"008E6C5290ACF24AAA2ACC90AC6C68AE2EEE50AACE2C8C1AACAE2C6E749054AE",
INIT_21 => X"CC4CAC8C8EAA3094D252AC506C8A3A486ECC6C4CAE308C2E504E388A2600D177",
INIT_22 => X"B24C4C8EAA4CB4B2ACD0B0B4AE4C8CCECCD2AC4CAC90B2EE328A4E8C6EAC7090",
INIT_23 => X"D1D537255151F175FBEF8ECE30CC5AAC34B4D2944C8E2E94D2AAEEEEF0308AAE",
INIT_24 => X"0F5373CFF1EFF195D1F129CFB19345AFF11175F1F12BADD173698DB1B1B109D1",
INIT_25 => X"99999999BB55BB9B9B3355531193F15593F1D18F25F173F347CFD1B1D13347EF",
INIT_26 => X"EFF111F1931111331133333317F12FEF1935F1D533F175F1D1B1EEF155F1B3D1",
INIT_27 => X"1F5533D7F3FDF111331575333395D11133F11111F15733F1F3FD111111F1F1F1",
INIT_28 => X"0CACEE12108CD81B111F551D353B551133111111D7133911F735331719F1F111",
INIT_29 => X"AE5A2C2E8C0CEEB0903AAC3AEECCAC2C50F0326CAC3E92E810AEACAECCAC2C30",
INIT_2A => X"004EB6CE2AAA32AA3A920CC8126CCC8ECCAC0E4E0C8E88ACCC52B6D44C666E8C",
INIT_2B => X"0EEA4E12100CD05088AC8ECEEE906A8A8A2A128E2CAE6CEE2A6CA89008209177",
INIT_2C => X"12AEF01C8EB4ACAEB6CE4EAC2CB4900E743C8E963C9056ACD4EEFE38EE36D0AE",
INIT_2D => X"F175F113F1EF23F1CC6A70CC90D22CEE12F032AC12B2CCACACAA0E4E58F0D0F0",
INIT_2E => X"13B1B1F113CFEF89CD1791CC37F1352373F1CD893751EE37F15503F155035351",
INIT_2F => X"353377BB5599BB99335715D12FF1F1F1F123D113138E93F111AB175353ACEFEF",
INIT_30 => X"11F1D11133EFD1B3D135F311111357733333131313131111EFEFD1EFEFEFEFEF",
INIT_31 => X"3393771133116F97D33333551111D1D133F111B3F1F1F1F3EF67EF73F1EFCFF1",
INIT_32 => X"0A3058EECEAE688AD0EED3F1331311357913133711F1F3F1F113F17B73331333",
INIT_33 => X"CE88AE2C4EA8324E8A30AC30AC8C6C32CC386CB0A84C6E4E6C6E4C704E8E8C6E",
INIT_34 => X"40AA6A12CC386AB0C82C8E2E6C8C4C704C908C4E0A108E4C2EA8684EB08C3690",
INIT_35 => X"14B2B2D2CCCE528C926E76AC2C8E502CAE94CE50B06A10CEAC4C2C4C24209397",
INIT_36 => X"EE6E6CA6F450CED2B4AC8E5ACECC8C74EA8890ACAA2C4CAC7232C4CE8A2E8EAE",
INIT_37 => X"05F1CEEE908C50908ED4948E588EACD26C2CF0769090AE34AC56D0F06E0CB06E",
INIT_38 => X"53CF2753EF33D1913927F5F355CF35D113330793CD0791F1D593CD35EF53F1EF",
INIT_39 => X"51B11313331B333553AF0FF1F18B33D1B555F1F349D1918E1175D18FB1131309",
INIT_3A => X"11B1D3EFADCDB51133F33311F1D111F1F535F713F7971575B3EF91D1D1F1B1EF",
INIT_3B => X"111511F5111717111713D311B511B1EF119311B3F1F1D191D171EFD1D173ADF1",
INIT_3C => X"6E6CF0B08C92F6AE92AC906E8EF313F313173333B711131313F11111F5F5F113",
INIT_3D => X"0E8E70A86E2ECE7256A86CAE0E6CAA906C4C6E50AC548AAA12AC90748C50AA30",
INIT_3E => X"225A8E8E6C6C6E708C548CCA128C8E748E50AA506E6C6E6C665216AC708A4EAE",
INIT_3F => X"0CAE6E968E6CEC508E4E7050EEAC6C6E6C4A8E6C90706EAC2EB0708C26206E97",
INIT_40 => X"4C705058A872B6B08CB290B06E6E6ED46ED42E8E7690D07270CC10CE6C346EAE",
INIT_41 => X"90708EB2B08CCE9292AED08E764CAC74AA4E8E6E944C6C4AAC6C8A2CAE908E6E",
INIT_42 => X"F15171EF918B13B1756F8991EFAF91714FCFB3B30DB1B169B38FEF8F6ECE726C",
INIT_43 => X"6DD1AD71B393F1B3F1918F93F1D3118DB3F1938DF593D1B36BD16FCF718951B3",
INIT_44 => X"551111EFD1F111D3F1113375331111F11355775533F31151D1332573F153D173",
INIT_45 => X"33F5F5B5111313111133F133D11111DBB1D111F1F173EE110F0FF171EED111EF",
INIT_46 => X"CAF472CEEE4CF22C8C8ED4D0D26E52CCCCEF13D3D13311571191137313F11111",
INIT_47 => X"6C366C9016AE2A6A8E88742EACD0AC326C1ACE4E386C8E1A2E6C884C8AB6308C",
INIT_48 => X"00CEAA324E38CE50386C8E382C8C882C8AB4306CCAB890CE888ACC8C10AC5872",
INIT_49 => X"108E8C2E56ACD6704CAE50CA2C308CD070304CCE4CAC94B48E481AAC02208E77",
INIT_4A => X"12AE70B23076AE7090B2AC3A6C6E8CCE2E8CAE6C8E6CB410AA728EB2D08EAA50",
INIT_4B => X"CC928C3CAA2C48AA2CCE524CD0AA2A2C6E74C8CE4CCE4C68AEB0E810AE2C8A8A",
INIT_4C => X"4FF1F153CFF1D1EFAEAE0FCF53B3ADD1F1EECFAFD1D18F0DD1D353888AD4CEAC",
INIT_4D => X"CFF1F133D1D1F173F155AB31279355B193F153CF4F4CF1514D731371CFF1D1EF",
INIT_4E => X"F1B3D11517D133F1EF3711113393D111111D551133113311EF73EFF1EFF1EFF1",
INIT_4F => X"333333EF331DF8F3F13333113391ACF1CFEF55EFEFF173F10FCD11F1EFF153EF",
INIT_50 => X"0A2AAEF052B6CCCCEE8EEE2CE8F4AE8A922E4CF133D1B1F11133111173373311",
INIT_51 => X"AAAAD86CAC887070CC0CD2AC122A0AEE506ACC74AC8C92ACAA6C12EE2AB2CE30",
INIT_52 => X"204E2AEE6E6ACA56AC8AB6ACAA8A12EE4A92EE500C684C12880CA64CCC12A858",
INIT_53 => X"D04E52AC6E1A6C6CCE686ED4340C2CEE4ECE8A10CE0AAA0C4E5268AA04207677",
INIT_54 => X"0CAEF2EEE8EE3CEED870708A9476CC30A83A8A723CC66CAC1AB0CCAE8C1C4E52",
INIT_55 => X"28C890D01298AA8CD0B2B2D2CE6A880E8C6C368CEE8C4A6E3A2E0EAC50CE0E68",
INIT_56 => X"CE4C30CE4C32AC4ED4D4CC32EECE2CAC6E2ECC6CAC526CCE52CCEE2A881CAA2C",
INIT_57 => X"CCB18CF1B3D12FF12FF1F73533F1F1F1F1331191684848ACB0B0CCAE8C128C8C",
INIT_58 => X"11F1EF0F4F11111111EFB315F3EFEFF133353355D5F5B3F5D111D1F1F1F1D1EF",
INIT_59 => X"111333F911EF49F33327B57511F1F3CD8BEFEE93CFD1F1CCF1CFEFD1D1EFB1D1",
INIT_5A => X"52CC6CCED04C8C2E946C92CC386A388EB0F0AC6C2AECAE8C4E73CCD10FD1D1F3",
INIT_5B => X"2C4C683268368A4CAE504C6A8C6E944ECC12884C4C2A4E6A6C70685070882E8A",
INIT_5C => X"008C722ECC30886C4C2A4C4A6A548832906A0E8A528C2ECE14882C728EAC2E8C",
INIT_5D => X"4CAEAE3A6EAC0CB02C54906E3A4E6852CE4CB26EAE8C4EAC4E6A32AC0220CE97",
INIT_5E => X"ACCEAC3AD2AA8C726AD6548EAC4ECE10928A58CA88584CD2CE74AE4E50EE6CAE",
INIT_5F => X"ACAC12EE8C906E4CAC34AE4CD0548A4C14AC6E30AC2A4CAC4CAC8A308C2A6C8A",
INIT_60 => X"22D2D0AAB0F2CCD0B4ACB0EC36AC8CD6CEEE9088B6EEAAACD2948C8C70F01098",
INIT_61 => X"D18B2FEF4751CF71F1356F4753911351EEEE4C8C102A8E8CAA74D0AAB4F0CCB2",
INIT_62 => X"95D1F111D1F195D1F191111191EFEEB333393557333311F5D51193D1D1F1B393",
INIT_63 => X"95D1F1EEF173F7D111B511F1B5D1918BF391CF8FCF91AFF175D1F193EF91EFEF",
INIT_64 => X"6CEE966CB2908E946ECE72AC6CAC54908CCE6EAECE72908E8AAC6E91AE91F1F1",
INIT_65 => X"AC908A6C6E6A688C52AE4EAA0EAE6C4E8A10AC6E928C8C4CAE68AA4E904C6E2E",
INIT_66 => X"00706C4E6A30CC4E908C8A4CD048AA6E726C504C6ECE6C4AAC4E506C4AAC5030",
INIT_67 => X"CE906CEEB04C904E8C4E4C6AB2728EAE50EC108E10AE2C8C588C6C302420B177",
INIT_68 => X"906C72CCB08E6CB070AC90B050906E2C904C8A8E8CAE6C12AA94B070AED28E52",
INIT_69 => X"B2708ECE6C4C686E8CF08ECC7290B06E6E6ED26ED42E9076B0B07270CECE2E52",
INIT_6A => X"4E906E3492B070B0B08C52E8306C0CAE8E70B0904EB0AE0E8EB050B42EB074CE",
INIT_6B => X"A9AF91918F91CF71716FCBF0AEB2CEB04ECE706E902A8A76886C0E8C8C928CB0",
INIT_6C => X"D1EF3337B10FD1F1F1F311111393EFD1B31133333337F52F1195F11173F1B1B3",
INIT_6D => X"8C29D13169D1111111D1B3D1D1EF11D135B1F1EF53D1B1EFAF7531D1EFD111EF",
INIT_6E => X"A82CAC2CAEAA4CACA63A8ECE8E748E4AAC4C58AC32D04AEE50CC68AAAEEE6FF1",
INIT_6F => X"30882E8C2C4E304C6A8A542ACE8A2CAE8E70884E884C6C2E4C303088881A8AAE",
INIT_70 => X"20AE4CCE8E70884C8A6C4C2C2C4E10A688188A8EC82C90CEAA6AD04C8E8E6E68",
INIT_71 => X"30AE322E8838E86E8C486C2C8E682E4ECE4CB030AA4E502ECC548CD022209397",
INIT_72 => X"887090366C8CAE5690AC8C4ECE6A8CCE6AAE2C4EAC6E8CB6AC302C8E9090528E",
INIT_73 => X"F02EAA344C2EAACC588828A630AC3A6C6E8CCE2E8CAE6C8E6CB410AA52CCB0B0",
INIT_74 => X"0C12CACCB4D0D0B432CE90CCB0B46AB06E0ACA8CAC38AC10AC702C8CCE2C8C36",
INIT_75 => X"337335CFB391CDF1D1CE8E30ACACB4B2AC54B06C4E6A56702E6C8C704E2C48AE",
INIT_76 => X"F10FEFF1F111EF1133111535F1F1EFF17313331B1133333355F1EFEFF1EFF1F1",
INIT_77 => X"EE4FCCD1714FEF8911EFF1CDCF8F2F45F1338C91F1CD71F12EEFF1B3B3338ED1",
INIT_78 => X"CACCF0EE72F40AD23C2ACE3AAC74CAB456D0D0B2EE8694CCAE8C0E480CAC2C2C",
INIT_79 => X"4650A60AAC2CEE7472AA6ED02CCA8E2C4E688E6A10AA48AC8AAEAC3AACAC524C",
INIT_7A => X"225A900C4E688E6A10AA688C8A6EAC3AACAC326CAAC82A683058944E4E0E6A8E",
INIT_7B => X"CE2CC81C8ECE2A6C881A6A8C703012CE10D0ACB09032EA12B04C682C24409177",
INIT_7C => X"1CAC2CAE762E2E90D00E78AC288A2C122A6E3272F0B48A0EAEB6B64C5A88CC2A",
INIT_7D => X"8E7212EE6A466850ACC6CC3A8C908A9496CC30A83A8A723CC66CAC1AB0AC2C2C",
INIT_7E => X"AA92BACAAC38AAB0923CAC3290B0AC3AD4ACCA12EE8A5AD08C4CC8384CB65686",
INIT_7F => X"32ABAD33CCCC2C8E68D4ACEE1A6AAC2CD2F02C6C8C2A4CE8AA2C0E8C8C0EAAEE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000070000000000000000000000000000000004000900",
INITP_01 => X"0000000700000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000010080000000000000000000008000000000000200000000700000000",
INITP_04 => X"0000000000000000000000000000000000000007000000000000000000000000",
INITP_05 => X"0000000000000000000000070000000000000000000000000000000000000000",
INITP_06 => X"0000000700000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000200000000080180000180000000100000000000000000000000000000000",
INITP_08 => X"0800800001001001002000002002002002004004004000002002000700000020",
INITP_09 => X"0020020020020020020040040040020020020047080000200200200200080080",
INITP_0A => X"DA6F4DB4DB4EDB6DA6DA6ED76DB66DA6DA6DAFDB6F69FFBFFBFFBEDB6DB6DB6D",
INITP_0B => X"FFFFFFF77FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE6DB6DA6DA6DA6",
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFFFFF",
INITP_0F => X"FDDFBBFBBFBDFFDFFDFDDFF77F7FDFDDFDDFFFFFDFF7FFFFFFFFEFFEFFEFFEFF",
INIT_00 => X"CCD3D1F3EF11B191EF55EFF13993F153F1F14FCF33F1F133D1B1AB918DD171D1",
INIT_01 => X"CECC4E31C8CD2E71F1B19153EF8BAFEFCFCC4FCD53AF8FACF1883145CFEFD147",
INIT_02 => X"0E4C8C326CACB0508410726AD8A852902EAECE8C54B0AC3AEE8C106EAA4CF030",
INIT_03 => X"0C8A16CE0EAA4A2AAC104C8C2E0C8ACE0C4A304AAC0C940C4E880C88502C8C4C",
INIT_04 => X"004A6ACE0C4A304AAC0A762C30A80C88702C8C4C0E2C904EC88A2AAC4E2A4C6A",
INIT_05 => X"7072AE0E4C68B04E4C8E74524C6CB050AC302C4EAE4C2A4C6A50905022204E97",
INIT_06 => X"8C56B2CA8E94EED2AAAE90AC0E4EACCA6CCE2E8A30AA5694AA6C2A8C8A90564E",
INIT_07 => X"4CD0B054B08E3A8C8A0E4ECE2C548EAC4ECE10928A58CA88584CD2CE542E90D0",
INIT_08 => X"924CCC8E6CAC906EAC8CB0EED652B26C522E2E8E3AACAE2CAE32D26CB2A86E70",
INIT_09 => X"B15373EECCD48CACACAE2E8EF0B4CEB06ED0ACAC8C2C484A0C6A8C502C664E6C",
INIT_0A => X"EF8FEF91CD8F91D1F1F1B191EFCDCDEFD1F1F1D191F1CFEFAFD171B18991AB8F",
INIT_0B => X"B06CAE884E4CAA8CAD916D6FAC916F8B4F73CDAFEF2B8F6F692DCDD173CCAFB1",
INIT_0C => X"4CAA6A768C2E6EAE6E8E8C906E8E6E8AAC6C908ECE7052CE8E92AE6C8E8CB28A",
INIT_0D => X"8C8C6E4A6A6E2C6E4E328C4E4E8C0C6A2E4E8A4ECC2E6C6A6E4E6E4E328E6C4E",
INIT_0E => X"206A0C8A2E4CA830CC0E6C6A8E4E6E4E308E6C4E4EAA4E744C6C4C2C2E4C6C2E",
INIT_0F => X"4E6E90528A4A6E4CAC146EAE12AE2E2A4C4C4C506C6E6C0E8A6E528A22207277",
INIT_10 => X"6CAC4E4C906C8E4E8A726CAA2E8C4C4C704C906C8A54AC6C56708A706C744A70",
INIT_11 => X"6E30CC768A904C708C2E8C4C6C90B050B06E2C904C8A8E8CAE6C12AA948E4E8C",
INIT_12 => X"5892AE14AC9652AE906E70AC4EB0726C484A4A9070B072CC4E8C746A8C8E8C8E",
INIT_13 => X"91B1CCD0ACD28EB46E8C70B2CE8EAE4E6C10AE508E2A482C4A88488A8EB2906A",
INIT_14 => X"CC8FCF3393AC45CF53F1F1ACF191EF55EF53F1F1ACD1AF5355CFACD18FF171EF",
INIT_15 => X"3ACE4CEC6CAC304C2ACC8E8C4EAC2553CF8E458FEF8B8B31AF09EF682FAC7151",
INIT_16 => X"0C50AC8E4ED42C6C30D07052AE8C6A3870ACAC2ECE6CB2863070CCAC4CCE8CAC",
INIT_17 => X"2A6A2A6E2AAE2A8A8EAECE308A2EB0AC8E104C6C6A4A4E2A4C4C888C8ECE6E6C",
INIT_18 => X"004AAEAA8E302A8E6A484C2A4C6E688C8ECE6C6E2C308A8E482A68CE6EAE0EAE",
INIT_19 => X"2CCE28306E0E308E8C8E4C882C8C0CAE4CCE4E6A2A6C6A102A2CA8160220B097",
INIT_1A => X"2EAECA8C96CEB24C304E8E8A2E6A10CE0EA8526CAA6EAC2C6E2E0A4E92328EAE",
INIT_1B => X"CEB48E1010AC92B4EEAC90AE688C4ECE4A8CCE6AAE4C4EAC6E8CB6AC30AA5050",
INIT_1C => X"8E4C58A82EB2308E18EECC588CB032CE6A0E686C8C50AA2CACCC2C8E702CAC4C",
INIT_1D => X"CC8ED090B056EECECEEEAA504EAE90EEAE8C58AC526C4868708EAA324A90308E",
INIT_1E => X"2EEF4F23CC33CF6DF12F89CD11ABCDCFCDF133EF33EFF1EFCC5503EFEFCCEF53",
INIT_1F => X"AC286CEE6C2C88A8EE32AE68886A86ACCC2ED16EEF5367CF23CEF153EFEFF1F1",
INIT_20 => X"EE6C8A1C4CCCACEEEEAC7088CC74A88C8E2E30CAAC0A6EB2CEAAEE4AAA32B08E",
INIT_21 => X"126EB0124C66122ACE0A488B32CA2E102CACAA50AC32720E860E4C4C4C682A30",
INIT_22 => X"00502E124A8CAA6E8C329010A62C4C2C6C682A4ECE86480E5252AC104A12ACAC",
INIT_23 => X"6A904AAC6AEECE6A3AD02C100AA86A302A682C70D05272AC4CB00ACC4600D177",
INIT_24 => X"928EB4168A2CD072F012CC32D070AC2CCE3C6C6E1C8850D0326A1C8C8CF05030",
INIT_25 => X"684EB4B6AE32AC6C8C0A6C88DE76AC288A0C122A6E3272F0B48A0EAEB6F030EE",
INIT_26 => X"ACB2E41CD4F8ACACEE32746CB28CAC0E2A46AA34F08A48AA0C0E4C70B012F290",
INIT_27 => X"CCCEB4CC8ECEAE563ACCD6AED06EAC3AB22CCE8E0E88566CB00CEEAEAE12CE3A",
INIT_28 => X"D1EF554FB1CFD1F1CDCFB1D1B153EF4C6F8EEF71CEABF13171EFD1717153AFCF",
INIT_29 => X"4CB28E0CAC8C9274368A6CCE2A484C2E2A8AAACC2EEE4ECE4E7133AF91538FAF",
INIT_2A => X"2E4E92AACC58AE0E8E4CCE5AAA50AC4A70ACF44E388A6C6A908E2E6EAC2E86CE",
INIT_2B => X"CE0E8ACE908C4ECA5068706AA82E8CCC6C684EAE2E2CACCE504EA8904AAA34A8",
INIT_2C => X"006E6CCC4C68708C4E0CACCE506CA8AE4CAA16A82E505AA8AC8C0CAC4CAA6A4C",
INIT_2D => X"B0300ECACE4E508C8C2A8A8CC81032684EAE30AC4CAE2C8C1068126C04209177",
INIT_2E => X"2C708EAE32AC0C948E0E6CCE4C6E32AC8C8EAA6A8C8C8E4A8C4E8C4C502A6A4E",
INIT_2F => X"3CB28850548E2C6A50CE90506A70AC0E4EACCA6CCE2E8A30AA5694AA6C2CAE4E",
INIT_30 => X"346C4E2E56AC2E90AE309052CE34B2AC6A8E36AC308C4A12CACC2CAE8C6C50AA",
INIT_31 => X"CE8AACAE74D04AACEE2A8E504ACC308C6CB252902E8C6E8CAC50AA2C689034AC",
INIT_32 => X"6F8B6EEFADCE916BCF8DB191918D6D71899191B1CE2BAEEF896F8FAFAFEF91CC",
INIT_33 => X"6C8EA8908C8C488A4CD08C6CCC6C6CAC6E8C6C4E8A4C4A688A6EACAA6C6CAFCF",
INIT_34 => X"AA6C8E4E8CCC0A6872908CAA3488764A884E6A6EA84A8C4C8C4A6CAC4A6C8C6C",
INIT_35 => X"4C6C8C108C6A706E8A2E708C348A0CAC6E6A4E6E8A304E6CAC6EA8322ECC3432",
INIT_36 => X"408A0CCC4E6A4C708A106E4CCC4CAA344CCC3650AC6A6A4E6C8A4A4C4EAC4C70",
INIT_37 => X"12CC704C6A8CCC4AAC684E4A52A8EC106C0C8C52CE704C8C6C6E6E7024209197",
INIT_38 => X"EE504C8C6E8A4E704C6E70504C70706C32126630908C74CA6E726CAC4CAC3488",
INIT_39 => X"EE4A0C529092ECB26A4C2ECC6C6C4E8E6CAC6E528A6E8ECE6E6E0E6C14CE8E72",
INIT_3A => X"708A70AC6E6CB08894AE908A74EA8C70506E4E4EACAC8A4A504A6E6C4C4CAA2A",
INIT_3B => X"10ACD0AE8E92748E8E70ACCC8C524C2C7012AAAEF48C906E6E328AAE0ECE32AA",
INIT_3C => X"E2E0C2E2E2E2E2E0E2E2C2C2E2C2C2C4E0E2C2E2E2C2E2E2C0C2E2E2E2E2C202",
INIT_3D => X"C2C2E00202E2C0C2C2E2E2C2E2E2E2E2E2E2C2E2E0C2C0E0E0C2E20202C2E2E2",
INIT_3E => X"E2C2E2C2E2E2C2C2E2C2E2E0E4E0C4C2E2C2C0C4E0C2E2E002E0C2E0E0C2E2E2",
INIT_3F => X"C2E2E2C2E2E0E2E2E2C2E2E2C4C2C2E2E2E202C2E2C2C2E2E2C2E0C4C2E2E2C4",
INIT_40 => X"20E0C2E2E2E2E0C2E2C2E2E2E2C2E0C4C2E2C2C4E2C2E2C2E2E000C2C2E2E2C2",
INIT_41 => X"C2E202E2C0E0E2C0E2E0C2E0C4E020C2E2C2E2E2E2E2C2E0E2C2E2C240204E97",
INIT_42 => X"E2E0C2E2C2C0E2E2C202E2C2C2E2C2E2E4C2E0C2E2E0E4E2E2C4E2E2C2E2C4E0",
INIT_43 => X"E2E2C2E2C2E220E2C0C2E2E2E2E2C2E2E202E2C4C0E2E2E2C2C2C2E2C222E2C4",
INIT_44 => X"C2E202E2C0E0E2C0E2E0C2E0C4E020C2E2C2E2E2E2E2E0E0C2E002E2C2E0E2C2",
INIT_45 => X"C2C2E2E2C2E2C4E2E2C402E2E2E2C2E2E4C2E0C2E2E0E4E2E2C4E2E2C2E2C4E0",
INIT_46 => X"E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606",
INIT_47 => X"E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6",
INIT_48 => X"E6E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6",
INIT_49 => X"E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6",
INIT_4A => X"00E6E6E606E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6",
INIT_4B => X"E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E606E6E642408E77",
INIT_4C => X"E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6",
INIT_4D => X"E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6",
INIT_4E => X"E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6",
INIT_4F => X"E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6E6E606E6E6E6E6E6E6E6E6E6",
INIT_50 => X"E80606E80608E80606E80608E80608E80608E80606E80608E80608E80608E806",
INIT_51 => X"0606080606E80606080606080606080606E80606080606E80606E80606E80606",
INIT_52 => X"E80606E806080808E82608E806E8E826080826080806080606E8060608060608",
INIT_53 => X"2608E82608E806E8E82608E82608E82608E806E8080608060608E80606E80606",
INIT_54 => X"400606E80606E80608E80608E80608E8E82608E82608E82608E806E8E82608E8",
INIT_55 => X"08E806E8E80608E80608E80608E806E8E82608E8260808E80606E80640207477",
INIT_56 => X"2608E82608E82608E806E8E8060608E80608E80608E80606E80608E80608E806",
INIT_57 => X"2608E82608E806E8E82608E826080608E806E8E82608E82608E82608E806E8E8",
INIT_58 => X"08E806E8E80608E80608E80608E806E8E82608E82608E82608E806E8E82608E8",
INIT_59 => X"0606080606080606080606E8E80608E80608E80608E80606E80608E80608E806",
INIT_5A => X"6AAA8A6AAA8A6A886A6AAA8A6AAA8A6AAA8A6A886A6ACA8A6ACA8C6AC88C6A88",
INIT_5B => X"8CCA6A6A886A8CAA6A8AAA6A8AAA6A6A886A8AAA6AAAAA6AAAAA6A6A6A6AAA8A",
INIT_5C => X"6AAA8A6AAA8A6A6A8CC86A6A886A8CC86A8CC86A8CC86A6A886A8CC86A8CC86A",
INIT_5D => X"C86A8CC86A6A886A8CC86A8CC86A8CC86A6A886A8CC86A8CC86A6AAAAA6A6A6A",
INIT_5E => X"20AA8A6A686A6AAA8A6AAA8A6AAA8A6A6AC86C6AC86C6CC86C6A886A8CC86A8C",
INIT_5F => X"8C6A886A6AC88C6AC88C6AC88C6A886A6AC86C6AC86C6A6A6A6A6AAA8420D197",
INIT_60 => X"C86A8CC86A8CC86A6A886A8CC8AA8A6AAA8A6AAA8A6A886A6ACA8C6AC88C6AC8",
INIT_61 => X"C86A8CC86A6A886A8CC86A8CC86AC88C6A886A6AC86C6CC86C6CC86C6A886A8C",
INIT_62 => X"8C6A886A6AC88C6AC88C6AC88C6A886A6AC86C6AC86C6CC86C6A886A8CC86A8C",
INIT_63 => X"8CCA6A8CAA6A8CAA6A6A886A8CAA8A6AAA8A6AAA8A6A886A6ACA8C6AC88C6AC8",
INIT_64 => X"2EB12ECE2ECE2ECE4ECE2ECE4E912ECE2ECE4ECE2ECE2ECE4E6E2EAE2ECE6ECE",
INIT_65 => X"2E6E4EEE8ECE2E8E4EF12ECE2E8E4EEE6ECE2E8E4ED12ECE2EAE2EEE4ECE2ECE",
INIT_66 => X"EE2ECE2EB12ECE6E4E4E8ECEAE8E4E4E8EF12E8E4E4E6EEE8EAE2E6E6EF12EAE",
INIT_67 => X"2E6E4E4EAECEAE6E4E4E8ECE2E8E4E4E8ECE8E8E4E4E6EF12EAEEE2EAE2EEE4E",
INIT_68 => X"002ECE2ECE4ECE2ECE4EB12ECE2ECE4E8E2ECEAE4E4E6E2EAEAEAE6E6E4EAECE",
INIT_69 => X"EE6ECE2EAE2ECE8E4E4E8E2ECE8ECE4E8E2ECEAE4E4EEE2EEE4ECE2E44209177",
INIT_6A => X"4EAECE2E6E4E4E8ECEAE8E4E2E2ECE4E912ECE2ECE4ECE2EAE2ECE6E6E2EAE2E",
INIT_6B => X"2E6E4E4EAECEAE6E4E4E8ECE2E8E4ECE8ECE4E8E2ECEAE2E4E6E2EAEAEAE6E6E",
INIT_6C => X"EE6ECE2EAE2ECE8E4E4E8E2ECE8ECE4E8E2ECEAE4E4E6E2EAEAEAE6E6E4EAECE",
INIT_6D => X"2E6E4EF12ECE2E8E4EEE6ECE2E2ECE4E912ECE2ECE4ECE2EAE2ECE6E6E2EAE2E",
INIT_6E => X"AE71AEF14E2EAE6ECE2EAE2EAE71AED14E2E8E8EAE2EAE0E8E91AEB16E0E6EAE",
INIT_6F => X"0E6E8E2EEE2EAE6E8E53AEEE0E6E8E2ECE2EAE4EAE73AEEE2E4EAE4ECE0EAE2E",
INIT_70 => X"0EAE2EAE71AEEECE2E8E4E2EEE6E8E8E6E53AECE0E8E6E2EEE4EAE8E8E53AEEE",
INIT_71 => X"AECE2EAE4E2EEE6E8E8E4E53AECE2E8E6E2EEE4EAE8E6E53AEEEF12E2EAE4ECE",
INIT_72 => X"402E2EAE6ECE2EAE2EAE71AED14E2E8E6EAE2E71AECE6EAE2E4EEE8E8EAE4E73",
INIT_73 => X"0E6ECEAE4EAE2E91AEAE918E2E6ECE8E6EAE2E71AECE6EAE4ECE0EAE84207395",
INIT_74 => X"AE4E73AECE2EAE4E2EEE6E8EAEAE2EAE91AED16E2E8E8EAE2EAE0E8E8EAEB18E",
INIT_75 => X"AECE2EAE4E2EEE6E8E8E4E53AECEAE2E4ECE8E6EAE2E71AECE4EAE2E2EEE6E8E",
INIT_76 => X"0E6ECEAE4EAE2E91AEAE918E2E6ECE8E6EAE2E71AECE6EAE2E4EEE8E8EAE4E73",
INIT_77 => X"AE6E8E53AEEE0E6E8E2ECE2EAEAE2EAE91AED16E2E8E8EAE2EAE0E8E8EAEB18E",
INIT_78 => X"8E8EAE2E4ECE314C6EAE6E84AE6EAE314ECE312C8EAE8E84AE4EAE316CCE4E0C",
INIT_79 => X"538C51AC2CCE2E2A4CAE6E4E51AC318C2CCE4EE86CAE8E2E51CE316C4CAE4EA6",
INIT_7A => X"AE4EA48E8EAE2E8E536A918EECAE2E8C08CE4E6E538C71AE0CAE2E6C2AAE4E4E",
INIT_7B => X"2E8E536A918EECAE4E8EE8CE4E6E536C71AE0CAE2E6C08CE4E4E2E51CE116C6E",
INIT_7C => X"4051CE116C6EAE6EA48E8EAE314ECE316EAE84AE2EAE516AAE8EECAE4EAEC6AE",
INIT_7D => X"CE4E0C8E8EAE84AE4EAE316CCE6EECAE6EAE84AE2EAEAE318C4CAE4E84208E77",
INIT_7E => X"AEC6AE2E8E536A918EECAE4EAE6E84AE6EAE316ECE312C8EAE8E64AE4EAE316C",
INIT_7F => X"2E8E536A918EECAE4E8EE8CE4E6E4ACE6EECAE6EAEA4AE2EAE516AAE8EECAE4E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"30C00F30C008F30008F30008C30008C3EBF33FF7F3CFF7F3FFF7F3FFF7F2FFF7",
INIT_01 => X"0C00230C0020F04D3CC0023000220C00220C00F30C00F3CC002220C00F30C00F",
INIT_02 => X"00F30C00230C00230C00230C00220C00220C00F83000883000883000230C0023",
INIT_03 => X"7010404010404004103301040401040001040001040001040C01040C00101C04",
INIT_04 => X"701040404101C04101C0411030104070104070104070414D0041030040701040",
INIT_05 => X"5555555555555555555555555555555540001050301040701040701040701040",
INIT_06 => X"555555555555554D155555555555555555555555555555555555555555555555",
INIT_07 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_08 => X"55555556455540155451545555645554645554755514055514055514D5555495",
INIT_09 => X"5555555555555555555555555355555255555655555555410155453555555555",
INIT_0A => X"5355D75355D75045D75055D75055174155474555535555525555565555555555",
INIT_0B => X"0554510554501141141175D4145135550535514535517941175C535514535517",
INIT_0C => X"5D7535575D41545D055451055451355505355144155144D55514D5575D41545D",
INIT_0D => X"5555055555055155455155505555505555515455515455515455515555515555",
INIT_0E => X"5555055555155554155554055555455555455555455554411554551545555505",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFD1555505555505555545555545555545555505",
INIT_10 => X"FFFFFFFFFFFFFF8D3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"05555FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"55555555555555555555555555555555555555555555555555555555556DA266",
INIT_13 => X"55555555555555555555555555555555555555555555550D1555555555555555",
INIT_14 => X"96BAA186BAA28ABAAEBABAAEBA07AA2A98A5B155555555555555555555555555",
INIT_15 => X"EA2ABAE92AB2AE4D2EAEABAEAABAE96A8A286A4928AA5AEAEAB89286A4968AA5",
INIT_16 => X"A2A7F3AABAEAEABAEA2ABAE92ABAE96A8A286A4BA4AAEBA5AA28A1AABAEAEABA",
INIT_17 => X"AAAAAAAAAAAAAAAA6A9AAAAAAAAAAAAAAA9AAAAA9AAAAA9AA69A9AA69A86A3CF",
INIT_18 => X"AAAAAAA9AAAA69AAAAAAAAAA9A6A6A9A6AAA9A6AAA9AA68126A6A9A6AA9A6AAA",
INIT_19 => X"000000000000000000000000000763CFA6A799AA9A6A6A9A6AAA9A6AAA9A6AAA",
INIT_1A => X"0000000000000041000000000000000000000000000000000000000000000000",
INIT_1B => X"001CC00000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000D00000D000002C00000D00000D00000E00000E00000B00000B000041BC0F",
INIT_1D => X"0000D000004000004000036C00001C0000100000100003010002C00010000010",
INIT_1E => X"00000200000200000200000E0003A2B03FA6002C00001C000010000010000010",
INIT_1F => X"00003C00003C004D00000380003C00003C00003C00002800000BC00003C00002",
INIT_20 => X"004B80003800003800003C00003C00003C00003C0000F00000F0000038000038",
INIT_21 => X"3C41043C41043C20820FC41043C420830820830820830820830820830844ED30",
INIT_22 => X"3C41043C4104F00410F104023C20823C20413C10413E084D020820C2013C1004",
INIT_23 => X"2F42002F850012B50012F44001F837B40A63C2023C20823C20413C10413C1004",
INIT_24 => X"04B10300B207ED4D04BD0000B203407303403303B433004BD4003803303B4230",
INIT_25 => X"0B70C0210007E10004B10300B20340730340330C01C80D01CC0D00E10007E100",
INIT_26 => X"147958147A542C8DC80947954247A14213A142136242236202236202237DA2EC",
INIT_27 => X"14795812B52052B56051E508088D88089D88189D481CD80D08D880888814AD48",
INIT_28 => X"410550410454414454414444004405BF0903E208088D88089D88189D4814AD48",
INIT_29 => X"0111101111105101105111005114115114115104105501051151410510410550",
INIT_2A => X"22B5045110011110011110111114115114115100454450454450415110011110",
INIT_2B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABE",
INIT_2C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA412AAAAAAAAAAAAAAA",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_2E => X"FFFFFFFFFFFFFF813FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"040EA0040FA00D01740040EA0040FE0040BE03408D03404D03805D03805C03C0",
INIT_31 => X"040EA00036C0103A80103AF40F01700B0170080DB0001340E01740E070080DB0",
INIT_32 => X"1C10800C51800C51800C51400C514048E00408F40F01700B0170080DB0080DB0",
INIT_33 => X"2245012204031460031450030401520401420401810800314500142080181080",
INIT_34 => X"0801C50501324501224501220401520401420404481005481005080501324501",
INIT_35 => X"0800020800020200014080002080002080002080002080006040005040005000",
INIT_36 => X"0800020000082000082000014100010400010400020000082000141002040002",
INIT_37 => X"D80330EC0330EC0720BC0720B80B504802080001410001040001040002040002",
INIT_38 => X"202D00103A0301C82F01C82F3A00503A00403B00803703B01C80040370180370",
INIT_39 => X"330DC01C41E02D41202D00103A00503A00403B0040E80140EC0100DC41E02D41",
INIT_3A => X"0002DF0001EF00022740002EF0005EE0004FE0008CE00089E000CAD000CAD000",
INIT_3B => X"0002DF000C7C00087C000B6B40031B00031F00031F0023780032B4001F00021F",
INIT_3C => X"9103A49102E09142E09142E05042E050FE00042B40031B00031F00031F00021F",
INIT_3D => X"410B85513E8450B82450B8247E85513E85513245103642450B805103645103A4",
INIT_3E => X"3A49100B81410B81410B85513E85513E8551324544FA1544F915400B81410B81",
INIT_3F => X"F4683CF46830FC2C0CBF46830F46831F0A431F0A431F0B031E0B032E08032E05",
INIT_40 => X"F4683CF020F3D0E0F3D1A00CB8140CF8140CF8083CF6D0C782C0CB82BCF4383C",
INIT_41 => X"00800700400B01400F01000F02000E0231F0A40CB8140CF8140CF8083CF4383C",
INIT_42 => X"0C00380C00341003C04003C0C0343C00303C00303C007C05003F03C007008007",
INIT_43 => X"007008003C0800380C00380C00343C00303C00303000D0F000C0F0003C080038",
INIT_44 => X"0330C203700001D80000330000330C20370000230000521860761850B5000085",
INIT_45 => X"03B0000C82480EC0000CC00002040002109103A0000580001086141D80032000",
INIT_46 => X"57EED19BBED29ABED76ABED769BAC2650002300002040002109103A0000320C2",
INIT_47 => X"92FB29A2EA09AFB4A8AFB5DAEA0963EA097CFE357DED1D9AFB4497CEE193DFE3",
INIT_48 => X"ED193EFB4986EB0992FB29A2EA0963FA29BCEE15CFE8A6BFA825F3BB4986EB09",
INIT_49 => X"9C5F7FAC8EFFFE217FFDC5E3FAC897FBC8BFFF964FFFA677F78837F7480BF348",
INIT_4A => X"9C5EFFF286BF7174FE7178EFCD202FCD60AFDC50BFFA11FCE20DFDD23FCC5D3F",
INIT_4B => X"D3E3C7CCF3CB8C8FEBA28FDF61CFDF347F7C88EFCD202FCD60AFDC50BFFC5E7F",
INIT_4C => X"83FDE493FAF4B3FAD863F7E847F7DC0AD3C207F3C916D3C40FF3CAFFF3C61FE7",
INIT_4D => X"FF792F3CBCC0FEBA1378F8C0FDF711FDF342B4F04AFCF28EFCF2BFFCE583FDE5",
INIT_4E => X"86991A52051995061640851643C8020EE80D25964E2956051DD8081EC8294E48",
INIT_4F => X"F08965B680C35D4594614590324991B209A1B20147760962620207760A539225",
INIT_50 => X"595D202D2E206D6A50596A505A6F1498686C84D29962589884A1965298E48284",
INIT_51 => X"4AC61649D4165AC5165A94169BC5260A84371BC92509543A1799651758552754",
INIT_52 => X"718591D206D6B14592A20AD6B14986F14982950EC5E51565E65945E61949D615",
INIT_53 => X"1826A5745B365825E8709F28B09F19F48EB2945DF5905DC6E88D96D84D94D06C",
INIT_54 => X"16CE9609A97CA1991C27CA1C27C62C2796282796BA2365382B65BA1365341B3A",
INIT_55 => X"ECD934C28928823537CD3433CD28F1C28A09E76945DD4E09EF5905DD4D06D94D",
INIT_56 => X"28AD342C4DF71D7C304D0CF34E3C70B497410B38A0F4A2821778E0D37BE0A23A",
INIT_57 => X"2B4D0C938C235B0C1C62C8138F0C228F1C3D24D041CB7D65DE3834DEF8289EF4",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \douta[2]\(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal ena_array : STD_LOGIC_VECTOR ( 16 to 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"DFADFBF77FEFFADFADFEDFFFFAB7FB7FB7FF7DFFDFFDFFD6FFFDFFDFFDFDDFDD",
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFBFFADFADFADFADFDBF5BF5BFBFFA",
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFFFFF",
INITP_04 => X"EFFDFFDFFDFFEFFEFFEFFFF77FFFFEFFEFFEFFFFFFBFFBFFBFFBFFFFFFFF7FF7",
INITP_05 => X"FFFFFFF77FF7FFFFFFFFFFDFFDFFFFFEEFEFFEFFEFFEFFFFFEFFEFFEFFEFFEFF",
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFFDFFFFFFFFFFFFFFFFFFFFFFFDFFF",
INITP_07 => X"FFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_08 => X"FFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFFFFF",
INITP_09 => X"0000000000000000000000070000000000000000000000000000000000000D7F",
INITP_0A => X"7FB7FFD77DEDFFFFFFFFFFFF7BFFFFFFFBFFBFFBFBBDBEFFFD60000000000000",
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFEAFB7FB7FB7FFFFFFFEFFFFFFFFB7FB",
INITP_0C => X"FFFFFFFFFFFFFDFFFD7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_0D => X"FBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFFFFF",
INITP_0E => X"FFBFF7FF7FF7FFBFFBFFBFF77FFFBFFBFFBFFBFFFFFEFFEFFFFFFFFFFFFFF6BF",
INITP_0F => X"FFFFFFF77FFFFFFFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFFBFFBFFB",
INIT_00 => X"CE4E0C8E8EAE84AE4EAE316CCE6EECAE6EAE84AE2EAE516AAE8EECAE4EAEC6AE",
INIT_01 => X"2E4A4AAE6E4E51AC318C2CCE2E6E84AE6EAE316ECE312C8EAE8E64AE4EAE316C",
INIT_02 => X"3191C8712E4EB12E119151933191A8710C71910C119151933171A871EC7191EC",
INIT_03 => X"71EC9171EC71715333910C4E510EB151EE7171733391EA714E2EB14E0F915173",
INIT_04 => X"9151733191C851EA71CA9171CC51713353714E0C71CC9171EC71715353912E2E",
INIT_05 => X"71EA71CA9191CA51713373714E0C71CC9171CC51713353912E2C712E2EB14E11",
INIT_06 => X"202E4EB12E119151933191A8710E51917133935171C871CA9191CA5171337371",
INIT_07 => X"7191EC319131935171A871CC9191EC319133935171C871B14E0E915144206E97",
INIT_08 => X"33737171EA71CA9191CC51713151933191A8710C71910C319151935171A871EC",
INIT_09 => X"71EA71CA9191CA51713373714E0CCA9191EA319133737171C871CA9191CA5171",
INIT_0A => X"7191EC319131935171A871CC9191EC319133935171C871CA9191CA5171337371",
INIT_0B => X"715333912C4E510C9151EE717151933191A8710C71910C319151935171A871EC",
INIT_0C => X"53D38E53D15373955373B5F153B38E53D15373B35375B3D173B58C73D15375B3",
INIT_0D => X"D1B15377935377D153F19353D1937395937395D153D19153D1737395737395F1",
INIT_0E => X"7395F153D38E536EB1D15377B15377D193F17571D1B15377B15377D173F19353",
INIT_0F => X"778EB1D15377D15377D193D17571D1B15377B15377D173F1757153D173739573",
INIT_10 => X"40D1737395537395F153B38E53D1537377D1D3B1978E93D15375D15375D1B3D1",
INIT_11 => X"5375D35375D3D193958C93D15375D15375D1D3B1978E33739573739584207477",
INIT_12 => X"D1B3D1776EB1D15377D15377D1B5F173B38E53D15375B35375B3D173958C73D1",
INIT_13 => X"778EB1D15377D15377D193D17571D15375D15375D1B3B1778EB1D15375D15377",
INIT_14 => X"5375D35375D3D193958C93D15375D15375D1D3B1978E93D15375D15375D1B3D1",
INIT_15 => X"77D173F19353D1935397935377B5F173B38E53D15375B35375B3D173958C73D1",
INIT_16 => X"7797977797777797777797977797977797777797777797977797977797777797",
INIT_17 => X"9797777797777797779797779797779797779797779797779777779777779797",
INIT_18 => X"7797977797977797979777779777779797979777979777779777779777979777",
INIT_19 => X"7797979777779777779797979797979777779777779777979777779777779777",
INIT_1A => X"2297777797777797977797977797777777979797779797977777977777979797",
INIT_1B => X"777797777797977797979797777797777797979777977777977777976640CE95",
INIT_1C => X"9797977797979777779777779797977797977797777797777797977797977797",
INIT_1D => X"7797979777779777779797979797977777977777979797779797977777977777",
INIT_1E => X"7777977777979777979797977777977777979797779797977777977777979797",
INIT_1F => X"7797779797779797777797777797977797977797777797777797977797977797",
INIT_20 => X"537777DD1153775577999977537799DDEC75777577999977557799DDCA777777",
INIT_21 => X"77CA775377779977557777DD55EE775577779977537777DD3331775577999977",
INIT_22 => X"999977537777DDBB99A6775377779977757777BB77A8775377779977557777DD",
INIT_23 => X"77BB9986775577779977757777BB99A8775377779977557777DDDD3333775577",
INIT_24 => X"223153775577999977537799DD0E5577779977757799BB867755777799777777",
INIT_25 => X"77777777999977757799BBA877557777999977757799BB77557799996800B177",
INIT_26 => X"77777777BB99867755777799999977557799DDEC77777777999977557799DDC8",
INIT_27 => X"77BB9986775577779977757777BBA877557777999977777799BB867755777799",
INIT_28 => X"77777777999977757799BBA877557777999977757799BB867755777799777777",
INIT_29 => X"9977557777DD55EC77537777999977557799DDEC77777777999977557799DDC8",
INIT_2A => X"0E9797EC77BBBB3177D5BB770EB597EC77BB995397D5BB7731B5770E77DD9755",
INIT_2B => X"7799DDEE77B5DD772E97B5EC77BBDD0E77B5DD770E9797EC77BBBB1177D5BB77",
INIT_2C => X"D5BB770E9797EC335599DD0E77B5DD775377B5117799DD0E77B5DD773197B5EE",
INIT_2D => X"B3535599DD107797DB775377B5317799DD0E77B5DD773177B50ECA77BBBB1177",
INIT_2E => X"4277BBBB3177D5BB770E9597EC77BB9975997553B5553399DD327797DB995575",
INIT_2F => X"DD775597D7997731B5771177DD557797D9997553B55575BB1177D5DD66209197",
INIT_30 => X"775575B5335599DD107795DD99BB772EB597EC77BB995397D7997731B5770E77",
INIT_31 => X"B3535599DD107797DB775377B53177DD557797D9997553B5555399DD307797DB",
INIT_32 => X"DD775597D7997731B5771177DD557797D9997553B5553399DD327797DB995575",
INIT_33 => X"DD772E97B5EC7799DD0E77B5DDBB772EB597EC77BB995397D7997731B5770E77",
INIT_34 => X"779797537799997777B7F997779797557799997777B9F7977797775577999977",
INIT_35 => X"779999777797FDB577979753779999777797FDB577979753779999777797FB97",
INIT_36 => X"B7FB977797975375779999997797FDD377779755779999997797FDD377979755",
INIT_37 => X"9777779999997797FDD377779755779999997797FDD377979755537799997777",
INIT_38 => X"427799997777B7F99777979753779999BBF377779777779999997797DDD37777",
INIT_39 => X"99997797B9F577779777557799997797DBF3777797777799777797FB84209177",
INIT_3A => X"D377779777779999997797FDF3F997779797557799997797B9F7977797775577",
INIT_3B => X"9777779999997797FDD3777797557799997797DBF377779777779999997797DD",
INIT_3C => X"99997797B9F577779777557799997797DBF377779777779999997797DDD37777",
INIT_3D => X"FDD377979755779999777797FFF997779797557799997797B9F7977797775577",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8455555555555555555555",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"22FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88204E95",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"55535555555555555544FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"444444444444444444444444444444444444444477B9EE77EA99FF995599DD99",
INIT_49 => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_4A => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_4B => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_4C => X"0044444444444444444444444444444444444444444444444444444444444444",
INIT_4D => X"4444444444444444444444444444444444444444444444444444444400209077",
INIT_4E => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_4F => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_50 => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_51 => X"999999FF9999C677A8FF11444444444444444444444444444444444444444444",
INIT_52 => X"BBBB0EBBBBEEBBBBBBECBBBBBBBBECBBBBECBBBB113397CCDDDDBBBB53BBBBBB",
INIT_53 => X"BB5577BBBBEEBBBBBBBB5377BB3397BBBBECBBBBBBBB3199BB1199BBBBECBBBB",
INIT_54 => X"ECBBBBBBBBEE9931BB9731BBBB3397BBBBBB7753BB7755BBBB1199BBBBBB5577",
INIT_55 => X"9911BB9931BBBB5377BBBBBB7733BB7733BBBB3199BBBBBB7755BBBB0E99BBBB",
INIT_56 => X"22BB0EBBBBBBECBBBBBBBBECBBBBECBBBBBBBBBB990EBB990EBBBB7575BBBBBB",
INIT_57 => X"ECBBBB9931BBBBBBBBECBB99ECBBBB7733BBBBBB990E3199BBBBECBB6620B297",
INIT_58 => X"BBBBBB9931BB9931BBBB5377BBBBBBBBBBECBBBBECBBBB990EBBBBBBBBECBBBB",
INIT_59 => X"9911BB9931BBBB5377BBBBBB773399ECBBBB7753BBBBBB990EBB990EBBBB5577",
INIT_5A => X"ECBBBB9931BBBBBBBBECBB99ECBBBB7733BBBBBB990EBB990EBBBB7575BBBBBB",
INIT_5B => X"DDDD11BBBBBBBBEEDDEE55ECBBBBBBBBBBECBBBBECBBBB990EBBBBBBBBECBBBB",
INIT_5C => X"BBBB97BBBB97BBBBBB77BBBBBBBB77BBBB77BBBBBB337799CCEEDD7676FFB6B8",
INIT_5D => X"BBB9BBBBBB97BBBBBBBB99BBBB99BBBBBB77BBBBBBBB99BBBB99BBBBBB77BBBB",
INIT_5E => X"77BBBBBBBB97BB99BBBB99BBBB99BBBBBBBBBB99BBBBB9BBBB99BBBBBBBBBBBB",
INIT_5F => X"BB99BBBB99BBBB99BBBBBBBBBB99BBBB99BBBB99BBBBBBBBBBBBBBBB99BBBBBB",
INIT_60 => X"22BB97BBBBBB77BBBBBBBB77BBBB77BBBBBBBBBBBB97BBBB97BBBBBBBBBBBBBB",
INIT_61 => X"77BBBBBB99BBBBBBBB77BBBB77BBBBBB99BBBBBBBB9799BBBBBB77BB8A00D177",
INIT_62 => X"BBBBBBBB99BBBB99BBBB99BBBBBBBBBBBB77BBBB77BBBBBB97BBBBBBBB77BBBB",
INIT_63 => X"BB99BBBB99BBBB99BBBBBBBBBB99BB97BBBBBB99BBBBBBBB97BBBB97BBBBBBBB",
INIT_64 => X"77BBBBBB99BBBBBBBB77BBBB77BBBBBB99BBBBBBBB97BBBB97BBBBBBBBBBBBBB",
INIT_65 => X"BBBB97BBBBBB88DDAA77DD77BBBBBBBBBB77BBBB77BBBBBB97BBBBBBBB77BBBB",
INIT_66 => X"FFFFFFF3F9F1FFFFF3F1F1FDFFFFFFF3F7F1FFFFFFFFCCDD7754FFFEFEFFFEFE",
INIT_67 => X"FFF1FDFFF9F1F1F7FFFFFFF3FDF1FDFFF7F1F1F9FFFFFFF3FBF1FFFFF5F1F1FB",
INIT_68 => X"F1F1FDFFFFFFF3F9FDF1F7FFFDF1F1F3FFFFFFF7FDF1F9FFFBF1F1F5FFFFFFF5",
INIT_69 => X"FFFBFDF1F7FFFDF1F1F3FFFFFFF9FDF1F9FFFDF1F1F5FFFFFFF5F1FBF1FFFFF5",
INIT_6A => X"22FBF1FFFFF3F1F1FDFFFFFFF3F9F1FFF7F1FFFFFFFDF9F1F5FFFFF1F1F1FFFF",
INIT_6B => X"F1FFFFF1F1F1FFFFFFFDF7F3F3FFFFF1F1F1FFFFFFFDF1FFFFF5F1F184209177",
INIT_6C => X"F1FFFFFFF9FDF1F7FFFDF1F1F1F1FDFFFFFFF3F7F1FFFFF1F1F1FFFFFFFFF5F5",
INIT_6D => X"FFFBFDF1F7FFFDF1F1F3FFFFFFF9F1F3FFFFF1F1F1FFFFFFFBFBF1F5FFFFF1F1",
INIT_6E => X"F1FFFFF1F1F1FFFFFFFDF7F3F3FFFFF1F1F1FFFFFFFDF9F1F5FFFFF1F1F1FFFF",
INIT_6F => X"FFFFFFFFFF66FF3398FDF1F1F1F1FDFFFFFFF3F7F1FFFFF1F1F1FFFFFFFFF5F5",
INIT_70 => X"F1FBFDFFFFFFFFF7FFFF52ACF3F9FFFFFFFFFDF988FFFF88BBEE98FDF3F36E98",
INIT_71 => X"FFFFFFF5FDFFDC08F1FFF9FFFFFFFFF5FFFFB84AF1FDFBFFFFFFFFF7FFFF768C",
INIT_72 => X"FF74ACF1FBFDFFFFFFFFFFF5FDFFFEA4F1FDF5FFFFFFFFF5FDFFFEC6F1FFF7FF",
INIT_73 => X"F5FFFFFFFFF5FDFFFEA4F1FDF5FFFFFFFFF5FDFFFEC6F1FFF7FFFFFFFFFFF7FF",
INIT_74 => X"62FFFFFFF7FFFF52ACF3FBFDFFFFFFFDF9A6F1F9F5FFFFFFFFF7FDFFFF84F1FB",
INIT_75 => X"FFFBFBFFFFA8F1F7F5FFFFFFFFF9FBFFFFA6F1F9F5FFFFFFF5FFFF9600209397",
INIT_76 => X"84F1FDF5FFFFFFFFF5FDFFFEA630CEF3F9FFFFFFFFFDF9FFFFECEEF5F7FFFFFF",
INIT_77 => X"F5FFFFFFFFF5FDFFFEA4F1FDF5FFFFFFF9FBFFFF86F1F9F5FFFFFFFFF7FDFFFF",
INIT_78 => X"FFFBFBFFFFA8F1F7F5FFFFFFFFF9FBFFFFA6F1F9F5FFFFFFFFF7FDFFFF84F1FB",
INIT_79 => X"F576B69832BB770EF5FFFFFFFF30CEF3F9FFFFFFFFFDF9FFFFECEEF5F7FFFFFF",
INIT_7A => X"F9F7FD0EF7F7FFF9FDFFF7F9F9F7FE10F7F7FFF7FFFFFBFE1099333232FEFBFF",
INIT_7B => X"F7F7FDFFF7FFF7F9F9F7FB10F7F7FFFDF9FFF7F9F9F7FD10F7F7FFFBFBFFF7F9",
INIT_7C => X"FFF7F9F9F7FF1098D4F7FBFFF3FFF9F9F9F7F954F6F7FDFFF5FFF7F9F9F7FB32",
INIT_7D => X"F798B4F7FBFFF3FFF9F9F9F7F976D4F7FBFFF3FFF9F9F9F7F954EEF7F7FFFBFB",
INIT_7E => X"42F7F7FFF9FDFFF7F9F9F7FE0EF7F7FFFBF9F9F7F7BA92F7F9FFF1FFF9F9F9F7",
INIT_7F => X"F7FFF3FFFDF9F9F9F7DC72F7F9FFF3FFFBF9F9F7F7BA92FFFBFBFFF786206E97",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(16),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(15),
I1 => addra(14),
I2 => addra(16),
I3 => addra(12),
I4 => addra(13),
O => ena_array(16)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal ena_array : STD_LOGIC_VECTOR ( 17 to 17 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFF7BFEF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_01 => X"FFFFEFFEFFEFFFD7DFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_02 => X"F7FDFFDFFDFFDFFDFFDFFBFFBFFDFFDFFDFFDFF77F7FDFFDFFDFFFFFDFFFFFFF",
INITP_03 => X"EFFDFFDFFDFFFFFEFFEFFFF77FFFFEFFEFFEFFFFFFBFFBFFBFFFFFFFFFFFFEEB",
INITP_04 => X"000000070000000000000000000000000000000000000007AFFFFFFEFFEFFEFF",
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEC0000000000000000000000000000000",
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFF",
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FFFFFFFFFFFFFFFFFFFFFFF",
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0C => X"FFFFFFFFFFFFFEFFEFFDFFDFFDFFFFFFFFFFFFFFFFFFFEFFEFFFFFFFFFBFFFFF",
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_00 => X"F9F9F7F998D4F7FBFFF3FFF9F9F7F9F9F7FE30F7F7FFF7FFFDF9F9F9F7FE50F7",
INIT_01 => X"F798B4F7FBFFF3FFF9F9F9F7F976D4F9FFF3FFFBF9F9F7F7BA94F7F9FFF1FFF9",
INIT_02 => X"F7FFF3FFFDF9F9F9F7DC72F7F9FFF3FFFBF9F9F7F7BA92F7F9FFF1FFF9F9F9F7",
INIT_03 => X"FFFBFB0077333294ECFFFBFFF7F7F9F9F7FE30F7F7FFF7FFFDF9F9F9F7FE50F7",
INIT_04 => X"FFFDFFB8FDFDFFFFFFFFFFFFFFFDFFBAFDFDFFFF88FFFDFFFECCFF5532FEFDF7",
INIT_05 => X"FDFDFFFFFDFFFDFFFFFDFFBAFDFDFFFFFFFFFDFFFFFDFFBAFDFDFFFFFFFFFDFF",
INIT_06 => X"FFFDFFFFFDFFBADCFCFDFFFFFDFFFDFFFFFDFDDCFCFDFFFFFDFFFDFFFFFDFDBA",
INIT_07 => X"FDDCFCFDFDFFFDFFFDFFFFFDFDDCFCFDFFFFFDFFFDFFFFFDFDBA98FDFDFFFFFF",
INIT_08 => X"22FDFDFFFFFFFFFFFFFFFDFFBAFDFDFFFFFFFFFFFDFEDAFDFDFFFDFFFDFFFFFD",
INIT_09 => X"FDFFFDFFFFFFFFFFFDFEDAFDFDFFFDFFFFFFFFFFFDFEDAFFFFFFFFFD88208E77",
INIT_0A => X"FFFFFDFDDCFCFDFFFFFDFFFDFFFFFFFFFDFEBAFDFDFFFDFFFFFFFFFFFDFEBAFD",
INIT_0B => X"FDDCFCFDFDFFFDFFFDFFFFFDFDDCFCFDFFFDFFFFFFFFFDFDFEDAFDFDFFFDFFFD",
INIT_0C => X"FDFFFDFFFFFFFFFFFDFEDAFDFDFFFDFFFFFFFFFFFDFEDAFDFDFFFDFFFDFFFFFD",
INIT_0D => X"FFFDCCBB7754FFDC98FFFFFFFDFFFFFFFDFEBAFDFDFFFDFFFFFFFFFFFDFEBAFD",
INIT_0E => X"FEFFFFF3FFFEFFFEFEF2FE66FEFFFFF3FFFEFFFEF0F4FEF3FBF844FFAADC2AFF",
INIT_0F => X"FFFEFEFEFEF5FE32BAFFFFF3FFFEFEFEFEF3FEEEDCFFFFF3FFFEFFFEFEF2FE88",
INIT_10 => X"F2FE88FEFFFFF3F9FDFEFEFFFEF9FCBA10FEFFF7FFFEFEFEFEF7FE7676FEFFF5",
INIT_11 => X"FFFBFDFEFEFFFEF9FCBAEEFEFFF9FDFEFEFEFEF7FE9854FEFFF7F1FFFEFFFEFE",
INIT_12 => X"62FFFEFFFEFEF2FE66FEFFFFF3FFFEFFFEFE88FEFFFDFBFEFEFFFEFBFADCAAFE",
INIT_13 => X"FEFFFEFFF6FE44FEFFFDF7FEFEFFFEFDF8FE88FEFFFDFAFEFEFEF2FE88207677",
INIT_14 => X"DCCCFEFFFBFDFEFEFFFEF9FCFEFE66FEFFFFF5FFFEFFFEFEF4FE44FEFFFFF5FF",
INIT_15 => X"FFFBFDFEFEFFFEF9FCBAEEFEFFF9FCFEFFFEFDF8FE88FEFFFBFBFEFEFFFEFBFC",
INIT_16 => X"FEFFFEFFF6FE44FEFFFDF7FEFEFFFEFDF8FE88FEFFFDFBFEFEFFFEFBFADCAAFE",
INIT_17 => X"FF3377DDCCFEF3F9FCFEFFF3FEFE66FEFFFFF5FFFEFFFEFEF4FE44FEFFFFF5FF",
INIT_18 => X"FEFEFEFE76BAFEF8FEFEFEFEFEFEFEFE32DCFCFAFEFEF888FEFEFEAAFE88BAFF",
INIT_19 => X"DCEEFEF4FEFEFEFEFEFEFEFEBA32FEF4FEFEFEFEFEFEFEFE9876FEF6FEFEFEFE",
INIT_1A => X"FEFEFEFEFEFEFEFEFEAAFEF4FEFEFEFEFEFEFEFEFECCFEF4FEFEFEFEFEFEFEFE",
INIT_1B => X"FEFEFE88FEF4FEFEFEFEFEFEFEFEFEAAFEF4FEFEFEFEFEFEFEFEFE9898FEF6FE",
INIT_1C => X"2276BAFEF8FEFEFEFEFEFEFEFE32DCFCF8FEFEFEFEFEFE88FEF6FEFEFEFEFEFE",
INIT_1D => X"FEFAFCFEFEFEFEFEFEFEFEAAFEF8FEFEFEFEFEFEFEFEFEFEF6FEFEFE8A20CE97",
INIT_1E => X"FEFEFEFEFEFE88FEF4FEFEFEFEFEFEFEFEFEFE10DCFCFAFEFEFEFEFEFEFEFECC",
INIT_1F => X"FEFEFE88FEF4FEFEFEFEFEFEFEFEAAFEF8FEFEFEFEFEFEFEFEFE88FEF6FEFEFE",
INIT_20 => X"FEFAFCFEFEFEFEFEFEFEFEAAFEF8FEFEFEFEFEFEFEFEFE88FEF6FEFEFEFEFEFE",
INIT_21 => X"76EFBB88FFFFFFFEF4FEFEFEFEFEFEFEFEFEFE10DCFCFAFEFEFEFEFEFEFEFECC",
INIT_22 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEAAAAFF10BA",
INIT_23 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_24 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_25 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_26 => X"00EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_27 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE4420B177",
INIT_28 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_29 => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_2A => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_2B => X"339922EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE",
INIT_2C => X"9999999999999999999999999999999999999999999999999999999999FFDDAA",
INIT_2D => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_2E => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_2F => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_30 => X"4299999999999999999999999999999999999999999999999999999999999999",
INIT_31 => X"9999999999999999999999999999999999999999999999999999999966209397",
INIT_32 => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_33 => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_34 => X"9999999999999999999999999999999999999999999999999999999999999999",
INIT_35 => X"FFDD999999999999999999999999999999999999999999999999999999999999",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"62FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88409177",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FDFBF1F0A8FDFFFF88F5FFF5FDF9F1F0AAFFFFFF66F5FFF5FDF7F1CECEFFFFFD",
INIT_41 => X"64F7FFFFD2CEFDFBFBFFF1F264F9FFFFAEF1FDF9FBFDF1F286FBFFFF8AF3FDF7",
INIT_42 => X"F5FDF7FDFBF1F3F186F5FFFFF8AAFBFDF9FFF3F164F7FFFFD6CCFDFDF9FFF3F3",
INIT_43 => X"F3F186F5FFFFF8A8FBFFF7FFF3F164F5FFFFD6ACFBFDF9FFF3F3F286FDFFFF88",
INIT_44 => X"F088FDFFFF88F5FFF5FDFBF1F0AAFFFFFFFFF5FFF5F1A8F3FFFFFA86F9FFF7FF",
INIT_45 => X"FFFFFD64F7FFF5FFF5F1AAF1FFFFFC86F9FFF5FFF5F1FBFFFF8CF3FDF7FDFBF1",
INIT_46 => X"FFF7FFF3F186F5FFFFF8AAFBFFFFF5FDF9F1CEACFFFFFD64F5FFF5FDF7F1CECE",
INIT_47 => X"F3F186F5FFFFF8A8FBFFF7FFF3F1F3FFFFFC86F9FFF5FFF3F188F3FFFFFA88FB",
INIT_48 => X"FFFFFD64F7FFF5FFF5F1AAF1FFFFFC86F9FFF5FFF5F1A8F3FFFFFA86F9FFF7FF",
INIT_49 => X"FDFBFBFFF3F364F9FFFFB0F1FDFFF5FDF9F1CEACFFFFFD64F5FFF5FDF7F1CECE",
INIT_4A => X"F9FFFBFFFBF9FFFDF9FFFDFFF9FFF9FFFDF9FFFBF9FFFDFFFBFFF9FDFDF9FFFB",
INIT_4B => X"F9FDFDFFF9FFF9FFFBFFFDFFF9FBFFFFF9FFFBFFF9FFFBFFFBFBFFFDF9FFFBFF",
INIT_4C => X"FFFBFFF9FFFBFFFBFBFFFBFFF9FDF9FFFDFFFFFDF9FDFDFFF9FDF9FFFBFFFDFF",
INIT_4D => X"FFFBFBFFFBFFF9FBFBFFFDFFFFFDF9FFFBFFF9FDF9FFFBFFFFFDFFFBF9FFFDF9",
INIT_4E => X"FFFBF9FFFDF9FFFBFFF9FFFBFFFDF9FFFDFFFFFDFFFBFBFFF9FFF9FBFBFFFDFF",
INIT_4F => X"F7FFFBF9FDFFFFFBFFF9FDFFF9FFF9FBFDFFFFFDFFFBFBFFFFF9FFFBFFF9FFFB",
INIT_50 => X"FFFDFFFFFBFBFFFBFFF9FDFBFFFDFFFBFFF9FFFDF9FFFBF9FFFDFFFBFFF9FDFF",
INIT_51 => X"FFFBFBFFFBFFF9FBFBFFFDFFFFFDFFF9FFF9FBFBFFFFFDFFFBFBFFF9FFF9FBFB",
INIT_52 => X"F7FFFBF9FDFFFFFBFFF9FDFFF9FFF9FBFDFFFFFDFFFBFBFFF9FFF9FBFBFFFDFF",
INIT_53 => X"F9FFFBFFFDFFF9FDFFFFF9FFF9FDFFFBFFF9FFFDF9FFFBF9FFFDFFFBFFF9FDFF",
INIT_54 => X"FFFFFFFFFFFDF5FFFFFFFFFFFFFFFFFFFFFDF5FFFFFFFFFFFFFFFFFFFFFDF7FF",
INIT_55 => X"FFFFF5FFFFFFFFFFFFFFFFFFFFFFF5FFFFFFFFFFFFFFFFFFFFFDF5FFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFF9FDFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFF9FDFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFDF5FFFF",
INIT_58 => X"FFFFFDF5FFFFFFFFFFFFFFFFFFFFFDF5FFFFFFFFFFFFFFFFFBFBFFFFFFFFFFFF",
INIT_59 => X"FBF7FFFFFFFFFFFFFFFFFFFFFBF9FFFFFFFFFFFFFFFFFDF5FFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFF9FDFFFFFFFFFFFFFFFFFFFFFFFDF7FFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFF9FDFFFFFFFFFFFFFFFFFFFBF9FFFFFFFFFFFFFFFFFFFFF9FDFFFFFF",
INIT_5C => X"FBF7FFFFFFFFFFFFFFFFFFFFFBF9FFFFFFFFFFFFFFFFFFFFFBFBFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFF5FFFFFFFFFFFFFFFFFFFFFFFDF7FFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFF394ACFFFFFFFFFFFFFFFFFFF34ECEFFFFFFFFFFFFFFFFFFF52AF1FFFF",
INIT_5F => X"FC26FBFFFFFFFFFFFFFFFFF3DA68FDFFFFFFFFFFFFFFFFF3B68AFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFF3F9FDE2F7FFFFFFFFFFFFFFFFF7FD04F9FFFFFFFFFFFFFFFFF5",
INIT_61 => X"FFFBFDE2F7FFFFFFFFFFFFFFFFF9FD04F9FFFFFFFFFFFFFFFFF7F1B6ACFFFFFF",
INIT_62 => X"F394ACFFFFFFFFFFFFFFFFFFF370CEFFFFFFFFFFFFFDFBE4F5FFFFFFFFFFFFFF",
INIT_63 => X"F3FFFFFFFFFFFFFFFFFDF706F3FFFFFFFFFFFFFFFFFDF1FFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFBFDE2F7FFFFFFFFFFFFFFFFFFFFF54EEEFFFFFFFFFFFFFFFFFFF508",
INIT_65 => X"FFFBFDE2F7FFFFFFFFFFFFFFFFF9E4F3FFFFFFFFFFFFFFFFFBFBE2F5FFFFFFFF",
INIT_66 => X"F3FFFFFFFFFFFFFFFFFDF706F3FFFFFFFFFFFFFFFFFDFBE4F5FFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFF5DC48FDFFFFFFFFFFFFFFFFFFF54EEEFFFFFFFFFFFFFFFFFFF508",
INIT_68 => X"FFFBF3FFF7FFFDFFFFFF8CDBFFF9F3FDF9FFFDFFFFFD6AFFFFF7F3FBFBFFFDFD",
INIT_69 => X"F1FFFDFFFDFFD070FFFFF3FDF3FFFDFFFFFFD095FFFDF3FFF5FFFDFFFFFFAEB9",
INIT_6A => X"FFAEDBFFFBF3FFF9F3FFFFFFFDFFF42AFFFFF3FBF3FFFDFFFDFFF24CFFFFF3FD",
INIT_6B => X"F3F7F3FFFFFFFDFFF42AFFFFF3F9F3FFFFFFFDFFF22CFFFFF3FBFFF5FFFDFFFF",
INIT_6C => X"FFF5FFFDFFFFFF8CDBFFFBF3FDF7FFFDF928FFFFF5F7F7FFFFFFFDFFF708FFFF",
INIT_6D => X"FFFDFDFFFB28FFFFF5F5F9FDFFFFFDFFF928FFFFF5F7FFFDFFFFFFAEB9FFFBF3",
INIT_6E => X"08FFFFF3F9F3FFFFFFFDFFF4288CDDFFF9F3FDF9FFFDFDFFFD4AFFFFF7F5FBFB",
INIT_6F => X"F3F7F3FFFFFFFDFFF42AFFFFF3F9FFFFFFFDFFF908FFFFF5F7F5FFFFFFFDFFF7",
INIT_70 => X"FFFDFDFFFB28FFFFF5F5F9FDFFFFFDFFF928FFFFF5F7F7FFFFFFFDFFF708FFFF",
INIT_71 => X"F24EFFFFF3FDF3FFFDFFFFFFF38CDDFFF9F3FDF9FFFDFDFFFD4AFFFFF7F5FBFB",
INIT_72 => X"FFFFF9FFFBFFF9FDFFF9FB70FFFFF9FFFDFFFBFBFFF9FB6EFFFFF9FDFDFFFBFB",
INIT_73 => X"F9FFFBFFFBF9FFB2DDFFFBFFF9FFF9FFFDF9FF92FFFFFBFFFBFFF9FDFDF9FD70",
INIT_74 => X"F7FD70FFFFF9FFFBFBFFFDFFF9FBFFD4B7FFFFFDF9FFFBFFFBFBFFD4DBFFFDFD",
INIT_75 => X"FFFBFBFFFDFFF9FDFFF497FFFFFBF9FFFDFFFBFBFFD4B9FFFDFDFFFBFFF9FDFF",
INIT_76 => X"FFFBFFF9FDFFF9FD70FFFFF9FFFDFFFBFFF672FFFFF9FBFFFFFDF9FDFDF694FF",
INIT_77 => X"FFFBFBFFFBF970FFFFF9FDFFFFFDF9FFFBF672FFFFF9FFF9FFFDF9FD90FFFFF9",
INIT_78 => X"F694FFFFFBFBFFFDFFF9FBFFF9FB6EFFFFF9FFFDFFFBFBFFF9FB6EFFFFF9FDFF",
INIT_79 => X"FFFBFBFFFDFFF9FDFFF497FFFFFBFFFFFDF9FFFDF672FFFFF9FBFFFDFDF9FDFD",
INIT_7A => X"FFFBFBFFFBF970FFFFF9FDFFFFFDF9FFFBF672FFFFF9FBFFFFFDF9FDFDF694FF",
INIT_7B => X"FFD4DBFFFDFFF9FFFBFFFDF9FFFB6EFFFFF9FFFDFFFBFBFFF9FB6EFFFFF9FDFF",
INIT_7C => X"FFFFFDFFFFF5DD70FFF3FFCEFFFFFDFFFFF5DB95FFF3FDCEFFFFFDFFFFF5B7B9",
INIT_7D => X"FFFBFD08FFF3FFF6FDFFFFFFFFF9FD2AFFF3FFD2FFFFFDFFFFF7FD4CFFF1FFD0",
INIT_7E => X"F1FFD0FFFFFDFFFFFFFFF92AFFF9FDF8F7FFFFFFFFFDFB08FFF5FFF8FBFFFFFF",
INIT_7F => X"FFFDFFFFF92AFFF9FDFAD4FFFFFFFFFDF92AFFF7FFF8F9FFFFFFFFFFF7FD4EFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(17),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(15),
I1 => addra(14),
I2 => addra(13),
I3 => addra(12),
I4 => addra(16),
O => ena_array(17)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized22\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized22\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized22\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized22\ is
signal ena_array : STD_LOGIC_VECTOR ( 18 to 18 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_04 => X"FFBFFFFEFFFFFFEFFFF6FF67FF7FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_05 => X"FEFFFFFFBBFFBFFFFFFFFEFFEBFEFFEBFFFFD7FDFFFFFEFFEBFEFFBFFBFFFFEF",
INITP_06 => X"FDBFFFFDBFFFFFFFFF7FFDEFFB7FB7FB7FB7DDFFB7DDFFFEFFFF6EFFFF6FF6FB",
INITP_07 => X"FFFEFFFF7FF7FF7FF7FFFFFFFFFFFFFFFDEFFFBDEFFEFFFFFFBFFBBFFFFFFDFF",
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFFBFFEFFFFFEEFFFF7",
INITP_09 => X"DBFFFFDBDFFDFFDFFFFFFFFCFFEFFFFFFFFFFFFFFFFFFFFFFFFFFEDFFFFFFFFF",
INITP_0A => X"FDFFCFFFFFFFFFB77FFFFF7FFFFFFFFFFFEDFBFEFFEFFEFFEFFEFFEFFE7FFFFF",
INITP_0B => X"F6F7FFFFF3FFEDFEDFBFFFFFEDFEDFEDFEDFFFFFFFFFFDBF7FFDBD7FFDBFDBFF",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFF7FD70FFF3FFCEFFFFFDFFFFF5DB92FCD0FFFFFDFFFFF74EFFFBFBFAD2FF",
INIT_01 => X"F5B7DBFFF7FDCEFFFFFDFFFFF593DDFDF9FCD0FFFFFDF9FD4CFFF1FFD0FFFFFD",
INIT_02 => X"FAD2FFFFFDFFFFF92AFFF9FDFDFFCEFFFFFDFFFFF5D997FFF5FDCEFFFFFDFFFF",
INIT_03 => X"FFFDFFFFF92AFFF9FDFAD4FFFFFFFFF573FDFDF9FCD0FFFFFDFFFFF74EFFFBFB",
INIT_04 => X"F5B7DBFFF7FDCEFFFFFDFFFFF593DDFDF9FCD0FFFFFDFFFFF74EFFFBFBFAD2FF",
INIT_05 => X"FFF6FBFFFFFFFFFBFD2AFFF3FFFFCEFFFFFDFFFFF5D997FFF5FDCEFFFFFDFFFF",
INIT_06 => X"FFFBFDFFFFFFFFFFFFFDF7FFFFF9FDFFFFFFFFFFFFFBFBFFFFF7FFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFF3FFFFFDF7FFFFFFFFFFFFFFF5FFFFFDFBFFFFFFFFFFFFFFF5FF",
INIT_08 => X"FDF7FFFFFBFDFFFFFFFFFFFEFFFFF3FFFFFFF5FFFFFFFFFFFFFFF3FFFFFFF5FF",
INIT_09 => X"F3FFFFFFFFFEFFFFF3FFFFFFF3FFFFFFFFFEFFFFF3FFFFFFF5FFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFDF7FFFFF9FDFFFFFFFFF6FFFFFFF3FFFFFFFFFEFFFFF5FFFFFF",
INIT_0B => X"FFFFFFFFF9FDFFFFF3FFFFFFFFFFFFFFF7FFFFFFF3FFFFFFFFFFFFF5FFFFFBFD",
INIT_0C => X"FFFFFFF3FFFFFFFFFEFFFFF3FDF9FFFFF7FFFFFFFFFFFFFFFBFBFFFFF5FFFFFF",
INIT_0D => X"F3FFFFFFFFFEFFFFF3FFFFFFF3FFFFFFFFFFFFF7FFFFFFF3FFFFFFFFFEFFFFF5",
INIT_0E => X"FFFFFFFFF9FDFFFFF3FFFFFFFFFFFFFFF7FFFFFFF3FFFFFFFFFEFFFFF5FFFFFF",
INIT_0F => X"F3FFFFFFF7FFFFFFFFFFFFFFF1F9FFFFF7FFFFFFFFFFFFFFFBFBFFFFF5FFFFFF",
INIT_10 => X"FFFFFFFFF9FDF5FFFDFFFFFFFFFFFFFDF9FDF5FFFDFFFFFFFFFFFFFDFDFDF7FF",
INIT_11 => X"F5FFF5FFFFFFFFFFFFFFFFFFF5FFF5FFFFFFFFFFFFFFFFFFF7FFF5FFFDFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFF5FFF9FDFFFFFFFFFFFFFFFFF5FFF7FFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFF7FFF9FDFFFFFFFFFFFFFFFFF5FFF7FFFFFFFFFFFFFFFFFFFFF7FDF5FFFD",
INIT_14 => X"FFF7FDF5FFFDFFFFFFFFFFFFFDF9FDF5FFFFFFFFFFFFF9FFFBFBFFFDFFFFFFFF",
INIT_15 => X"FBF7FFFDFFFFFFFFFFFFFBFDFBF9FFFDFFFFFFFFFFFFFDF5FFFDFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFF5FFF9FDFFFFFFFFFFFFFFFFFFFDFBFDF7FFFDFFFFFFFFFFFFFBFD",
INIT_17 => X"FFFFF7FFF9FDFFFFFFFFFFFFFFFFFFFDF9FFFDFFFFFFFFFFFFF7FFF9FDFFFDFF",
INIT_18 => X"FBF7FFFDFFFFFFFFFFFFFBFDFBF9FFFDFFFFFFFFFFFFF9FFFBFBFFFDFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFF5FFF5FFFFFFFFFFFFFFFFFFFDFBFDF7FFFDFFFFFFFFFFFFFBFD",
INIT_1A => X"FFFFFFFF55FBDD55FAFFFFFFFFFFFFDD77F9DD99F8FFFFFFFFFFFFFFFFF9FFFF",
INIT_1B => X"EFFDFF11FCFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFAFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFDFFFEFDFFFFFFFFFFFFFFFFFDFFFEFDFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFBFFFEFBFFFFFFFFFFFF11FFFD11FEFDFFFFFFFFFFFFFF33FBFF55FA",
INIT_1E => X"FFFFFBFFFFFAFFFFFFFFFFFFDD77F9DD77FFFFFFFFFFFFFFFBFFFFFAFFFFFFFF",
INIT_1F => X"F9FFFFF8FFFFFFFFFFFF77DDF977DDFAFFFFFFFFFFFFFBFF33FAFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFBFFFEFDFFFFFFFFFFFFFFFFFFF9FFFFF8FFFFFFFFFFFFFFFF",
INIT_21 => X"FFFF33FFFB33FEFBFFFFFFFFFFFFFFFFFFFFFAFFFFFFFFFFFF55FFFB33FEFAFF",
INIT_22 => X"F9FFFFF8FFFFFFFFFFFF77DDF977DDFAFFFFFFFFFFFFFFFFFBFFFFFAFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFDFFFFFCFFFFFFFFFFFFFFFFFFF9FFFFF8FFFFFFFFFFFFFFFF",
INIT_24 => X"DDFFF7FF77D3FFD7A8FF55BBDDFFF5FF77F3FFD588F7FFFFFFFFF5FFFFF5FFF7",
INIT_25 => X"9973FDB96EB0FFFFFFFFFFFFABFFFFA92CD3FFFFFFFFFFFFCDFFFFCBEAFF7799",
INIT_26 => X"F5FFFFFFFFFFFFF9FFFFF9FFB02CFFFFFFFFFDFBFFFDFBFF8E77FFCDDDFFFBFD",
INIT_27 => X"FFF7FFFFF9FFD010FFABFFFFFDF9BB53F9BBB04CFFFFFFFFFFFFFF77D3FFB7C8",
INIT_28 => X"FFFFF7FFFBA8FF55BBDDFFF5FF77F3FFDDFFFFFFFFF7FFFFF7FFF2CAFDFFFFFF",
INIT_29 => X"F5FFF788FFABFFFFFFF5DD55F5DDF3A8F9FFFFFFFFFFF9FFB7EAF3FFFFFFFFF7",
INIT_2A => X"FFFFFFFFF9FFFFF9FFD02CFDFFFFFFFFFFF5FFFFF5FFF986F7FFFFFFFFF5FFFF",
INIT_2B => X"FFF7BB53F9BBD00AFDFFFFFFFFFFFFFF33D1AAFF89FFFFFFF7BB53F7BBD2EAFD",
INIT_2C => X"F5FFF788FFABFFFFFFF5DD55F5DDF3A8F9FFFFFFFFFFFFFFF7FFF2CCFF89FFFF",
INIT_2D => X"FFFFFFFFFBFDFFFBFDFF4CB1FFFFFFFFFFF5FFFFF5FFF986F7FFFFFFFFF5FFFF",
INIT_2E => X"DDCD5FFFFF67FFFF3FDF7F3FBB113FFFFF45FFFFFEFFFFFFFFFFFF7777FF7797",
INIT_2F => X"FF5599FFFEFFCFEFDDF3FFFFDD99FFF3FEFF8D33DDF5FFFFBBBBFFF35FFF5F5F",
INIT_30 => X"FFFFFFFFFFFFFFFF67FFFF67FEFEFFFFFFFFFFFF45FFFF45BFBF3FBFBF45BFDF",
INIT_31 => X"FFD7FDFFFF33FFF9FDFFFFFFFFFFFFFFEFDDFFCDDDFFF745FFF5FFFFFF33FFF3",
INIT_32 => X"DDCDFFDDCD3FFF7F3FBBEF3FFFFF65FFFFFFFFFFFFFFFFFF7755FF7577FFFB85",
INIT_33 => X"43FFFFFFFFFFFFFFFF45FFFF659FDF3F7FDF897FFFFFCDDDFFFEFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFF89FFFF67FEFEFFFFFFFFFFFF45FFFF45FFFFFFFFFFFFFFFF43FFFF",
INIT_35 => X"FF5599FF5399FFF965FFD7FDFFFF33FFF7FD3F7FDF5FCDDD5FFFDDA9FFFFFEFF",
INIT_36 => X"DDCDFFFD4B99DBF7FFFF99DDFDF9FFFFFFFFFFFFFF9955FF7755FFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFF45FFFF45FEFFAF11DDF3FFFFDD99FFF5FFFFFFFFFFFFFFDDABFF",
INIT_38 => X"FF9FDD669FDF5FFFDFFD7DDDFF9FDD687FDF5FFFDFFDF1BFBBD3DD8A7599FFFF",
INIT_39 => X"BF7D7FDFBDDD5F9FDF899746D90D9DFF7DDD5F7FDFA97966D7EBBFFFDFFD7BDD",
INIT_3A => X"FFDFDF89DFBBF3B3FB51DDFFFFFFDFABDFB9F38EFD53DDFFFFFD9B7FFFDF7D88",
INIT_3B => X"5D77713B8AD589FFFFDFFFABDFBBF1BBB353BBFFFF5B9FBF7DEFB355B3B3CFFF",
INIT_3C => X"64BB97FFFFDFFD7DDDFF9FDD669FDF5FFFDFFD11BDBBD3DD8A7599FFFF39BDBF",
INIT_3D => X"FFFFFDBDF1DDB9F768FD75FFFFFFFD9B9FFFBFBD66BFBF5FDFDFFD7979DDB7DB",
INIT_3E => X"89DFBBF1B5D931DDFFFFFFDFABDFB9F391FD51DDFFFFFDBFCDDDB9F58AFF53FF",
INIT_3F => X"DD8C73BBFFFF39BFBF5D5591398ED3ABFFFFDFDB5FFDDF5DD7B75DBF9FFFDFDF",
INIT_40 => X"FFFF5BFD7F5DDDEB5B66D7A9DFFFDFFD13BDDDD5DD8A9799FFFFDFFDCFDFBBF3",
INIT_41 => X"BDEFDDB9F768FD53FFFF9DDD5F9FDFA97966D90BBDFFDFFD7957DDB7DB66BB77",
INIT_42 => X"DD57AF7151B9FFBFB97753FBDF33CF712FDBFFDF99F97D9FD55797F99933BFF9",
INIT_43 => X"752FFF9FBBD7F1BDF77FD9F733BF9F9F95D713DBF77FD7F735DF9F9DB77731DB",
INIT_44 => X"F7B7B77FBD5379B7F77759FFF7D7977FDB3379D9F7575BFFF7792B9DFD9F4B91",
INIT_45 => X"F9DB9FF1B77DDF9FF997D97F9F9577B7F79935DFF753539FF9BD9FF3739FDF7F",
INIT_46 => X"F9D7339FFDB77733FBDF55CF712FBBFFDF99F97D9FD55597F9B9339FF933B57B",
INIT_47 => X"FFD7F9997FF93379F9F7557DFFD7792DBDDD7B8D917395FFBFBBF9999FF73397",
INIT_48 => X"7FBD5379B7F77737FFF7D7977FDB3379D9F77759FFF7D9977FDB3379D9F7575D",
INIT_49 => X"97F99933BFF933957DF9BB9FF1957DDF7FF9974F7DF9BFE9D195E9FFBFFFB7B7",
INIT_4A => X"7FFD53F735FBF97FF3D759DF9FBB97F97B9FD75597F9B9339FFB97D97D9FB557",
INIT_4B => X"977FF93379F9F7557DFF95D711DDF77FD7F735BF9F9DB7F9999FF73397F9D733",
INIT_4C => X"FF5D5DBD5B55FFFF5D9B11ABDF7D5DBD7B55FFFF5D9955FFDD9FFDDF9FDD9FDD",
INIT_4D => X"3D77DDDDFF5F9B9FDB9D31559B2DFFDFFF5F9BBFDB797555796FFFDF7DBDCDCD",
INIT_4E => X"FD7DC9DFFF5FDFFF5DDFDF5FDD9FA7DFFF5FDFFF5DDFDF5FDD9F8779773F7BBD",
INIT_4F => X"FFDBADFB79ABF5FFFD5D539BFF9FBFFD9FBFDD7FFDBF7D5FFFDD89D99D87F7DF",
INIT_50 => X"FF7DDDBF9F5DBDEFABDF7D5DBD7B55FFFF5DB933FFDD9FFDDF9FDD9FDDDF5D5F",
INIT_51 => X"5FBDDF87DFFD5FFFFF5DDFDF5F9DBFA913BD5F5BBD5D55FFDD7DDFCBFFFD7FFD",
INIT_52 => X"DFFF7FDFFD5DDFDF5FFD9FA9DFFF5FDFFF5DDFDF5FDDBF87DFFD5FDFFF5DDFDF",
INIT_53 => X"FDBFBFDD9FDDBF5D5FFFDDABDB79ABF5FFFD5D0F9DCD7F9B5D7D9977DDFF7DCB",
INIT_54 => X"BF7FDF3F7DDFDB35B95535B1FFFF5DBB33FFDD9FFDDF9FDDBFBD5D9777FFBDBF",
INIT_55 => X"85DFFD5FDFFF5DDFDF5FFF5F9B9FDB9B33559B4DFFDF9DDFCBFFFD7FFDFF7DDD",
INIT_56 => X"FFFFFF1117DF3FFFFF3F9FDFFFFFFF1119DF3FDDFF5F7FFFDDADDD55ABFDF5FF",
INIT_57 => X"135F5FFF7DDF4533BB3F9FDF3F77D1DD7FDF69EFDD5F7FDF5F55F1DDFF3FBFBF",
INIT_58 => X"FFBFBF3FFFFF4599DD45F9FDFF9FDF3FDDFF8976DD89F7FFFF5FDF5FFFFFFF55",
INIT_59 => X"45BFBF3F9FBF31F5FFDF7F3FFFDF67DD9945FDF9FF5FCDBD897FDF5F5FDD51D9",
INIT_5A => X"335599F3FFFF3F9FBFFFFFFF1119DF3FDDFF3F7FFFDDCDDD55ADFDF5FF3F5779",
INIT_5B => X"FFFF5FDF7FDDBDEF33BBEFF3FFFF3FBF9FFFFFFF33159F3FFFFF3FBFBFDD5799",
INIT_5C => X"3FFFFF45BBDD45F9FDFF9FBF3FFFFF6776DD67F7FFFF7FDF5FDDDDAB54DDABF5",
INIT_5D => X"FF5789FFF7FF3F339B459FBF3F9FDF31D7FFDF9F3FFFFFFFBB111FBFBFDDBFBF",
INIT_5E => X"F3FF5FDDCD69DF7F3FDF7F33F3FFFF3F7FFFDDEFDD55CDDDF5FFFF5F5FFFDD89",
INIT_5F => X"DF7FDDDDCD33BDEFF3FF9FDF6711BB3F7FDF3F77F1DDFF3FBFBFDD7777335799",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(18),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addra(15),
I1 => addra(14),
I2 => addra(12),
I3 => addra(13),
I4 => addra(16),
O => ena_array(18)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "COMMON";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"9569D6036DF64F66FA6FB6FB6B96B96AD2AD3ADBED9EC9ECD2AD2A52ED72D72D",
INIT_01 => X"510110111014014004004824824820A20440440420028028DDAE5AE4BDB5CB5E",
INIT_02 => X"8D58C5CC5441571571930B38DBBDAB1A9400500500A00A00200226BE12410510",
INIT_03 => X"4C58C5C4414C86C84B56B563476AC6AC6AC39178220AB8AB8A98EDCEDDED58D5",
INIT_04 => X"682990D91301B21B21B4313B128928D28D0840840A603643643653653251A51A",
INIT_05 => X"499BE3FF80188389389209209209209209308308300310712416512512412412",
INIT_06 => X"08608609641640650610610410410C10800840A42C82C80CC248248250490490",
INIT_07 => X"60B20B21A21BA17A1251250A014816C14590590180B2032030A1013F08082086",
INIT_08 => X"60A21A219A91A91B602902D83205A05B05A901FF08190FD0AD0AC0AC0A40B60B",
INIT_09 => X"D3523523646A46A46E8006FE000CBB8B38B38958948D48D58DD8DF85F95F1771",
INIT_0A => X"8018407CE6120D21D21921931110110010050A51A41A41A40DD85D85A2220220",
INIT_0B => X"0850850850850800800A81A81A818810A02640640A10A1008444404408808808",
INIT_0C => X"121121523523523400980988E4224224514214200428400402F9417FE6144085",
INIT_0D => X"D21D23D213E93E9ACC844844889089089007307F2F8691A11A01221321121121",
INIT_0E => X"B27D27D35E4FA4BA6806303F0F8CE94E94ED48D49F49F4D74D64560560D29D29",
INIT_0F => X"9407413C8006A722722732B32B32A92A92AD2A52A56E54E40554540565765525",
INIT_10 => X"440440440440444444404404404404C852AD2AD3808808889CAE4AA4B995C954",
INIT_11 => X"31930B38B28B2AA3C44044045226B26B2011111102022222211F011F90942242",
INIT_12 => X"71B31B38B39DBB1B9D44D64C69A89AC98C070003918D55155155151151359359",
INIT_13 => X"4B773763676EC6EC6F270DC28E22B8AB8AB8E9CEDCEDD8DD8C58C5C454515715",
INIT_14 => X"20800018000908D08408408408401601641651251251211A4C78C7C4B10802C8",
INIT_15 => X"1481483481481C01800840A40A4280290920920110290300202180590200300B",
INIT_16 => X"1251250A50830C3164AA4AA4A4A2CA2CA20520601A40A00C0084101200240140",
INIT_17 => X"9251A71A796816C1C594594488B28B2892A14040000841861861865165165165",
INIT_18 => X"602D82D83E05B05B0501404000050E50AD0AC0AC0B40B60A60A21A21AA1AA1C9",
INIT_19 => X"6EC00D13C038ABABBA908908948948D58DD85D85F95F157420B21BA1A291A91B",
INIT_1A => X"0582582482682602602640640700300891D11901984C04C0D2523563644A46AC",
INIT_1B => X"8098098898890A132C26C0EC32102102220980981341301301327FD032018058",
INIT_1C => X"519D49DCE4224324514204604408408C0CC06024C44854850850850850810811",
INIT_1D => X"CC8648648990C90C90E90E91E91A91A89AA1321321321921921D23D23D235237",
INIT_1E => X"2AA2A82A02A0E84ED4ED48D48D48D4DD4554540540D41D8A925D21D221A91A9B",
INIT_1F => X"F26FB6BB2BB2B92A92AD2AD3AD3E5DE456814854C5765725B23527536A46A4EA",
INIT_20 => X"444044044044040912ADBADBB08808888CAECAE4BD95D9549569569D69F2DF26",
INIT_21 => X"EE4AE40E5326B263201101110202222222022022022020420404404404404444",
INIT_22 => X"DD64D64C69AC9AC98D98D9C59D5955955B5535135935935931B31B38B3AB2AB3",
INIT_23 => X"67C63E23E20A20AB8AB8A9CA9EADF8DF8C78C7C47441441571939B3893D5BF1B",
INIT_24 => X"908948A4824820820920920120120121E4364364884904124B7AB7E3756FC6FC",
INIT_25 => X"E4AA4AA4AA4AA40B09209209503803C982082082524104104904900900900908",
INIT_26 => X"64AA4AA4ACA2CA24200700792E00E20F25525525525521520521401C01C01C41",
INIT_27 => X"C594594488B28B28928938D38538418418610651651651651251A71A70A30830",
INIT_28 => X"0590D90C50AD0AD0AD0AC8A48B48B60B60B21BA19A15A15B9271270A796816C1",
INIT_29 => X"8A08A0880000100511D1190194194194694A14A500200200622D02D83A45B05B",
INIT_2A => X"6C26C0EC0B44B44B90911951984D84D840040144240080288688E88CA0CA0CA0",
INIT_2B => X"AC2EC0EC3A1823832B09B09B13613613613607605A05A25A25825824C26C26C2",
INIT_2C => X"524304706648608E8CEA4EE4EF4AF48F08D0CD0CD0C91C19D19D49DC9DE95E91",
INIT_2D => X"92E90E91A91A91AE12A12A13A1925925D25D21D2352350354018498EC4324BA4",
INIT_2E => X"E2AE0AE0AA02A12A1681485485585DC480454455294254258E86497489D2C92E",
INIT_2F => X"92ADBADBADBEDBF452A16A56C576D72510A84A85B0150950B40A42A42AC2EE2E",
INIT_30 => X"1BBDBBDBB49D49DCCDAEDAE4BDB5D95C95EDD6DD6DF6DFA6FB6FB6BB6BB6BB2B",
INIT_31 => X"6A13A93B8752772772572172072A70E04E50E14E84EA4EE4EE4AE40E50E54E1D",
INIT_32 => X"AC9CD9C59D5B50424355B51B5135135931939B38B3AB6AB7CE40E40E7226B26B",
INIT_33 => X"EAE0A80A82AC324724364364344144146D18C10C10558E48DD44D64D69A89AC9",
INIT_34 => X"092092093093117127127127124124125A6224225561D63923B21B21A20A30BF",
INIT_35 => X"41A41A01803883C9C4DC4DC494490490490490498498979FF6EB893892892092",
INIT_36 => X"290690600E00F21F257255245245120FF100D20C01C01E4BE4AA4AA48A48A48A",
INIT_37 => X"9289385384398837EC850650651651251271270A70860820820C20CA2CA24A24",
INIT_38 => X"EC8509B09A896894A94A14A54A1481691611613713512D128208328328B28928",
INIT_39 => X"10911951B41B41A01A4124122022022084584D84D44B44A54A50A52A50A6510F",
INIT_3A => X"44B84B84D84D84D8904904900880880884884A8DA0DC0EC3E5E7209001101101",
INIT_3B => X"2F12E12613613613617607605E240FC3F9605C24C26C26C2EC2EC0EC0BC4BC50",
INIT_3C => X"08C24C3487481E0CF804CD0C91C11C11C018498E90E90014111A19A192382382",
INIT_3D => X"6AEA4A4484C84C84C0454455015023BFFBDC094890990990468668648E08E08E",
INIT_3E => X"12A16A56A54A8E3FEFE4E656654254250702522522426426026222A20A81AE26",
INIT_3F => X"E22DF6D76D76D7259139159951950950950B52B52B528826808722B32A12A12A",
INIT_40 => X"DB7DB7DB5DB5DB5C9DEDDEDDEDFEB0406007B6BB6BB6BB2BDBBDBBDBFDBEC81F",
INIT_41 => X"72472072070041264170E04E84CA4CE48E40E40E40420067D9889C099099499C",
INIT_42 => X"4BE1FF5ED5ED5AD5AD18C10C14E7CA37FD863DABDAB5AB5A3020027026426726",
INIT_43 => X"6436536532503907EFA51810C04C86C81EF7CAF6AF6AD6AD68C60860A60A57E9",
INIT_44 => X"F1A4712712512512742E54301301B21B21B21B29928929018C08C08602643643",
INIT_45 => X"FC7FF0049C494490490498498C98DBA938A10838928928920930930931903F03",
INIT_46 => X"21525525525525D21D22BFC4A1C41E42E42A4AA4AA447831F00E3A43803881C8",
INIT_47 => X"B9FE7FFFCA02A02202200320321438007463601481405404FC7FF0010E00E217",
INIT_48 => X"8D48D5857854B8DC5596712F1291A91A207FE230520501101100190190990B80",
INIT_49 => X"0003243222220220C0BFC008B44A46A46A46AC2BC2BCAB8BB8103FC2148948D4",
INIT_4A => X"C08BC000C888880880885A8D20D20D21D060DFC00110110110910B51A41A30CD",
INIT_4B => X"605605605605625E3840CF910ACC2EC2EC0AC0AC0AC0210418084984985D85D8",
INIT_4C => X"1B142FF909021021121021021021FE05FFF2302206204224086FD98616617617",
INIT_4D => X"4564560560524890D35D891891D92C9AE60FC9B2881081089081081081081181",
INIT_4E => X"4E44664665625425C60FC1B5724F64B26B22B02B0290E84EA0720FDBCEC96496",
INIT_4F => X"FE07F13259950950950952B52B52A722407E07E28332A12A12A12A56A56A5400",
INIT_50 => X"9569D6DF6DF64F66E1F063E00B96B96AD2AD3ADBED9EC9ECDF4DF6DF6D72D72D",
INIT_51 => X"407000ECC814014004004824824820A20A20220220028028E06370065DB5CB5E",
INIT_52 => X"8D58C5CC5441571571D39DB9DBBDAB1AE000767180A00A002002012412410510",
INIT_53 => X"11A10810C14C86C8E1B8D5AAE76AC6AC6AC62C62A20AB8AB8371B8AD19ED58D5",
INIT_54 => X"C1BA80005301B21B21B29B29928928D288619B0002603643643653653251A51A",
INIT_55 => X"4984184180188389388208300209209209308308300310712712412412412412",
INIT_56 => X"09FC0BEFF41640650610610410410C10C10C10C12C82C80C0600C00490490490",
INIT_57 => X"60B20B21A21BA17A15A15815814816C12E08FC0300B203203083082082082086",
INIT_58 => X"6712712B1A91A91B09093E085205A05B0590590D10D90FD0AC7123AC6A40B60B",
INIT_59 => X"C16248C4A46A46A46EC6FC2FCAFCBB8B38B16358948D48D58DD8DF85F95F1771",
INIT_5A => X"8028528D20D20D21D21A01931110110010050A51A41A41A43A43243222220220",
INIT_5B => X"0850850850850800800A81A81A818810A10A10A10A10A10094110C9888808808",
INIT_5C => X"12112152352352342340264264224224457C28428428400400540D40D40C4085",
INIT_5D => X"DA9DA91B93E93E9AD00D10990890890890890A91A91A91A11A01221321121121",
INIT_5E => X"A76A46A4FE4FA4BA6B22B02B02B0E94E94ED48D49F49F4D74D64560560D29D29",
INIT_5F => X"954952952B52A722722732B32B32A92A92AD2A52A56E54E44E45665665765525",
INIT_60 => X"440440440440444444404404404404C84880880880880888913995995995C954",
INIT_61 => X"31930B38B28B2AA2AA2A22A26A26B26B21220220220222222202202202202242",
INIT_62 => X"71D39D39DB9DBB1B8AA8A88A89A89AC98C985985945955155155151151359359",
INIT_63 => X"55C74E74E76EC6EC6EC62C62E22AB8AB8AB8E9CEDCEDD8DD8C58C5C454515715",
INIT_64 => X"20B28928928908D08408408408401601641651251251211A10810810810802C8",
INIT_65 => X"1481483481481C01800840A40A4280280290290690290300284204204200300B",
INIT_66 => X"1251250A50830C30C30C20CA2CA2CA2CA40A41A41A40A00C0040042052040140",
INIT_67 => X"15A15815816816C1C30C328B28B28B2892892852841841861861865165165165",
INIT_68 => X"685605605E05B05B0530D10D10D50E50AD0AC0AC0B40B60A60A21A21AA1AA1CA",
INIT_69 => X"6EC6EC2FCAF8ABABBA908908948948D58DD85D85F95F1575731211291291A91B",
INIT_6A => X"0582582482682602602640640700300B00B04B04904C04C0D58C4844A44A46AC",
INIT_6B => X"8098098898890A10A10A10A10A1021022C02C124134130130132032032018058",
INIT_6C => X"0254264264224324428428428408408C0CC04C44C44854850850850850810811",
INIT_6D => X"D509D0990990C90C90E90291E91A91A89AA1321321321921921D23D23D235235",
INIT_6E => X"2A80202A02A0E84ED4ED48D48D48D4DD4554540540D41D89DA9DA91A91A91A9B",
INIT_6F => X"F26FB6BB2BB2B92A92AD2AD3AD3E5DE4DE6DF65765765725A76A46A46A46A4EA",
INIT_70 => X"44404404404404084080880880880888937DB5D95D95D954954BFEBF69F2DF26",
INIT_71 => X"AB6A26A26B26B26320020220220222222179FF6F022020420404404404404444",
INIT_72 => X"DAA9A89A89AC9AC98920FF109D5955955B5535135935935931B31B38B3AB2AB2",
INIT_73 => X"70817EC8220A20AB8AB8A9CA9EADF8DF8C78C7C474414415715315395BD5BF1B",
INIT_74 => X"908948A4824820820920920120120121121109149049041255C54E54F56FC6FC",
INIT_75 => X"E4AA4AA4AA4AA40A40A43803803803C984484524524104106D30FFE820900908",
INIT_76 => X"C30CA0CA2CA2CA24290A80E00E00E20F20EC3F7C325521520521401C01C01C41",
INIT_77 => X"C30C328B28B28B28C0FC1F840538418418610651651651651251A71A70A30830",
INIT_78 => X"21E0CF8050AD0AD0AD0AC8A48B48B60B60B21BA19A15A15A15915914916816C1",
INIT_79 => X"8A08A0880000100511D11901941941941141140100200200685645245A45B05B",
INIT_7A => X"6C26C0EC0B44B44B44B04B84D84D84D850450440040080289AE262AEA0CA0CA0",
INIT_7B => X"E11A19A19A1823832D12C12613613613688268085A05A25A25825824C26C26C2",
INIT_7C => X"478668668648608E8B040A006F4AF48F08D0CD0CD0C91C19D19D49DC9DE95E91",
INIT_7D => X"90126413291A91AE12A12A13A1925925D25D21D235235035C254274274324BA4",
INIT_7E => X"44960AE0AA02A12A1681485485585DC5DC15C15C154254259509509D09D2C92E",
INIT_7F => X"92ADBADBADBEDBF4DF6DF6D76D76D7251770570550150950B4FE9EBA2AC39019",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"E1CA9C09D09D49DCDB7DB7DB5DB5D95C95E036DD6DF7B7DB5DB7B6BB6BB6BB2B",
INIT_01 => X"72870A74275277277257E172072B0A742750E14E84EA4EE4EE4AE40E50E54E1C",
INIT_02 => X"AC9CD9C59D5BA8DA89A9B51B5135135931939B38B3AB6AB6AB6A36A26A26B26B",
INIT_03 => X"1562A80A82AC324724364364344144144140150150558E48DAADA8DA89A89AC9",
INIT_04 => X"09209209309311713713712712412412500540541561D63923B21B21A20B4054",
INIT_05 => X"41A41A01803883C9C4DC4DC4944904904904904984984DC4944B893892892092",
INIT_06 => X"290690600E00F21F25725524524490600E00D20C01C01E4BE4AA4AA48A48A48A",
INIT_07 => X"928938538438328328B10650651651251271270A70860820820C20CA2CA24A24",
INIT_08 => X"D44B09B09A896894A94A14A54A1481691611613713512D12A608328328B28928",
INIT_09 => X"10911951B41B41A41A4124122022022000584D84D44B44A54A50A52A50A44D84",
INIT_0A => X"C4B84B84D84D84D81CC904900880880884884A8DA0DB04900881209001101101",
INIT_0B => X"7912E12613613613617607605E24E12613625C24C26C26C2EC2EC0EC0BC4BC4B",
INIT_0C => X"08C24CA4874868648E08CD0C91C11C11C018498E90E90E11A11A19A192382382",
INIT_0D => X"22404A4484C84C84C045445501501D01D09C094890990990FBDF68648E08E08E",
INIT_0E => X"12A16A56A54A54E44E44E65665425425FFF7D225224264260263B3F60A805225",
INIT_0F => X"DF6DF6D76D76D7251F88959951950950950991E32B531599519722B32A12A12A",
INIT_10 => X"FF0837DB5DB5DB5C9DEFE7FC0DFFB7DB5DB7B6BB6BB6BB2BDBBDBBDBFDBFDBF4",
INIT_11 => X"725583FC4F0102702640E04E84CA4CE48E40E40E4040040C00C09C099099499C",
INIT_12 => X"AF69ED5ED5ED5AD5AD18C10C14E15FFDA15A3DABDAB5AB5A7E660A7026426726",
INIT_13 => X"643653653251240251811810C04C86C87C6612F6AF6AD6AD68F20DF8060B6AF6",
INIT_14 => X"27127127125125127F7604301301B21B21A445FB200804301302C08602643643",
INIT_15 => X"7B3F89C49C4944904955C3FF211849C49C4B8938928928920930930931900080",
INIT_16 => X"2103B0FE795490E10E01D21C21C41E42E42A4AA4AA4073FFB5A43A43803881C8",
INIT_17 => X"520700A40A02A022022003203217C7FD01016014814054043F8D88E10E00E217",
INIT_18 => X"8D48D5857863C7FFFE12712F1291A91A1C8001A052050110108FC376001805A0",
INIT_19 => X"10432432222202201F9189C4B44A46A46A07833E893C49C4B4498978948948D4",
INIT_1A => X"03918898C888880880EB898A63D30C98C88B21931910110110910B51A47103FE",
INIT_1B => X"605410200304E12616624C24C2CC2EC2EC0AC0AC0A840CFC00384984985D85D8",
INIT_1C => X"88118118310210211210210210D4CCFC8C62302206204224D206212616617617",
INIT_1D => X"456456056071C3FECC3D891891D92C9A180010C0881081089098518F810808C0",
INIT_1E => X"5D2466466562542512001624724F64B26B28499182904624724C48C48EC96496",
INIT_1F => X"4000019959950950950912152F539199599732332B32A12A12A12A56A00F30FE",
INIT_20 => X"9569C05F6DF7B7DB5DB7B6FB6B96B96AD2AD3ADBE80F307F1D2DF6DF6D72D72D",
INIT_21 => X"80A110111014014004004824861FC33900002202200280284409C7DB5DB5CB5E",
INIT_22 => X"8D58C5CC571F031F63239DB9DBBDAB1A3427408880A00A002002012412408088",
INIT_23 => X"63210810C14C86C835C74E76E76AC6AC6AC62C62A20B4E76E768EDCEDDED58D5",
INIT_24 => X"084604205301B21B21B29B2992880420530240840A60364364365365330F0007",
INIT_25 => X"4984184180184904904A09209209209209308308312E09DC0C72412412412412",
INIT_26 => X"00B0860964164065061061041048303C006C10C12C82C80CC490490490490490",
INIT_27 => X"60B20B21A268300C00215815814816C14304304300B203203083082082083043",
INIT_28 => X"0012712B1A91A91B685605605205A05B0590590D10D805605206C0AC0A40B60B",
INIT_29 => X"C59C49C4A46A46A46EC6FC2FCAFC49C4A4698958948D48D58DD8DF85F961A0C0",
INIT_2A => X"8028528D20D30C98888121931110110010050A51A40088042043243222220220",
INIT_2B => X"8428850850850800800A81A81A819250A10A10A10A10A10090C90C9888808808",
INIT_2C => X"12112152352380742340264264224224428428428428400400540D40D40C2842",
INIT_2D => X"DA9DA91B93E93E9AD00D10990890890890890A91A91B10990891221321121121",
INIT_2E => X"A76A46A4FE4FA4BA6B22B02B02B046A4FE4D48D49F49F4D74D64560560D28D29",
INIT_2F => X"954952952B539599599732B42B32A92A92AD2A52A56E54E44E45665665765525",
INIT_30 => X"220040498440444444404404404404C84880880880880888913995995995C954",
INIT_31 => X"31930B38B28B2AA2AA2A22A26A26B26B21220220220222222202202202200220",
INIT_32 => X"71D39D39DB9DBB1B8AA8A88A89A89AC98C9859859458A88A89A91505D1359359",
INIT_33 => X"55C74E74E76EC6EC6EC62C62E22B4E74E76CE9D3DCEDD8DD8C58C5C454515715",
INIT_34 => X"20B28928928908D084084097C8401601641651251251211A10810810810802C8",
INIT_35 => X"14814837C1481C01800840A40A4280280290290690290300284204204200300B",
INIT_36 => X"1251250A50830C30C30C20CA2CA2CA2CA40A41A41A40A00C0040042052040140",
INIT_37 => X"15A15815816816C1C30C328B28B28B2892892852841841861861865E65165165",
INIT_38 => X"685605605E05B05B0530D10D10D50E50AD0AC0A00B40B60A60A21A21AA1AA1CA",
INIT_39 => X"6EC6EC2FCAF8ABABBA90890A148948D58DD85D85F95F1575731211291291A91B",
INIT_3A => X"0582582202682602602640640700300B00B04B04904C04C0D58C4844A44A46AC",
INIT_3B => X"207396682446B4341A40623C8A81AA0A2C02C124134130130132032032018058",
INIT_3C => X"5A0480E1A129E0436A1298618DCDC23415420A24D209C4A8C430372822017FC9",
INIT_3D => X"6DAE2A953238C6CDA011A6CD68FA4947114E7350787EAF175A947956EEB4E2D1",
INIT_3E => X"5A4E916B748DC1916E15858825027EF9F4F2B68815074828204FA8057F130994",
INIT_3F => X"090260421AAEBA87D92FFEF3F2983114020000F8FF0000241C62CC2158893931",
INIT_40 => X"6AEFFFD6342A6A0485200114FF861A410276C6605354860A10B02A1835089C0A",
INIT_41 => X"1693D4043F0402B8DDA5194404861D27622591204267FEC054A169923535D28C",
INIT_42 => X"21AD38989F5DB8CAB07225DCD49FFFB48159534260F3DB3BDC1FFFFDDA9553A8",
INIT_43 => X"042A8B22A5FFFFFB921C2472257EFFC6AAFFFFFEB2E0C8110E40711BFE6C4D80",
INIT_44 => X"C0AB37507FF77FEA1FFFFFFFF9287458A421B3273F6F2080C2D75571384C17F6",
INIT_45 => X"9FFFFFFFFD5544E410962EFF1F8136C07BF10494905EFFFBFFAC39870FFFFFF8",
INIT_46 => X"8D42C5F0CC804063FFC8D060121EFFFFF7EB044C8FFFFFF604BFFFE87FFFFFFF",
INIT_47 => X"FFFA54648BFFFFFFFD7DCB5C9FFFFFF7DFBFFFF83FFFB7FE1FFFFFFFFEE872AA",
INIT_48 => X"FFEFBFFFFFFFFFFB7FFFFFFA7FFFFFFFDFFFFFFFFFFE0D141C3030E063B32565",
INIT_49 => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFF42AAB6A95880EEC86800FFFD0913673FFFFF",
INIT_4A => X"FFFFFFFFFFFFAAF031B0C6848B04801EFFFEE5D45BFFFFFFFFFEFFFFFFFFFFFF",
INIT_4B => X"8C6C306029610A03FFFFBEF5D7FFFFFFFFFFBFFFFFFFFFFEFFFFFFFA7FFFFFFF",
INIT_4C => X"FFFFFFDF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF87FFFFFFFFFFFFFFF7F6A654A",
INIT_4D => X"FFFFFFFFFFFFFFFFFFFFFFF87FFFFFFFFF7B77FFFFB5927573B7C7CA5A484021",
INIT_4E => X"FFFFFFF87FFFFFFFFFFFFAFFFFDF95EB666FD59A1D529B20FFFFFF7B7FFFFFFF",
INIT_4F => X"FFFEFD7FFFFAEFF4C81620E95E590581FFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"166AC606202EA042FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFF5FFFFDFAFFFC31BEAD",
INIT_52 => X"FFFFFFFFFF4DFFFFFFFFFFF27FFFFFDFFFF7FC27ECEB63D169FD88E00FC43F01",
INIT_53 => X"FFFFFFF87FBFFFF7FFFEBFFFFDDE96BCAD5548487BC72840FFFFFFFFFFFFFFFF",
INIT_54 => X"FFBCAAFBFFF55EE960E7932523FC39C1FFFFFFFFFFFFFFFFFFFFFFFFFE6FFFFF",
INIT_55 => X"8E2925005A06CE14FFFFFFF7FFFFFFFFFFFFFFF7E4CADFFFFFFFFFF07FEFFFEE",
INIT_56 => X"2BFFFEFF7FF7FFFFFFFFFFFF297CBFFFFFFFFFF87FFFF0D3FFDFD32DE7B4F1B4",
INIT_57 => X"FFFFFFE68492B7FFFFFEF7FA7FDFFDFDFFCF2F97BE7524836DA500BA02E93282",
INIT_58 => X"FFFFF5FA6BFDDAEB7F64F9772B9E8AFEDF5200842A6B9729DE7FFF7FDFBDFFFF",
INIT_59 => X"55B15689747575B43B3439004508D620BFFFFFFFFFFFFFFFFFFFFFEFA340DFFF",
INIT_5A => X"9D8B101868B609DE3EFFFFFD6D7FF3FFFFFFFFD348895F9FFFEDFE927F6FFF5A",
INIT_5B => X"DFBFFBFEFE25EF7FFFFFF7EFD480A4E6FFBDDBFA3F77EE897D2615AE8ADDDA5E",
INIT_5C => X"FFFFFEE15FC87F300F6BB6D842180249BD42EA4A7F7EE966EE65468334A6C640",
INIT_5D => X"000000800FFFFFCA008001A6FFBEB6DF78A8A0244A5413A0FFFFFFFF75CA56AB",
INIT_5E => X"FFC02017E3B7D66D01D2405905089214FFFFFFFFFFD2A53B7BFF801FFFFFFFFF",
INIT_5F => X"90218F0218754AC2FFFFFECBFFF77B5DFFFD07EFFFFF7FFF37CFFFB04BDFBB5D",
INIT_60 => X"FFFFFC91FFBA778859BC7FFBFFFDEFF7FFFFDE827D7EFFBF9DBFF649EEB962B6",
INIT_61 => X"EEF3ADD7F3FEDDFEFBF7FDA272ED7BD77FF7B9FA7C769A652DAC446440C01601",
INIT_62 => X"FF7FA5425F9CD1CEEDEFBB6F4FEB689A497980648A404954FFFEC5675714D2D3",
INIT_63 => X"78DD6DA8A396D6B0A99310809A3591C1FFF2BF4D23ED6FB36FCFD3FA6FBFB7F4",
INIT_64 => X"4324C16B24A0162AFFCEA8DA8E92525AB9357FCAFFFFF75EEFAD6B506DFA0EFD",
INIT_65 => X"7F915786507F06E446DB55F76FFF35E1AEEDDFD07D43EF7DA5AF1A3EEE21A10F",
INIT_66 => X"BFF7CE8D5BEAEF1E5DF96E70025A49455D8825A48DD6EE31548B0840512EA961",
INIT_67 => X"BEE6BF523494241E50434B026AC8C294A05020001CD00480AD5AEDAD66893551",
INIT_68 => X"B3FEB25D55E9800503824B2C249322A23015380181022B0FFFF22FF7EFFE94DB",
INIT_69 => X"5E1722408174D501E2A9440000C0401FEFDF3BCD36EB4F9F76CF3DD26A29D4DC",
INIT_6A => X"B4400FFBDBEF7B7BF656D431DD98B77A5B76EF222498CA9ADCD249CCA2122130",
INIT_6B => X"8FBA6FEDAE7F4BBFCE9671C273427335E2BB346715D5CFBC94502B2A6483205C",
INIT_6C => X"4FB857603C65491C27378654D11492EA10810194100A36224AD0F7BF7FF7FFEF",
INIT_6D => X"5496CA82D32B567DE632404A81B65195281FCF9E6DD79EAD76A7D298FF727EAB",
INIT_6E => X"A00129E254010AA8145FB567AF7F1AB6E32D69F7EEF4BFED52FEC5206C882EF7",
INIT_6F => X"CFF7FFB2BBAECD6DFC8F96EF735686F76F113AF03372CA3B944F372DE3496997",
INIT_70 => X"E5DFE975BFF235BD3CECA7222DD37516C33ADD776C549664EE48C1CB825C4214",
INIT_71 => X"ACA16A721A2148AC12B1A254A96D608B8708000C080000041FDF328DFEFA37A2",
INIT_72 => X"FFC16BDAB220062C21FE68748E180C203DE6A4376FB5E59EAE2E4FD79BB55B5A",
INIT_73 => X"D51FD0CBA80682A4FBAF966FD46D1D6FF7D697FEDB5CCDA28CFE2EC256BDA96A",
INIT_74 => X"FE7AEDC2EF9F6D8138D6D0DCEE0FA5588B4EE9B02691733B0962691A0F79DD53",
INIT_75 => X"672E46B4A3F97FB5B4D10F403CC4583F664BCC45B0C30090906AFF9002496801",
INIT_76 => X"591028E048D00664CC94992003052C2944102CFC26008A0177DDCDB9572354AD",
INIT_77 => X"000000000000000000000000000000007D9825445974A979628CCB726CA8014D",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000200000000",
INIT_79 => X"0000000000000000000000000000000000000002000000000000000000000000",
INIT_7A => X"6DB5B6DB6DB36CB6DB6DB72212DBB6DB6DB6DA6497B6DA4924924924965B65B6",
INIT_7B => X"FFFFFFF07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF249B6CB6DB6DB6DB",
INIT_7C => X"FFFFFEFFF7FFBFFBFFBFFBFFBFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFBFFBFFAFFAFFAFEFFF7FFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFF07FDFFFFF",
INIT_7E => X"EFFF5FFDFEDFEFFEFFEFFDFFDFFF5FFDFEDFEFF07FD7EFFEFFEFFEDFF7FFBFFB",
INIT_7F => X"D7FFFBBFBAFDDBDDFDDFDEF22F76DDFDD7FD7FEBDF5FF5FF5FF5FF5EFDEEDEEF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"80000000180100100000000000000000000062FF000000000000000000000000",
INITP_04 => X"03002002006004004003E3FF0C00C00C00C00C00C00C00800800801801801801",
INITP_05 => X"0003FFFF80800800800800800000000000000001001001000000000000000000",
INITP_06 => X"0000000000000020020000000000000000000000000000040000000000000000",
INITP_07 => X"0000000000000000020000000000000000000000800001009007FFFFEF000000",
INITP_08 => X"000000000000000000000000000000000007FFFFFF8000000000000000000000",
INITP_09 => X"0000000000000000003FFFFFFFC0000000000000000000000002002002000000",
INITP_0A => X"007FFFFFFFF00000000040040040040040000000000000000002002000080080",
INITP_0B => X"0000000000000000000000000000000000000000000000000001001002002002",
INITP_0C => X"001000000000000000000000002002000000000000000000007FFFFFFFF00000",
INITP_0D => X"0110300300000000800400400800800803FFFFFFFFF000001001001001001001",
INITP_0E => X"000000000000000003FFFFFFFFF0000000000000000000000000080080000000",
INITP_0F => X"03FFFFFFFFF80000000000000000000000000000000000000000000000000000",
INIT_00 => X"45B1B153B1D1316953EF2BD15391B15391CF2F8B53CD2FCF7371B17371EF2FAD",
INIT_01 => X"EF2DAD257335F17125D1EFD1558BAF279137F15125D1EFD15567AF29B117F131",
INIT_02 => X"D1736755B1D15391CF539125B191455591CF5371CF737125B1B1257571EF7353",
INIT_03 => X"EF7173B17153CF2DAD53AB33CF9153B19153D12BAF738935D1B153B1B153B127",
INIT_04 => X"53B1D1316953EF2BD15391B15391CF318B53CD2FD17371B17371CF2F8D53AB31",
INIT_05 => X"4591D1257353CF7153CF91534591F1279353D19153D1B1534773EF29B153B1B1",
INIT_06 => X"55B1D15391D153B127B191455591CF5371CF539125B1B1457571CF7373EF7173",
INIT_07 => X"D17173CF2DAD53AB33CF9153B19153CF2BAF538935D1B1310000000000007367",
INIT_08 => X"EF2DADEF2BD153B1B15391CF316953CD2DD15391B17371CF2F8B53CD31EF7173",
INIT_09 => X"257373AEB1B153B1CF316953CD2DD15391B15391CF2F8B53CD2FCF7371B17173",
INIT_0A => X"7191B1EF6B51F171F1716F51F1B191CD6D51F191F16F7171D1D191CD6F71D191",
INIT_0B => X"47919171B191CF8D6F91CD91CFAF9171AF91CF8D6FB1AB93CFCF9171CF91CF8B",
INIT_0C => X"91D169759171F1AF6771B191B1B16975B173F1CF6771B171B1B16975D173D1EF",
INIT_0D => X"71D1D18FAB6F71D191F16D7371B1F1AFAB7171B191D16B759191F1AF89719191",
INIT_0E => X"EF6951F171F1716D51F1B1B1EF6B51F191F16F6F51D1B191CD6D71D191F16F73",
INIT_0F => X"71B1916975D173D1EF4771F171D1916B73F173B1EF4971F171CF716B53F191B1",
INIT_10 => X"759171F1AF6771919191D16975B173F1CF6771B191B1B16975D173D1CF4771D1",
INIT_11 => X"91CD6F71D191F16D7371B1F1AFAB664466066667754E6666CCABAAAAAAAA6666",
INIT_12 => X"71D191716D51F191B1EF6B51F191F1716F51D1B191CD6D71D191F16F7171D1D1",
INIT_13 => X"6975D19391B1EF6B51F171F1716F51F1B191CD6D51D191F16F7171D1D191CD6F",
INIT_14 => X"D1AF4F250BAFEF6E25B109AFCCAD4F2509AFEF4F258F09AFCFAD2F2707D1CF4F",
INIT_15 => X"0F0BD1D1AB2F53B1B1F12B355193F1D189315191D1D129375173F1D167337173",
INIT_16 => X"2F672D07CFD18B2B0D05F1AD2D690D27CFD18B290F27F18C2D8D0D29CDD16B27",
INIT_17 => X"D1CFAB2F2907D1CF4F456F07D1CF8B2D0905D1CF2F474F07CFCF8B2D0D05D1AF",
INIT_18 => X"250B8DEF6E25B109AFCCAF4F250BAFEF6F25AF09AFCDAD2F2709D1EF4F258F07",
INIT_19 => X"8C2BAD0D49CDD16D250F49F18C29AF0B6BCCCF6D250D6BEF6E27AF0B8DCCAF4F",
INIT_1A => X"06CFD18B2B0D05F1AF2F692D27CFD18B290F27F18C2D8B0D29CFD16B270F49F1",
INIT_1B => X"2F2707D1CF4F456F07D1CFAB2D01CCEEEE111144044611CD7777999999771111",
INIT_1C => X"D1CF4FB10BAFCCAF4F250BAFEF6F25AF09AFCDAD2F2709CFEF4F258F07D1CFAB",
INIT_1D => X"0D49CD53AF4F250BAFEF6F25B109AFCDAD4F2509AFEF4F258F09D1CFAD2F2707",
INIT_1E => X"110DAD3311EF0F6733EEEFEF030BCD33F1EF0D8933EEEFEF0507EF33EFEF0BAD",
INIT_1F => X"33EFAB0F0705F1EF2F238F03EFCF890D0B03F1CD0F454F03EFEF890B0D03F1CD",
INIT_20 => X"D151EEEFAB0F231133CD8F03D171EFEF6711231133CD6F03B1B1EFEF45114513",
INIT_21 => X"EF0705F133EFEF09CD33EEEFCD0B03F133EFCF07CF33EEEFAB0D031133CDAF05",
INIT_22 => X"3311EF0F6733EEEFEF030BCD3311EF0D8933EEEFEF0507EF33EFEF0BAB13EEEF",
INIT_23 => X"0391D1EFEF2311673333EF2F2371D1EFEF230F893313EF0F4551F1EFEF030DAB",
INIT_24 => X"00AB0F031133CD8F03D171EFEF8911231133CD6F03B191EFEF4511451333EF4F",
INIT_25 => X"F133EFEF0BCD33EEEFCD0903F188113333557766004455117777BB9999775555",
INIT_26 => X"EF0BADEEEFEF030BCD3311EF0D6933EEEFEF0509CF33EFEF0BAB13EEEFEF0705",
INIT_27 => X"EFEF45D10DCD3311EF0D6733EEEFEF0509CF33F1EF0D8913EEEFEF0707EF33EF",
INIT_28 => X"D1EF730573532FF5D1AF09CF53EF5307915351B5F18F2BEF73CD53098F337173",
INIT_29 => X"558F27D1F1EFB12BAF53EFCFCD0B25D1F3EFB129AF73EFCFAD2D25D1F3EF9127",
INIT_2A => X"53F1274CB1D1AD2D33AD313553F1076C91F1AF0B35AF113573D1056E73EF8F09",
INIT_2B => X"F173CD330BAF339173F16B2CD191CD310DAF33D353F1494CD1B1CD2F31AD3315",
INIT_2C => X"0573732FF5D1AF09CF53EF530771534FD5F1AF29EF73CD530991537193F18D2B",
INIT_2D => X"5771D1058E53EF8F0755910F3591D107AF53EF710755710F15B1D107CF53EF73",
INIT_2E => X"99444422224444441153F1274C91F1AF0B33AF113553F1076E73EFAF09358F0F",
INIT_2F => X"330BAF339173F16B2AF171CC0EAB9999BB99BB7777779999BBBBBB999999BB99",
INIT_30 => X"337173AF09CF53EF530771532FD5F1AF29EF53EF530991535193F18D2BF173CD",
INIT_31 => X"058E73D1EF530773532FD5D1AF29EF53EF5307915351B5F18D2BF173CD3309AF",
INIT_32 => X"7171EF918FF191B189938F6FF16FEFB16DF191B169938D6FD18DF1B14D1191CF",
INIT_33 => X"EF4D89932F699391B1F12F8FF1D189934F6993B191D12FB1F1D16971716973F3",
INIT_34 => X"EF6B9389AF9389D1F12BD171CD6D938BAF93ABD1EF4DD171CD8F938BCF73ABB1",
INIT_35 => X"8FD18BF1B12D1191CF69938B8FB38BF1D12BF171EF69938B8FB389F1D10BF171",
INIT_36 => X"91AFD191B189918F6FF16FEF918DF191B189938D6FD18DF1B14D1191D169938B",
INIT_37 => X"71CD8F938BF173CDB1CF8FB191AB91918DF171CD91CFAF91918991916DF171EF",
INIT_38 => X"773333EF1133333322CD6B938BAF93ABD1F12DD171CD8D938BCF73ABB1EF4DB1",
INIT_39 => X"11B12D1191CF69938B8F8800223377BB77777777777777BB777799BBBBBBBBBB",
INIT_3A => X"1191CF918F6FF16FEF918DF191B189938D6FF18DF1B16D1191D169938D6FD18B",
INIT_3B => X"938BCF936FEF918DF191B189938F6FF18FEFB16DF191D169938D6FD18DF1B14D",
INIT_3C => X"EF8DCD55F153F195AFF115D3458BCD55F153F175AFD114F34769EF75D153F157",
INIT_3D => X"F193AFEFF12F1191D145D1474F93AFEFF12FF171CF47D1456F75CDEFF111F153",
INIT_3E => X"59CD7512ADAF45B3D1B191D157EF55328BAF4593F1B1B1D157EF355269B16775",
INIT_3F => X"F16947F193D153F157CDB312D16B45D193D153F159CD9312CF8D45B1D1D173D1",
INIT_40 => X"55F153F195AFF115D3458BCD55F153F175AFD114F34769EF75D153F177CDB312",
INIT_41 => X"D175EF377247AF8955F191D1B373EF359245AFAB55F173F1B391F135B2458DCD",
INIT_42 => X"77777777777777771144EF55328BAF4593F1B1B1D157EF555269B16775F191D1",
INIT_43 => X"F175D153F157CDB312F188CDEF5577997777777777777799BB99BBBBBBBBBB99",
INIT_44 => X"53F157F135D3458BCD55F153F195AFD114D34769CF75F153F177CDD114F16747",
INIT_45 => X"375267558DCD55F153F195AFD115D34569CF55F153F177CDD114F36767EF75D1",
INIT_46 => X"1B7553D10DCDF1532335ED23D19533D109CFD1710355ED23B1D533B107EFB38E",
INIT_47 => X"134745F175F133F139EF9316F16923D193F153F139EF7516EFAB23B3B3F153F1",
INIT_48 => X"AA09ACCF673513733323F1378A0DCACD8937F3913345F137890FE8ABAB37D3B1",
INIT_49 => X"23B3F5339105F1938E0571EF239313337303F1758C078EEF455513535303F155",
INIT_4A => X"D10DADF1532335ED25D19533D10BCFD1712335ED23B1B533B107EFB38F0353EF",
INIT_4B => X"176913E88BCD37B3D11167F1356715EA69CD5793D10F8BF1354515EA45CF7753",
INIT_4C => X"777777777777777777330000CD6737F3913325F137890FEAADAB37D3B11345F1",
INIT_4D => X"33B105F1B38E0371EF22555533555577775577777799997799BB9999BBBBBB77",
INIT_4E => X"F1B38E37EB45D19553D10BCDD1732335ED23D1B533B109EFD3710353EF23B1F5",
INIT_4F => X"E8ABABCF7553D10BCDD1532335ED23D1B533D109CFD1710353ED23B1D533B105",
INIT_50 => X"ACCFCFF1D155ACCFF3CDB31313CFCFF1F155AFCFF3CD931113EFAFF1F135AFAF",
INIT_51 => X"D1B3F353B127D1B3AC2791D1259313539125D193AC29AFD1477513717325D175",
INIT_52 => X"AEF1EF3573D1EFCFD1F173EFAEF1EF35B3CFEFCFD1D171EFAECFF135D3AFEFEF",
INIT_53 => X"1111EFAFF1F155CFAFF3EF5531F1EFCFF1F155CFACF3EF3551D1EFCFD1F153EF",
INIT_54 => X"F1D175ACCFF3CDB31333CFCFF1F155AFCFF3CD931313EFAFF1F155AFAFF3CD75",
INIT_55 => X"EFAECFF135F3AFCFEFD1B38EEFD1CDD11313CFCFEFD1938EEFD1CDD11333CFCF",
INIT_56 => X"99BB997777BBBB77773333110293CFEFCFD1D171EFAEEFF135D3AFEFEFD1B36E",
INIT_57 => X"AFF1F135CFAFF1000077331111555533331177777777777777BB99BBBBBB7777",
INIT_58 => X"35AFAFCDB31333CFCFF1F155ADCFF3CD931313CFAFF1F155AFAFF3CD751111EF",
INIT_59 => X"F135F353CFCFF1F155ACCFF3CD931313CFAFF1F155AFCFF3CD751113EFAFF1F1",
INIT_5A => X"518F91CFB19129D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714B91",
INIT_5B => X"93AFD171D1F193917193AB9333D1F191B3F193B17191CD9353B1F19193F173D1",
INIT_5C => X"714FCFF1B1916DB193CF2DCF714DCFF1B1916DAF93CF2DEF912BEFD1CF916FCF",
INIT_5D => X"93CF6D91B1CF716B91716DF193AF6D91B1CF518D916F8DF1B3B16DB1B1CF4FAF",
INIT_5E => X"CFB19109D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714BB1914BEF",
INIT_5F => X"F1912BEFD1CF916FCF93AF0BF1910BEFD1CF918FCFB39109D19109EFB3CF9191",
INIT_60 => X"99995577779999777777773302B1916DAF93CF2DEF912DEFF1CF916FCF93AF0B",
INIT_61 => X"91CFCF716B910889AA773355557777337755777777777799777799999999BB99",
INIT_62 => X"714B9109EFB3CF8F91CFB1912BB1912BEF93CF6F91CFB1714BB1914BEF93CF6F",
INIT_63 => X"EFD1CF698F91CFB19129D19129EF93CF6F91CFB1712BB1914BEF93CF6F91CFCF",
INIT_64 => X"AF67EF35B1B1EFAF35CF11CD2F69EF5591B1EF8F35CF11CD2F8BF17371D1EF6F",
INIT_65 => X"F1714DD1CFCD3169CFB16FF1D1CF4DCFCFCD2F8BAF8F8FF1D1CF4BCFD1CD2FAD",
INIT_66 => X"3175F1EF8F27CFB3D133F1EF3173F1EF6F25CF93F151F1EF3193F1EF5125CF55",
INIT_67 => X"AD2DADF17351D1EF4F55EF11AD2BADD19353D1EF4F55EFEFAF29CFD1B133D1EF",
INIT_68 => X"35B1B1EFAF35CF11CD3169EF5591B1EF8F35CF11CD2F8BF15571D1EF6F35CF11",
INIT_69 => X"EF31B111EF5145EF55F171F1CF33B111EF3145EF55D191F1CF33D111CD3167EF",
INIT_6A => X"777777779999999933555577AB2A25CF93F153F1EF3193F1EF7125CF73F151F1",
INIT_6B => X"F17351D1EF443333775533777799997777557755777777557777BB9999999977",
INIT_6C => X"D1EF4FCF11CD3169EF5591B1EF8F35CF11CD2F89F15571D1EF6F35CF11CD2DAB",
INIT_6D => X"11EF51AB67EF55B1B1EF8F35CF11CD2F89F15591D1EF6F35CF11CD2D8BF17351",
INIT_6E => X"2FB3D1F1CDF1158925CE0CCFF193D1EFCFF113AB23CE0EEFEF55F1EFEFF111EF",
INIT_6F => X"CCABADF17533F1112F37EF11AC0BCDD1933311113155F1EF8E07EFB3B3331111",
INIT_70 => X"13474C2FEFEF37F1CCF19305F1692C2FF1EF55F1CCF17503CFAB0C4FF1EF55F1",
INIT_71 => X"EFEF55EFEFEFF10FF1238E0FEFEF37F1CFEFD10B11256C0FEFEF37F1CDF1B307",
INIT_72 => X"F1CDF1156945EE0CCFF193D1EFCFF113AB23CE0EEFEF75F1EFEFF111CF03AE0E",
INIT_73 => X"23CDCD0C6FF1D175F1CCF137238BCD0C8FF1D193F1CDF1374567EF0CAFF1B1D1",
INIT_74 => X"777777779999999911333377CD68EF37F1CCF17503EF8B0C4FF1EF55F1CCF155",
INIT_75 => X"EFEFEFF10F007733773333777799997777557755777777557777BB9999999955",
INIT_76 => X"F10FEFEE0CCEF193D1EFCFF1138B25CE0ECFF173F1EFEFF111CD03AE0EEFEF55",
INIT_77 => X"0C6FF12393D1EFCDF1158925CE0ECFF173F1EFCFF113AD23AE0EEFEF55F1EFEF",
INIT_78 => X"EF676753B1D1B10BAFEFCF55AF69453373F1B109AFEFCF55AD8D255355F19127",
INIT_79 => X"EF7355CDCFD1F10FCD45AF2ED1EF55CDCFD1D10BEF678F2FD1CD55CDCDD1B309",
INIT_7A => X"45D1CDB37547AF0BD137F12F45F1CDB39345AD0DD135F10F47F1CDB393458D2F",
INIT_7B => X"558BAD257335F17125D1EFD1558BAF279137F15125D1EFD15567AF29B117F131",
INIT_7C => X"13B3D1B10BADEFCF55AF69453393D1B109AFEFCF55AD8B255355F19127D1EFD1",
INIT_7D => X"0F69F1CD93B1458B11D173D10D69F1CD75B1476913D193D10D8DEFCF75AF6747",
INIT_7E => X"337777777777777777773333116845AF0DD135F10F47F1CDB39345AD0FF155D1",
INIT_7F => X"255335F171243355557755555599BBBB77BB777777777777777799BB99997777",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000000000000FFFFFFFFF00000",
INITP_02 => X"0000000000000000000000000000000000FFFFFFFFF000000000000000000000",
INITP_03 => X"0000000000000000007FFFFFFFF0000000000000000000000000000000000000",
INITP_04 => X"003FFFFFFFE00000000000000000000000000000000000000000000000000000",
INITP_05 => X"8008008000000000000000000010010000000000000000000000000000000000",
INITP_06 => X"020000000000000000000000000000040000000000000000001FFFFFFFC00800",
INITP_07 => X"02002000000001000000000080000000101FFFFC0FC000000000000000000000",
INITP_08 => X"0000002000004004005FFFFC0FC0000000000000000008008000000000000000",
INITP_09 => X"00003FE010010000000000000000000000020020020000024000000000000000",
INITP_0A => X"0000000400400000000000000000000000020020000000000000000000000000",
INITP_0B => X"0000000000000001000000000000000000000000020000000000000000000000",
INITP_0C => X"0010010002202202000000400000000800000000000000000000000000000001",
INITP_0D => X"8044044048088088088080180180100110110110110110110110300300300220",
INITP_0E => X"0000000000000000000000000000000000000000000000000200200200000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"F19127EFCF55AF69453393D1B109AFEFCF55AD8B453375F19127D1EFD1558DAD",
INIT_01 => X"CD93B3CD69473393D1B10BAFEFCF55AF8B453375F19129CFEFCF55AD8D255355",
INIT_02 => X"89D1697591EF918B91EF8DCF91AF7191AFCF8F6D91EF8FCFB1B171B1B1CF8F6F",
INIT_03 => X"71CD6F6B7335F14F6991CD73938D716B9135F12D6991AB73938D716DB115D10B",
INIT_04 => X"71B1AB93AFCF9171CF91AF8B71D18993AFCF9191CFB1B18971D189B1B1CF8F73",
INIT_05 => X"CFB19171B191CF8D6F91CD91CFAF9171AF91CF8D6FB1AB93CFCF9171CF91CF8B",
INIT_06 => X"91CFCF918B91EF8DCF91AF7191AFCF916D91EF8FCFB1B171B1B1CF8F6D91CD91",
INIT_07 => X"8971F189B191CF9191CFAF918991F18BB191CF7191CFAF918B91EF8BCF91CF71",
INIT_08 => X"335577335555555511557733EF48CF9191CF91B18971D189B3B1CF9191CFB1B1",
INIT_09 => X"71B1B1CF8F6F89AA337755999999BBBB77777777777777557777779977557777",
INIT_0A => X"CF8F6FEF8DCF91AF7191AFCF918D91EF8FCF91B17191B1CF8F6D91CD91CFB1B1",
INIT_0B => X"89B1B173AF7191AFCF918D91EF8FCF91AF7191B1CF8F6D91EF8FCFB1B171B1B1",
INIT_0C => X"2F672D07CF51F171EF312D33D193D1CD2B33D191F12F3133D1B1D1CD2F33B1B1",
INIT_0D => X"D1CCCF51CFCFCDCF4FD1EFD1CDCFD151CFD1CDCF4FD1EFD1CDCFD171CDD1CFCD",
INIT_0E => X"D1B127397155F1EF45339153D19125399155F1EF2533B153D1732537B135AF07",
INIT_0F => X"33B1D1D1AB2F53B1B1F12B355193F1D189315191D1D129375173F1D167337173",
INIT_10 => X"EF2933F171EF312D33F193D1CD2B33D191F12F2F33D1B3D1CD2D33D191F12F33",
INIT_11 => X"53D1732537D155F1EF2533D153F1532735F155F1EF2733F153EF332935F173D1",
INIT_12 => X"113377117733555511557755CD6655F1EF4533B153D1912537B135F1EF2333D1",
INIT_13 => X"D1AB2F33B1B1EF00117777777799BBBB77777777777777777777777777775555",
INIT_14 => X"33B1B1312B33F193D1EF2B33D171F1312F33D1B3D1CD2D33D191F12F3333B1D1",
INIT_15 => X"2537D1B373D1EF2933F171F1312F33D193D1CD2B33D191F12F3133D1B1D1AB2F",
INIT_16 => X"D151EEEFABCDEF6C03CF09CDCCAD0F0509CFEF4E03AF07EFCDAB0F0707EFEF2E",
INIT_17 => X"EF09D1F1AB0F3391D1D10B173393D1F167113373D1D109195355F1F145135353",
INIT_18 => X"0F472F03EFEF69090F23F1AC0D692F25CFEF6B071125F1AC0BAB0F45CDEFABEF",
INIT_19 => X"EFCDAB0F0705F1EF2F238F03EFCF890D0B03F1CD0F454F03EFEF890B0D03F1CD",
INIT_1A => X"030DADEF6C05D109CDCCCD2F030BCFEF4E03AF07CFCDAB0F0507EFEF4E03AF05",
INIT_1B => X"AC0BAD0D47CDEF4B031167F18C09CD0D89CCCF4D030F8BEF8C07CF0BABCCCD2F",
INIT_1C => X"77775577331111777733113322CDEF69071125F1AC0D8B0F45CDEF6B051145F1",
INIT_1D => X"0F0705F1EF2E238E02555533555577997777777711337799BB55557755333355",
INIT_1E => X"F1EF2ED109CDCCCD2F030BCDEF6E03CF07CFCDAB0F0509EFEF4E03AF05EFCDAB",
INIT_1F => X"0D47CD33CD2F030BCDEF6C03CF09CFCCAD0F0509CFEF4E03AF07EFCDAB0F0705",
INIT_20 => X"4EF1274CB1B10F8953EFCDEF072BAFF1F1D10D8B53EFCFEF0729D1F1F1B10DAD",
INIT_21 => X"F173692F4B27EFAD4F25AE25EFAD692D4D25EFAD2F278E25EFAF672D4F25EFAB",
INIT_22 => X"B173CDCF8B2F45F1F3EF7147B191CDCF693147F1F5EF5147B1B1CDCF4731232B",
INIT_23 => X"EF0927D1F1EFB12BAF53EFCFCD0B25D1F3EFB129AF73EFCFAD2D25D1F3EF9127",
INIT_24 => X"F1F3D10F6953EFCDEF072BAFF1F1D10D8B53EFCFEF0729CFF1F1D10DAD53EFCF",
INIT_25 => X"4591D1CDEF273169F1F3CF2F6791F1CDEF052F8BF1F3CF0F6773EFCDEF052FAD",
INIT_26 => X"773333333377773333333322CF8B3145F1F5EF5147B1B1CDCF493167F1F5CF2F",
INIT_27 => X"D1F1EFB10BAF53EFCF2233777777777777777777777777777777775555777733",
INIT_28 => X"B10BADEFCDEF052DAFF1F1D10D8B53EFCFEF072BAFF1F1D10DAD53EFCFEF0927",
INIT_29 => X"CDCF27F12DADF1F3D10F8B53EFCDEF072BAFF1F1D10D8D53EFCFEF0929D1F1F1",
INIT_2A => X"716B9389AFD32FF3F1714EF1B1ABB10D6DB351D1F1516EF1B1ABB32D6BB371B1",
INIT_2B => X"8FD18B718FD1714F9191CD6DCF4F8B718FEF516D71B1AB6DAF4F896F93EF518D",
INIT_2C => X"91D10FB1D1F169717169711391B10CB1D1EF894F738B511391B10CD1B1EF6B8B",
INIT_2D => X"F1B189932F699391B1F12F8FF1D189934F6993B191D12FB1F1D16971716973F3",
INIT_2E => X"0B8FB12FF3F1714EF191ABB10D8DB32FD3F1516EF1B1ABB32D6BB351B1F1518E",
INIT_2F => X"33B1910CD1B1EF8D2D918D2F13B1912CD191EF8F0D918F0F13D1712EF191CDB1",
INIT_30 => X"55333377555555555555880CB1D1F1694F7389511391B10CD1B1EF8B2D938B31",
INIT_31 => X"B32D6B9371B1F1518E89CD555555557777775577557777777777777755555555",
INIT_32 => X"B371B1714EF191CDB10D8DB12FD3F1514EF1B1ABB32D6DB351B1F1516EF1B189",
INIT_33 => X"0CD1B193CDB10D8FB12FF3F1714EF1B1ABB30D6DB351D1F1516EF1B189B32D6B",
INIT_34 => X"AFCD7512ADCDB19145D18B2FD171EFD16FF1B1B145D1692FD191EFD14F1191D1",
INIT_35 => X"F16767F35147F371CFF112D3F1F145D37145D3B1CFD112F3F1F145B39145B3D1",
INIT_36 => X"EF67D1258F55CDEFF131F153CD69D1278F55CDD1F151F153CD8DD127CF558F12",
INIT_37 => X"4FB3AFEFF12F1191D145D1474F93AFEFF12FF171CF47D1456F75CDEFF111F153",
INIT_38 => X"D1B1D1B17145D18B2DF171EFD191F1B19145D1692FD191EFD14FF191B145D167",
INIT_39 => X"53ABADB129CF55CDD1D171D15389AFAF2BF155EFD1D1B1D17367D1AD2DF173EF",
INIT_3A => X"4444446655777755551100AF258F55CDD1F131F153CD8BD127AF55CDD1F151D1",
INIT_3B => X"EFD12F1191D145D1474F88115555771155335555777777777733555555332244",
INIT_3C => X"1191D1D18D2DF173EFD191F1B19145D18B2FD191EFD16FF1B1B145D1694FB3AF",
INIT_3D => X"D129CFB373EFD191D1B19145D18B2FD191EFD16FF1B1B145D1694FD18FEFD14F",
INIT_3E => X"EF09ACCF6733EF95D1D116F52389CD37F133F177D1D116134547EF55F133F159",
INIT_3F => X"23B3B1EFF1331191D123F1232F93D1EFF1331173CF45F1234F75EFEFF113F153",
INIT_40 => X"3BEF5536ADCD2393D1D173F139EF373689CF4575F1B1B1F159EF175467CF43EF",
INIT_41 => X"134745F175F133F139EF9316F16923D193F153F139EF7516EFAB23B3B3F153F1",
INIT_42 => X"37F153EF95D1F116F52389CD37F133EF77D1D116134567EF55F133F157EFB316",
INIT_43 => X"D157EF177445CF6737EF91D1D375F117B423CD8937EF73F1B3B3F117D423ABCD",
INIT_44 => X"00000022337777333311001336ABCD2373F1D191F159EF175467CF4555F1B1D1",
INIT_45 => X"F175F133F139EF93161101115555771133115555777777777733335555330000",
INIT_46 => X"33F159F116F42389CD37F133EF95D1D116132567CF55F133F157EFB316134545",
INIT_47 => X"177445378BCD37F133EF95D1D116F32369CF55F133F177F1D316134545F155F1",
INIT_48 => X"39F1EF3573F1D1714555ED25F1B553D12BAFD1914573EF05D3D553D129D1B18E",
INIT_49 => X"111367B175CD53F157CD9336CD6B47B193CD53F137CD7334CD8D45B393CD73D1",
INIT_4A => X"AA2BCCB1695513915345D155AA2DEAAF8B55F3B15347F1558931EA8DAD553375",
INIT_4B => X"05B3F353B127D1B3AC2791D1259313539125D193AC29AFD1477513717325D175",
INIT_4C => X"F12DAFCF734555ED27F1B553D12BAFD1714553EF05D1D553D129D1B18F4573CF",
INIT_4D => X"558933EA6DCD55D3D13169EF558933EB6BEF7593F12F8BEF536755EB27F19573",
INIT_4E => X"B14775112222220222222DCAAF895513915347F155AB2FEA8DAD55F3D13167EF",
INIT_4F => X"53B127D1B1AE2791D125B3262222220422AB335511115577777711EE222229CC",
INIT_50 => X"D1B18E55ED27F19553F12BAFD1714553ED05D1D553D129D1D18F4573CF05D3F3",
INIT_51 => X"EA8DCDAF9573F12DAFD1714555ED25F1B553D12BB1D18F4573CF05D3F353B127",
INIT_52 => X"AC4FCFF1B19371B19389D115F1B171F1B39371919389B315F1D171D1D1939191",
INIT_53 => X"93AFF191D18B93B1ACADD1932BD31191D18B93B1ACADCF734BB311B1B18993B3",
INIT_54 => X"518FCD737391F1B193F173F1518DEF739371D1B193F171F1716BEF73D371EFEF",
INIT_55 => X"15D1D171D1F193917193AB9333D1F191B3F193B17191CD9353B1F19193F173D1",
INIT_56 => X"F1B3B371B19389D11511B191F1B39371B19389B315F1D171D1D193919193ABB3",
INIT_57 => X"F1716BF153F371B1F193D171F17369F153F391B1F193B371D17369D135119191",
INIT_58 => X"937391F1B193F173D1518FEF739391F1B193F171F1716DEF73B371D1D193D171",
INIT_59 => X"71D1D193917193ABB333D1F171B3F193B10A0A888888AA6688AA896AD1518FCD",
INIT_5A => X"93917189D11511B191F1B39371B19389D115F1B171D1D19391919389B315F1D1",
INIT_5B => X"F153D391B191F1B3B371B19389D115F1B171F1D19371919389B315F1D171D1D1",
INIT_5C => X"3375F1EF8F3325CFD12DEFD1CD8FAFCDCF5327CFD12DEFD1CD6DD1CFCF3147CF",
INIT_5D => X"AD33D153B3D1B191513189D13591D15393F1B1B13331ABD15573F17175F191D1",
INIT_5E => X"AF8FCFF1CFCF4BCFD1AD0DCDAF6FCFF1CFD14DCFD1AF09EFAF4FEFF1CFD16D11",
INIT_5F => X"D1CF4DD1CFCD3169CFB16FF1D1CF4DCFCFCD2F8BAF8F8FF1D1CF4BCFD1CD2FAD",
INIT_60 => X"CDCF5105EFD12DEFD1CD8FAFCDCF5127CFD12DEFD1CD6DD1CFCF3147CFB14D11",
INIT_61 => X"EFAF2DEFF1CDB16DCDD18F07EFAF2DEFF1CDAF8FCDD17105EFD10DEFD1CD8FAF",
INIT_62 => X"F1CFCF4BCFD1AD0DCDAF6FCFF1CFD14DCFD1AF0BEFAF4FEFF1CFD16DCDD18F07",
INIT_63 => X"D1CFCD3169CFB16FF1D1CF4DD1CFCD318BAFAC00000000000000AC2FADAF8FAF",
INIT_64 => X"3149CF0DEFD1CD8FAFCDCF5125CFD12DEFD1CD6DB1CDCF3147CFB14D11D1CF4D",
INIT_65 => X"EFF1CD458FAFCDCF5125CFD12DEFD1CD6DAFCDCF5327CFD14D11D1CD6DD1CFCF",
INIT_66 => X"CD474C2FEFF1338F17EF11CD1169F13571D1336F17EF11AC0FABF15553F1114F",
INIT_67 => X"EFF14BEECDCD1167CFCF6F11EFCE2BEECFCC0F89CFAF8F11EFEE2BEEEFAC0DAD",
INIT_68 => X"1155F1EF6E05EF93D13311111173F1EF7103EF75D15311F111B311EF5103AE0E",
INIT_69 => X"AC0DADF17533F1112F37EF11AC0BCDD1933311113155F1EF8E07EFB3B3331111",
INIT_6A => X"37B1B133AF15EF11CD1167F13791D1336F17EF11CC0F89F15553F1334F17EF11",
INIT_6B => X"EE13B111EF3123EF35D17333CF13D111CD1323EF37D19133AF15F111CD1345EF",
INIT_6C => X"EF8E05EFB3D13311111175F1EF6F03EF73D13311F11193F1EF5103EF55F15333",
INIT_6D => X"F17553F1112F37EF11AC0BCDD19333F1113135EFEF8C07EFB1913311111155F1",
INIT_6E => X"F1114FEF11CD1167F13791D1338F17EF11CC0F89F15573F1336F17EF11AC0DAB",
INIT_6F => X"11EF31CD67EF3791D1338F17EF11CC1189F13571F1336F17EF11AC0FABF15553",
INIT_70 => X"51D1CDB375F1356945EF2EB1EF91AFD1CFF1338B45CF2ED1EF73CDCFD1F131AD",
INIT_71 => X"558BAFF1735311F15133EFCFAC2BAFD1935311F15133EFCFAE29D1D1B15311CF",
INIT_72 => X"EF676D51F1CD55CFCCD1B307CD894D51F1CD55CFCCD19305CDAB2D71F1CD73D1",
INIT_73 => X"D1EF55CDCFD1F10FCD45AF2ED1EF55CDCFD1D10BEF678F2FD1CD55CDCDD1B309",
INIT_74 => X"D1CFF1356945EF2EB1EF91AFD1CFF1338B45CF2EB1EF73CDCFCFF131AD45AF2E",
INIT_75 => X"05ABCD2C71F1AD73D1CCF1552589CF2C91F1AF91D1CDF1354767EF2C91EF8FAF",
INIT_76 => X"51D1CD55CFCDD1B307EF894D51F1CD55CFCCD19307CDAB4D51F1CD73CFCCD175",
INIT_77 => X"CDCFD1F12FCD45AF2ED1EF55CDCFD1D10DCF458F2ED1EF55CDCFD1D109EF676D",
INIT_78 => X"F12FCDEF2CB1EF91AFD1CFF1336945CF2EB1EF73ADCFCFF131AB45CF2ED1EF53",
INIT_79 => X"2C71F14591AFD1CFF1336945CF2EB1EF71ADCFCFF1338B45CF2ED1EF73CDCFD1",
INIT_7A => X"89B1AB93AFF1712971EF6D93718D8B3373D1514971CD6F936F6F895355F14F69",
INIT_7B => X"CF8F91699193F14F6989CF8F93AB9169B193F12F89ABAF9193AB936BCF93D12D",
INIT_7C => X"89B18975938B714DD135D10B8BB18975738B712FD135B1098BD1697573896F91",
INIT_7D => X"936F6F6B7335F14F6991CD73938D716B9135F12D6991AB73938D716DB115D10B",
INIT_7E => X"13B3D1712971EF6D93718D8B3393D1514971EF6F936F6F8B5353F14F6971CD71",
INIT_7F => X"098DD16975738B6F11D17391098DF16993738B8D13D19371296FEF6B93718B8B",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000100000000000000000000000000000000000000000000000000",
INITP_06 => X"9200010000000000000000000400000000000000000000008008800800800000",
INITP_07 => X"0000000080000000100100000000000000000000000000000200200000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000400400000000200200200000200000000000800000000000000000000",
INITP_0A => X"0000000000000003000000200000000000010000020000000000010010000000",
INITP_0B => X"0000000000000200000000000000000000000000000000000000000000000000",
INITP_0C => X"0000004000008008008008000000000000000000000010010010010000000001",
INITP_0D => X"1001001001000000000000000000000002002002002000000010010004000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000080000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"75938B714DD135D10B8BB18975938B714FD135B1098BD1697573896F31F15391",
INIT_01 => X"895335F14F6991CD71936D716B7335F12D6991AB73938D716BB115D12B89B189",
INIT_02 => X"F14F69EF6D93718D8B3393D1714971EF6F93716F8B3373F14F4971CD71936F6F",
INIT_03 => X"697573CD8D8B3393D1714971EF6D93716D8B3373F14F4971CD6F936F6F895355",
INIT_04 => X"CDB1273971CDD18FB1EFCFCDD1CF51CFCFCDCF6FD1EFCFCDCFCF51CFCFCDCF4F",
INIT_05 => X"33EF51AD7333F10DAB53AB33B17153AF9135D10BAD738935B38F538FB115B107",
INIT_06 => X"51D1CDD1CFCDB171CDD1CFCD51F1CDD1CFCDB191CDCFCFCD51F1CDD1CFCD8D33",
INIT_07 => X"CDCFCF51CFCFCDCF4FD1EFD1CDCFD151CFD1CDCF4FD1EFD1CDCFD171CDD1CFCD",
INIT_08 => X"D1CFCDD18DB1EFCFCDD1CF51D1CFCDCF6FB1EFCFCDCFCF51CFCFCDCF6FD1EFD1",
INIT_09 => X"AD71F1CDCFCFCD91B1CDCFD1AD71F1CDCFD1CD71B1CDCFD1AD91EFCFCFD1CF51",
INIT_0A => X"D1CFCDB171CDD1CFCD51F1CDD1CFCDB191CDCFCFCD51F1CDD1CFCDB191CDCFCF",
INIT_0B => X"51CFCFCDCF4FD1EFD1CDCFD151CFD1CDCF4FD1EFD1CDCFD151CFD1CDCD4FD1CD",
INIT_0C => X"CDCF4FEFCFCDD1CF51D1CFCDD18FB1EFCFCDCFCF51CFCFCDCF6FD1EFD1CDCFCF",
INIT_0D => X"CDCFCF35CF51D1CFCDD18FB1EFCFCDD1CF51CFCFCDCF6FD1EFCFCDCFCF51CFCF",
INIT_0E => X"0F472F03EF31F173EF110D15D193F1CD0B13D191F10F1113B1B3F1AB0D13B1B1",
INIT_0F => X"EFCCEE2FCEEFCCEF2FF1EFF1CCCFEE2FCEEFCCEF2FF1EFF1CDCDEF51CCEFCCEF",
INIT_10 => X"F1B1051B7335F1F123137133F19103199137F1EF2313B133F1730319B137AF05",
INIT_11 => X"33B3D1F1AB0F3391D1D10B173393D1F167113373D1D109195355F1F145135353",
INIT_12 => X"EF0713F173EF110B15D175F1CD0B13D191F10F0F15D1B3F1AB0D13B1B1F10D15",
INIT_13 => X"33F1530319D137F1EF0313D133F1330517D135F1EF0513F153EF130915F155F1",
INIT_14 => X"1B7355F1F123137333F191051B9137F1EF23139133F1730319B137F1EF0313D1",
INIT_15 => X"F1AB0F33B1D1F10B173393D1F189113393D1D109195375F1F145135353F1B105",
INIT_16 => X"33B1B1110B15F175F1CD0913D171F1110F15D193F1CD0D13D1B1F10F1313B3D1",
INIT_17 => X"0319D1D175F1EF0913D173F1110D15D193F1CD0B13D191F10F1313B3B3F1AB0F",
INIT_18 => X"D173CDCF8BCDCF6C07EE2BCDAB8B2F472BEFCF4C05CE29EFAB8B2F4929EFAD4E",
INIT_19 => X"EF0BB1CF690D53B1B1AD0B135393CFCF690F5391B1AF09157373CFCF270F7351",
INIT_1A => X"2F496E45CDCF672B5145EFAB2D694F45CDCF49293145EF8B2DAB2F67ABCF89CF",
INIT_1B => X"EFAD692F4B27EFAD4F25AE25EFAD692D4D25EFAD2F278E25EFAF672D4F25EFAB",
INIT_1C => X"452DCDCF6C07EE2BCDAB8D2F472BEFCF6C05CE29EFAB8B2F4929EFAF4E05AE27",
INIT_1D => X"8A2BCD2F89ABCF4B273189CF8A0BCF2DABABAF4B252FABCF6A09EF2DCD8BAD4D",
INIT_1E => X"45CDCF672B5145EFAB2F694F45CDCF49295145EF8B2D8B4F67ABCF49273367D1",
INIT_1F => X"2F4927EFAD4E25AE25EFAD692D4B25EFAD2F278E25EFAF672D4F25EFAB2F476E",
INIT_20 => X"EFAD4EEE2BCD8BAD2F472DCDCF6C05CE29EFAB8B2F4729EFAF4C05CE27EFAB89",
INIT_21 => X"2F67AB53AD2D452DCDCF6C07CE29EFAB8B2F472BEFCF4C05CE27EFAB892F4927",
INIT_22 => X"8ED10FB1D1730FAF91EF6BEF0D8D718BD3712F9191CD6BEF2D8B718DD1714F91",
INIT_23 => X"F191478FAF8BEF6B8D2BCE8BEF6B458FAF89EF698F2DAE89CD6D458FB189CF49",
INIT_24 => X"73B1898F8F71896F93CF31AD73D1898F6D718B8D95CF31AD73D1698F4D914B8E",
INIT_25 => X"EF2D8B718FD1714F9191CD6DCF4F8B718FEF516D71B1AB6DAF4F896F93EF518D",
INIT_26 => X"8BB3910FAF91EF69EF0B8D718BB3912FAF91EF6BEF2D8D718DD1712F9191CD6D",
INIT_27 => X"CD71F167AF2D918D8B95B10FCF71F169AF2B8F6F8BB5B10FAF91EF69CF0B8F6F",
INIT_28 => X"8DAF71896F93EF51AD73D1898F8D718B8D95CF31AD73D1698F4D918B8B95D10F",
INIT_29 => X"718DD1714F9191CD6DCF4F8B718FF1516D71B1AB6DCF4F896F91EF518D71B189",
INIT_2A => X"714F91EF69EF0B8D718BB3912FAF91EF6BEF0D8D718DD1712F9191CD6BEF2D8B",
INIT_2B => X"67AF2DF18F718BB3910FAF91EF6BEF0D8D718BD3712F9191CD6BEF2D8B718DD1",
INIT_2C => X"3167D1258FF32FF1EF3372F1D189D13169F12FD1EF3392F1D167F33167F351CF",
INIT_2D => X"4FF1CD314BD1339173D1AB2BCF71CD314FD133B153D1892DAF91CD2F51EF31F1",
INIT_2E => X"AFB112F3F1F14593B14591F1CF9112F1F1EF4771B1677111CF7312F1D1EF6767",
INIT_2F => X"F1D167F35147F371CFF112D3F1F145D37145D3B1CFD112F3F1F145B39145B3D1",
INIT_30 => X"118DD10FF1EF337211D1ABD1318BD12FF1EF3392F1D189F33169F351CFF133B2",
INIT_31 => X"11CF7312F1D1EF8B31AF8B3111CF533211D1CDAD11AFAD0FF1EF335211D1ABCF",
INIT_32 => X"F3F1F14593B14593F1AFB112F1F1EF4771B14771F1CF9112F1D1EF6951B16951",
INIT_33 => X"F35147F371CFF112D3F1F145D37145D391CFD112F3F1F145B39145B3D1AFB112",
INIT_34 => X"F371CF337211D1ABD1118BD12FF1EF3392F1D189F33169F351D1F133B2F1D167",
INIT_35 => X"12F1D155ABD1118BD12FF1EF3372F1D189F13169F351D1F133B2F1D167F35147",
INIT_36 => X"CFEF5536ADCDD17323F1890DD173EFF171F1D19123F1670FB1B3EFF153F1B1D1",
INIT_37 => X"1367451351251371CFD114F5F1F123F39123F391CFD11413F1F123D3B123D3D1",
INIT_38 => X"EF47F1036F55EFEFF133F133CD69F1038F37EFEFF133F133ABABEF05AF37B116",
INIT_39 => X"2FB3B1EFF1331191D123F1232F93D1EFF1331173CF45F1234F75EFEFF113F153",
INIT_3A => X"F1B1D1D17345F18B0DD173EFF191D1D19123F1670FD193EFF151F1B1B123F145",
INIT_3B => X"33ABADCF07CF37EFEFD171F13389CFCD09D135EFEFD191F15367EFAB0BF155EF",
INIT_3C => X"036F55EFEFF133F133CD67F1038F37EFEFF133F133CD8BEF05AF37EFEFF153F1",
INIT_3D => X"EFF1331191D123F1252F93D1EFF1331171CF25F1234F75EFEFF113F153EF45F1",
INIT_3E => X"11B1D1F18B0DF175EFF191D1D19123F1690FD193EFF171F1B1B123F1450FB3B1",
INIT_3F => X"EF07CFD175EFF191D1D17123F1890DD193EFF171F1B1B123F1470FB3B1EFF153",
INIT_40 => X"B12BCCB16973F195AFB334D1458BAF55CF53F175AFB334EF4769B175CD53F157",
INIT_41 => X"05B3AFEFF153D1B1B345F1275191AFEFF153D191B167F1076F73CDCFF153D173",
INIT_42 => X"37CF5554ABAF4593B1AD91D157CF555489AF4773B1AFB1D155CF357467B165CF",
INIT_43 => X"EF6967B175CD53F157CD9336CD6B47B193CD53F137CD7334CD8D45B393CD73D1",
INIT_44 => X"55CF51F195AFB334D1458BAF55CF53F175AFB334F14769B155CF53F157CD9334",
INIT_45 => X"B375D1359245AF6955D18FD1B373D1359245AF8B55CF71F1B391D135D1458DAD",
INIT_46 => X"54ABAF4593B1AD91D137CF555489AF4773B1AFB1D155CF357467B16775D18FD1",
INIT_47 => X"B175CD53F157CD9336EF6947B173CD53F137CD7334CD8B45B393CD73D137CF53",
INIT_48 => X"53F157B134D1458BAF55CF53F175AFB334F14769AF55CF53F177CDB334EF6767",
INIT_49 => X"357467358DAF55CF51F195AFB334D1458BAF55CF53F175CDB334EF6769B175CD",
INIT_4A => X"738FCD737393CFB1AB93D10B13D391F18D73CFAFABB1B10BF3F391D18B73CFAD",
INIT_4B => X"15F3AD73936991D173697393898FAD737369B1B3736B91938971AB737369B193",
INIT_4C => X"AAADEF736D9311B1B18BB193AA8FED538D93F1D1918BB193AA91ED51CF9311B3",
INIT_4D => X"09F3F191D18B93B1ACADD1932BD31191D18B93B1ACADCF734BB311B1B18993B3",
INIT_4E => X"F18F71CFB1AB93CF0B13D391F18D73CFAFABB3B10BF3D391F18B73CFAFABB193",
INIT_4F => X"93AB91ED4FF193D1F1918FCF93AB93ED2FF193D1F18F6FCF91AB93CF2D11B3B1",
INIT_50 => X"736DB311B1B18B9193AA8FED738D93F1D1918BB193AA91ED51AF93F1D1918DCF",
INIT_51 => X"91D18B73B1ACADB1932BD3F191D18B93B1ACADCF734BB31191B18993B1ACADEF",
INIT_52 => X"73CFAC93CF0B13B391F18D73CFAFABB3B10BF3D391F18D73CFAFABB19309F3F1",
INIT_53 => X"ED51CF71B391F18D73CFB1AB93B10B13D391F18D73CFAFABB1B109F3F191D18B",
INIT_54 => X"CC8FCFF1CFD153B13345F135F19153D1B3D151913367F115D1B153D1D1D17151",
INIT_55 => X"D1CDF1AFF1CD55CFCCF1F1552DF1F1CFF1CD55CFCCF1EF554FD111CFD1CD73D1",
INIT_56 => X"332FCDB37553F19155F191D1332BEFB39353D1B155F173F13329EF93B3531111",
INIT_57 => X"15B1D153B3D1B191513189D13591D15393F1B1B13331ABD15573F17175F191D1",
INIT_58 => X"F175D133B13345F135F19153D193D151913345F115D1B153D1B3D171713367D1",
INIT_59 => X"F13327F173D153B1D155F153D13325F175F15391F175F133D13345F135F17173",
INIT_5A => X"B15573F17155F191D1332DCDB39353D19155F171F13329EF93B353D1D155F153",
INIT_5B => X"53B3D1B171513189D135B1D15393F1B1915331ABD15593F17375F191B1332FCD",
INIT_5C => X"B1715145F135F19153F193D151913345F115D1B153D1B3D151713367D115D1D1",
INIT_5D => X"F193D3B17153F193D151913345F135F19153D1B3D151713367D115D1D153B3D1",
INIT_5E => X"1355F1EF6E1323EFEF2FEFF1CC8DCFCDCF3325EFEF2F11F1CC4DEFCDCD1345EF",
INIT_5F => X"AC13D133B3D1D173331167F13791D13395F1D191330FABF15573F15355F1B1D1",
INIT_60 => X"CF8FCFF1EFEE2BCEEFAC0BCDCF6FCFF1CFEE2BCCEF8C09EFCF4FEFF1CDEF4D11",
INIT_61 => X"F1CC4BEECDCD1167CFCF6F11EFCE2BEECFCC0F89CFAF8F11EFEE2BEEEFAC0DAD",
INIT_62 => X"CCEF3103EFEF2FEFF1CC8DCFCCCF3323EFEF2F11F1CC6DEFCDCD1345EFF14F11",
INIT_63 => X"EFCF2FEFF1CDCF6DCCEF6F05EFEF2FEFF1CCCF8DCCEF5103EFEF0FEFF1CCAFAF",
INIT_64 => X"F1EFEE2BCEEFAC0BCDCF8FCFF1CFEE2BCEEF8C09EFCF4FEFF1CDEF4DCCF18E05",
INIT_65 => X"EECDCD1167CFD16F11EFCC2BEECFCC1189CFAF8F11EFCE2BEEEFAC0FABCFAFAF",
INIT_66 => X"1347CF0FEFF1CC8DCFCCCF3323EFEF2F11F1CC6DCFCDCD1345EFEF4F11F1CC4B",
INIT_67 => X"EFF1CD238DCFCCCF3323EFEF2FEFF1CC6DCFCDCD1325EFEF4F11F1CC4DEFCDCD",
INIT_68 => X"AD676D51F111F38F13EFCFCC316BF15591F1F36F13EFCFCC2F8DF17571F1F36F",
INIT_69 => X"D1EF4BEFCFAF3189CFB18F11EFAD4BEFCFAC2FABAFB1AF11CFAD4BEFEF8E2FCD",
INIT_6A => X"3153CFCF8F27D1B3D15313CF3171CFCF7125D193CF73F3CD31B1CFCF7125912E",
INIT_6B => X"AC2DAFF1735311F15133EFCFAC2BAFD1935311F15133EFCFAE29D1D1B15311CF",
INIT_6C => X"55B1D1F38F13EFCFCC3169F15591F1F38F13EFCFCC2F8BF17571F1F36F13EFCF",
INIT_6D => X"AD31D1CFCF5145F155CF91F3AD31D1CFCF5147F155D1B1F5AD13F1CFCD3167F1",
INIT_6E => X"CF8F27D1B3D15313CF3171CFCF8F25D193D153F3CD3191CFCF7125D175CE73F3",
INIT_6F => X"F1737311F14F33EFCFAC2BAFD1935311F15133EFCFAE29D1D1B15311CF3153CF",
INIT_70 => X"11F16FEFCFCD3169F15591D1F38F13EFCFCC2F8BF17571F1F36F13EFCFCC2FAD",
INIT_71 => X"CFCF51AB69F155B1D1F38F13EFCFCC318BF15591F1F36F13EFCFCC2F8DF17573",
INIT_72 => X"B3B1897593F1732B89EF8F73EF6D6991B1F1714989EF8F73CD8F699193F15169",
INIT_73 => X"936F71F1B191F18FB12BAF6FCF8D73F1B191F16DB12DAF6FCF8B73D1CF91D16B",
INIT_74 => X"89ABAF91B389936BCF93D10D89CD8F91B389916DCE93B30B89CD8F91D1698F71",
INIT_75 => X"73CD91699193F14F6989CF8F93AB9169B193F12F89ABAF9193AB936BCF93D12D",
INIT_76 => X"71B1D1732B89EF8F73EF6D6991B1F1714989EF8F73CD8F699193F1716989CF8F",
INIT_77 => X"0B89EF8F91F1698F71CFB3930B89EF8F73F1696D71CFD1932B89EF8F73EF6B6B",
INIT_78 => X"91B389936BCF93D10D89CDAF91B389916DCE93B30B89CD8F91D1698F6FCEB3B3",
INIT_79 => X"699193F1516989CF8F93CD9169B193F14F69ABAF8F93AB936BAF93D12D89ABAF",
INIT_7A => X"F15169EF8F73EF6D6991B1F1734B89EF8F73EF8F699191F1714989CF8F73CD91",
INIT_7B => X"8F91D1896B6991B1F1734B89EF8F73EF8D6991B1F1714989EF8F73CD8F699193",
INIT_7C => X"45D1CDD1CFF1314751EF2BB3538FAD3373D12F6953CD2FB35171AD5353F12F8B",
INIT_7D => X"CD8DAF257155F17127CDEFCF5589AF279155F15125CDEFD17567B127B155F131",
INIT_7E => X"CD73675593AF536FD135B107AD91455573AD5151D1339105AFB1257573AD71D1",
INIT_7F => X"D17151AD7333F10DAB53AB33B17153AF9135D10BAD738935B38F538FB115B107",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000007800000000000000000000000000000000000000000000000",
INITP_03 => X"F000000000000000000000000000000180000000100000000000000000000000",
INITP_04 => X"000000000000010010000000000000000000000000000000000000000000079F",
INITP_05 => X"110010010012412400400000000000000000000000000FFFF808000000000000",
INITP_06 => X"40040040040049049000080080083FFFFFE08008008209201200010010010010",
INITP_07 => X"0000000000007FFFFFF000000000000000000000000000000000000000000000",
INITP_08 => X"FFF8000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"400000200200000000000800800800800000000000000000000000000000FFFF",
INITP_0A => X"00000000000000000002002002002002000001001003FFFFFFFC400400400400",
INITP_0B => X"0000000000000000000000000003FFFFFFFC0000000000000000000000000000",
INITP_0C => X"008008000001FFFFFFFC000001001001001001000000000F8000000000200200",
INITP_0D => X"FFF80000000000000000000000001F7FE0000000000000000000000008008008",
INITP_0E => X"0000000000003FFFF00000000000000000000000000000000000000000007FFF",
INITP_0F => X"FFC000000000000000000000000000000000000000007FFFFFF8000000000000",
INIT_00 => X"13B1D1314751EF2BB3538FAD3393D1316953CD2FB35171AD5353F12F8B53AB31",
INIT_01 => X"058FD1257553AD7133D17353258FF1279353AF8F13D191332771EF2993538FAF",
INIT_02 => X"5593AF536FD135B107AD91455593AD5171D1339105AFB1455573AD7131F15373",
INIT_03 => X"AD5333F12DAB53AB33B17153AF7333D10BAD538935B18F538FB115D109AD7367",
INIT_04 => X"F12D8BEF2BB3538FAF3393D1316953CD2DB35171AD3373F12F8953CD31B17151",
INIT_05 => X"257553CD8FAF3393D1314953CD2DB35171AD3373F12F6953CD2FB17171AD5353",
INIT_06 => X"EFB1051B73CCF18FD1EFEFCCEFCE2FEECFCCEF6FD1EFEFCCEFEE2FEEEFCCEF4F",
INIT_07 => X"33EF53CF7333F10BCD338913D17133D19133D109CF536715B1B133B1B113B105",
INIT_08 => X"2FF1EFEECDCDD171CCEFCCEF2FF1EFEECFCCD191CCEFCEEF51F1EFEEEFCCAB15",
INIT_09 => X"CCEFEE2FCEEFCCEF2FF1EFF1CCCFEE2FCEEFCCEF2FF1EFF1CDCDEF51CCEFCCEF",
INIT_0A => X"EECDCDF18FD1EFEFCCEFCC2FEECFCCEF6FD1EFEFCCEFCE2FEEEFCCEF4FF1EFF1",
INIT_0B => X"0046F1EFCEEFCC91D1CCCFEECF71EFEFCEEFCC71CFCDCDEEAFB1EFEFCCEFCC4F",
INIT_0C => X"EFCDCDD171CCEFCCEF2FF1EFEECFCCD191CCEFCEEF51F1EFEEEFCCB1B1000000",
INIT_0D => X"2FEEEFCCEF2FF1EFF1CCCFEE2FCEEFCCEF2FF1EFF1CDCDEE4FCCEFCCEF2FF1EF",
INIT_0E => X"CCEF4FEFEFCCEFCC2FEECFCCEF8FD1EFEFCCEFCE2FEEEFCCEF4FF1EFEFCCEFEE",
INIT_0F => X"EFEEEF17CC2FEECDCDEF8FD1EFEFCCEFCE2FEECFCCEF6FF1EFEFCCEFEE2FEEEF",
INIT_10 => X"2F496E45CD51F171CD310B33D193CFAB0B33D191CD2F0F33D1B1CF8B0D53B1B1",
INIT_11 => X"EF8AEF4FCCCFACF151F1CFD1ADCFEF4FCCCFAEF151F1CFD1AFAFEF6FAAD1AED1",
INIT_12 => X"CF8F07177155EFCF25119151CF8F05159155EFCF0511B133CF710515B155AF27",
INIT_13 => X"53B1B1CF690D53B1B1AD0B135393CFCF690F5391B1AF09157373CFCF270F7351",
INIT_14 => X"AB0933F171CD310B33D193CFAB0933D171CD2F0F33D1B1CF8B0B33D191CD2F11",
INIT_15 => X"55EE224615D155CFCD0511D151CF510715CF55CFCD0731F151CD310935CF73CF",
INIT_16 => X"177175EFCF25119151CF8F07159155EFCF0511B10F4444444488134422773355",
INIT_17 => X"CF890D53B1B1AD0D135393CFCF690F5391B1AF0B157373CFCF470F7371CF8F07",
INIT_18 => X"53B1B1310B33D173CFAB0933D171CD310D33D191CF8B0B33D191CD2F1153B1B1",
INIT_19 => X"0515D1F173CFAB0933F171CD310D33D193CFAB0B33D191CD2F0F33B1B1CF890D",
INIT_1A => X"712FCD33EFEF6F690BEE8DEF474B8FAD8DEF6D6B0BEE8BEF49498FAD8BEF6D6D",
INIT_1B => X"118BAD6F490991CF6F694D0D91B1AD6F2909B1AF6F692D0DB1B1AD6D2909B18F",
INIT_1C => X"8F4DAE89AB6F458DB389AF476F6D8FABAB7147ADB389AF476FAF8FAB89716711",
INIT_1D => X"EF69478FAF8BEF6B8D2BCE8BEF6B458FAF89EF698F2DAE89CD6D458FB189CF49",
INIT_1E => X"AB8FEF6F690DEE8DEF474B6DAD8DEF6F6B0BEE8BEF49498FAD8BEF6D6D0BCE8B",
INIT_1F => X"BB995577CC4466240006668F474DCF8FCD676F6BABB1CD6F692DEF8DCD476D6D",
INIT_20 => X"89CD6F458FB389CF476F6D8FABAB71458DB389AA8977777799EFCC9955BBBB99",
INIT_21 => X"8FAF8BEF6B8D2BCE8BEF6B478FAF89EF6B8F2DAE89CD6D458FB189CF498F4DAE",
INIT_22 => X"6F8931EE8DEF474D6DAD8FEF6F6B0BEE8DEF49498FAD8DEF6D6D0BCE8BEF6947",
INIT_23 => X"8FAB677189B1AB8D6F896E6BEF8D674F89B1AD8D6F895189EF8B674DABB18D8B",
INIT_24 => X"13CF514795532FD3B1EF27CF31CF5147B3534FB3B1CD29EF31CF3149D1336F73",
INIT_25 => X"57B12F1551CD258C33CD910355912DF571CD25AE13CD710375712DD591CD27CE",
INIT_26 => X"53D1674C8FB1AD2D53D111F353F1454C6FB1AF2B55D1111353F1256C4FD18F27",
INIT_27 => X"EF51CD314BD1339173D1AB2BCF71CD314FD133B153D1892DAF91CD2F51EF31F1",
INIT_28 => X"4595732FD3B1EF27CE11CF514793532FB3B1CD29EF31CF3149B3334F93D1AB2B",
INIT_29 => X"BBBBBBBB55EECCEFEEEEAA0D1371EF258E2FCF712775910FF391EF27CE11CF51",
INIT_2A => X"4CAF91AD2D53F111F353F1454C8FB1AD2B5522AA3399999999777799BB9999BB",
INIT_2B => X"314BD1337173D1AB2BCF51CD314DD133B153D1892BCF71CD2F51F131D153D167",
INIT_2C => X"0FD3B1EF27CE11CF514793532FB3B1CD29EF31CF5349B3334F93D1CD29EF51CD",
INIT_2D => X"256C2FD18F2757B10F1373F1258E2FCF712775910FF391EF25AE11CF71457573",
INIT_2E => X"F1ABEF138BEF2FEFEF159411F189113369112FEFEF15B411F1671353451351EF",
INIT_2F => X"CF675111EF533613F1CD8933CD8B31EFEF335611F1CDAD33ADCD11EFEF137411",
INIT_30 => X"CFB11633F1EF23B3D123B3D1CF911633F1EF4593D14571F1EF731633F1EF6753",
INIT_31 => X"F1F1451351251371CFD114F5F1F123F39123F391CFD11413F1F123D3B123D3D1",
INIT_32 => X"13ABEF0FEFEF157411F189F13389112FEFEF15B411F167135347134FEFF114F4",
INIT_33 => X"99BBBB997777777777775522F1EF333611F1CDAB33ADAD31EFEF135411F1ABEF",
INIT_34 => X"33F1F123B3B123B3D1CF911633F1EF4593023311777799777777777799BB99BB",
INIT_35 => X"1353451371CFF114F5F1F123F37123F391CFD11413F1F123D39123D3B1CFB114",
INIT_36 => X"0FEFEF157411F189F13389F12FEFEF15B411F167133367134FEFF114D411F145",
INIT_37 => X"1613F1EF6953CF8931F1EF333611F1CDAB33CDAB31EFEF135411F1ABCF13ABEF",
INIT_38 => X"AD73EFD1B1B1F17347F16B2FAF71EFD191B1D19345F1494FAF91EFD173D1B1B3",
INIT_39 => X"F173F1538DCDB109AD55CDD1D173F1536BEFAF2BAD55CDD1D191F17367EF8D2D",
INIT_3A => X"B167D1076F55CDCFF153F153AF89D1078F55CDD1F153F153AFABD109AD55CDD1",
INIT_3B => X"5191AFEFF153D1B1B345F1275191AFEFF153D191B167F1076F73CDCFF153D173",
INIT_3C => X"D1B1B1F17347F16D2FAF71EFD191B1D19345F14B2FAF91EFD173D1D19345F129",
INIT_3D => X"BBBB997799997777997777772200CDAF2BAD55CDD1D191F15369EF8D2DAD73EF",
INIT_3E => X"056F55CDCFF153F153B189D1078F55CC6633771199557733777799BB7799BB99",
INIT_3F => X"EFD173D1B1B345F1275191AFEFF153D191B345F1076F73CDCFF153D173B167D1",
INIT_40 => X"F17347F16D2FAD73EFD1B1B1D17345F16B2FAF91EFD191D1D19345F129518FAF",
INIT_41 => X"B109AD55CDD1F173F1538BCDAF2BAD55CDD1D191F15369EF8F2DAD73CDD1B1B1",
INIT_42 => X"899191936D8FF1736973918B8B8F71936D91F173697391898B8F71936B91D173",
INIT_43 => X"716BF1756F718E8F89738F93716DF1756D73908D89938F936F8FF1756B73908B",
INIT_44 => X"736B91938971AB737369D193716D91918973AD937169D175716F8E9189738D93",
INIT_45 => X"898DAD73936991D173697393898FAD737369B1B3736B91938971AB737369B193",
INIT_46 => X"936F8FF1736973918B8B9171936D91F173697391898B8F71936B91D173697393",
INIT_47 => X"BB99BB779955777799777777558871908D89938F936F8DF1756B73908D899191",
INIT_48 => X"938971AB737369B193716D919189668911335555775555557777777799777799",
INIT_49 => X"73936991D173697393898FAD739369B1B373699193896FAB737369B193736B91",
INIT_4A => X"F1736973918B8B9171936D91F1736973918B8B8F71936B91D173697393898DAD",
INIT_4B => X"8E8F89738D93716BF1756D738E8F89738F936F8DF1756B73908D89918F936F8F",
INIT_4C => X"33D1CFF1CF55CDCFEFD1B30F13D1CFF1CF55CDCFEFD1930D13F1AFF1CD55CFCD",
INIT_4D => X"0491AFD1CCD1EF13F1D1F1EFD191AFD1EFD1D11113D1CFEFCF73CDCFEFD1B10F",
INIT_4E => X"CCF1EF356FD111CFD1AF71D1CCF1EF35B1D1F1CFD1AF91D1CCD1EF2F22042422",
INIT_4F => X"0D13F1AFF1CD55CFCCF1F1552DF1F1CFF1CD55CFCCF1EF554FD111CFD1CD73D1",
INIT_50 => X"F1CF55CDCFEFD1B10F33D1CFF1CF55CDCFEFD1930D13F1AFF1CF55CFCDEFD175",
INIT_51 => X"BB9955777777779999BB3355553326CF1113D1CFEFCF73CDD1EFD1D10F33D1CF",
INIT_52 => X"356FD111CFD1AD73D1CCF1EF3508113355335577BB7777557755777777779999",
INIT_53 => X"AFF1CD55CFCCF1F1552DF1F1CFF1CD55CFCCF1EF554FF111CFD1CD73D1CCF1EF",
INIT_54 => X"CDCFEFD1B10F33D1CFF1CF55CDCFEFD1930F13F1AFF1CF55CFCDEFD1730D13F1",
INIT_55 => X"EF33F1B1F1EFD191AFD1CDD1CF1113D1CFEFCF73ADD1EFD1D11113D1CFF1CF53",
INIT_56 => X"F17353F175F133911323F137D19133D193F133711345F117D1B133B3B3F15353",
INIT_57 => X"00F153F11305EF93D13391D137F133D11303F175F15373F155F133B11303F135",
INIT_58 => X"130DCDD17553F17337F191D1130BCDD19333D19137F173F11307EFAA00000000",
INIT_59 => X"17B1D133B3D1D173331167F13791D13395F1D191330FABF15573F15355F1B1D1",
INIT_5A => X"F175F133B11323F137F17333D193F133711345F137D1B133D3B3F153531345F1",
INIT_5B => X"99BB77773377779977997777333322F175D13373F155F133B11303F155F15353",
INIT_5C => X"D15553F17355F191D1130BCDD10C553377557777BBBB99BB77777777777799BB",
INIT_5D => X"33B3D1D173331167F13791D13393D1D191330F89F13573F15375F1B1B1130DCD",
INIT_5E => X"33B11323F137F17333D175F133911323F137D19133D1B3F153531345F117B1D1",
INIT_5F => X"EF93D133B1D137F133D11305F173D13371D155F133D11303F155F15353F155F1",
INIT_60 => X"8C8DCFAECF5145CFD14F11EFAC8DEFAFCF5367CFD16F11EFAC6BEFAFAF3167CF",
INIT_61 => X"334444CCAF51EFEFADAD8DAEEF7147EFD151EFEFACADAFAEEF5145EFD14FEFEF",
INIT_62 => X"AF91CFEFCFCD4BCFEF8E2DCDAF91EFEFCFCD4B6644444422AB66448877335555",
INIT_63 => X"EFAC4BEFCFAF3189CFB18F11EFAD4BEFCFAC2FABAFB1AF11CFAD4BEFEF8E2FCD",
INIT_64 => X"AECF5145EFD14F11EFAC8DCFAFCF5367CFD14F11EFAC6BEFAFAF3367CFD16F11",
INIT_65 => X"BB3377777777335577553377551122EFEFACADADAEEF5145EFD151EFEF8C8DCF",
INIT_66 => X"EFCFCD4BCFEF8E2DCDAF91CFEFCF023355557799999999777777777733777777",
INIT_67 => X"EFAFAF3189CFB18F11EFAD4BEFCFAC31ABAFB1AF11CFAD4BEFCF8C2FCDAF91CF",
INIT_68 => X"45EFD14F11EF8C8DCFAFCF5345CFD14F11EFAC6BEFAFCF3367CFD16F11EFAC4B",
INIT_69 => X"EFEFADAD8DAEEF6F27EFAF51EFEFACAD8DAEEF5145EFD151EFEFAC8DCFAECF51",
INIT_6A => X"918DD193AFF1958B2DEF6FCE918FF193AFF1938D0BCF6FCE8F71F1B1B1F191AF",
INIT_6B => X"999977CE084666660802B3B3CED195694FCF6FAF918BD193CFD1958B2DEF6FCF",
INIT_6C => X"B14D8F6FCF8B93D1CF91D369916D8F8FB189661177779955AA559977BBBBBBBB",
INIT_6D => X"CE8F71F1B191F18FB12BAF6FCF8D73F1B191F16DB12DAF6FCF8B73D1CF91D16B",
INIT_6E => X"93CFF1958B2DEF6FCE918FF193AFF1938D0BEF6FCE8F6FF1B3B1F1918F0BCF6F",
INIT_6F => X"77555555555555551177335533CD886FAF918BD193CFD1958B2DEF6FCF918DD1",
INIT_70 => X"6FCF8B93D1CF91D36B916D8F8FAF8B0CEE773377559999777777557777995577",
INIT_71 => X"F1B1B1F191AF2BCF6FCE8D73F1B191F18FB12BAF6FCF8D73F1CF91D16BB14D8F",
INIT_72 => X"958B2DEF6FCF918DF193AFF1938D0BEF6FCE8F6FF1B3B1F1938F0BCF6FCE8F71",
INIT_73 => X"6D8FB18BB3B3CEB1B5696FCF6FAF918BB393CFD195894DEF6FAF918DD193CFF1",
INIT_74 => X"EF694753B1D1B10BABEFCF55CD6B455393F1B129CDEFCF55CD8D257175F19127",
INIT_75 => X"BBBBBB77EECCCDEEEECE0431D193D10D89EFCF73F1476931D1B3D10DABEFCF55",
INIT_76 => X"45CDCFB19345AF29CF55F13145EFCFB12C221177BB999977777799BB999999BB",
INIT_77 => X"55ABAF257155F17127CDEFCF5589AF279155F15125CDEFD17567B127B155F131",
INIT_78 => X"53B1D1B10BABEFCF55EF69455393F1B129ABEFCF55CD8B257373F19127CDEFCF",
INIT_79 => X"3377555577555533555555551188EFCF73F1476931D1B3D10D89EFCF75EF6747",
INIT_7A => X"B17567B129D155F13145EFCFB19345AF22333377777777777777777777997777",
INIT_7B => X"257175F17127CDEFCF55ABAF259155F17125CDEFD17589AF27B155F13145CDCF",
INIT_7C => X"B10BABEFCF55EF69475393D1B12BABEFCF55CD8B457373F19129CDEFCF55ABAD",
INIT_7D => X"CF93D1458D2FD193D10F89EFCF93D1456931D1B3D10D89EFCF75EF676753B1D1",
INIT_7E => X"33B1B11391D1116733CD0BD13391CF3373D10F8933CD0FD15353CF5353F10DAB",
INIT_7F => X"BBBB9977777777777777AA11D173332371D1059333B19113B1B1134553EF09B3",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"00000000000000000000000000003FFFFFF00000000000000000000000003FFF",
INITP_01 => X"0000000000001DFF8080000000000000000000000000FFFFFFE0000000000000",
INITP_02 => X"0000000000000000000000000001FFFFFFF00000000000000000000000000000",
INITP_03 => X"000000000007FFFFFFF80000000000000000000000000000000000000000007E",
INITP_04 => X"FFF900100000000008BF80000000000000000000000000000000000000000000",
INITP_05 => X"7FFFE00000000000000000000080080080001F0000000000000000010017FFFF",
INITP_06 => X"9009000000000000001E7FC000120120120000000003FFFFFFF8000000024024",
INITP_07 => X"007FFFE000000000000000000003FFFFFFF8000000000000FFFFE00000000900",
INITP_08 => X"000000000001FFFFFFF8000000000000FFFFFFC0000000000000000000000000",
INITP_09 => X"FFF0080880880880FFFFFFF000000000000000000000000000FFFFFFC0000000",
INITP_0A => X"FFFFFFF022022022022020020020020023FFFFFFE4404404404404004004FFFF",
INITP_0B => X"000000000000000003FFFFFFE00000000000000000007FFFA7E0000000000000",
INITP_0C => X"07FFFFFFF100100100100000000003FE0000200200200200FFFFFFF800000000",
INITP_0D => X"00000000000001FC0000000000000000FFFFFFFC080080080080000000000000",
INITP_0E => X"0000000000000000FFFFFFFC0000000000000000000000001FFFFFFFF8000000",
INITP_0F => X"FFFFFFFC0000000000000000000000001FFFFFFFF80000000000000000000000",
INIT_00 => X"CF73453791D13391D1339105CF912313AAEF55779977777777777799BB99BB99",
INIT_01 => X"D15353CF7333F10BCD338913D17133D19133D109CF536715B1B133B1B113B105",
INIT_02 => X"13B1D1114733EF0BD13391D13393D1118933CD0DD15371CF5353F10FAB33AB11",
INIT_03 => X"7733773355337777555577772291D1059333D19133D191134553EF07B333B1B1",
INIT_04 => X"37B1B13391D1339105CF73233793CF3371021133335577773355557777777777",
INIT_05 => X"CF5333F10DCD338913D17133D17333D109CD536715B19133B1B113B107CF5345",
INIT_06 => X"134753EF09D13391D13391D1116933CD0DD13371CF3373F10FAB33AB11D15353",
INIT_07 => X"035553CF7333F173332391D1057533D19133D191332571EF07B333B1B113B1B1",
INIT_08 => X"EFAF6FEEADAFF191D1D1CFAEEFCF4FEEADACF171F1CFD1ACEFCF4FEEAFACF151",
INIT_09 => X"BBBB7799997777999977776644ADEFB1B1D1CDAEEFAE8FEFABAFEFB1D1D1CFAE",
INIT_0A => X"4FF1CDD1CFAFEF8FABD1CFD14FEFCC66553333777777777777BB997777BB99BB",
INIT_0B => X"ACCFEF4FCCCFACF151F1CFD1ADCFEF4FCCCFAEF151F1CFD1AFAFEF6FAAD1AED1",
INIT_0C => X"EEADAFF191D1D1CFAEEFCF4FEEADAEF171F1CFCFAEEFCF4FEEAFACF171F1CFD1",
INIT_0D => X"33AA0200042226EE33EEEEEE048FD1CDAEEFAE8FEFABAFEFB1B1D1CFAEEFAE6F",
INIT_0E => X"D1AFAFEF8FAAD1CED14FF1CDD1CFAFCF8FAA26111111EF115555775577773355",
INIT_0F => X"4FCCCFACF151F1CFD1ACCFEF4FCCCFACF151F1CFD1AFCFEF6FAAD1AED14FF1CD",
INIT_10 => X"F191D1D1CFAEEFCF4FEEADAFF191F1CFCFAEEFCF4FEEAFACF171F1CFD1ACCFEF",
INIT_11 => X"CDB1EFAEAFCF8BAFEFB10800000000228FEFABAFEFB1B1D1CFAEEFAE6FEFABAF",
INIT_12 => X"CE918F670B6FEF6F69710B71CFAF6F470971EF6F696F0B91CFAF6F490991CF6F",
INIT_13 => X"99BB99997777779999777777EF48F16F6B91094FCE918F670B4FF16F69910B71",
INIT_14 => X"6F6B2B0DB193AD6D0B0BD18F6F88AA775555777733557777777799997755BBBB",
INIT_15 => X"91CFAD6F490991CF6F694D0D91B1AD6F2909B1AF6F692D0DB1B1AD6D2909B18F",
INIT_16 => X"670B6FF16F69710B71CEAF6F670B71EF6F696F0B91CFAF6F490991CF6F694F0B",
INIT_17 => X"66288F092FCF9126000844896F6B91094FCE9166660208666F6B910971CE918F",
INIT_18 => X"0DB193AD6D0B0BB18F6F6B0B0DAF93AD6B0B098866064466CC333377555533AA",
INIT_19 => X"6F490991CF6F694D0B91B1AD6F2909B1AF6F692D0DB1B1AD6D2909B18F6F6B2B",
INIT_1A => X"F16F69710B71CEB18F670B71EF6F69710B71CFAF6F490991CF6F696F0B91CFAD",
INIT_1B => X"090B460A6666002D680888CC89AAAAAA6666014DF16F6B910951CE918F670B6F",
INIT_1C => X"232DADF1F1EF2F692FEECFEF252BADF1CFEF2D8B0FEECFEF2727CFF1CDEF2BAD",
INIT_1D => X"9999777777779999BB55335555882D456FEFCFEF252F8BF1F1EF2F472FEFCFEF",
INIT_1E => X"AF4FCECDAB2F23EFF3ABAF25243377553377999977777733777777777777BBBB",
INIT_1F => X"EF2925CFF1CDEF2BAD2FEECDCD2B25CFF3ADCF29AF2FCECDCD2D23CFF3ABAF25",
INIT_20 => X"F1F1EF2F672FEECFEF252BADF1CFEF2D690FEECFEF2729CFF1CFEF2D8B0FEECD",
INIT_21 => X"238FCFCFEF453167EFF3CD4F456FCFCFEF452F0000000000454FEFCFEF232D8D",
INIT_22 => X"CDAB2F23CFF3ABAF25AF6FCFCD893125EFF3CD8F258F8FCCAB2244442244662C",
INIT_23 => X"CFF1CDEF2BAD2FEECDEF2B25CFF1CDCF29AF2FEECDCD2D23CFF3ABCF27AF4FCE",
INIT_24 => X"2F672FEECFEF252BADF1CFEF2D692FEECFEF2529AFF1CFEF2D8B0FEECDEF2727",
INIT_25 => X"0244EEEE11EFAB0011EF11777799997733CDEF884F454FEFCFEF252F8BF1F1EF",
INIT_26 => X"13EF530375332FD5D1CD05CE33EF330593334FB5D1CD07EE53EF1307B3137175",
INIT_27 => X"BB777711777777999977775555AA0D3791EF038E33EF710355730F15B1EF05CE",
INIT_28 => X"33F1452C91B1CF0B13D1113522555577555599BBBB9999777777777777779999",
INIT_29 => X"F151EF1109D1139155F1890AD171EF110DD113D333F1670AB191EF0F11F11115",
INIT_2A => X"0375532FF5D1EF05CE33EF330593334FB5D1CD07CE33EF1307B3137175F1AB09",
INIT_2B => X"5753F1036C33F191053788000000000306004477113333330000EF05AE13EF53",
INIT_2C => X"2CB1B1CF0D13F1113533F1232C91D1CF0915D1113553F1034C51EEB10515B10F",
INIT_2D => X"1309D1139155F1890BD171EF110DD113D333F1670AD191EF0F0FF113F533F145",
INIT_2E => X"2FF5B1EF05CE13EF330575332FB5D1CD07CE33EF3307B3137195F1AB09F153EF",
INIT_2F => X"EF3399BB9999775577BB99BBBB99BB99BB9999AA00000000000011EF53035553",
INIT_30 => X"F18DEF538BEF51CFCD3392D1F18B1153691151CFCD33B3D1F1691373471371EF",
INIT_31 => X"33777777775555775533555511882CD1CD5354F1F1AFCD53ADCD51D1CD3374D1",
INIT_32 => X"EF8F34EFF1D145D3D127B1B1CD88335577BB9999BB77777777777733777777BB",
INIT_33 => X"D1F1471391271371EFAD34D1D1F145F39125F391EFAF34F1D1D145F3D105F3B1",
INIT_34 => X"0E89EF51CFCD3392D1F18B11538B1151CFCD33B2D1F1691173491371CFCD34D1",
INIT_35 => X"D1CD5154EFF1AF893122AA5555773344EE55339999BBBB9977556652CDCD89AB",
INIT_36 => X"EFD1D145D3D125D1B1EF8F34EFF1D167B3F147B1B1EF7134EFF1D16773EF6971",
INIT_37 => X"1373271371EFAD34D1D1F1451391251391EFAF34F1D1F145F3B105F391EF8F34",
INIT_38 => X"51CFCD3392D1F18BEF538BF151CFCD3392D1F1691173691151CFCD34D1D1F147",
INIT_39 => X"115599BB9999777777BB99BBBB99BB99BB9999CC442222224444CD89EF53ADEF",
INIT_3A => X"698FCD93D173F1938BF13191698DCF93D173F1758BD12FB16B6BEF93B173D175",
INIT_3B => X"7755771155117733771111773389CC938FEF53716991CD93F173F1938DF15391",
INIT_3C => X"75AB930C8D9189B1F191B19175441177557799BBBB7777777777777777777777",
INIT_3D => X"B16B6BEFB3B191D17589D10FB16D69D1B39191B175ABB30CAF8F69D1D191B1B1",
INIT_3E => X"AA6A51F1938BF15191698DCD93D173F1758BF131916B6DEF93B173D17589D10F",
INIT_3F => X"9371EF734E899366AA3355BB999999777799BB999999BBBBBBBB99AA888888AA",
INIT_40 => X"0C8F9189D1F191B1B175CD930E8D9189B1F191D19173CD732E8B938993F191D1",
INIT_41 => X"EFB3B191D17589D10FB16D69CFB39191D175ABB30EAF8F69D1D19191B175AB93",
INIT_42 => X"F1938BF15191698FCD93D173F1958BF13191696DEF93B173F17589D12FB16B6B",
INIT_43 => X"7777997777777777779999BB99BBBBBBBBBB9977775555777777AA88CD93D173",
INIT_44 => X"AD7573B12DADF1534555CF47AF9353B12BAFD1732553CF45AFB353B329D1B371",
INIT_45 => X"5533557777775511773355331166EF556933CC69AD7591B12F8DF1554735CC67",
INIT_46 => X"8F29ACB16755F1735345F1558D0B2655555577779977777777557799BB335577",
INIT_47 => X"4591D1539327D1B3912571D14591D1537325D1938F278FD16773F1737325D175",
INIT_48 => X"775526F1534555CD47AF9353B12BAFD1732555CF45AFB353B329D1D1712573D1",
INIT_49 => X"356B31CA8DAB44EF3377779977777777777799BB99BB99BBBB99777777777777",
INIT_4A => X"D16755F1735345F1558D2BACAF8955D1935347F1558D2FCCAF8955D1933167F1",
INIT_4B => X"539327D1B3912571D14591D1539325D1938F2791D16773F1537325D1758F29AE",
INIT_4C => X"F1534755CD47AD9353B12BAFD1734555CF45AFB353B129CFD1712573CF458FD1",
INIT_4D => X"BB99777755777777BB779999BB99BBBBBB997777777777777777775588042FAD",
INIT_4E => X"33EFEFEFEF35CCCF11F1931133EFCFEFEF37CDCD33F1750F33EFCFF1EF37CDCD",
INIT_4F => X"7777337755553355553355332293ACEFEFF1D11313EFEFEFEF55ACEF11F1B311",
INIT_50 => X"CC13EF1771EFEFEFF1D153EFCC11EF4433777777777777777777777799777733",
INIT_51 => X"0F11EFCFF1EF37CDCC33F1372F11EFCFF1EF35CFCC33EF1751F1EFEFF1EF53EF",
INIT_52 => X"777777004411F1931133EFCFEFEF37CDCF33F1751133EFCFEFEF37CDCD33F155",
INIT_53 => X"F1EE11F11502337711BB99777777777799997799BB99BBBBBB99777777777777",
INIT_54 => X"1771EFEFEFF1D153EFCC11EF1791EFEFEFF1D171EFCC11F115D3CFEFEFF1B18E",
INIT_55 => X"CFF1EF37CDCD33F1372F11EFCFF1EF35CFCC33EF3751F1EFEFF1EF55EFCC13EF",
INIT_56 => X"CCEF11F1B31133EFCFEFEF37CCCF11F1931133EFCFEFEF37CDCD33F1550F13EF",
INIT_57 => X"BB99777755777777BB777777BB77BBBBBB99777777777777777777776600EF55",
INIT_58 => X"EF7153CF73D12FB13325EF55CF7153D193D12F913327EF55D19153B1B1B14F73",
INIT_59 => X"33EF11EEEE3377555577552455EF31D13305EF93D15371CF75D10FD13305EF75",
INIT_5A => X"332DCDF17353AF9155EF71CF330BCFCD89333355337755337777777777777777",
INIT_5B => X"55B1AF53B1D1B16F533169F15591AF5393D1B18F532F8BF17571AF7375EF91AF",
INIT_5C => X"77777722283325EF55CF7153D193D12F913325EF55D19153D1B1D14F713147EF",
INIT_5D => X"F13307EE6E26555511BB77777755777799997777BB99BBBBBB77779977777799",
INIT_5E => X"F17373AF7155EF71CF330BCDD19353AF9155EF51D13309EFD1B153B1B155EF31",
INIT_5F => X"53B1D1B16F533169EF5591AF5393D1B18F532F8BF17571AF7373EF91AF332FAD",
INIT_60 => X"0FB13305EF55CF7153D193D12F913325EF55D19153D1B3D14F713347EF55B1AF",
INIT_61 => X"777733555577777777999977999999BB9999779977777799BB77777755EF44D1",
INIT_62 => X"4F69EF73B191ABAF738F11EF4F6BEF73B191CDAF73AF11CF4D8BF1919191CD8F",
INIT_63 => X"882AAA680A6888888888880CF171ADEF719111EF6F69CF73D171ABCF739111EF",
INIT_64 => X"6F73EFEFAF698DB1D1518FEF6F73EFEF6C88AAAA66AA335555335577775555CC",
INIT_65 => X"CF6D8BF1917191CD8F73CF11CF6B8DF1B17191CD6F73CFEFAF6B8DD1D1518FEF",
INIT_66 => X"77777755AA518F11EF4F69EF73B191ABAF73AF11CF4F8BEF919191CD8F73AF11",
INIT_67 => X"EF7191668855335555777733557777777777997755BB9999BB99997777777799",
INIT_68 => X"EFAF698DB1D1518FEF6F73EFEF8F69ADB1F171ADEF7191F1EF8F67AF91F171AD",
INIT_69 => X"F1917191CD8F73AF11CF6D8DF1B17191CD6F73CFEFAF6B8DD1D1718FEF6F73EF",
INIT_6A => X"ABCF738F11EF4F69EF73B191ABAF73AF11CF4F8BEF719191CD8F73AF11CF4D8B",
INIT_6B => X"BB99557777555577777777775599BB99BB77777755777799997733555555666F",
INIT_6C => X"D191D1D1CFF1358927EE2FCED191F1D1CFF133AD27CE2FEFCF73F1D1CFF131CF",
INIT_6D => X"8AD175458DCD084CCDAC51D1CCF155476BCF2DAFD1AFB3D1CDF1556749EF2DCF",
INIT_6E => X"F1496C4FEFCD55F1CDD1B327D16B4C4FD1CC31CD88AB443333557733557744AB",
INIT_6F => X"EFCF55F1CFCFF12FD127AE2FEFCF55F1CFD1D12BF1278C2FEFCF55F1CFD1D329",
INIT_70 => X"BB3355553326EE2FCED191D1D1CFF1338B27CE2FCFCF73F1D1CFF131CF05AE2F",
INIT_71 => X"45AF22335555337777BB9977777733777777777777BBBB999977777777779999",
INIT_72 => X"4FEFCD55F1CDD1B327D1694C4FEFCD55F1CCD19525CF8B4D6FD1CD75D1CCD175",
INIT_73 => X"F1CFCFF12FCF27AE2FEFCF55F1CFD1D12DF1278E2FEFCF55F1CFD1D329F1496C",
INIT_74 => X"356929EE2DCFD191D1D1CFF1338B27CE2FCECF73F1D1CFF131AD07CE2FEFCF53",
INIT_75 => X"BBBB777755111177777755779999BB99BB117777777777BB997711113377ABAA",
INIT_76 => X"EF474533B3D1D10BCDF1EF37CD69233373F1B109CDF1EF37ABAB035355F1B105",
INIT_77 => X"F175F11167EFEF93D1238911D193F10F89EFEF75F1456713B1B3F10DABF1EF55",
INIT_78 => X"23EFEFD17545CF09D137F13323EFEFD19323CD0BD155EF22000000000022AB0F",
INIT_79 => X"37ABAD037355F19105EFEFF13789CD059137F17103EFEFF15567CF07B137F133",
INIT_7A => X"997777333344F1EF37CD67233393D1D109CDF1EF37CD8B035375F1B107EFEFEF",
INIT_7B => X"116722775577557777BBBBBB9999777777777777779999BB7777117777779977",
INIT_7C => X"D17545CF09D137F13323EFEFD19323CD0BD155F11345EFEFB1B323AB0FF155F1",
INIT_7D => X"037355F19105EFEFEF3789CD039137F17103EFEFF15567CF05B137F15323EFEF",
INIT_7E => X"D10DABF1EF35EF67233393D1D10BCDF1EF37CD89235375F1B107EFEFEF37ABAD",
INIT_7F => X"BBBBBB99BB77777777777777779999BB9977775577777799777777775555CCAB",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"00000000000000000FFFFFFFF800000000000000000000000000000000000000",
INITP_01 => X"07FFFFFFF800000000000000000000000000000000000000FFFFFFFC00000000",
INITP_02 => X"00000000000000000000000000000000FFFFFFFC000000000000000000000000",
INITP_03 => X"8018018018010010FFFFFFFC00000000000000000000000007FFFFFFF0000000",
INITP_04 => X"FFFFFFFA00600400400400C00C00C00C03FFFFFFF00C00800800801801801801",
INITP_05 => X"000000000080080080FFFF4FE000000000000001001001001001001000000000",
INITP_06 => X"0007FC000000002002000000000000000000000000000004FFFFFFF000000000",
INITP_07 => X"00000000000000000000000000000000FFFF03F0000001009001000000000000",
INITP_08 => X"00000000000000000FFC00000000000000000000000000000003F80000000000",
INITP_09 => X"07F800000000000000000100100000000003F800000000000002002002000000",
INITP_0A => X"0000000000000000000000040040040040000000000000000000080080080080",
INITP_0B => X"00000000000000000000000000000000000000000000000000CA002002002002",
INITP_0C => X"0010000000000000020020020020020000000000000000000000000000000000",
INITP_0D => X"0000000000000000800800800800800800800000000000001001001001001001",
INITP_0E => X"0000000000000000000040040040000000000000000000000000080080000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53B1B153B1D1316953EF2BD15391B15391CF2F8B53CD2FCF7371B17371EF2FAD",
INIT_01 => X"EF71734591D1259353CF7153CF91534571F127B353D19153D1B1336773EF29D1",
INIT_02 => X"D1736755B1D15391CF539125B191455591CF5371CF737125B1B1257571EF7353",
INIT_03 => X"EF7173B17153CF2DAD53AB33CF9153B19153D12BAF738935D1B153B1B153B127",
INIT_04 => X"553377551144EF2BD15391B15391CF318B53CD2FD17371B17371CF2F8D53AB31",
INIT_05 => X"4591D14433555599999999BB7777777777773377777799337777777755335577",
INIT_06 => X"55B1D15391D153B127B191455591CF5371CF539125B1B1457571CF7373EF7173",
INIT_07 => X"D17173CF2DAD53AB33CF9153B19153CF2BAF538935D1B153B1B153B129AF7367",
INIT_08 => X"316753EF2BD153B1B15391CF316953CD2DD15391B17371CF2F8B53CD31EF7173",
INIT_09 => X"9999BB7777777777777755777777BB337777777777335577773333555511CCAB",
INIT_0A => X"F191B1EF6B51F171F1716F51F1B191CD6D51F191F16F7171D1D191CD6F71D191",
INIT_0B => X"4771D171B1916973D173D1EF4771F171CF916B73F171B1EF4971F171CF716D51",
INIT_0C => X"91D169759171F1AF6771B191B1B16975B173F1CF6771B171B1B16975D173D1EF",
INIT_0D => X"71D1D18FAB6F71D191F16D7371B1F1AFAB7171B191D16B759191F1AF89719191",
INIT_0E => X"771133773322716D51F1B1B1EF6B51F191F16F6F51D1B191CD6D71D191F16F73",
INIT_0F => X"71B191676677775577BBBBBB7777777777777777777777775555115533117733",
INIT_10 => X"759171F1AF6771919191D16975B173F1CF6771B191B1B16975D173D1CF4771D1",
INIT_11 => X"91CD6F71D191F16D7371B1F1AFAB7171B191F16B757191F1AF8971919191D16B",
INIT_12 => X"F171EF716D51F191B1EF6B51F191F1716F51D1B191CD6D71D191F16F7171D1D1",
INIT_13 => X"BBBBBB777777777777777777777777777711773377115555553311117733AB4C",
INIT_14 => X"CCAF4F250BAFEF6E25B109AFCCAD4F2509AFEF4F258F09AFCFAD2F2707D1CF4F",
INIT_15 => X"0F49F18C2BAD0B4BCCD16D250F6BF18C29AF0B6DCCCF4D250D8DEF6E27B10B8D",
INIT_16 => X"2F672D07CFD18B2B0D05F1AD2D690D27CFD18B290F27F18C2D8D0D29CDD16B27",
INIT_17 => X"D1CFAB2F2907D1CF4F456F07D1CF8B2D0905D1CF2F474F07CFCF8B2D0D05D1AF",
INIT_18 => X"77555511CC01B109AFCCAF4F250BAFEF6F25AF09AFCDAD2F2709D1EF4F258F07",
INIT_19 => X"8C2BAD0B011177337733559977777777557799BB335577553355777755773311",
INIT_1A => X"07CFD18B2B0D05F1AF2F692D27CFD18B290F27F18C2D8B0D29CFD16B270F49F1",
INIT_1B => X"2F2707D1CF4F456F07D1CFAB2D0905D1CF2F474F07CFCF8B2D0B05D1AF2F672D",
INIT_1C => X"EF6E27B10BAFCCAF4F250BAFEF6F25AF09AFCDAD2F2709CFEF4F258F07D1CFAB",
INIT_1D => X"3355997777777755777799BB337777551155557755775511335577553333228D",
INIT_1E => X"030DAD3311EF0F6733EEEFEF030BCD33F1EF0D8933EEEFEF0507EF33EFEF0BAD",
INIT_1F => X"33EF4F2391D1EFEF2311673333EF2F2371F1EFEF230F893313EF0F4553F1EFEF",
INIT_20 => X"D151EEEFAB0F231133CD8F03D171EFEF6711231133CD6F03B1B1EFEF45114513",
INIT_21 => X"EF0705F133EFEF09CD33EEEFCD0B03F133EFCF07CF33EEEFAB0D031133CDAF05",
INIT_22 => X"555533116633EEEFEF030BCD3311EF0D8933EEEFEF0507EF33EFEF0BAB13EEEF",
INIT_23 => X"0391D1EFEF445555777777777777777777777799777733777755775555553377",
INIT_24 => X"EFAB0F031133CD8F03D171EFEF8911231133CD6F03B191EFEF4511451333EF4F",
INIT_25 => X"F133EFEF0BCD33EEEFCD0903F133EFCF07CF33EEEFCD0D031133CDAF05CF51EE",
INIT_26 => X"0F4733EEEFEF030BCD3311EF0D6933EEEFEF0509CF33EFEF0BAB13EEEFEF0705",
INIT_27 => X"77777777777777777777999977771177775555553355553377555555332211EF",
INIT_28 => X"53EF730573532FF5D1AF09CF53EF5307915351B5F18F2BEF73CD53098F337173",
INIT_29 => X"558F0F5571D1058E53EF910755910F3591D107AF53EF710553710F15B1CF07CF",
INIT_2A => X"53F1274CB1D1AD2D33AD313553F1076C91F1AF0B35AF113573D1056E73EF8F09",
INIT_2B => X"F173CD330BAF339173F16B2CD191CD310DAF33D353F1494CD1B1CD2F31AD3315",
INIT_2C => X"55777722F5D1AF09CF53EF530771534FD5F1AF29EF73CD530991537193F18D2B",
INIT_2D => X"5771D1058E5344EF33335533775533777777777777777733EF11EEEE33337755",
INIT_2E => X"4CB1D1AD2D33AD313553F1274C91F1AF0B33AF113553F1076E73EFAF09358F0F",
INIT_2F => X"330BAF339173F16B2AF191CD310DAF33B353F14B4CD1B1CD2F31AD33F353F127",
INIT_30 => X"2FF5D1AF09CF53EF530771532FD5F1AF29EF53EF530991535193F18D2BF173CD",
INIT_31 => X"3333337777111177777777777777773311773333557777553377555566057373",
INIT_32 => X"F171EF918FF191B189938F6FF16FEFB16DF191B169938D6FD18DF1B14D1191CF",
INIT_33 => X"EF6DB191CD8F938BF173CDB1CF8FB191AB91918DF171CD91AFAF91918991916F",
INIT_34 => X"EF6B9389AF9389D1F12BD171CD6D938BAF93ABD1EF4DD171CD8F938BCF73ABB1",
INIT_35 => X"8FD18BF1B12D1191CF69938B8FB38BF1D12BF171EF69938B8FB389F1D10BF171",
INIT_36 => X"88888888B189918F6FF16FEF918DF191B189938D6FD18DF1B14D1191D169938B",
INIT_37 => X"71CD8F938BF17388AA888866AA335555335577775555EE882A228867068888AA",
INIT_38 => X"89AF9389D1F12BF171CD6B938BAF93ABD1F12DD171CD8D938BCF73ABB1EF4DB1",
INIT_39 => X"11B12D1191CF69938B8FD18BF1D12B1171CF69938B8FB389F1D10BF171EF6B93",
INIT_3A => X"919189918F6FF16FEF918DF191B189938D6FF18DF1B16D1191D169938D6FD18B",
INIT_3B => X"3355335533555555557777773355771166AA888888AA1155555555556691AFD1",
INIT_3C => X"458DCD55F153F195AFF115D3458BCD55F153F175AFD114F34769EF75D153F157",
INIT_3D => X"F191D1B175EF357247AF8955F191F1B393EF359245AFAB55F173F1B391F135B2",
INIT_3E => X"59CD7512ADAF45B3D1B191D157EF55328BAF4593F1B1B1D157EF355269B16775",
INIT_3F => X"F16947F193D153F157CDB312D16B45D193D153F159CD9312CF8D45B1D1D173D1",
INIT_40 => X"13CC2EF195AFF115D3458BCD55F153F175AFD114F34769EF75D153F177CDB312",
INIT_41 => X"D175EF377247AF6731CC6EACAB4411115577335577440AACB391F135B2458989",
INIT_42 => X"12ADAF45B3D1B191D157EF55328BAF4593F1B1B1D157EF555269B16775F191D1",
INIT_43 => X"F175D153F157CDB312F16945D193D153F159CD9312CF8B45D1B3D173D159CD75",
INIT_44 => X"F193AFF135D3458BCD55F153F195AFD114D34769CF75F153F177CDD114F16747",
INIT_45 => X"444422443355555533557777555566226713CC4EAC8F2A4444444444AA55F153",
INIT_46 => X"CF7553D10DCDF1532335ED23D19533D109CFD1710355ED23B1D533B107EFB38E",
INIT_47 => X"1347F1176913E88BCD37B3D11169F1354715EA67CF5773D10FABF1354515EA45",
INIT_48 => X"AA09ACCF673513733323F1378A0DCACD8937F3913345F137890FE8ABAB37D3B1",
INIT_49 => X"23B3F5339105F1938E0571EF239313337303F1758C078EEF455513535303F155",
INIT_4A => X"D10DADF1532335ED25D19533D10BCFD1712335ED23B1B533B107EFB38F0353EF",
INIT_4B => X"176913E88BCD37B3D11167F11300111177771133770088F1354515EA45CF7753",
INIT_4C => X"EF675513733323F1378A0BCACD6737F3913325F137890FEAADAB37D3B11345F1",
INIT_4D => X"33B105F1B38E0371EF2393F3339303F1958C058EEF457513535303F155AC09AC",
INIT_4E => X"F1532337EB45D19553D10BCDD1732335ED23D1B533B109EFD3710353EF23B1F5",
INIT_4F => X"E889AB1500113311777733555500CC3793D10F89F1354515E845CF5573D10DAD",
INIT_50 => X"33CFCFF1D155ACCFF3CDB31313CFCFF1F155AFCFF3CD931113EFAFF1F135AFAF",
INIT_51 => X"D1B38EEFCECFF115F3AFCFEFD1938EEFD1CDD11313CFCFEFD1758EEFF3CDB313",
INIT_52 => X"AEF1EF3573D1EFCFD1F173EFAEF1EF35B3CFEFCFD1D171EFAECFF135D3AFEFEF",
INIT_53 => X"1111EFAFF1F155CFAFF3EF5531F1EFCFF1F155CFACF3EF3551D1EFCFD1F153EF",
INIT_54 => X"F1D175ACCFF3CDB31333CFCFF1F155AFCFF3CD931313EFAFF1F155AFAFF3CD75",
INIT_55 => X"EFAECFF135F3AFCFEFD1B38EEFD122220422020222D1938EEFD1CDD11333CFCF",
INIT_56 => X"3573D1EFCFD1F153EFAEF1EF3593CFEFCFD1D171EFAEEFF135D3AFEFEFD1B36E",
INIT_57 => X"AFF1F135CFAFF3EF5531F1EFCFF1F155CFACF3EF5551F1EFCFD1F153EFAEF1EF",
INIT_58 => X"ACCFF3CDB31333CFCFF1F155ADCFF3CD931313CFAFF1F155AFAFF3CD751111EF",
INIT_59 => X"F135F3AD22CCEFEF3333EFEE110411CFCFEFD1938EEFD1CDD11313CFCFF1D175",
INIT_5A => X"CF8F91CFB19129D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714B91",
INIT_5B => X"93AF0BF1910BEFD1CF916FCF93AF0BF1910BEFB3CF918FCFB39109D19109EFB3",
INIT_5C => X"714FCFF1B1916DB193CF2DCF714DCFF1B1916DAF93CF2DEF912BEFD1CF916FCF",
INIT_5D => X"93CF6D91B1CF716B91716DF193AF6D91B1CF518D916F8DF1B3B16DB1B1CF4FAF",
INIT_5E => X"CFB19109D19129EFB3CF8F91CFB1712BB1912BEF93CF6F91CFCF714BB1914BEF",
INIT_5F => X"F1912BEFD1CF916FCF93AF0BF1910BEFD1CF918FCFB39109D19109EFB3CF9191",
INIT_60 => X"F1B1916DB193CF4FCF714DCFF1B1916DAF93CF2DEF912DEFF1CF916FCF93AF0B",
INIT_61 => X"91CFCF716B91716BF193AF6D91B1CF518D916F8DF1B3B16DB1B1CF4FAD914FAF",
INIT_62 => X"09D19109EFB3CF8F91CFB1912BB1912BEF93CF6F91CFB1714BB1914BEF93CF6F",
INIT_63 => X"EFD1CF916F6889280388880888D1CF918FCF93B10BF19109EFB3CF9191CFB191",
INIT_64 => X"3167EF35B1B1EFAF35CF11CD2F69EF5591B1EF8F35CF11CD2F8BF17371D1EF6F",
INIT_65 => X"F171F1EF33B111EF5145EF55D171F1CF33B111EF3145EF55D191F1CF35D111CD",
INIT_66 => X"3175F1EF8F27CFB3D133F1EF3173F1EF6F25CF93F151F1EF3193F1EF5125CF55",
INIT_67 => X"AD2DADF17351D1EF4F55EF11AD2BADD19353D1EF4F55EFEFAF29CFD1B133D1EF",
INIT_68 => X"35B1B1EFAF35CF11CD3169EF5591B1EF8F35CF11CD2F8BF15571D1EF6F35CF11",
INIT_69 => X"EF31B111EF5145EF55F171F1CF33B111EF3145EF55D191F1CF33D111CD3167EF",
INIT_6A => X"EF8F27CFB3D133F1EF3173F1EF6F25CF93F153F1EF3193F1EF7125CF73F151F1",
INIT_6B => X"F17351D1EF4F55EF11AD2BADD19351D1EF4F55EFEFAF29CFD1B133D1EF3175F1",
INIT_6C => X"EFAF35CF11CD3169EF5591B1EF8F35CF11CD2F89F15571D1EF6F35CF11CD2DAB",
INIT_6D => X"11EF5145EF55F171F1EF33B111EF3145EF55D191F1CF33D111CD3167EF35B1B1",
INIT_6E => X"F1B3D1F1CDF1158925CE0CCFF193D1EFCFF113AB23CE0EEFEF55F1EFEFF111EF",
INIT_6F => X"CCF15523ADCD0C6FF1D175F1CCF1374589CF0C8FF1B1B3F1CDF1176747EF0CAE",
INIT_70 => X"13474C2FEFEF37F1CCF19305F1692C2FF1EF55F1CCF17503CFAB0C4FF1EF55F1",
INIT_71 => X"EFEF55EFEFEFF10FF1238E0FEFEF37F1CFEFD10B11256C0FEFEF37F1CDF1B307",
INIT_72 => X"F1CDF1156945EE0CCFF193D1EFCFF113AB23CE0EEFEF75F1EFEFF111CF03AE0E",
INIT_73 => X"23CDCD0C6FF1D175F1CCF137238BCD0C8FF1D193F1CDF1374567EF0CAFF1B1D1",
INIT_74 => X"2FEFEF37F1CDF1930511672C2FEFEF37F1CCF17503EF8B0C4FF1EF55F1CCF155",
INIT_75 => X"EFEFEFF10FEF238E0FEFEF37F1CFEFD10B11256C0FEFEF37F1CDF1B30711454C",
INIT_76 => X"156745EE0CCEF193D1EFCFF1138B25CE0ECFF173F1EFEFF111CD03AE0EEFEF55",
INIT_77 => X"0C6FF1D175F1CCF13723ABCD0C8FF1D193F1CDF1374569EF0CAFF1B1B3F1CDF1",
INIT_78 => X"AF69471393D1B10BAFEFCF55AF69453373F1B109AFEFCF55AD8D255355F19127",
INIT_79 => X"F155D10F69F1CD93B1458B11D173D10D8BF1CD75B1476913B1B3D10D8DEFCF55",
INIT_7A => X"45D1CDB37547AF0BD137F12F45F1CDB39345AD0DD135F10F47F1CDB393458D0F",
INIT_7B => X"558BAD257335F17125D1EFD1558BAF279137F15125D1EFD15567AF29B117F131",
INIT_7C => X"13B3D1B10BADEFCF55AF69453393D1B109AFEFCF55AD8B255355F19127D1EFD1",
INIT_7D => X"0F69F1CD93B1458B11D173D10D69F1CD75B1476913D193D10D8DEFCF75AF6747",
INIT_7E => X"B17547AF29D137F13145F1CDB37345AF0DD135F10F47F1CDB39345AD0FF155D1",
INIT_7F => X"255335F17125D1EFD1558BAF257137F17125D1EFD15569AF27B117F13125D1CD",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_prim_width is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_pixel_blk_mem_gen_prim_wrapper_init
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => \douta[0]\(0),
ram_ena => ram_ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized1\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized10\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized11\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized12\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized13\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized14\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized15\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized16\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized17\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized18\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized19\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
\douta[2]\(1 downto 0) => \douta[2]\(1 downto 0),
ram_ena => ram_ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized20\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized21\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized22\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized22\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized22\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized22\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized3\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized7\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized8\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_pixel_blk_mem_gen_prim_width__parameterized9\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_pixel_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \bg_pixel_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \bg_pixel_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\bg_pixel_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_pixel_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ram_douta : STD_LOGIC;
signal \ram_ena__1\ : STD_LOGIC;
signal ram_ena_n_0 : STD_LOGIC;
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_pixel_bindec
port map (
addra(4 downto 0) => addra(16 downto 12),
ena_array(14 downto 7) => ena_array(15 downto 8),
ena_array(6 downto 0) => ena_array(6 downto 0)
);
\has_mux_a.A\: entity work.bg_pixel_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\(0) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_0\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[22].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[22].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[22].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[22].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[22].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[22].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[22].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[22].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[23].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[23].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[23].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[23].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[23].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[23].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[23].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[23].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[22].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(7) => \ramloop[10].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(6) => \ramloop[10].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(5) => \ramloop[10].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(4) => \ramloop[10].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(3) => \ramloop[10].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(2) => \ramloop[10].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(1) => \ramloop[10].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\(0) => \ramloop[10].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(7) => \ramloop[9].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(6) => \ramloop[9].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(5) => \ramloop[9].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(4) => \ramloop[9].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(3) => \ramloop[9].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(2) => \ramloop[9].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(1) => \ramloop[9].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_11\(0) => \ramloop[9].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(7) => \ramloop[16].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(6) => \ramloop[16].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(5) => \ramloop[16].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(4) => \ramloop[16].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(3) => \ramloop[16].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(2) => \ramloop[16].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(1) => \ramloop[16].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_12\(0) => \ramloop[16].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(7) => \ramloop[15].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(6) => \ramloop[15].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(5) => \ramloop[15].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(4) => \ramloop[15].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(3) => \ramloop[15].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(2) => \ramloop[15].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(1) => \ramloop[15].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_13\(0) => \ramloop[15].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(7) => \ramloop[14].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(6) => \ramloop[14].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(5) => \ramloop[14].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(4) => \ramloop[14].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(3) => \ramloop[14].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(2) => \ramloop[14].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(1) => \ramloop[14].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_14\(0) => \ramloop[14].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(7) => \ramloop[13].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(6) => \ramloop[13].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(5) => \ramloop[13].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(4) => \ramloop[13].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(3) => \ramloop[13].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(2) => \ramloop[13].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(1) => \ramloop[13].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_15\(0) => \ramloop[13].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(7) => \ramloop[20].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(6) => \ramloop[20].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(5) => \ramloop[20].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(4) => \ramloop[20].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(3) => \ramloop[20].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(2) => \ramloop[20].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(1) => \ramloop[20].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_16\(0) => \ramloop[20].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(7) => \ramloop[19].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(6) => \ramloop[19].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(5) => \ramloop[19].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(4) => \ramloop[19].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(3) => \ramloop[19].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(2) => \ramloop[19].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(1) => \ramloop[19].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_17\(0) => \ramloop[19].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(7) => \ramloop[18].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(6) => \ramloop[18].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(5) => \ramloop[18].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(4) => \ramloop[18].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(3) => \ramloop[18].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(2) => \ramloop[18].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(1) => \ramloop[18].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_18\(0) => \ramloop[18].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(7) => \ramloop[17].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(6) => \ramloop[17].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(5) => \ramloop[17].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(4) => \ramloop[17].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(3) => \ramloop[17].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(2) => \ramloop[17].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(1) => \ramloop[17].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_19\(0) => \ramloop[17].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[23].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_20\(0) => \ramloop[8].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_21\(0) => \ramloop[7].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_22\(0) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_23\(0) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_24\(0) => \ramloop[12].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_25\(0) => \ramloop[11].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\(0) => \ramloop[10].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\(0) => \ramloop[9].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_28\(0) => \ramloop[16].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_29\(0) => \ramloop[15].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_30\(0) => \ramloop[14].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_31\(0) => \ramloop[13].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_32\(0) => \ramloop[20].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_33\(0) => \ramloop[19].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_34\(0) => \ramloop[18].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_35\(0) => \ramloop[17].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(7) => \ramloop[12].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(6) => \ramloop[12].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(5) => \ramloop[12].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(4) => \ramloop[12].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(3) => \ramloop[12].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(2) => \ramloop[12].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(1) => \ramloop[12].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\(0) => \ramloop[12].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(7) => \ramloop[11].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(6) => \ramloop[11].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(5) => \ramloop[11].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(4) => \ramloop[11].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(3) => \ramloop[11].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(2) => \ramloop[11].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(1) => \ramloop[11].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\(0) => \ramloop[11].ram.r_n_7\,
DOADO(7) => \ramloop[21].ram.r_n_0\,
DOADO(6) => \ramloop[21].ram.r_n_1\,
DOADO(5) => \ramloop[21].ram.r_n_2\,
DOADO(4) => \ramloop[21].ram.r_n_3\,
DOADO(3) => \ramloop[21].ram.r_n_4\,
DOADO(2) => \ramloop[21].ram.r_n_5\,
DOADO(1) => \ramloop[21].ram.r_n_6\,
DOADO(0) => \ramloop[21].ram.r_n_7\,
DOPADOP(0) => \ramloop[21].ram.r_n_8\,
DOUTA(0) => ram_douta,
addra(4 downto 0) => addra(16 downto 12),
clka => clka,
\^douta\(11 downto 0) => douta(11 downto 0)
);
ram_ena: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(16),
O => ram_ena_n_0
);
\ram_ena__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => addra(15),
I1 => addra(14),
I2 => addra(16),
O => \ram_ena__1\
);
\ramloop[0].ram.r\: entity work.bg_pixel_blk_mem_gen_prim_width
port map (
DOUTA(0) => ram_douta,
ENA => ram_ena_n_0,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
wea(0) => wea(0)
);
\ramloop[10].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized9\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[10].ram.r_n_0\,
\douta[10]\(6) => \ramloop[10].ram.r_n_1\,
\douta[10]\(5) => \ramloop[10].ram.r_n_2\,
\douta[10]\(4) => \ramloop[10].ram.r_n_3\,
\douta[10]\(3) => \ramloop[10].ram.r_n_4\,
\douta[10]\(2) => \ramloop[10].ram.r_n_5\,
\douta[10]\(1) => \ramloop[10].ram.r_n_6\,
\douta[10]\(0) => \ramloop[10].ram.r_n_7\,
\douta[11]\(0) => \ramloop[10].ram.r_n_8\,
ena_array(0) => ena_array(5),
wea(0) => wea(0)
);
\ramloop[11].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized10\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[11].ram.r_n_0\,
\douta[10]\(6) => \ramloop[11].ram.r_n_1\,
\douta[10]\(5) => \ramloop[11].ram.r_n_2\,
\douta[10]\(4) => \ramloop[11].ram.r_n_3\,
\douta[10]\(3) => \ramloop[11].ram.r_n_4\,
\douta[10]\(2) => \ramloop[11].ram.r_n_5\,
\douta[10]\(1) => \ramloop[11].ram.r_n_6\,
\douta[10]\(0) => \ramloop[11].ram.r_n_7\,
\douta[11]\(0) => \ramloop[11].ram.r_n_8\,
ena_array(0) => ena_array(6),
wea(0) => wea(0)
);
\ramloop[12].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[12].ram.r_n_0\,
\douta[10]\(6) => \ramloop[12].ram.r_n_1\,
\douta[10]\(5) => \ramloop[12].ram.r_n_2\,
\douta[10]\(4) => \ramloop[12].ram.r_n_3\,
\douta[10]\(3) => \ramloop[12].ram.r_n_4\,
\douta[10]\(2) => \ramloop[12].ram.r_n_5\,
\douta[10]\(1) => \ramloop[12].ram.r_n_6\,
\douta[10]\(0) => \ramloop[12].ram.r_n_7\,
\douta[11]\(0) => \ramloop[12].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[13].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized12\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[13].ram.r_n_0\,
\douta[10]\(6) => \ramloop[13].ram.r_n_1\,
\douta[10]\(5) => \ramloop[13].ram.r_n_2\,
\douta[10]\(4) => \ramloop[13].ram.r_n_3\,
\douta[10]\(3) => \ramloop[13].ram.r_n_4\,
\douta[10]\(2) => \ramloop[13].ram.r_n_5\,
\douta[10]\(1) => \ramloop[13].ram.r_n_6\,
\douta[10]\(0) => \ramloop[13].ram.r_n_7\,
\douta[11]\(0) => \ramloop[13].ram.r_n_8\,
ena_array(0) => ena_array(8),
wea(0) => wea(0)
);
\ramloop[14].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized13\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[14].ram.r_n_0\,
\douta[10]\(6) => \ramloop[14].ram.r_n_1\,
\douta[10]\(5) => \ramloop[14].ram.r_n_2\,
\douta[10]\(4) => \ramloop[14].ram.r_n_3\,
\douta[10]\(3) => \ramloop[14].ram.r_n_4\,
\douta[10]\(2) => \ramloop[14].ram.r_n_5\,
\douta[10]\(1) => \ramloop[14].ram.r_n_6\,
\douta[10]\(0) => \ramloop[14].ram.r_n_7\,
\douta[11]\(0) => \ramloop[14].ram.r_n_8\,
ena_array(0) => ena_array(9),
wea(0) => wea(0)
);
\ramloop[15].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized14\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[15].ram.r_n_0\,
\douta[10]\(6) => \ramloop[15].ram.r_n_1\,
\douta[10]\(5) => \ramloop[15].ram.r_n_2\,
\douta[10]\(4) => \ramloop[15].ram.r_n_3\,
\douta[10]\(3) => \ramloop[15].ram.r_n_4\,
\douta[10]\(2) => \ramloop[15].ram.r_n_5\,
\douta[10]\(1) => \ramloop[15].ram.r_n_6\,
\douta[10]\(0) => \ramloop[15].ram.r_n_7\,
\douta[11]\(0) => \ramloop[15].ram.r_n_8\,
ena_array(0) => ena_array(10),
wea(0) => wea(0)
);
\ramloop[16].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized15\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[16].ram.r_n_0\,
\douta[10]\(6) => \ramloop[16].ram.r_n_1\,
\douta[10]\(5) => \ramloop[16].ram.r_n_2\,
\douta[10]\(4) => \ramloop[16].ram.r_n_3\,
\douta[10]\(3) => \ramloop[16].ram.r_n_4\,
\douta[10]\(2) => \ramloop[16].ram.r_n_5\,
\douta[10]\(1) => \ramloop[16].ram.r_n_6\,
\douta[10]\(0) => \ramloop[16].ram.r_n_7\,
\douta[11]\(0) => \ramloop[16].ram.r_n_8\,
ena_array(0) => ena_array(11),
wea(0) => wea(0)
);
\ramloop[17].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized16\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[17].ram.r_n_0\,
\douta[10]\(6) => \ramloop[17].ram.r_n_1\,
\douta[10]\(5) => \ramloop[17].ram.r_n_2\,
\douta[10]\(4) => \ramloop[17].ram.r_n_3\,
\douta[10]\(3) => \ramloop[17].ram.r_n_4\,
\douta[10]\(2) => \ramloop[17].ram.r_n_5\,
\douta[10]\(1) => \ramloop[17].ram.r_n_6\,
\douta[10]\(0) => \ramloop[17].ram.r_n_7\,
\douta[11]\(0) => \ramloop[17].ram.r_n_8\,
ena_array(0) => ena_array(12),
wea(0) => wea(0)
);
\ramloop[18].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized17\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[18].ram.r_n_0\,
\douta[10]\(6) => \ramloop[18].ram.r_n_1\,
\douta[10]\(5) => \ramloop[18].ram.r_n_2\,
\douta[10]\(4) => \ramloop[18].ram.r_n_3\,
\douta[10]\(3) => \ramloop[18].ram.r_n_4\,
\douta[10]\(2) => \ramloop[18].ram.r_n_5\,
\douta[10]\(1) => \ramloop[18].ram.r_n_6\,
\douta[10]\(0) => \ramloop[18].ram.r_n_7\,
\douta[11]\(0) => \ramloop[18].ram.r_n_8\,
ena_array(0) => ena_array(13),
wea(0) => wea(0)
);
\ramloop[19].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized18\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[19].ram.r_n_0\,
\douta[10]\(6) => \ramloop[19].ram.r_n_1\,
\douta[10]\(5) => \ramloop[19].ram.r_n_2\,
\douta[10]\(4) => \ramloop[19].ram.r_n_3\,
\douta[10]\(3) => \ramloop[19].ram.r_n_4\,
\douta[10]\(2) => \ramloop[19].ram.r_n_5\,
\douta[10]\(1) => \ramloop[19].ram.r_n_6\,
\douta[10]\(0) => \ramloop[19].ram.r_n_7\,
\douta[11]\(0) => \ramloop[19].ram.r_n_8\,
ena_array(0) => ena_array(14),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => \ramloop[1].ram.r_n_0\,
ram_ena => \ram_ena__1\,
wea(0) => wea(0)
);
\ramloop[20].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized19\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[20].ram.r_n_0\,
\douta[10]\(6) => \ramloop[20].ram.r_n_1\,
\douta[10]\(5) => \ramloop[20].ram.r_n_2\,
\douta[10]\(4) => \ramloop[20].ram.r_n_3\,
\douta[10]\(3) => \ramloop[20].ram.r_n_4\,
\douta[10]\(2) => \ramloop[20].ram.r_n_5\,
\douta[10]\(1) => \ramloop[20].ram.r_n_6\,
\douta[10]\(0) => \ramloop[20].ram.r_n_7\,
\douta[11]\(0) => \ramloop[20].ram.r_n_8\,
ena_array(0) => ena_array(15),
wea(0) => wea(0)
);
\ramloop[21].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized20\
port map (
DOADO(7) => \ramloop[21].ram.r_n_0\,
DOADO(6) => \ramloop[21].ram.r_n_1\,
DOADO(5) => \ramloop[21].ram.r_n_2\,
DOADO(4) => \ramloop[21].ram.r_n_3\,
DOADO(3) => \ramloop[21].ram.r_n_4\,
DOADO(2) => \ramloop[21].ram.r_n_5\,
DOADO(1) => \ramloop[21].ram.r_n_6\,
DOADO(0) => \ramloop[21].ram.r_n_7\,
DOPADOP(0) => \ramloop[21].ram.r_n_8\,
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
wea(0) => wea(0)
);
\ramloop[22].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[22].ram.r_n_0\,
\douta[10]\(6) => \ramloop[22].ram.r_n_1\,
\douta[10]\(5) => \ramloop[22].ram.r_n_2\,
\douta[10]\(4) => \ramloop[22].ram.r_n_3\,
\douta[10]\(3) => \ramloop[22].ram.r_n_4\,
\douta[10]\(2) => \ramloop[22].ram.r_n_5\,
\douta[10]\(1) => \ramloop[22].ram.r_n_6\,
\douta[10]\(0) => \ramloop[22].ram.r_n_7\,
\douta[11]\(0) => \ramloop[22].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[23].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[23].ram.r_n_0\,
\douta[10]\(6) => \ramloop[23].ram.r_n_1\,
\douta[10]\(5) => \ramloop[23].ram.r_n_2\,
\douta[10]\(4) => \ramloop[23].ram.r_n_3\,
\douta[10]\(3) => \ramloop[23].ram.r_n_4\,
\douta[10]\(2) => \ramloop[23].ram.r_n_5\,
\douta[10]\(1) => \ramloop[23].ram.r_n_6\,
\douta[10]\(0) => \ramloop[23].ram.r_n_7\,
\douta[11]\(0) => \ramloop[23].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized1\
port map (
DOUTA(0) => \ramloop[2].ram.r_n_0\,
ENA => ram_ena_n_0,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(1),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
\douta[2]\(1) => \ramloop[3].ram.r_n_0\,
\douta[2]\(0) => \ramloop[3].ram.r_n_1\,
ram_ena => \ram_ena__1\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized3\
port map (
DOUTA(0) => \ramloop[4].ram.r_n_0\,
ENA => ram_ena_n_0,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(2),
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[5].ram.r_n_0\,
\douta[10]\(6) => \ramloop[5].ram.r_n_1\,
\douta[10]\(5) => \ramloop[5].ram.r_n_2\,
\douta[10]\(4) => \ramloop[5].ram.r_n_3\,
\douta[10]\(3) => \ramloop[5].ram.r_n_4\,
\douta[10]\(2) => \ramloop[5].ram.r_n_5\,
\douta[10]\(1) => \ramloop[5].ram.r_n_6\,
\douta[10]\(0) => \ramloop[5].ram.r_n_7\,
\douta[11]\(0) => \ramloop[5].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[6].ram.r_n_0\,
\douta[10]\(6) => \ramloop[6].ram.r_n_1\,
\douta[10]\(5) => \ramloop[6].ram.r_n_2\,
\douta[10]\(4) => \ramloop[6].ram.r_n_3\,
\douta[10]\(3) => \ramloop[6].ram.r_n_4\,
\douta[10]\(2) => \ramloop[6].ram.r_n_5\,
\douta[10]\(1) => \ramloop[6].ram.r_n_6\,
\douta[10]\(0) => \ramloop[6].ram.r_n_7\,
\douta[11]\(0) => \ramloop[6].ram.r_n_8\,
ena_array(0) => ena_array(1),
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[7].ram.r_n_0\,
\douta[10]\(6) => \ramloop[7].ram.r_n_1\,
\douta[10]\(5) => \ramloop[7].ram.r_n_2\,
\douta[10]\(4) => \ramloop[7].ram.r_n_3\,
\douta[10]\(3) => \ramloop[7].ram.r_n_4\,
\douta[10]\(2) => \ramloop[7].ram.r_n_5\,
\douta[10]\(1) => \ramloop[7].ram.r_n_6\,
\douta[10]\(0) => \ramloop[7].ram.r_n_7\,
\douta[11]\(0) => \ramloop[7].ram.r_n_8\,
ena_array(0) => ena_array(2),
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[8].ram.r_n_0\,
\douta[10]\(6) => \ramloop[8].ram.r_n_1\,
\douta[10]\(5) => \ramloop[8].ram.r_n_2\,
\douta[10]\(4) => \ramloop[8].ram.r_n_3\,
\douta[10]\(3) => \ramloop[8].ram.r_n_4\,
\douta[10]\(2) => \ramloop[8].ram.r_n_5\,
\douta[10]\(1) => \ramloop[8].ram.r_n_6\,
\douta[10]\(0) => \ramloop[8].ram.r_n_7\,
\douta[11]\(0) => \ramloop[8].ram.r_n_8\,
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\bg_pixel_blk_mem_gen_prim_width__parameterized8\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[9].ram.r_n_0\,
\douta[10]\(6) => \ramloop[9].ram.r_n_1\,
\douta[10]\(5) => \ramloop[9].ram.r_n_2\,
\douta[10]\(4) => \ramloop[9].ram.r_n_3\,
\douta[10]\(3) => \ramloop[9].ram.r_n_4\,
\douta[10]\(2) => \ramloop[9].ram.r_n_5\,
\douta[10]\(1) => \ramloop[9].ram.r_n_6\,
\douta[10]\(0) => \ramloop[9].ram.r_n_7\,
\douta[11]\(0) => \ramloop[9].ram.r_n_8\,
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_pixel_blk_mem_gen_top;
architecture STRUCTURE of bg_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_pixel_blk_mem_gen_generic_cstr
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_pixel_blk_mem_gen_top
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_pixel_blk_mem_gen_v8_3_5 : entity is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_pixel_blk_mem_gen_v8_3_5 : entity is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_pixel_blk_mem_gen_v8_3_5 : entity is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 9.042558 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_pixel_blk_mem_gen_v8_3_5 : entity is "bg_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_pixel_blk_mem_gen_v8_3_5 : entity is "bg_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(16 downto 0) => addra(16 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_pixel : entity is "bg_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_pixel;
architecture STRUCTURE of bg_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 9.042558 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_pixel_blk_mem_gen_v8_3_5
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => B"00000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(16 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(16 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(16 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(16 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 |
CprE488/Final | system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng.vhd | 2 | 4028 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
CprE488/Final | repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_clocks.vhd | 1 | 61726 | -- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: gert.rijckbosch $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2011-05-13 10:06:42 +0200 (vr, 13 mei 2011) $
-- Revision : $Revision: 943 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--xilinx:
---------
--Library XilinxCoreLib;
library unisim;
use unisim.vcomponents.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity iserdes_clocks is
generic (
SIMULATION : integer := 0;
DATAWIDTH : integer := 10; -- can be 4, 6, 8 or 10 for DDR, can be 2, 3, 4, 5, 6, 7, or 8 for SDR.
DATA_RATE : string := "DDR"; -- DDR/SDR
CLKSPEED : integer := 50; -- APPCLK speed in MHz. Everything is generated from Appclk to be as sync as possible
--DATAWIDTH, DATARATE, and clockspeed are used to calculate high speed clk speed.
--SIM_DEVICE : string := "VIRTEX5"; --VIRTEX4/VIRTEX5, for BUFR
C_FAMILY : string := "virtex5";
DIFF_TERM : boolean := TRUE;
USE_INPLL : boolean := TRUE;
USE_OUTPLL : boolean := TRUE; --use output/multiplieng PLL instead of DCM
USE_HS_EXT_CLK_IN : boolean := FALSE; -- use external clock high speed clock in
-- YES -> use as CLK source, either via BUFG or BUFIO/BUFR,
-- -> when USE_HS_REGIONAL_CLK = YES
-- use BUFIO (only IOblock can be clocked)
-- -> when USE_HS_REGIONAL_CLK = NO
-- use BUFG
--
-- NO -> when use USE_LS_EXT_CLK_IN = YES
-- not supported
-- when use USE_LS_EXT_CLK_IN = NO
-- appclk combined with DCM as CLK source
-- use BUFG as CLK source
USE_LS_EXT_CLK_IN : boolean := FALSE; -- use external clock low speed clock in
-- YES -> use as CLKDIV source, either via BUFG or BUFIO/BUFR,
-- -> when USE_LS_REGIONAL_CLK = YES
-- use BUFR
-- -> when USE_LS_REGIONAL_CLK = NO
-- use BUFG
--
--
-- NO -> when USE_HS_EXT_CLK_IN = YES
-- -> when USE_HS_REGIONAL_CLK =YES and BUFR can divide
-- use BUFIO/BUFR to divide HS
-- -> when USE_HS_REGIONAL_CLK =YES and BUFR can not divide
-- use BUFIO/BUFR + DCM to divide HS
-- -> when USE_HS_EXT_CLK_IN = NO
-- use DCM (same as HS_EXT_CLK_IN) as clk source, sync with appclk
--
--
USE_DIFF_HS_CLK_IN : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_IN : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_HS_REGIONAL_CLK : boolean := FALSE; -- only used when USE_HS_EXT_CLK_IN = yes
USE_LS_REGIONAL_CLK : boolean := FALSE; -- only used when USE_LS_EXT_CLK_IN = yes
USE_HS_EXT_CLK_OUT : boolean := FALSE; -- use external clock high speed clock out
USE_LS_EXT_CLK_OUT : boolean := FALSE; -- use external clock low speed clock out
USE_DIFF_HS_CLK_OUT : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_OUT : boolean := FALSE -- differential mode, automatically instantiates the correct buffer
);
port (
CLOCK : in std_logic; --appclock
RESET : in std_logic; --active high reset
CLK_RDY : out std_logic; --CLK status (locked)
CLK_STATUS : out std_logic_vector(15 downto 0); -- extended status
-- 8 LSBs: transmit clk (if any)
-- 8 MSBs: receive clk (if any)
EN_LS_CLK_OUT : in std_logic;
EN_HS_CLK_OUT : in std_logic;
--reset for synchronizer between clk_div and App_clk
CLK_DIV_RESET : out std_logic;
-- to iserdes
CLK : out std_logic;
CLKb : out std_logic;
CLKDIV : out std_logic;
-- to sensor (external)
LS_OUT_CLK : out std_logic;
LS_OUT_CLKb : out std_logic; -- only used in differential mode
HS_OUT_CLK : out std_logic;
HS_OUT_CLKb : out std_logic;
-- from sensor (only used when USED_EXT_CLK = YES)
LS_IN_CLK : in std_logic;
LS_IN_CLKb : in std_logic;
HS_IN_CLK : in std_logic;
HS_IN_CLKb : in std_logic
);
end iserdes_clocks;
architecture rtl of iserdes_clocks is
-- functions
function calcoutplldivider(
DATAWIDTH : integer;
DATA_RATE : string;
CLKSPEED : integer
)
return integer is
variable output : integer := 1;
variable a : integer := 1;
begin
a := 1000 / CLKSPEED;
if (DATA_RATE = "SDR") then
output := a / DATAWIDTH;
else
output := a / (DATAWIDTH/2);
end if;
return output;
end function;
function calcoutpllmultiplier(
DATAWIDTH : integer;
DATA_RATE : string;
CLKSPEED : integer
)
return integer is
variable output : integer := 1;
begin
output := 1000 / CLKSPEED;
if (DATA_RATE = "SDR") then
output := output / DATAWIDTH;
else
output := output / (DATAWIDTH/2);
end if;
if (DATA_RATE = "SDR") then
output := output * DATAWIDTH;
else
output := output * (DATAWIDTH/2);
end if;
return output;
end function;
function calcclockmultiplier(
DATAWIDTH : integer;
DATA_RATE : string;
CLKSPEED : integer
)
return integer is
variable output : integer := 0;
begin
if (DATA_RATE = "SDR") then
output := DATAWIDTH;
else
output := DATAWIDTH/2;
end if;
return output;
end function;
function checkBUFRdividable( clockmultiplier : integer
)
return boolean is
variable output : boolean := FALSE;
begin
if ( clockmultiplier = 2 or
clockmultiplier = 3 or
clockmultiplier = 4 or
clockmultiplier = 5 or
clockmultiplier = 6 or
clockmultiplier = 7 or
clockmultiplier = 8 ) then
output := TRUE;
else
output := FALSE;
end if;
return output;
end function;
function calcperiod(
CLKSPEED : integer;
MULTIPLIER : integer
)
return real is
variable output : real := 0.0;
begin
output := 1000.0/real(CLKSPEED*MULTIPLIER);
return output;
end function;
function setlocktime( USECLKFX : boolean;
USEPLL : boolean;
SIMULATION : integer;
CLKSPEED : integer
)
return std_logic_vector is
variable output : std_logic_vector(23 downto 0) := X"000000";
begin
if (SIMULATION > 0) then
output := X"000080";
else
if (USEPLL = TRUE) then --PLL lock time is always 100us
output := std_logic_vector(to_unsigned((CLKSPEED*100),24));
elsif (USECLKFX = TRUE) then --DFS locktime is always 10ms
output := std_logic_vector(to_unsigned((CLKSPEED*10000),24));
else --locktime is worst case for 30MHz; 5000us resulting in 150000 clocks
output := std_logic_vector(to_unsigned(150000,24));
end if;
end if;
return output;
end function;
function calcinpllmultiplier(
CLKSPEED : integer
)
return integer is
variable output : integer := 1;
begin
-- PLL frequency needs to be within 400MHz and 1000MHz
if (CLKSPEED > 500) then
output := 1;
elsif (CLKSPEED > 250) then
output := 2;
elsif (CLKSPEED > 125) then
output := 4;
else
output := 8;
end if;
return output;
end function;
--constants
constant clockmultiplier : integer := calcclockmultiplier(DATAWIDTH, DATA_RATE, CLKSPEED);
constant BUFR_dividable : boolean := checkBUFRdividable(clockmultiplier);
constant inpllmultiplier : integer := calcinpllmultiplier(CLKSPEED*clockmultiplier);
constant outpllmultiplier: integer := calcoutpllmultiplier(DATAWIDTH ,DATA_RATE,CLKSPEED);
constant outplldivider : integer := calcoutplldivider(DATAWIDTH ,DATA_RATE,CLKSPEED);
constant zero : std_logic := '0';
constant one : std_logic := '1';
constant zeros : std_logic_vector(31 downto 0) := X"00000000";
constant ones : std_logic_vector(31 downto 0) := X"FFFFFFFF";
constant LockTimeMULT : std_logic_vector(23 downto 0) := setlocktime(TRUE, USE_OUTPLL, SIMULATION, CLKSPEED);
constant LockTimeDIV : std_logic_vector(23 downto 0) := setlocktime(FALSE, USE_INPLL, SIMULATION, CLKSPEED);
constant ResetTime : std_logic_vector(23 downto 0) := X"000100";
--signals
type lockedmonitorstatetp is (
Idle,
AssertReset1,
WaitLocked1,
CheckLocked1,
AssertReset2,
WaitLocked2,
CheckLocked2,
AssertReset3,
WaitLocked3,
CheckLocked3
);
signal lockedmonitorstate : lockedmonitorstatetp;
signal Cntr : std_logic_vector(23 downto 0);
signal dcm_mult_gen : std_logic := '0';
signal dcm_div_gen : std_logic := '0';
signal lsoutclk : std_logic;
signal lsoddroutclk : std_logic;
signal hsinclk : std_logic;
signal lsinclk : std_logic;
signal lsdcmmultclk : std_logic;
signal hsdcmmultclk : std_logic;
signal hsoddroutclk : std_logic;
--signal lsdcmdivclk : std_logic;
--signal hsdcmdivclk : std_logic;
signal clk_tmp : std_logic;
signal MULT_CLK0 : std_logic;
signal MULT_CLK180 : std_logic;
signal MULT_CLK270 : std_logic;
signal MULT_CLK2X : std_logic;
signal MULT_CLK2X180 : std_logic;
signal MULT_CLK90 : std_logic;
signal MULT_CLKDV : std_logic;
signal MULT_CLKFX : std_logic;
signal MULT_CLKFX180 : std_logic;
signal MULT_LOCKED : std_logic;
signal MULT_CLKFB : std_logic;
signal MULT_CLKIN : std_logic;
signal MULT_RST : std_logic;
signal MULT_DO : std_logic_vector(15 downto 0);
signal DIV_CLK0 : std_logic;
signal DIV_CLK180 : std_logic;
signal DIV_CLK270 : std_logic;
signal DIV_CLK2X : std_logic;
signal DIV_CLK2X180 : std_logic;
signal DIV_CLK90 : std_logic;
signal DIV_CLKDV : std_logic;
signal DIV_CLKFX : std_logic;
signal DIV_CLKFX180 : std_logic;
signal DIV_LOCKED : std_logic;
signal DIV_CLKFB : std_logic;
signal DIV_CLKIN : std_logic;
signal DIV_RST : std_logic;
signal DIV_DO : std_logic_vector(15 downto 0);
--only for PLL
signal DIV_PLLFBI : std_logic;
signal DIV_PLLFBO : std_logic;
signal LOCKED : std_logic;
signal dividable_s : boolean := BUFR_dividable;
--signal clk_div
signal CLK_LOW : std_logic;
-- lock signals AND'ed with DRP DO(1)
signal multiplier_lock : std_logic;
signal divider_lock : std_logic;
signal divider_lock_r : std_logic;
signal divider_lock_r2 : std_logic;
-- output of reset sequencer
signal multiplier_status : std_logic;
signal divider_status : std_logic;
attribute syn_preserve : boolean;
attribute equivalent_register_removal : string;
attribute shreg_extract : string;
attribute equivalent_register_removal of divider_lock_r : signal is "no";
attribute syn_preserve of divider_lock_r : signal is true;
attribute shreg_extract of divider_lock_r : signal is "no";
attribute equivalent_register_removal of divider_lock_r2 : signal is "no";
attribute syn_preserve of divider_lock_r2 : signal is true;
attribute shreg_extract of divider_lock_r2 : signal is "no";
begin
-- DO bit assignment (DCM only)
-- DO[0]: Phase shift overflow
-- DO[1]: Clkin stopped
-- DO[2]: Clkfx stopped
-- DO[3]: Clkfb stopped
CLK_STATUS(7) <= '0';
CLK_STATUS(6) <= multiplier_lock;
CLK_STATUS(5) <= MULT_LOCKED;
CLK_STATUS(4 downto 1) <= MULT_DO(3 downto 0);
CLK_STATUS(0) <= multiplier_status;
CLK_STATUS(15) <= '0';
CLK_STATUS(14) <= divider_lock;
CLK_STATUS(13) <= DIV_LOCKED;
CLK_STATUS(12 downto 9) <= DIV_DO(3 downto 0);
CLK_STATUS(8) <= divider_status;
-- in 'normal' cases only one clock entity will be needed per project
-- DCM is needed: 1. when a high speed clock out is required, then HS clock is generated internally,
-- 2. when no high speed clock in is available and it needs to be generated internally
-- 3. when a high speed clock in needs to be divided
-- or when a only a low speed clock in is available
-- in the latter case a clock reconstruction algorithm is required that is applied on the data, which is not supported yet
gen_oserdes_multiplier_DCM: if (USE_HS_EXT_CLK_OUT = TRUE or USE_HS_EXT_CLK_IN = FALSE) generate
gen_oserdes_multiplier_v5 : if (C_FAMILY = "virtex5" ) generate
gen_dcm: if (USE_OUTPLL = FALSE) generate
DCM_ADV_inst : DCM_ADV
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => clockmultiplier, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => calcperiod(CLKSPEED,1), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE, FIXED,
-- VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibration circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
--SIM_DEVICE => "VIRTEX5", -- Set target device, "VIRTEX4" or "VIRTEX5"
SIM_DEVICE => C_FAMILY,
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => MULT_CLK0, -- 0 degree DCM CLK output
CLK180 => MULT_CLK180, -- 180 degree DCM CLK output
CLK270 => MULT_CLK270, -- 270 degree DCM CLK output
CLK2X => MULT_CLK2X, -- 2X DCM CLK output
CLK2X180 => MULT_CLK2X180, -- 2X, 180 degree DCM CLK out
CLK90 => MULT_CLK90, -- 90 degree DCM CLK output
CLKDV => MULT_CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => MULT_CLKFX, -- DCM CLK synthesis out (M/D)
CLKFX180 => MULT_CLKFX180, -- 180 degree CLK synthesis out
DO => MULT_DO, -- 16-bit data output for Dynamic Reconfiguration Port (DRP)
DRDY => open, -- Ready output signal from the DRP
LOCKED => MULT_LOCKED, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
CLKFB => MULT_CLKFB, -- DCM clock feedback
CLKIN => MULT_CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
DADDR => zeros(6 downto 0), -- 7-bit address for the DRP
DCLK => CLOCK, -- Clock for the DRP
DEN => zero, -- Enable input for the DRP
DI => zeros(15 downto 0), -- 16-bit data input for the DRP
DWE => zero, -- Active high allows for writing configuration memory
PSCLK => zero, -- Dynamic phase adjust clock input
PSEN => zero, -- Dynamic phase adjust enable input
PSINCDEC => zero, -- Dynamic phase adjust increment/decrement
RST => MULT_RST -- DCM asynchronous reset input
);
-- lock status generation
-- required because of funny condition where DCM lock does not deassert when input clock operates outside allowed range
multiplier_lock <= MULT_LOCKED and not MULT_DO(1);
end generate; -- gen_dcm: if (USE_OUTPLL = FALSE) generate
gen_pll: if (USE_OUTPLL = TRUE) generate
PLL_ADV_INST : PLL_ADV
generic map( BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => calcperiod(CLKSPEED,1),
CLKIN2_PERIOD => 10.000,
CLKOUT0_DIVIDE => outplldivider,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => outpllmultiplier,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map (
CLKFBIN => MULT_CLKFB,
CLKINSEL => one,
CLKIN1 => MULT_CLKIN,
CLKIN2 => zero,
DADDR(4 downto 0) => zeros(4 downto 0),
DCLK => CLOCK,
DEN => zero,
DI(15 downto 0) => zeros(15 downto 0),
DWE => zero,
REL => zero,
RST => MULT_RST,
CLKFBDCM => open,
CLKFBOUT => MULT_CLK0, -- naming not ideal, matches DCM naming
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => MULT_CLKFX, -- naming not ideal, matches DCM naming
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => MULT_DO,
DRDY => open,
LOCKED => MULT_LOCKED
);
--unused signals
MULT_CLK180 <= '0';
MULT_CLK270 <= '0';
MULT_CLK2X <= '0';
MULT_CLK2X180 <= '0';
MULT_CLK90 <= '0';
MULT_CLKDV <= '0';
MULT_CLKFX180 <= '0';
multiplier_lock <= MULT_LOCKED;
end generate; -- gen_pll: if (USE_OUTPLL = TRUE) generate
end generate; --gen_oserdes_multiplier_v5 : if (C_FAMILY = "virtex5" ) generate
gen_oserdes_multiplier_v6 : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 1.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => calcperiod(CLKSPEED,1),
REF_JITTER1 => 0.005000)
port map
-- Output clocks
(CLKFBOUT => MULT_CLK0, -- naming not ideal, matches DCM naming
CLKFBOUTB => open,
CLKOUT0 => MULT_CLKFX, -- naming not ideal, matches DCM naming
CLKOUT0B => open,
CLKOUT1 => open,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => MULT_CLKFB,
CLKIN1 => MULT_CLKIN,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => MULT_LOCKED,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => MULT_RST);
--unused signals
MULT_CLK180 <= '0';
MULT_CLK270 <= '0';
MULT_CLK2X <= '0';
MULT_CLK2X180 <= '0';
MULT_CLK90 <= '0';
MULT_CLKDV <= '0';
MULT_CLKFX180 <= '0';
multiplier_lock <= MULT_LOCKED;
end generate; --gen_oserdes_multiplier_v6 : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
-- necessary BUFG instansiations
mult_feedback_BUFG_inst : BUFG
port map (
O => MULT_CLKFB, -- Clock buffer output
I => MULT_CLK0 -- Clock buffer input
);
--LSoutput_BUFG_inst : BUFG
--port map (
--O => lsdcmmultclk, -- Clock buffer output
--I => MULT_CLK0 -- Clock buffer input
--);
--
--HSoutput_BUFG_inst : BUFG
--port map (
--O => hsdcmmultclk, -- Clock buffer output
--I => MULT_CLKFX -- Clock buffer input
--);
--
--lsoutclk <= lsdcmmultclk;
--MULT_CLKIN <= CLOCK;
--
--end generate;
LSoutput_BUFGMUX_inst : BUFGMUX_CTRL
port map (
O => lsdcmmultclk, -- Clock buffer output
I0 => MULT_CLK0, -- Clock buffer input 0
I1 => CLK_LOW,
S => EN_LS_CLK_OUT
);
HSoutput_BUFGMUX_inst : BUFGMUX_CTRL
port map (
O => hsdcmmultclk, -- Clock buffer output
I0 => MULT_CLKFX, -- Clock buffer input
I1 => CLK_LOW,
S => EN_HS_CLK_OUT
);
lsoutclk <= lsdcmmultclk;
MULT_CLKIN <= CLOCK;
CLK_LOW <= '0';
end generate; -- gen_oserdes_multiplier_DCM
gen_no_iserdes_multiplier_DCM: if (USE_HS_EXT_CLK_OUT = FALSE) generate
LSoutput_BUFGMUX_inst : BUFGMUX_CTRL
port map (
O => lsoutclk, -- Clock buffer output
I0 => CLOCK, -- Clock buffer input 0
I1 => CLK_LOW,
S => EN_LS_CLK_OUT
);
-- lsoutclk <= CLOCK;
CLK_LOW <= '0';
lsdcmmultclk <= '0';
hsdcmmultclk <= '0';
multiplier_lock <= '1';
MULT_LOCKED <= '1';
MULT_DO <= (others => '0');
end generate; -- gen_no_iserdes_multiplier_DCM
gen_iserdes_divider: if ((USE_HS_EXT_CLK_IN = TRUE and USE_HS_REGIONAL_CLK = FALSE) or ( BUFR_dividable = FALSE and USE_HS_EXT_CLK_IN = TRUE and USE_HS_REGIONAL_CLK = TRUE)) generate
gen_iserdes_divider_v5 : if (C_FAMILY = "virtex5" ) generate
gen_pll: if (USE_INPLL = TRUE) generate
PLL_ADV_INST : PLL_ADV
generic map( BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => calcperiod(CLKSPEED,clockmultiplier),
CLKIN2_PERIOD => 10.000,
CLKOUT0_DIVIDE => clockmultiplier*inpllmultiplier,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => inpllmultiplier,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
COMPENSATION => "SOURCE_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => inpllmultiplier, --this could be wrong for other implementations
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map (
CLKFBIN => DIV_PLLFBO,
CLKINSEL => one,
CLKIN1 => DIV_CLKIN,
CLKIN2 => zero,
DADDR(4 downto 0) => zeros(4 downto 0),
DCLK => CLOCK,
DEN => zero,
DI(15 downto 0) => zeros(15 downto 0),
DWE => zero,
REL => zero,
RST => DIV_RST,
CLKFBDCM => open,
CLKFBOUT => DIV_PLLFBI, -- naming not ideal, matches DCM naming
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => DIV_CLKDV, -- naming not ideal, matches DCM naming
CLKOUT1 => DIV_CLK0,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => DIV_DO,
DRDY => open,
LOCKED => DIV_LOCKED
);
DIV_CLKIN <= hsinclk;
divider_lock <= DIV_LOCKED;
CLK_DIV_RESET<= not DIV_LOCKED;
div_PLLfeedback_BUFG_inst : BUFG
port map (
O => DIV_PLLFBO, -- Clock buffer output
I => DIV_PLLFBI -- Clock buffer input
);
end generate;
gen_dcm: if (USE_INPLL = FALSE) generate
DCM_ADV_inst : DCM_ADV
generic map (
CLKDV_DIVIDE => real(clockmultiplier), -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => calcperiod(CLKSPEED,clockmultiplier), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE, FIXED,
-- VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibration circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
-- HIGH: 25MHz < CLKIN < 350MHz
-- : 140MHz < CLKFX < 350MHz
DLL_FREQUENCY_MODE => "HIGH", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
--
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
--SIM_DEVICE => "VIRTEX5", -- Set target device, "VIRTEX4" or "VIRTEX5"
SIM_DEVICE => C_FAMILY,
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => DIV_CLK0, -- 0 degree DCM CLK output
CLK180 => DIV_CLK180, -- 180 degree DCM CLK output
CLK270 => DIV_CLK270, -- 270 degree DCM CLK output
CLK2X => DIV_CLK2X, -- 2X DCM CLK output
CLK2X180 => DIV_CLK2X180, -- 2X, 180 degree DCM CLK out
CLK90 => DIV_CLK90, -- 90 degree DCM CLK output
CLKDV => DIV_CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => DIV_CLKFX, -- DCM CLK synthesis out (M/D)
CLKFX180 => DIV_CLKFX180, -- 180 degree CLK synthesis out
DO => DIV_DO, -- 16-bit data output for Dynamic Reconfiguration Port (DRP)
DRDY => open, -- Ready output signal from the DRP
LOCKED => DIV_LOCKED, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
CLKFB => DIV_CLKFB, -- DCM clock feedback
CLKIN => DIV_CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
DADDR => zeros(6 downto 0), -- 7-bit address for the DRP
DCLK => CLOCK, -- Clock for the DRP
DEN => zero, -- Enable input for the DRP
DI => zeros(15 downto 0), -- 16-bit data input for the DRP
DWE => zero, -- Active high allows for writing configuration memory
PSCLK => zero, -- Dynamic phase adjust clock input
PSEN => zero, -- Dynamic phase adjust enable input
PSINCDEC => zero, -- Dynamic phase adjust increment/decrement
RST => DIV_RST -- DCM asynchronous reset input
);
DIV_CLKIN <= hsinclk;
divider_lock <= DIV_LOCKED and not DIV_DO(1);
CLK_DIV_RESET<= not DIV_LOCKED and DIV_DO(1);
end generate;
end generate; --gen_iserdes_divider_v5 : if (C_FAMILY = "virtex5" ) generate
gen_iserdes_divider_v6 : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 5.0*real(inpllmultiplier), --this could be wrong for other implementations
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(clockmultiplier)*real(inpllmultiplier),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => inpllmultiplier,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => calcperiod(CLKSPEED,clockmultiplier),
REF_JITTER1 => 0.005000,
CLKIN2_PERIOD => calcperiod(CLKSPEED,clockmultiplier),
REF_JITTER2 => 0.005000
)
port map
(
-- Output clocks
CLKFBOUT => DIV_PLLFBI, -- naming not ideal, matches DCM naming
CLKFBOUTB => open,
CLKOUT0 => DIV_CLKDV, -- naming not ideal, matches DCM naming
CLKOUT0B => open,
CLKOUT1 => DIV_CLK0,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => DIV_PLLFBO,
CLKIN1 => DIV_CLKIN,
--CLKIN2 => '0',
CLKIN2 => DIV_CLKIN,
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => CLOCK,
DEN => '0',
DI => (others => '0'),
DO => DIV_DO,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => DIV_LOCKED,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => DIV_RST
);
DIV_CLKIN <= hsinclk;
divider_lock <= DIV_LOCKED;
CLK_DIV_RESET<= not DIV_LOCKED;
div_PLLfeedback_BUFG_inst : BUFG
port map (
O => DIV_PLLFBO, -- Clock buffer output
I => DIV_PLLFBI -- Clock buffer input
);
end generate; --gen_iserdes_divider_v6 : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
div_feedback_BUFG_inst : BUFG
port map (
O => DIV_CLKFB, -- Clock buffer output
I => DIV_CLK0 -- Clock buffer input
);
LS_Input_BUFG_inst : BUFG
port map (
O => lsinclk, -- Clock buffer output
I => DIV_CLKDV -- Clock buffer input
);
end generate; -- gen_iserdes_divider
-- connect DCM input to appclock when used as a multiplier
-- connect DCM input to incoming hsclk when used as a divider
gen_no_iserdes_divider_DCM: if (USE_HS_EXT_CLK_IN = FALSE or USE_LS_EXT_CLK_IN = TRUE or (BUFR_dividable = TRUE and USE_LS_REGIONAL_CLK=TRUE)or (USE_HS_REGIONAL_CLK = TRUE and BUFR_dividable = TRUE)) generate
DIV_LOCKED <= '1';
divider_lock <= '1';
DIV_DO <= (others => '0');
CLK_DIV_RESET<= RESET; --FIXME should be in reset until a clock is comming from the device find a way to detect this.
end generate; -- gen_no_iserdes_divider_DCM
-- clocks out
-- high speed clock outs
gen_hs_clk_out: if (USE_HS_EXT_CLK_OUT = TRUE) generate
DataSampleClk : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (1 or 0)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hsoddroutclk , -- 1-bit DDR output
C => hsdcmmultclk , -- 1-bit clock input
CE => '1' ,
D1 => '1' ,
D2 => '0' ,
R => '0' , -- 1-bit reset input
S => '0' -- 1-bit set input
);
--high speed output can only be made on FPGA
gen_diff_hs_clk_out: if (USE_DIFF_HS_CLK_OUT = TRUE) generate
hs_clk_out_obufds : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => HS_OUT_CLK , -- Diff_p output (connect directly to top-level port)
OB => HS_OUT_CLKb , -- Diff_n output (connect directly to top-level port)
I => hsoddroutclk -- Buffer input
);
end generate;
gen_no_diff_hs_clk_out: if (USE_DIFF_HS_CLK_OUT = FALSE) generate
HS_OUT_CLK <= hsoddroutclk;
HS_OUT_CLKb <= '0';
end generate;
end generate;
gen_no_hs_clk_out: if (USE_HS_EXT_CLK_OUT = FALSE) generate
HS_OUT_CLK <= '0';
HS_OUT_CLKb <= '0';
end generate;
-- low speed clock outs
gen_ls_clk_out: if (USE_LS_EXT_CLK_OUT = TRUE) generate
DataSampleClk : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (1 or 0)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => lsoddroutclk , -- 1-bit DDR output
C => lsoutclk , -- 1-bit clock input
CE => '1' ,
D1 => '1' ,
D2 => '0' ,
R => '0' , -- 1-bit reset input
S => '0' -- 1-bit set input
);
gen_diff_ls_clk_out: if (USE_DIFF_LS_CLK_OUT = TRUE) generate
ls_clk_out_obufds : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => LS_OUT_CLK , -- Diff_p output (connect directly to top-level port)
OB => LS_OUT_CLKb , -- Diff_n output (connect directly to top-level port)
I => lsoddroutclk -- Buffer input
);
end generate;
gen_no_diff_ls_clk_out: if (USE_DIFF_LS_CLK_OUT = FALSE) generate
LS_OUT_CLK <= lsoddroutclk;
LS_OUT_CLKb <= '0';
end generate;
end generate;
gen_no_ls_clk_out: if (USE_LS_EXT_CLK_OUT = FALSE) generate
LS_OUT_CLK <= '0';
LS_OUT_CLKb <= '0';
end generate;
-- clocks in
-- high speed clock in
gen_hs_clk_in: if (USE_HS_EXT_CLK_IN = TRUE) generate
--assume always differential
gen_diff_hs_clk_in :if (USE_DIFF_HS_CLK_IN = TRUE) generate
IBUFDS_inst : IBUFDS
generic map (
CAPACITANCE => "DONT_CARE" , -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)
DIFF_TERM => DIFF_TERM , -- Differential Termination (Virtex-4/5, Spartan-3E/3A)
IBUF_DELAY_VALUE => "0" , -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO" , -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT"
)
port map (
O => hsinclk , -- Clock buffer output
I => HS_IN_CLK , -- Diff_p clock buffer input (connect directly to top-level port)
IB => HS_IN_CLKb -- Diff_n clock buffer input (connect directly to top-level port)
);
end generate;
gen_single_hs_clk_in :if (USE_DIFF_HS_CLK_IN = FALSE) generate
hsinclk <= HS_IN_CLK;
end generate;
-- gen_direct_connection: if (USE_HS_EXT_CLK_IN = TRUE) generate
-- CLK <= clk_tmp;
-- CLKb <= not clk_tmp;
gen_regional_hs_clk_in: if (USE_HS_REGIONAL_CLK = TRUE) generate
-- uses BUFIO because the only clocked instances with this clock are in the IO column
-- is limited to one clockregion
BUFIO_regional_hs_clk_in : BUFIO
port map (
O => clk_tmp, -- Clock buffer output
I => hsinclk -- Clock buffer input
);
CLK <= clk_tmp;
CLKb <= clk_tmp;
end generate;
-- gen_global_hs_clk_in: if (USE_HS_REGIONAL_CLK = FALSE) generate
-- -- uses BUFG
-- BUFG_regional_hs_clk_in : BUFG
-- port map (
-- O => clk_tmp, -- Clock buffer output
-- I => hsinclk -- Clock buffer input
-- );
--
-- CLK <= clk_tmp;
-- CLKb <= not clk_tmp;
-- end generate;
--end generate;
gen_no_direct_connection: if (USE_LS_EXT_CLK_IN = FALSE and USE_HS_REGIONAL_CLK = FALSE) generate --divider dcm is generated
CLK <= DIV_CLKFB;
CLKb <= DIV_CLKFB; --or DIV_CLK180
end generate;
end generate;
gen_no_hs_clk_in: if (USE_HS_EXT_CLK_IN = FALSE) generate
-- use DCM for high speed clocking
CLK <= hsdcmmultclk;
CLKb <= not hsdcmmultclk;
hsinclk <= hsdcmmultclk;
end generate;
--low speed clock in
gen_ls_clk_in: if (USE_LS_EXT_CLK_IN = TRUE) generate
gen_diff_ls_clk_in: if (USE_DIFF_LS_CLK_IN = TRUE) generate
IBUFDS_inst : IBUFDS
generic map (
CAPACITANCE => "DONT_CARE" , -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)
DIFF_TERM => DIFF_TERM , -- Differential Termination (Virtex-4/5, Spartan-3E/3A)
IBUF_DELAY_VALUE => "0" , -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO" , -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT"
)
port map (
O => lsinclk , -- Clock buffer output
I => LS_IN_CLK , -- Diff_p clock buffer input (connect directly to top-level port)
IB => LS_IN_CLKb -- Diff_n clock buffer input (connect directly to top-level port)
);
end generate;
gen_single_ls_clk_in :if (USE_DIFF_LS_CLK_IN = FALSE) generate
lsinclk <= LS_IN_CLK;
end generate;
gen_regional_ls_clk_in: if (USE_LS_REGIONAL_CLK = TRUE) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "BYPASS" , -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV, -- Clock buffer output
CE => one ,
CLR => zero ,
I => lsinclk -- Clock buffer input
);
end generate;
gen_noregional_ls_clk_in: if (USE_LS_REGIONAL_CLK = FALSE) generate
BUFG_regional_hs_clk_in : BUFG
port map (
O => CLKDIV, -- Clock buffer output
I => lsinclk -- Clock buffer input
);
end generate;
end generate;
gen_no_ls_clk_in: if (USE_LS_EXT_CLK_IN = FALSE) generate
gen_regional_hs_clk_in: if (USE_HS_REGIONAL_CLK = TRUE) generate
-- use BUFR if it can divide
-- multiplier can be 2 or bigger
gen_multiplier_2: if (clockmultiplier = 2) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "2", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_3: if (clockmultiplier = 3) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "3", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_4: if (clockmultiplier = 4) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "4", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_5: if (clockmultiplier = 5) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "5", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_6: if (clockmultiplier = 6) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "6", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_7: if (clockmultiplier = 7) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "7", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
gen_multiplier_8: if (clockmultiplier = 8) generate
BUFR_regional_hs_clk_in : BUFR
generic map (
BUFR_DIVIDE => "8", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
--SIM_DEVICE => SIM_DEVICE
SIM_DEVICE => C_FAMILY
)
port map (
O => CLKDIV , -- Clock buffer output
CE => one ,
CLR => zero ,
I => hsinclk -- Clock buffer input
);
end generate;
-- use DCM to divide when BUFR can't
gen_other_multiplier: if ( BUFR_dividable = FALSE ) generate
CLKDIV <= lsinclk;
end generate;
end generate;
-- use DCM to divide when global clocking is used (or PMCD)
gen_no_regional_hs_clk_in: if (USE_HS_REGIONAL_CLK = FALSE) generate
CLKDIV <= lsinclk;
end generate;
end generate;
-- only divider lock needs to be registered, multiplier lock is generated on same clock domain
register_process : process (RESET, CLOCK)
begin
if (RESET = '1') then
divider_lock_r <= '0';
divider_lock_r2 <= '0';
elsif (CLOCK = '1' and CLOCK'event) then
divider_lock_r <= divider_lock;
divider_lock_r2 <= divider_lock_r;
end if;
end process;
locked_monitor_process : process (RESET, CLOCK)
begin
if (RESET = '1') then
MULT_RST <= '1';
DIV_RST <= '1';
LOCKED <= '0';
multiplier_status <= '0';
divider_status <= '0';
CLK_RDY <= '0';
Cntr <= (others => '1');
lockedmonitorstate <= Idle;
elsif (CLOCK = '1' and CLOCK'event) then
LOCKED <= multiplier_status and divider_status;
CLK_RDY <= LOCKED;
case lockedmonitorstate is
when Idle =>
Cntr <= ResetTime; --reset should be asserted minimum one CLKDIV cycle
if (multiplier_lock = '0') then
multiplier_status <= '0';
divider_status <= '0';
MULT_RST <= '1';
DIV_RST <= '1';
lockedmonitorstate <= AssertReset1;
elsif (divider_lock_r2 = '0') then
divider_status <= '0';
MULT_RST <= '0';
DIV_RST <= '1';
lockedmonitorstate <= AssertReset2;
else
multiplier_status <= '1';
divider_status <= '1';
MULT_RST <= '0';
DIV_RST <= '0';
end if;
when AssertReset1 =>
If (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '1';
Cntr <= LockTimeMULT; --Cntr should be as long as lock time
lockedmonitorstate <= WaitLocked1;
else
Cntr <= Cntr - '1';
end if;
when WaitLocked1 =>
if (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '1';
lockedmonitorstate <= CheckLocked1;
else
Cntr <= Cntr - '1';
end if;
when CheckLocked1 =>
if (multiplier_lock = '1') then
multiplier_status <= '1';
MULT_RST <= '0';
DIV_RST <= '1';
Cntr <= ResetTime; --reset should be asserted minimum one CLKDIV cycle
lockedmonitorstate <= AssertReset2;
else
MULT_RST <= '1';
DIV_RST <= '1';
Cntr <= ResetTime;
lockedmonitorstate <= AssertReset1;
end if;
when AssertReset2 =>
If (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '0';
Cntr <= LockTimeDIV; --Cntr should be as long as lock time
lockedmonitorstate <= WaitLocked2;
else
Cntr <= Cntr - '1';
end if;
when WaitLocked2 =>
if (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '0';
lockedmonitorstate <= CheckLocked2;
else
Cntr <= Cntr - '1';
end if;
when CheckLocked2 =>
if (divider_lock_r2 = '1') then
--divider_status <= '1';
--lockedmonitorstate <= Idle;
DIV_RST <= '1';
Cntr <= ResetTime; --reset should be asserted minimum one CLKDIV cycle
lockedmonitorstate <= AssertReset3;
else
--check whether multiplier DCM did not get out of lock for some reason
if (multiplier_lock = '0') then
multiplier_status <= '0';
MULT_RST <= '1';
DIV_RST <= '1';
Cntr <= ResetTime;
lockedmonitorstate <= AssertReset1;
else
-- only reset divider DCM again in this state. Otherwise highspeedclock will not be available when no sensor is inserted (debug)
MULT_RST <= '0';
DIV_RST <= '1';
Cntr <= ResetTime;
lockedmonitorstate <= AssertReset2;
end if;
end if;
-- code needs to lock twice to avoid power up problems.
when AssertReset3 =>
If (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '0';
Cntr <= LockTimeDIV; --Cntr should be as long as lock time
lockedmonitorstate <= WaitLocked3;
else
Cntr <= Cntr - '1';
end if;
when WaitLocked3 =>
if (Cntr(Cntr'high) = '1') then
MULT_RST <= '0';
DIV_RST <= '0';
lockedmonitorstate <= CheckLocked3;
else
Cntr <= Cntr - '1';
end if;
when CheckLocked3 =>
if (divider_lock_r2 = '1') then
divider_status <= '1';
lockedmonitorstate <= Idle;
else
--check whether multiplier DCM did not get out of lock for some reason
if (multiplier_lock = '0') then
multiplier_status <= '0';
MULT_RST <= '1';
DIV_RST <= '1';
Cntr <= ResetTime;
lockedmonitorstate <= AssertReset1;
else
-- only reset divider DCM again in this state. Otherwise highspeedclock will not be available when no sensor is inserted (debug)
MULT_RST <= '0';
DIV_RST <= '1';
Cntr <= ResetTime;
lockedmonitorstate <= AssertReset2;
end if;
end if;
when others =>
lockedmonitorstate <= Idle;
end case;
end if;
end process;
end rtl; | gpl-3.0 |
CprE488/Final | repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/spi_top.vhd | 1 | 14767 | -- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (Fri, 02 Jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--user:
-----------
--library work;
--use work.all;
--use work.app_pack.all;
entity spi_top is
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50;
--LowLevel SPI settings
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 26;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '1'; --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK : std_logic := '0'; --'0': clock out on rising edge, '1': clock out on falling edge
--Seq SPI settings
gSyncTriggerWidth : integer; -- min 1, max 15
gRWbitposition : integer := 0 --seen from LSB
);
Port (
CLOCK : in std_logic;
RESET : in std_logic;
TIMING : in std_logic_vector(15 downto 0);
BUSY : out std_logic;
--START_READ : in std_logic;
--BUSY_READ : out std_logic;
--START_WRITE : in std_logic;
--BUSY_WRITE : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end spi_top;
Architecture structure of spi_top is
-------------------------
-- component declaration:
-------------------------
component spi_seq
generic (
gSIMULATION : integer;
gSysClkSpeed : integer;
gDATA_WIDTH : integer;
gSyncTriggerWidth : integer; -- min 1, max 15
gRWbitposition : integer --seen from LSB
);
port (
-- system:
CLK : in std_logic;
RESET : in std_logic;
BUSY : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
SPI_START : out std_logic;
SPI_BUSY : in std_logic;
SPI_DATA_TX : out std_logic_Vector(gDATA_WIDTH-1 downto 0);
SPI_DATA_RX : in std_logic_vector(gDATA_WIDTH-1 downto 0)
);
end component;
component spi_lowlevel
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50; -- Clock Speed in MHz
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 26;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '1'; --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK : std_logic := '0' --'0': clock out on rising edge, '1': clock out on falling edge
);
port
(
--
-- Control signals
--
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
SPI_DATA_TX : in std_logic_Vector((gDATA_WIDTH-1) downto 0);
SPI_DATA_RX : out std_logic_vector((gDATA_WIDTH-1) downto 0);
TIMING : in std_logic_vector(15 downto 0);
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end component;
----------------------
-- signal declaration:
----------------------
signal SPI_START : std_logic;
signal SPI_BUSY : std_logic;
signal SPI_DATA_TX : std_Logic_vector(gDATA_WIDTH-1 downto 0);
signal SPI_DATA_RX : std_logic_vector(gDATA_WIDTH-1 downto 0);
begin
---------------------------
-- component instantiation:
---------------------------
the_spi_seq: spi_seq
generic map (
gSIMULATION => gSIMULATION ,
gSysClkSpeed => gSysClkSpeed ,
gDATA_WIDTH => gDATA_WIDTH ,
gSyncTriggerWidth => gSyncTriggerWidth ,
gRWbitposition => gRWbitposition
)
port map (
-- system:
CLK => CLOCK ,
RESET => RESET ,
BUSY => BUSY ,
synctriggers => synctriggers ,
sync1_select => sync1_select ,
sync2_select => sync2_select ,
-- Fifo signals
APP_RDFIFO_CLK => APP_RDFIFO_CLK ,
APP_RDFIFO_EN => APP_RDFIFO_EN ,
APP_RDFIFO_DATA_OUT => APP_RDFIFO_DATA_OUT ,
APP_RDFIFO_EMPTY => APP_RDFIFO_EMPTY ,
APP_WRFIFO_CLK => APP_WRFIFO_CLK ,
APP_WRFIFO_EN => APP_WRFIFO_EN ,
APP_WRFIFO_DATA_IN => APP_WRFIFO_DATA_IN ,
APP_WRFIFO_FULL => APP_WRFIFO_FULL ,
ERROR => ERROR ,
SPI_START => SPI_START ,
SPI_BUSY => SPI_BUSY ,
SPI_DATA_TX => SPI_DATA_TX ,
SPI_DATA_RX => SPI_DATA_RX
);
the_spi_lowlevel: spi_lowlevel
generic map
(
gSIMULATION => gSIMULATION ,
gSysClkSpeed => gSysClkSpeed , -- Clock Speed in MHz
gSpiClkSpeed => 1000 , -- SPI Clock Speed in kHz
gUseFixedSpeed => 0 , -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH => 26 ,
gTxMSB_FIRST => 1 ,
gRxMSB_FIRST => 1 ,
gSCLK_POLARITY => '0' , --'0': idle low, '1': idle high
gCS_POLARITY => '1' , --'0': active high, '1': active low
gEN_POLARITY => '0' , --'0': normal, '1': invert
gMOSI_POLARITY => '0' , --'0': normal, '1': invert
gMISO_POLARITY => '0' , --'0': normal, '1': invert
gMISO_SAMPLE => '0' , --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK => '0' --'0': clock out on rising edge, '1': clock out on falling edge
)
port map
(
--
-- Control signals
--
CLK => CLOCK ,
RESET => RESET ,
START => SPI_START ,
BUSY => SPI_BUSY ,
SPI_DATA_TX => SPI_DATA_TX ,
SPI_DATA_RX => SPI_DATA_RX ,
TIMING => TIMING ,
--
-- SPI
--
SCLK => SCLK ,
MOSI => MOSI ,
MISO => MISO ,
CS => CS ,
EN => EN
);
end STRUCTURE ; | gpl-3.0 |
CprE488/Final | system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd | 1 | 5073 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-3.0 |
gau-veldt/InsideTheBox | Progress_2017_12_08/c64.vhd | 3 | 20988 | ----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library c64roms;
use c64roms.p_char_rom.all;
entity c64 is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end c64;
architecture c64_guts of c64 is
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
--
-- Master reset
--
signal res0 : std_logic;
signal res1 : std_logic; -- inverted slave of res0
--
-- Clocks,
-- timing signals,
-- and phase generators
--
-- VIC/CPU clock:
component clk_wiz_0
port
(-- output clock(s)
clk160 : out std_logic;
-- control signals
reset : in std_logic;
locked : out std_logic;
-- input clock(s)
clk_in1 : in std_logic
);
end component;
-- SSM2603 I2S audio clock:
component clk_wiz_1
port
(-- output clock(s)
clk12 : out std_logic;
-- control signals
reset : in std_logic;
locked : out std_logic;
-- input clock(s)
clk_in1 : in std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
-- 3-bit counter for dividing 160 MHz
-- into 8 20 MHz phases
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
--
-- Memory units and control signals
--
-- 64k x 8 main system RAM:
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal ramen : std_logic := '1';
signal ramdr : byte;
signal ramdw : byte;
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic; -- inverted slave of ram_r1w0
-- 1k x 4 color RAM
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
signal cramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic; -- inverted slave of cram_r1w0
signal ram_clk : std_logic;
signal rama : word;
--
-- Memory addressing
--
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
signal bank_sel : mbank_t;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
--
-- Determine when writes should write to RAM
--
-- Includes any banking configurations that would
-- read RAM or ROM and excludes any that access I/O.
--
signal bank_wt : std_logic;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when mbk_cgrom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
--
-- 6510 processor (CPU)
--
component chip6502 is
port (
a : out word;
di : in byte;
do : out byte;
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end component;
signal cpu_nmi0 : std_logic:='1';
signal cpu_irq0 : std_logic:='1';
signal cpu_rdy : std_logic:='1';
signal cpu_so0 : std_logic:='1';
signal cpu_r1w0 : std_logic;
signal cpu_r0w1 : std_logic; -- inverted slave of cpu_r1w0
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal abus : word;
signal cpu_ioi : byte;
signal cpu_ioo : byte;
signal cpudo : byte;
signal cpudi : byte;
signal cpu_on : std_logic; -- inverted slave of vic_on
signal cpu_ph4x : std_logic;
--
-- Video
--
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1'; -- write to VIC register
signal vic_va : slv14;
signal vic_cd : nybble;
signal vic_vd : byte;
signal vic_on : std_logic;
signal cgaddr : slv12;
signal cgdata : byte;
--
-- Audio path (SID/SSM2603)
--
-- Initialization data for SSM2603:
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"175";
when x"02" => return x"04" & x"010";
when x"03" => return x"05" & x"000";
when x"04" => return x"07" & x"000";
when x"05" => return x"09" & x"001";
when x"06" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
-- I2C xcvr to send initialization data:
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- The 6581 SID chip:
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : unsigned(4 downto 0);
signal hold_sam : signed(15 downto 0);
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
--
-- When to map CGROM into VIC's address space:
--
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
--
-- For coldstart reset
--
subtype u12 is unsigned(11 downto 0);
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal coldstart : std_logic;
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
coldstart <= '1';
else
coldstart <= '0';
end if;
end process initial_reset;
res0 <= coldstart nor btn(0);
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
begin
if (rising_edge(clk160)) then
clk20_ph <= c20_next(clk20_ph);
end if;
end process clk20gen;
clk20_ph1 <= clk20_ph(2) and (clk20_ph(1) nor clk20_ph(0));
clk20_ph2 <= not (clk20_ph(2) or clk20_ph(1) or clk20_ph(0));
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
bank_sel <= cpu_bank(u16(abus),bankctl);
bank_wt <= bank_is_writethru(abus,bankctl);
--
-- Determines character generator ROM source address
--
with cpu_on select cgaddr <=
abus(11 downto 0) when '1',
vic_va(11 downto 0) when others;
cgdata <= char_rom(cgaddr);
--
-- Determine write enables to RAMs
--
cram_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_cram) then
-- CPU only write to CRAM in CRAM bank
cram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1'; -- VIC never writes
end if;
end process cram_wren;
ram_wren: process(cpu_r1w0,cpu_on,bank_wt) is
begin
if (cpu_on='1' and bank_wt='1') then
-- writes to main RAM or write-thru ranges
ram_r1w0 <= cpu_r1w0;
else
ram_r1w0 <= '1'; -- VIC never writes
end if;
end process ram_wren;
-- Detemine write enable to VIC
vic_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_vic) then
vic_r1w0 <= cpu_r1w0;
else
vic_r1w0 <= '1';
end if;
end process vic_wren;
-- Detemine write enable to SID
sid1_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_sid) then
sid1_r1w0 <= cpu_r1w0;
else
sid1_r1w0 <= '1';
end if;
end process sid1_wren;
-- Only the CPU ever writes data
ramdw <= cpudo;
cramdw <= cpudo(3 downto 0);
--
-- Determine where the VIC reads from
--
vic_vd_sel: process(vbank,vic_va,cgdata,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
vic_vd <= cgdata;
else
vic_vd <= ramdr;
end if;
end process vic_vd_sel;
vic_cd <= cramdr; -- CRAM has no bank switching
--
-- Determine address given to RAMs
--
ram_a_sel: process(cpu_on,abus,vbank,vic_va) is
begin
if (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
-- For clocking RAM read/write cycles
with clk20_ph select ram_clk <=
'1' when "110",
'1' when "000",
'0' when others;
cpu: chip6502 port map (
nmi0 => cpu_nmi0,
irq0 => cpu_irq0,
so0 => '1',
rdy => '1',
a => abus,
do => cpudo,
di => cpudi,
r1w0 => cpu_r1w0,
pi => cpu_ioi,
po => cpu_ioo,
ph4Xin => cpu_ph4x,
res0 => res0
);
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
-- bank selection from CPU IO port
loram <= cpu_ioo(0);
hiram <= cpu_ioo(1);
charen <= cpu_ioo(2);
-- Connect data lines up
vic_regw <= cpudo;
sid1_dw <= cpudo;
-- Connect address lines
sid1_rga <= abus(4 downto 0);
vic_rga <= abus(5 downto 0);
-- Choose CPU data source (on reads)
with bank_sel select cpudi <=
ramdr when mbk_ram,
x"0" & cramdr when mbk_cram,
-- when mbk_lorom,
-- when mbk_hirom,
-- when mbk_xio2,
-- when mbk_xio1,
-- when mbk_cia2,
-- when mbk_cia1,
cgdata when mbk_cgrom,
vic_regr when mbk_sid,
sid1_dr when mbk_vic,
"ZZZZZZZZ" when others;
--
-- Audio section (including SID)
--
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,hold_sam,sid1_out,audio_frame) is
variable apos : nybble;
begin
-- flipped frame index to send MSB first
apos := not nybble(audio_frame(3 downto 0));
if (res1 = '1') then
audio_frame <= "00000";
elsif (falling_edge(bclk_cnt(1))) then
if (audio_frame = "11111") then
hold_sam <= sid1_out;
end if;
ac_pbdat <= hold_sam(to_integer(unsigned(apos)));
ac_pblrc <= audio_frame(4);
audio_frame <= audio_frame + 1;
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
led(0) <= ssm_error;
end c64_guts;
| gpl-3.0 |
gau-veldt/InsideTheBox | Progress_2017_12_08/chip6502.vhd | 1 | 158981 | ----------------------------------------------------------------------------------
--
-- Takes all the VHDL bits and makes a 6510 (6502) out of them
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end chip6502;
architecture interaction of chip6502 is
subtype slv2 is std_logic_vector(1 downto 0);
subtype u8 is unsigned(7 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant v_nmi_l : word := x"FFFA";
constant v_nmi_h : word := x"FFFB";
constant v_res_l : word := x"FFFC";
constant v_res_h : word := x"FFFD";
constant v_irq_l : word := x"FFFE";
constant v_irq_h : word := x"FFFF";
component clockgen
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out slv2;
res0 : in std_logic
);
end component;
subtype clkstg_t is std_logic_vector(1 downto 0);
signal clkStg : clkstg_t;
signal iph0 : std_logic;
signal iph1 : std_logic;
signal iph2 : std_logic;
constant sysclk_PH2_p : clkstg_t := "00";
constant sysclk_PH2_m : clkstg_t := "01";
constant sysclk_PH1_p : clkstg_t := "10";
constant sysclk_PH1_m : clkstg_t := "11";
component ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in byte;
dout : out byte;
ioi : in byte;
ioo : out byte
);
end component;
signal io_o : byte;
signal io_i : byte;
signal io_ce : std_logic;
signal io_clk : std_logic;
component alu_8bit
port (
a_in : in byte;
b_in : in byte;
c_in : in std_logic;
d_in : in std_logic; -- the dreaded BCD mode
op_in : in unsigned(2 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
r_out : out byte
);
end component;
signal ALUcin : std_logic;
signal ALUdin : std_logic;
signal ALUain : byte;
signal ALUbin : byte;
signal ALUop : unsigned(2 downto 0);
signal ALUrout : byte;
signal ALUnout : std_logic;
signal ALUvout : std_logic;
signal ALUzout : std_logic;
signal ALUcout : std_logic;
signal regbus : byte;
signal outval : byte;
signal abus : word;
signal DBen : std_logic := '1';
signal DBrw : std_logic := '1';
signal dbRE : std_logic;
signal dbWE : std_logic;
signal nDBen : std_logic;
signal aen0 : std_logic := '1';
signal aen1 : std_logic;
alias abus_off is aen0;
subtype seqType is byte;
function countSeq(src : seqType) return seqType is
variable v : unsigned(7 downto 0);
begin
v := unsigned(src);
v := v + 1;
return seqType(v);
end countSeq;
signal seq : seqType := x"00";
subtype dbctl_t is std_logic_vector(2 downto 0);
signal DB_ctl : dbctl_t := "011";
alias dbctl_sync : std_logic is DB_ctl(2);
alias dbctl_off : std_logic is DB_ctl(1);
alias dbctl_r1w0 : std_logic is DB_ctl(0);
subtype aop_t is std_logic_vector(2 downto 0);
signal aop : aop_t := "000";
constant aop_add : aop_t := "000";
constant aop_and : aop_t := "001";
constant aop_or : aop_t := "010";
constant aop_xor : aop_t := "011";
constant aop_lsl : aop_t := "100";
constant aop_lsr : aop_t := "101";
constant aop_rol : aop_t := "110";
constant aop_ror : aop_t := "111";
signal alu_bin_mode : slv2;
constant bin_reg : slv2 := "00";
constant bin_set : slv2 := "01";
constant bin_clr : slv2 := "10";
constant bin_ireg : slv2 := "11";
signal alu_cin_mode : slv2;
constant cin_psw : slv2 := "00";
constant cin_set : slv2 := "01";
constant cin_clr : slv2 := "10";
constant cin_aux : slv2 := "11";
signal alu_din_mode : std_logic;
constant din_clr : std_logic := '0';
constant din_psw : std_logic := '1';
--signal alu_bin_reg : byte;
alias alu_bin_reg : byte is ALUbin;
signal alu_bin_tie : byte;
type stage_t is (
stg_reset,
stg_fetch,
stg_sub_incpc, -- pc++
stg_sub_imm, -- mem=pc++
stg_sub_abs, -- meml=[pc++], memh=[pc++]
stg_sub_absx, -- meml=[X+(PC++)], memh=[C+(PC++)]
stg_sub_absy, -- meml=[Y+(PC++)], memh=[C+(PC++)]
stg_sub_zp, -- meml=[PC++], memh=[0]
stg_sub_zpx, -- meml=[X+(PC++)], memh=[0]
stg_sub_zpy, -- meml=[Y+(PC++)], memh=[0]
stg_sub_indx, -- buf2l=[X+(PC++)], buf2h=[0]. mem=[buf2].w
stg_sub_indy, -- buf2l=[PC++], buf2h=[0], mem=[Y+buf2].w
stg_mem2buf, -- BUF=[mem]
stg_mem2a, -- A=[mem]
stg_aCMPmem, -- NZC=A-[mem]
stg_aADDmem, -- NVZC,A=A+[mem]
stg_aSUBmem, -- NVZC,A=A-[mem]
stg_aORmem, -- A=A|[mem]
stg_aXORmem, -- A=A^[mem]
stg_aANDmem, -- A=A&mem
stg_xCMPmem, -- NZC=X-[mem]
stg_yCMPmem, -- NZC=Y-[mem]
stg_mem2x, -- X=[mem]
stg_mem2y, -- Y=[mem]
stg_a2mem, -- [mem]=A
stg_x2mem, -- [mem]=X
stg_y2mem, -- [mem]=Y
stg_ASLmem, -- ***TODO*** C <-- [7][mem][0] <-- 0
stg_ROLmem, -- ***TODO*** C <-- [7][mem][0] <-- C
stg_LSRmem, -- ***TODO*** 0 --> [7][mem][0] --> C
stg_RORmem, -- ***TODO*** C --> [7][mem][0] --> C
stg_INCmem, -- NZ=++[mem]
stg_DECmem, -- NZ=--[mem]
stg_BITmem, -- Z=[mem]&A, NV=[mem][7:6]
stg_BRK, -- ***TODO*** ++PC, B=1, raise (unmaskable) IRQ
stg_IRQ, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_irq_l], PCH=[v_irq_h]
stg_NMI, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_nmi_l], PCH=[v_nmi_h]
stg_CLC,
stg_SEC,
stg_CLI,
stg_SEI,
stg_CLV,
stg_CLD,
stg_SED,
stg_TXS,
stg_TSX,
stg_PHA,
stg_PLA,
stg_PHP,
stg_PLP,
stg_TAX,
stg_TXA,
stg_TAY,
stg_TYA,
stg_DEX,
stg_DEY,
stg_INX,
stg_INY,
stg_JMP_abs,
stg_JMP_ind,
stg_reljmp, -- take branch
stg_BCC,
stg_BCS,
stg_BNE,
stg_BEQ,
stg_BPL,
stg_BMI,
stg_BVC,
stg_BVS,
stg_ASL_a,
stg_LSR_a,
stg_ROL_a,
stg_ROR_a,
stg_RTS,
stg_RTI,
stg_JSR,
stg_tail
);
signal seq_stage : stage_t := stg_reset;
signal ret_stage : stage_t := stg_fetch; -- return stage for sub stage
signal ir : byte := x"00";
signal reg_a : byte := x"00";
signal reg_x : byte := x"00";
signal reg_y : byte := x"00";
signal reg_pc : word := x"0000";
signal reg_sp : byte := x"00";
signal reg_p : byte := x"00";
alias psw_n is reg_p(7);
alias psw_v is reg_p(6);
alias psw_b is reg_p(4);
alias psw_d is reg_p(3);
alias psw_i is reg_p(2);
alias psw_z is reg_p(1);
alias psw_c is reg_p(0);
signal buf_data : byte := x"00";
signal buf_addr : word := x"0000";
signal buf2 : word := x"0000";
alias reg_pcl : byte is reg_pc(7 downto 0);
alias reg_pch : byte is reg_pc(15 downto 8);
alias buf_addr_l : byte is buf_addr(7 downto 0);
alias buf_addr_h : byte is buf_addr(15 downto 8);
alias buf2l : byte is buf2(7 downto 0);
alias buf2h : byte is buf2(15 downto 8);
signal private_c : std_logic;
signal NMI_last : std_logic;
function isZero(src: byte) return std_logic is
begin
return ((src(0) nor src(1)) and (src(2) nor src(3))) and
((src(4) nor src(5)) and (src(6) nor src(7)));
end isZero;
function dec(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) - "000000001";
return byte(argu(7 downto 0));
end dec;
function inc(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) + "000000001";
return byte(argu(7 downto 0));
end inc;
function inc16(arg : word) return word is
variable argu : unsigned(16 downto 0);
begin
argu := ('0' & u16(arg)) + ('0' & x"01");
return word(argu(15 downto 0));
end inc16;
function sgn(arg : byte) return byte is
begin
return arg(7) & arg(7) & arg(7) & arg(7) &
arg(7) & arg(7) & arg(7) & arg(7);
end sgn;
function getb(arg : byte; bp : integer) return std_logic is
begin
return arg(bp);
end getb;
begin
clock: clockgen port map(
ph4Xin => ph4Xin,
ph0 => iph0,
ph1 => iph1,
ph2 => iph2,
stg => clkStg,
res0 => res0
);
ph0 <= iph0;
ph1 <= iph1;
ph2 <= iph2;
io8bit: ioport8bit port map(
ce => io_ce,
clk => io_clk,
res0 => res0,
r1w0 => dbRW,
a => abus(0),
din => io_i,
dout => io_o,
ioi => pi,
ioo => po
);
io_clk <= (not clkStg(1)) and clkStg(0);
io_ce <= not ( (((abus(15) or abus(14)) or (abus(13) or abus(12))) or
((abus(11) or abus(10)) or (abus( 9) or abus( 8)))) or
(((abus( 7) or abus( 6)) or (abus( 5) or abus( 4))) or
((abus( 3) or abus( 2)) or abus( 1) )) );
io_i <= regbus;
alunit: alu_8bit port map(
a_in => ALUain,
b_in => ALU_bin_tie,
c_in => ALUcin,
d_in => ALUdin,
op_in => ALUop,
n_out => ALUnout,
v_out => ALUvout,
z_out => ALUzout,
c_out => ALUcout,
r_out => ALUrout
);
alu_cin_mux: process(alu_cin_mode,psw_c,private_c) is
begin
case alu_cin_mode is
when cin_set => ALUcin <= '1';
when cin_clr => ALUcin <= '0';
when cin_aux => ALUcin <= private_c;
when others => ALUcin <= psw_c;
end case;
end process alu_cin_mux;
alu_din_mux: process(alu_din_mode,psw_d) is
begin
case alu_din_mode is
when din_clr => ALUdin <= '0';
when others => ALUdin <= psw_d;
end case;
end process alu_din_mux;
alu_bin_mux: process(alu_bin_mode,alu_bin_reg) is
begin
case alu_bin_mode is
when bin_clr => alu_bin_tie <= "00000000";
when bin_set => alu_bin_tie <= "11111111";
when bin_ireg => alu_bin_tie <= not alu_bin_reg;
when others => alu_bin_tie <= alu_bin_reg;
end case;
end process alu_bin_mux;
sync <= DB_ctl(2);
DBen <= DB_ctl(1);
DBrw <= DB_ctl(0);
nDBen <= not DBen;
DBre <= DBrw;
DBwe <= not DBrw;
aen1 <= not aen0;
r1w0 <= DBrw;
ALUop <= unsigned(aop);
-- Allow connection of data bus as output during write operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_ogate: process(nDBen,DBwe,outval) iS
begin
if ((nDBen and DBwe) = '1') then
if (io_ce='1') then
do <= io_o;
else
do <= outval;
end if;
else
do <= "ZZZZZZZZ";
end if;
end process db_ogate;
-- Allow connection of data bus as input during read operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_igate: process(nDBen,DBre,di) is
begin
if ((nDBen and DBre) = '1') then
regbus <= di;
else
regbus <= "ZZZZZZZZ";
end if;
end process db_igate;
addr_gate: process(aen1,abus) is
begin
if (aen1='1') then
a <= abus;
else
a <= "ZZZZZZZZZZZZZZZZ";
end if;
end process addr_gate;
main_proc: process(res0,ph4Xin) is
variable doNMI : std_logic;
variable tmp8 : byte;
begin
-- Status register stuff
reg_p(5) <= '0';
if (so0 = '0') then
psw_V <= '1';
end if;
if (res0 = '0') then
seq <= x"00";
seq_stage <= stg_reset;
ret_stage <= stg_reset;
dbctl_r1w0 <= '1';
dbctl_off <= '1';
dbctl_sync <= '0';
abus_off <= '1';
doNMI := '0';
elsif (rising_edge(ph4Xin)) then
-- allows sensing NMI on any clock
-- (but won't trigger until epilogue)
doNMI := doNMI or (NMI_last and (not nmi0)); -- only on transition to '0'
NMI_last <= nmi0; -- saves the state read
-- reset stage
if (seq_stage = stg_reset) then
if ((not (clkStg = sysclk_PH2_m)) and seq=x"00") then
else
-- we enter here at seq x00 on PH1+
case seq is
when x"00" => seq <= countSeq(seq); -- PH1+: put RES vector L on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= v_res_l;
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) write to PCL
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put RES vector H on abus
abus <= v_res_h;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
seq_stage <= stg_fetch; -- change to instruction decode
seq <= x"00";
when others => null;
end case;
end if;
end if;
-- instruction fetch/decode stage
if (seq_stage = stg_fetch) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
dbctl_sync <= '1'; -- sync on for instruction decode
abus_off <= '0';
abus <= reg_pc; -- PC on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) get instruction
ir <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: sync off
dbctl_sync <= '0';
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"05" => -- PH1-: store PCL=1+PCL
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"07" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
if (rdy = '1') then
abus_off <= '0';
dbctl_off <= '0';
seq <= x"00";
case ir is
when x"4C" =>
seq_stage <= stg_JMP_abs; -- JMP abs
when x"6C" =>
seq_stage <= stg_JMP_ind; -- JMP ind
when x"18" =>
seq_stage <= stg_CLC; -- CLC
when x"38" =>
seq_stage <= stg_SEC; -- SEC
when x"58" =>
seq_stage <= stg_CLI; -- CLI
when x"78" =>
seq_stage <= stg_SEI; -- SEI
when x"B8" =>
seq_stage <= stg_CLV; -- CLV
when x"D8" =>
seq_stage <= stg_CLD; -- CLD
when x"F8" =>
seq_stage <= stg_SED; -- SED
when x"A9" => -- LDA
ret_stage <= stg_mem2a; -- imm
seq_stage <= stg_sub_imm;
when x"AD" => -- abs
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_abs;
when x"BD" => -- abs+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absx;
when x"B9" => -- abs+y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absy;
when x"A5" => -- zp
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zp;
when x"B5" => -- zp+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zpx;
when x"A1" => -- indirect,X
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indx;
when x"B1" => -- indirect,Y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indy;
when x"A2" => -- LDX
ret_stage <= stg_mem2x; -- imm
seq_stage <= stg_sub_imm;
when x"AE" => -- abs
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_abs;
when x"BE" => -- abs+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_absy;
when x"A6" => -- zp
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zp;
when x"B6" => -- zp+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zpy;
when x"A0" => -- LDY
ret_stage <= stg_mem2y; -- imm
seq_stage <= stg_sub_imm;
when x"AC" => -- abs
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_abs;
when x"BC" => -- abs+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_absx;
when x"A4" => -- zp
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zp;
when x"B4" => -- zp+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zpx;
when x"8D" => -- STA
ret_stage <= stg_a2mem; -- abs
seq_stage <= stg_sub_abs;
when x"9D" => -- abs+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absx;
when x"99" => -- abs+y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absy;
when x"85" => -- zp
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zp;
when x"95" => -- zp+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zpx;
when x"81" => -- indirect,X
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indx;
when x"91" => -- indirect,Y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indy;
when x"8E" => -- STX
ret_stage <= stg_x2mem; -- abs
seq_stage <= stg_sub_abs;
when x"86" => -- zp
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zp;
when x"96" => -- zp+y
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zpy;
when x"8C" => -- STY
ret_stage <= stg_y2mem; -- abs
seq_stage <= stg_sub_abs;
when x"84" => -- zp
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zp;
when x"94" => -- zp+x
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zpx;
when x"09" => -- ORA A | mem
ret_stage <= stg_aORmem; -- imm
seq_stage <= stg_sub_imm;
when x"0D" => -- abs
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_abs;
when x"1D" => -- abs+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absx;
when x"19" => -- abs+y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absy;
when x"05" => -- zp
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zp;
when x"15" => -- zp+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zpx;
when x"01" => -- indirect,X
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indx;
when x"11" => -- indirect,Y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indy;
when x"29" => -- AND A & mem
ret_stage <= stg_aANDmem; -- imm
seq_stage <= stg_sub_imm;
when x"2D" => -- abs
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_abs;
when x"3D" => -- abs+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absx;
when x"39" => -- abs+y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absy;
when x"25" => -- zp
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zp;
when x"35" => -- zp+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zpx;
when x"21" => -- indirect,X
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indx;
when x"31" => -- indirect,Y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indy;
when x"24" => -- BIT Z=A&M, NV=[MEM][7:6]
ret_stage <= stg_BITmem; -- zp
seq_stage <= stg_sub_zp;
when x"2C" => -- abs
ret_stage <= stg_BITmem;
seq_stage <= stg_sub_abs;
when x"49" => -- EOR A ^ mem
ret_stage <= stg_aXORmem; -- imm
seq_stage <= stg_sub_imm;
when x"4D" => -- abs
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_abs;
when x"5D" => -- abs+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absx;
when x"59" => -- abs+y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absy;
when x"45" => -- zp
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zp;
when x"55" => -- zp+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zpx;
when x"41" => -- indirect,X
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indx;
when x"51" => -- indirect,Y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indy;
when x"69" => -- ADC C + A + mem
ret_stage <= stg_aADDmem; -- imm
seq_stage <= stg_sub_imm;
when x"6D" => -- abs
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_abs;
when x"7D" => -- abs+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absx;
when x"79" => -- abs+y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absy;
when x"65" => -- zp
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zp;
when x"75" => -- zp+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zpx;
when x"61" => -- indirect,X
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indx;
when x"71" => -- indirect,Y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indy;
when x"C9" => -- CMP NZC = A - mem
ret_stage <= stg_aCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"CD" => -- abs
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_abs;
when x"DD" => -- abs+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absx;
when x"D9" => -- abs+y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absy;
when x"C5" => -- zp
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zp;
when x"D5" => -- zp+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zpx;
when x"C1" => -- indirect,X
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indx;
when x"D1" => -- indirect,Y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indy;
when x"C0" => -- CPY NZC = Y - mem
ret_stage <= stg_yCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"C4" => -- zp
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_zp;
when x"CC" => -- abs
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_abs;
when x"E0" => -- CPX NZC = X - mem
ret_stage <= stg_xCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"E4" => -- zp
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_zp;
when x"EC" => -- abs
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_abs;
when x"E9" => -- SBC A + C - (mem+1)
ret_stage <= stg_aSUBmem; -- imm
seq_stage <= stg_sub_imm;
when x"ED" => -- abs
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_abs;
when x"FD" => -- abs+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absx;
when x"F9" => -- abs+y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absy;
when x"E5" => -- zp
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zp;
when x"F5" => -- zp+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zpx;
when x"E1" => -- indirect,X
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indx;
when x"F1" => -- indirect,Y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indy;
when x"9A" => -- TXS sp=x
seq_stage <= stg_TXS;
when x"BA" => -- TSX x=sp
seq_stage <= stg_TSX;
when x"48" => -- PHA [sp--]=a
seq_stage <= stg_PHA;
when x"68" => -- PLA a=[++sp]
seq_stage <= stg_PLA;
when x"08" => -- PHP [sp--]=P
seq_stage <= stg_PHP;
when x"28" => -- PLP P=[++sp]
seq_stage <= stg_PLP;
when x"AA" => -- TAX X=A
seq_stage <= stg_TAX;
when x"8A" => -- TXA A=X
seq_stage <= stg_TXA;
when x"A8" => -- TAY Y=A
seq_stage <= stg_TAY;
when x"98" => -- TYA A=Y
seq_stage <= stg_TYA;
when x"CA" => -- DEX X=X-1
seq_stage <= stg_DEX;
when x"88" => -- DEY Y=Y-1
seq_stage <= stg_DEY;
when x"C6" => -- DEC --[mem]
ret_stage <= stg_decmem; -- zp
seq_stage <= stg_sub_zp;
when x"D6" =>
ret_stage <= stg_decmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"CE" =>
ret_stage <= stg_decmem; -- abs
seq_stage <= stg_sub_abs;
when x"DE" =>
ret_stage <= stg_decmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"E8" => -- INX X=X+1
seq_stage <= stg_INX;
when x"C8" => -- INY Y=Y+1
seq_stage <= stg_INY;
when x"E6" => -- INC ++[mem]
ret_stage <= stg_incmem; -- zp
seq_stage <= stg_sub_zp;
when x"F6" =>
ret_stage <= stg_incmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"EE" =>
ret_stage <= stg_incmem; -- abs
seq_stage <= stg_sub_abs;
when x"FE" =>
ret_stage <= stg_incmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"10" => -- BPL PC+OP when N=0
seq_stage <= stg_BPL;
when x"30" => -- BMI PC+OP when N=1
seq_stage <= stg_BMI;
when x"50" => -- BVC PC+OP when V=0
seq_stage <= stg_BVC;
when x"70" => -- BVS PC+OP when V=1
seq_stage <= stg_BVS;
when x"90" => -- BCC PC+OP when C=0
seq_stage <= stg_BCC;
when x"B0" => -- BCS PC+OP when C=1
seq_stage <= stg_BCS;
when x"D0" => -- BNE PC+OP when Z=0
seq_stage <= stg_BNE;
when x"F0" => -- BEQ PC+OP when Z=1
seq_stage <= stg_BEQ;
when x"0A" => -- ASL C << T << '0'
seq_stage <= stg_ASL_a; -- a
when x"06" =>
ret_stage <= stg_ASLmem; -- zp
seq_stage <= stg_sub_zp;
when x"16" =>
ret_stage <= stg_ASLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"0E" =>
ret_stage <= stg_ASLmem; -- abs
seq_stage <= stg_sub_abs;
when x"1E" =>
ret_stage <= stg_ASLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"2A" => -- ROL C << T << C
seq_stage <= stg_ROL_a; -- a
when x"26" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"36" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"2E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"3E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"4A" => -- LSR '0' >> T >> C
seq_stage <= stg_LSR_a; -- a
when x"46" =>
ret_stage <= stg_LSRmem; -- zp
seq_stage <= stg_sub_zp;
when x"56" =>
ret_stage <= stg_LSRmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"4E" =>
ret_stage <= stg_LSRmem; -- abs
seq_stage <= stg_sub_abs;
when x"5E" =>
ret_stage <= stg_LSRmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"6A" => -- ROR C >> T >> C
seq_stage <= stg_ROR_a; -- a
when x"66" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"76" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"6E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"7E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"60" => -- RTS PCH=[++SP],PCL=[++SP],++PC
seq_stage <= stg_RTS;
when x"40" => -- RTI P=[++SP], PCH=[++SP],PCL=[++SP]
seq_stage <= stg_RTI;
when x"20" => -- JSR [email protected] to stack, PC=OP.w
seq_stage <= stg_JSR;
when others =>
seq_stage <= stg_tail; -- NOP
end case;
else
abus_off <= '1'; -- burn a full PH1/PH2 cycle if RDY=0
dbctl_off <= '1';
seq <= x"08";
end if;
when x"08" => seq <= countSeq(seq); -- PH1+: burn
when x"09" => seq <= countSeq(seq); -- PH1-: burn
when x"0A" => seq <= x"07"; -- PH2+: will check RDY again on PH2-
when others => null;
end case;
end if;
-- epilogue stage (also handles NOP)
-- checks for interrupts
if (seq_stage = stg_tail) then
case seq is
when x"00" => -- PH1+: burn
abus_off <= '0'; -- abus enabled
dbctl_off <= '0'; -- dbus enabled
dbctl_r1w0 <= '1'; -- dbus to read
seq <= countSeq(seq);
when x"01" => -- PH1-: burn
seq <= countSeq(seq);
when x"02" => -- PH2+: burn
seq <= countSeq(seq);
when x"03" =>
seq_stage <= stg_fetch; -- PH2-: return to fetch (on PH1+)
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_incpc) then
case seq is
when x"00" => -- PH1+:
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+1
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
seq <= x"00";
seq_stage <= ret_stage; -- PH2+: set return-to stage (on PH1+)
when others => null;
end case;
end if;
if (seq_stage = stg_incmem) then -- ++[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_set; -- ALU: Rout=Ain+1
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_decmem) then -- --[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_clr; -- ALU: Rout=Ain-1
alu_bin_mode <= bin_set;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_reljmp) then
case seq is -- PC+=(signed)BUF
when x"00" => -- PH1+:
ALUain <= reg_pcl;
ALUbin <= buf_data;
alu_cin_mode <= cin_clr;
alu_bin_mode <= bin_reg;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+BUF
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
ALUbin <= sgn(buf_data); -- sign extend BUF for PCH
alu_cin_mode <= cin_aux; -- apply carry from PCL+BUF
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C+sgn(BUF)
seq <= x"00";
seq_stage <= stg_tail; -- branch finished
when others => null;
end case;
end if;
-- JMP abs
if (seq_stage = stg_JMP_abs) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
reg_pcl <= buf_addr_l; -- copy buffered lobyte to PCL
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- JMP ind
if (seq_stage = stg_JMP_ind) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- save to MEML
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) write to PCH
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf_addr; -- put MEM on abus
ALUain <= buf_addr_l; -- set up for ++MEM
ALU_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf2l <= ALUrout;
private_c <= ALUcout; -- BUF2=MEM+1
seq <= countSeq(seq);
when x"0a" => -- PH2+:
ALUain <= buf_addr_h; --
ALU_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- PCL=(MEM)
buf_addr_l <= buf2l;
buf_addr_h <= ALUrout; -- ++MEM
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf_addr; -- put MEM (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- PCH=MEM (+1)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2buf) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
buf_data <= regbus; -- save to BUF
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2a) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= regbus; -- save to A
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aANDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A and regbus; -- A = A & [mem]
psw_z <= isZero(reg_A and regbus); -- Z flag
psw_n <= getb(reg_A and regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_BITmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
psw_z <= isZero(regbus and reg_A); -- Z flag as if A & [mem]
psw_n <= regbus(7); -- N flag <= [mem][7]
psw_v <= regbus(6); -- V flag <= [mem][6]
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aADDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_reg; -- reg => bin
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C +
ALUbin <= regbus; -- mem
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aSUBmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_xCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_x; -- X
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_yCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_y; -- Y
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A or regbus; -- A = A | [mem]
psw_z <= isZero(reg_A or regbus); -- Z flag
psw_n <= getb(reg_A or regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aXORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A xor regbus; -- A = A ^ [mem]
psw_z <= isZero(reg_A xor regbus); -- Z flag
psw_n <= getb(reg_A xor regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2x) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_x <= regbus; -- save to X
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2y) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_y <= regbus; -- save to Y
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_a2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_a; -- A to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_x2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_x; -- X to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_y2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_y; -- Y to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_imm) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
buf_addr <= reg_pc; -- MEM=PC
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
ALUain <= reg_pch;
seq <= countSeq(seq);
when x"02" => -- PH2+:
reg_pch <= ALUrout; -- PC=PC+1
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) store data to A
seq <= x"00";
seq_stage <= ret_stage;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_abs) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr) pass
buf_addr_l <= ALUrout; -- MEML=MEML+X
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zp) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+X
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- BUF2=00:MEML+X
buf2h <= x"00";
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => seq <= countSeq(seq); -- PH2-: (valid data) pass
when x"08" => -- PH1+:
abus <= buf2; -- buf2 on abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML=[buf2++]
buf2 <= inc16(buf2);
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf2; -- buf2 (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
buf_addr_h <= regbus; -- MEMH=[buf2] (+1)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
buf2h <= x"00";
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML = [PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
abus <= x"00" & buf_addr_l; -- put 00:MEML on abus
buf2 <= x"00" & buf_addr_l; -- buf2=00:MEML
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) pass
buf_addr_l <= regbus; -- MEML = [BUF2]
buf2 <= inc16(buf2); -- ++buf2
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf2; -- buf2 (buf+1) on abus
ALUain <= buf_addr_l; -- start MEM=MEM+Y
ALUbin <= reg_y; -- MEML+Y
ALU_cin_mode <= cin_clr;
ALU_bin_mode <= bin_reg;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"0a" => -- PH2+:
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
ALUain <= regbus; -- C+[BUF2] (MSB)
seq <= countSeq(seq);
when x"0c" => -- PH1+:
buf_addr_h <= ALUrout; -- MEMH=C+[BUF2] (MSB)
seq <= countSeq(seq); -- MEM=MEM+Y done
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
-- CLC
if (seq_stage = stg_CLC) then
case seq is
when x"00" => -- PH1+: C=0
psw_c <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEC
if (seq_stage = stg_SEC) then
case seq is
when x"00" => -- PH1+: C=1
psw_c <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLI
if (seq_stage = stg_CLI) then
case seq is
when x"00" => -- PH1+: I=0
psw_i <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEI
if (seq_stage = stg_SEI) then
case seq is
when x"00" => -- PH1+: I=1
psw_i <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLV
if (seq_stage = stg_CLV) then
case seq is
when x"00" => -- PH1+: V=0
psw_v <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLD
if (seq_stage = stg_CLD) then
case seq is
when x"00" => -- PH1+: D=0
psw_d <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SED
if (seq_stage = stg_SED) then
case seq is
when x"00" => -- PH1+: D=1
psw_d <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXS
if (seq_stage = stg_TXS) then
case seq is
when x"00" => -- PH1+:
reg_sp <= reg_x; -- store SP=X
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TSX
if (seq_stage = stg_TSX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_sp; -- store X=SP
psw_z <= isZero(reg_sp); -- Z flag
psw_n <= reg_sp(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- PHA
if (seq_stage = stg_PHA) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= reg_a;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PHP
if (seq_stage = stg_PHP) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= (reg_p(7 downto 6) & "01" &
reg_p(3 downto 0)); -- 6502 quirk: B always set on pushed psw
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLA
if (seq_stage = stg_PLA) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLP
if (seq_stage = stg_PLP) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_p <= (regbus(7 downto 6) & "0" &
regbus(4 downto 0)); -- store status value (unused bit forced to 0)
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- TAX
if (seq_stage = stg_TAX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_a; -- store X=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXA
if (seq_stage = stg_TXA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_x; -- store A=X
psw_z <= isZero(reg_x); -- Z flag
psw_n <= reg_x(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TAY
if (seq_stage = stg_TAY) then
case seq is
when x"00" => -- PH1+:
reg_y <= reg_a; -- store Y=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TYA
if (seq_stage = stg_TYA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_y; -- store A=Y
psw_z <= isZero(reg_y); -- Z flag
psw_n <= reg_y(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEX
if (seq_stage = stg_DEX) then
case seq is
when x"00" => -- PH1+: BUF=x-1
buf_data <= dec(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEY
if (seq_stage = stg_DEY) then
case seq is
when x"00" => -- PH1+: BUF=y-1
buf_data <= dec(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INX
if (seq_stage = stg_INX) then
case seq is
when x"00" => -- PH1+: BUF=x+1
buf_data <= inc(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INY
if (seq_stage = stg_INY) then
case seq is
when x"00" => -- PH1+: BUF=y+1
buf_data <= inc(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- BCC
if (seq_stage = stg_BCC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BCS
if (seq_stage = stg_BCS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc; -- ++PC then branch or finish
when others => null;
end case;
end if;
-- BNE
if (seq_stage = stg_BNE) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BEQ
if (seq_stage = stg_BEQ) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BPL
if (seq_stage = stg_BPL) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BMI
if (seq_stage = stg_BMI) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVC
if (seq_stage = stg_BVC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVS
if (seq_stage = stg_BVS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- ASL A
if (seq_stage = stg_ASL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & '0'; -- tmp = A << 1
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ASL [mem]
if (seq_stage = stg_ASLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & '0'; -- tmp = [mem] << 1
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR A
if (seq_stage = stg_LSR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := '0' & reg_a(7 downto 1); -- tmp = A >> 1
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR [mem]
if (seq_stage = stg_LSRmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := '0' & regbus(7 downto 1); -- tmp = [mem] >> 1
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL A
if (seq_stage = stg_ROL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & psw_c; -- tmp = A[6:0],C
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL[mem]
if (seq_stage = stg_ROLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & psw_c; -- tmp = [mem](6:0),C
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR A
if (seq_stage = stg_ROR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := psw_c & reg_a(7 downto 1); -- tmp = C,A[7:1]
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR [mem]
if (seq_stage = stg_RORmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := psw_c & regbus(7 downto 1); -- tmp = C,[mem](7:1)
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- RTS (PCH=[++SP], PCL=[++SP], incpc, tail)
if (seq_stage = stg_RTS) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf_data <= ALUrout; -- we didn't have addr ready on PH1+
seq <= countSeq(seq); -- so we'll store this SP+1 in BUF
when x"02" => -- PH2+: and pipeline BUF+1 (SP+2)
ALUain <= buf_data; -- through this bus cycle
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"03" => seq <= countSeq(seq); -- PH2-: (valid data)
reg_sp <= ALUrout; -- SP=SP+2
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"04" => -- PH1+: put out address of PCL
abus <= (x"01" & buf_data); -- 01:BUF
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"08" => -- PH1+: put out address of PCH
abus <= (x"01" & reg_sp); -- 01:SP
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pch <= regbus;
seq <= countSeq(seq);
seq <= x"00";
ret_stage <= stg_tail; -- JSR saves PC-1 so we incpc
seq_stage <= stg_sub_incpc; -- first, then tail (done)
when others => null;
end case;
end if;
-- RTI (P=[++SP], PCH=[++SP], PCL=[++SP], tail)
if (seq_stage = stg_RTI) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) not yet available
reg_sp <= ALUrout; -- ++SP (now on psw)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq); -- we need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have addresses for bus
abus <= (x"01" & reg_sp); -- 01:sp (psw) to abus
reg_sp <= ALUrout; -- ++SP (now on PCL)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
reg_p <= (regbus(7 downto 6) & "00" &
regbus(3 downto 0)); -- store psw (unused/brk set to 0)
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp (PCL) to abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- save PCL=[SP]
reg_sp <= ALUrout; -- ++SP (now on PCH)
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"0c" => -- PH1+: put out address of PCL
abus <= (x"01" & reg_sp); -- 01:sp (PCH) to abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- save PCH=[SP]
seq <= x"00";
seq_stage <= stg_tail; -- instruction done
when others => null;
end case;
end if;
-- JSR (buf_addr=[pc].w, ++pc, [sp--]=PCL, [sp--]=PCH)
if (seq_stage = stg_JSR) then
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to MEMH
buf_addr_h <= regbus; -- (PC not yet saved)
seq <= countSeq(seq);
when x"08" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0a" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pch; -- [01:SP]=PCH
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data) pass
seq <= countSeq(seq);
when x"0c" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"0d" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0e" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pcl; -- [01:SP]=PCL
seq <= countSeq(seq);
when x"0f" => -- PH2-: (valid data)
dbctl_r1w0 <= '1'; -- shut off write
reg_pc <= buf_addr; -- PC=MEM
seq_stage <= stg_tail;
seq <= x"00"; -- instruction done
when others => null;
end case;
end if;
end if;
end process main_proc;
end interaction;
| gpl-3.0 |
gau-veldt/InsideTheBox | Ep0002/AudioEcho.vhd | 1 | 7803 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2017 12:34:40 AM
-- Design Name:
-- Module Name: AudioEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AudioEcho is
port (
led : out std_logic_vector(3 downto 0);
sw : in std_logic_vector(3 downto 0);
clk_125 : in std_logic
);
end AudioEcho;
architecture Driver of AudioEcho is
subtype tCount is unsigned(31 downto 0);
constant cZero : tCount := to_unsigned(0,tCount'length);
constant cMod : tCount := to_unsigned(4,tCount'length);
constant cMax : tCount := to_unsigned(125000000,tCount'length);
signal led_st : std_logic_vector(3 downto 0) := "0001";
signal my_clk : std_logic := '0';
signal dCount : tCount := cZero;
signal pingpong : std_logic := '0';
begin
divider: process(clk_125) is
variable dCur : tCount := dCount;
begin
if (rising_edge(clk_125)) then
dCur:=dCur+cMod;
if (dCur >= cMax) then
dCur := dCur - cMax;
my_clk <= not my_clk;
end if;
end if;
end process divider;
lcount: process(my_clk) is
variable lCur : std_logic_vector(3 downto 0) := led_st;
begin
if (rising_edge(my_clk)) then
case sw is
when "0001" =>
-- L to R
case lCur is
when "0001" =>
led_st <= "1000";
when "0010" =>
led_st <= "0001";
when "0100" =>
led_st <= "0010";
when "1000" =>
led_st <= "0100";
when others =>
led_st <= "0001";
end case;
when "0010" =>
-- count binary
case lcur is
when "0000" =>
led_st <= "0001";
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0011";
when "0011" =>
led_st <= "0100";
when "0100" =>
led_st <= "0101";
when "0101" =>
led_st <= "0110";
when "0110" =>
led_st <= "0111";
when "0111" =>
led_st <= "1000";
when "1000" =>
led_st <= "1001";
when "1001" =>
led_st <= "1010";
when "1010" =>
led_st <= "1011";
when "1011" =>
led_st <= "1100";
when "1100" =>
led_st <= "1101";
when "1101" =>
led_st <= "1110";
when "1110" =>
led_st <= "1111";
when "1111" =>
led_st <= "0000";
when others =>
led_st <= "0000";
end case;
when "0100" =>
-- count gray
case lcur is
when "0000" =>
led_st <= "0001";
when "0001" =>
led_st <= "0011";
when "0011" =>
led_st <= "0010";
when "0010" =>
led_st <= "0110";
when "0110" =>
led_st <= "0111";
when "0111" =>
led_st <= "0101";
when "0101" =>
led_st <= "0100";
when "0100" =>
led_st <= "1100";
when "1100" =>
led_st <= "1101";
when "1101" =>
led_st <= "1111";
when "1111" =>
led_st <= "1110";
when "1110" =>
led_st <= "1010";
when "1010" =>
led_st <= "1011";
when "1011" =>
led_st <= "1001";
when "1001" =>
led_st <= "1000";
when "1000" =>
led_st <= "0000";
when others =>
led_st <= "0000";
end case;
when "1000" =>
-- ping-pong
case pingpong is
when '0' =>
case lCur is
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0100";
when "0100" =>
led_st <= "1000";
when "1000" =>
led_st <= "0100";
pingpong <= '1';
when others =>
led_st <= "0001";
end case;
when '1' =>
case lCur is
when "1000" =>
led_st <= "0100";
when "0100" =>
led_st <= "0010";
when "0010" =>
led_st <= "0001";
when "0001" =>
led_st <= "0010";
pingpong <= '0';
when others =>
led_st <= "1000";
end case;
end case;
when others =>
-- R to L
case lCur is
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0100";
when "0100" =>
led_st <= "1000";
when "1000" =>
led_st <= "0001";
when others =>
led_st <= "0001";
end case;
end case;
end if;
end process lcount;
led <= led_st;
end Driver; | gpl-3.0 |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9/simulation/dcm_TFT9_tb.vhd | 1 | 5373 | -- file: dcm_TFT9_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_TFT9_tb is
end dcm_TFT9_tb;
architecture test of dcm_TFT9_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
component dcm_TFT9_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_TFT9_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
| gpl-3.0 |
gau-veldt/InsideTheBox | Progress_2017_12_21/cia6526.vhd | 1 | 8149 | ----------------------------------------------------------------------------------
--
-- 6526 CIA
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cia6526 is
port (
PAo : out std_logic_vector(7 downto 0);
PAi : in std_logic_vector(7 downto 0);
PBo : out std_logic_vector(7 downto 0);
PBi : in std_logic_vector(7 downto 0);
irq0 : out std_logic;
rga : in std_logic_vector(3 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
ce : in std_logic;
clk : in std_logic -- 1 MHz
);
end cia6526;
architecture CIA_impl of cia6526 is
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
-- io ports A,B
signal PA : byte := x"00";
signal PB : byte := x"00";
signal PArd : byte; -- reg 0x0
signal PBrd : byte; -- reg 0x1
-- data direction registers (1=output, 0=input)
signal ddrA : byte := x"00"; -- reg 0x2
signal ddrB : byte := x"00"; -- reg 0x3
signal TAcnt : u16 := x"ffff";
signal TAltc : u16 := x"ffff";
signal TBcnt : u16 := x"ffff";
signal TBltc : u16 := x"ffff";
signal TActl : byte := x"00";
signal TBctl : byte := x"00";
alias TArun : std_logic is TActl(0);
alias TAto : std_logic is TActl(1);
alias TAupm : std_logic is TActl(2);
alias TAloop : std_logic is TActl(3);
alias TAsrc : pair is TActl(6 downto 5);
alias TBrun : std_logic is TBctl(0);
alias TBto : std_logic is TBctl(1);
alias TBupm : std_logic is TBctl(2);
alias TBloop : std_logic is TBctl(3);
alias TBsrc : pair is TBctl(6 downto 5);
signal ir_mask : slv5 := "00000";
signal ir_ltc : slv5 := "00000"; -- any bits set in here trigger an IRQ
signal ir_irq : std_logic;
constant src_ATO : integer := 0;
constant src_BTO : integer := 1;
constant src_TOD : integer := 2;
constant src_SDR : integer := 3;
constant src_FLG : integer := 4;
-- returns 1 if input is nonzero
function notZero(arg: slv5) return std_logic is
begin
return arg(0) or arg(1) or arg(2) or arg(3) or
arg(4);
end function notZero;
begin
ir_irq <= notZero(ir_ltc);
irq0 <= not ir_irq;
outA: process(ddrA,PA) is
begin
for i in 7 downto 0 loop
if (ddrA(i)='1') then
-- dump appropriate bit of port data register to any lines flagged output
PAo(i) <= PA(i);
else
-- if the line is flagged input read output a one to simluate hardware pullup
PAo(i) <= '1';
end if;
end loop;
end process outA;
outB: process(ddrB,PB) is
begin
for i in 7 downto 0 loop
if (ddrB(i)='1') then
-- dump appropriate bit of port data register to any lines flagged output
PBo(i) <= PB(i);
else
-- if the line is flagged input read output a one to simluate hardware pullup
PBo(i) <= '1';
end if;
end loop;
end process outB;
rd_A: process(ddrA,PA,PAi) is
begin
for i in 7 downto 0 loop
if (ddrA(i)='1') then
-- output lines just parrot the appropriate bit in the port data register
PArd(i) <= PA(i);
else
-- input lines reflect the corresponding external input lines
PArd(i) <= PAi(i);
end if;
end loop;
end process rd_A;
rd_B: process(ddrB,PB,PBi) is
begin
for i in 7 downto 0 loop
if (ddrB(i)='1') then
-- output lines just parrot the appropriate bit in the port data register
PBrd(i) <= PB(i);
else
-- input lines reflect the corresponding external input lines
PBrd(i) <= PBi(i);
end if;
end loop;
end process rd_B;
reg_access: process(clk,rgdi,ir_irq,ir_ltc,TAltc,TBltc,TAcnt,TBcnt,TActl,TBctl,PArd,PBrd,ddrA,ddrB) is
variable Acnt : u16;
variable Bcnt : u16;
begin
Acnt := TAcnt;
Bcnt := TBcnt;
if (rising_edge(clk) and ce='1' and r1w0='1') then
-- reading
case rga is
when x"0" => rgdo <= PArd;
when x"1" => rgdo <= PBrd;
when x"2" => rgdo <= ddrA;
when x"3" => rgdo <= ddrB;
when x"4" => rgdo <= byte(TAcnt( 7 downto 0));
when x"5" => rgdo <= byte(TAcnt(15 downto 8));
when x"6" => rgdo <= byte(TBcnt( 7 downto 0));
when x"7" => rgdo <= byte(TBcnt(15 downto 8));
when x"D" =>
rgdo <= ir_irq & "00" & ir_ltc;
when x"E" => rgdo <= TActl;
when x"F" => rgdo <= TBctl;
when others => rgdo <= x"FF";
end case;
end if;
if (falling_edge(clk)) then
if (TArun='1') then
if (Acnt=x"0000") then
ir_ltc(src_ATO) <= ir_mask(src_ATO);
if (TAloop='0') then
Acnt := TAltc;
else
TArun <= '0';
end if;
else
Acnt := Acnt - 1;
end if;
end if;
if (TBrun='1') then
if (Bcnt=x"0000") then
ir_ltc(src_BTO) <= ir_mask(src_BTO);
if (TBloop='0') then
Bcnt := TBltc;
else
TBrun <= '0';
end if;
else
Bcnt := Bcnt - 1;
end if;
end if;
if (ce='1' and r1w0='1') then
-- state-changes due to read cycles occur on downclock
case rga is
when x"d" =>
ir_ltc <= "00000";
when others => null;
end case;
end if;
-- writing
if (ce='1' and r1w0='0') then
case rga is
when x"0" => PA <= rgdi;
when x"1" => PB <= rgdi;
when x"2" => ddrA <= rgdi;
when x"3" => ddrB <= rgdi;
when x"4" => TAltc( 7 downto 0) <= unsigned(rgdi);
when x"5" => TAltc(15 downto 8) <= unsigned(rgdi);
when x"6" => TBltc( 7 downto 0) <= unsigned(rgdi);
when x"7" => TBltc(15 downto 8) <= unsigned(rgdi);
when x"D" =>
if (rgdi(7)='1') then
-- setting
for i in 4 downto 0 loop
if (rgdi(i)='1') then
ir_mask(i) <= '1';
end if;
end loop;
else
-- clearing
for i in 4 downto 0 loop
if (rgdi(i)='1') then
ir_mask(i) <= '0';
end if;
end loop;
end if;
when x"E" =>
TActl <= rgdi(7 downto 5) & '0' & rgdi(3 downto 0);
if (rgdi(4)='1') then
Acnt := TAltc;
end if;
when x"F" =>
TBctl <= rgdi(7 downto 5) & '0' & rgdi(3 downto 0);
if (rgdi(4)='1') then
Bcnt := TBltc;
end if;
when others => null;
end case;
end if;
TAcnt <= Acnt;
TBcnt <= Bcnt;
end if;
end process reg_access;
end CIA_impl;
| gpl-3.0 |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9/example_design/dcm_TFT9_exdes.vhd | 1 | 6821 | -- file: dcm_TFT9_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_TFT9_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm_TFT9_exdes;
architecture xilinx of dcm_TFT9_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
-- Need to buffer input clocks that aren't already buffered
signal clk_in1_buf : std_logic;
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component dcm_TFT9 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK9 : out std_logic;
CLK9_180 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Insert BUFGs on all input clocks that don't already have them
----------------------------------------------------------------
clkin1_buf : BUFG
port map
(O => clk_in1_buf,
I => CLK_IN1);
-- Instantiation of the clocking network
----------------------------------------
clknetwork : dcm_TFT9
port map
(-- Clock in ports
CLK_IN1 => clk_in1_buf,
-- Clock out ports
CLK9 => clk_int(1),
CLK9_180 => clk_int(2),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| gpl-3.0 |
gau-veldt/InsideTheBox | SideQuest 0001/clocking.vhd | 1 | 1559 | ----------------------------------------------------------------------------------
--
-- Clocking Example using an MMCM tile in the Zynq
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clocking is port (
led : out std_logic_vector(3 downto 0);
clk_125 : in std_logic
);
end clocking;
architecture clock_impl of clocking is
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk8M : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal clk8M : std_logic;
signal reset : std_logic;
signal locked : std_logic;
subtype u24 is unsigned(23 downto 0);
signal count : u24 := x"000000";
constant count8m : u24 := to_unsigned(4000000,24);
signal slow_clock : std_logic := '0';
begin
clock : clk_wiz_0
port map (
-- Clock out ports
clk8M => clk8M,
-- Status and control signals
reset => reset,
locked => locked,
-- Clock in ports
clk_in1 => clk_125
);
reset <= '0';
divider: process(clk8m) is
variable cur : u24;
begin
if (rising_edge(clk8m)) then
cur := count;
cur := cur + 1;
if (cur >= count8M) then
cur := x"000000";
slow_clock <= not slow_clock;
end if;
count <= cur;
end if;
end process divider;
led(0) <= slow_clock;
end clock_impl;
| gpl-3.0 |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9.vhd | 2 | 6366 | -- file: dcm_TFT9.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1_____9.000______0.000______50.0______373.081____240.171
-- CLK_OUT2_____9.000____180.000______50.0______373.081____240.171
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_TFT9 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK9 : out std_logic;
CLK9_180 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm_TFT9;
architecture xilinx of dcm_TFT9 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm_TFT9,clk_wiz_v3_2,{component_name=dcm_TFT9,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 9,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 50,
CLKOUT1_PHASE => 180.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK9,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK9_180,
I => clkout1);
end xilinx;
| gpl-3.0 |
forflo/yodl | thesis/synthesisShowcase/clusterfuck.vhd | 2 | 1021 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clufu is
port(A : out std_logic;
B : out std_logic;
Co : out std_logic;
sel : in std_logic_vector(1 downto 0);
enable : in std_logic;
enable2 : in std_logic;
clock : in std_logic);
end clufu;
architecture b of clufu is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if A = B then
if not A then
if rising_edge(clock) then
case sel is
when "00" =>
if rising_edge(clock) and enable = '1' and (not enable2 = '0') then
Co <= '0';
end if;
when "01" => Co <= '1';
when "10" => Co <= '1';
when "11" => Co <= '1';
end case;
end if;
end if;
end if;
end process;
end b;
| gpl-3.0 |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_simple.vhd | 1 | 568 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
-- sum <= A xor B xor carryIn;
sum <= '0';
carryOut <= (a and b) or
(b and carryIn) or
(a and carryIn);
fnord <= ('1' or '0') and '1';
end behv;
| gpl-3.0 |
freecores/hilbert_transformer | vhdl/analytic_filter_h_a4.vhd | 1 | 7497 | -- Implementation of Filter H_a4(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
package analytic_filter_h_a4_pkg is
component analytic_filter_h_a4
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a4_pkg;
package body analytic_filter_h_a4_pkg is
end analytic_filter_h_a4_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.fsf_comb_filter_pkg.all;
use work.fsf_pole_filter_pkg.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
use work.real_pole_filter_shift_reg_pkg.all;
use work.complex_fsf_filter_c_90_pkg.all;
use work.complex_fsf_filter_inv_c_m30_m150_pkg.all;
use work.resize_tools_pkg.all;
entity analytic_filter_h_a4 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a4;
architecture analytic_filter_h_a4_arch of analytic_filter_h_a4 is
--signal y : std_logic_vector (data_width-1 downto 0);
--signal x : std_logic_vector (data_width-1 downto 0);
signal data_i_res : std_logic_vector (data_width-1 downto 0);
signal t1 : std_logic_vector (data_width-1 downto 0);
signal t1_res : std_logic_vector (data_width-1 downto 0);
signal t2 : std_logic_vector (data_width-1 downto 0);
signal t3 : std_logic_vector (data_width-1 downto 0);
signal t4 : std_logic_vector (data_width-1 downto 0);
signal t4_res : std_logic_vector (data_width-1 downto 0);
signal t5 : std_logic_vector (data_width-1 downto 0);
signal t5_res : std_logic_vector (data_width-1 downto 0);
signal t6 : std_logic_vector (data_width-1 downto 0);
signal c1_i : std_logic_vector (data_width-1 downto 0);
signal c1_q : std_logic_vector (data_width-1 downto 0);
signal c2_i : std_logic_vector (data_width-1 downto 0);
signal c2_q : std_logic_vector (data_width-1 downto 0);
signal c3_i : std_logic_vector (data_width-1 downto 0);
signal c3_q : std_logic_vector (data_width-1 downto 0);
signal c4_i : std_logic_vector (data_width-1 downto 0);
signal c4_q : std_logic_vector (data_width-1 downto 0);
signal c4_i_res : std_logic_vector (data_width-1 downto 0);
signal c4_q_res : std_logic_vector (data_width-1 downto 0);
signal t1_str : std_logic;
signal t2_str : std_logic;
signal t3_str : std_logic;
signal t4_str : std_logic;
signal t5_str : std_logic;
signal t6_str : std_logic;
signal c1_str : std_logic;
signal c2_str : std_logic;
signal c3_str : std_logic;
signal c4_str : std_logic;
begin
data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),2)),data_width);
real_pole_filter_1 : real_pole_filter_shift_reg
generic map (
data_width => data_width,
internal_data_width => data_width,
shift_value => 1
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => data_i_res,
data_str_i => data_str_i,
data_o => t1,
data_str_o => t1_str
);
t1_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(t1),2)),data_width);
real_pole_filter_2 : real_pole_filter_shift_reg
generic map (
data_width => data_width,
internal_data_width => data_width,
shift_value => 1
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t1_res,
data_str_i => t1_str,
data_o => t2,
data_str_o => t2_str
);
comb_stage1 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t2,
data_str_i => t2_str,
data_o => t3,
data_str_o => t3_str
);
comb_stage2 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t3,
data_str_i => t3_str,
data_o => t4,
data_str_o => t4_str
);
c_0_180_filter1 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t4,
-- data_i => t4_res,
data_str_i => t4_str,
data_o => t5,
data_str_o => t5_str
);
c_0_180_filter2 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
-- data_i => t5_res,
data_i => t5,
data_str_i => t5_str,
data_o => t6,
data_str_o => t6_str
);
complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => t6,
data_q_i => (others => '0'),
data_str_i => t6_str,
data_i_o => c1_i,
data_q_o => c1_q,
data_str_o => c1_str
);
complex_fsf_filter_c_90_2 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c1_i,
data_q_i => c1_q,
data_str_i => c1_str,
data_i_o => c2_i,
data_q_o => c2_q,
data_str_o => c2_str
);
complex_fsf_filter_inv_c_m30_m150_1 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c2_i,
data_q_i => c2_q,
data_str_i => c2_str,
data_i_o => c3_i,
data_q_o => c3_q,
data_str_o => c3_str
);
complex_fsf_filter_inv_c_m30_m150_2 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c3_i,
data_q_i => c3_q,
data_str_i => c3_str,
data_i_o => c4_i,
data_q_o => c4_q,
data_str_o => c4_str
);
data_i_o <= c4_i;
data_q_o <= c4_q;
data_str_o <= c4_str;
end analytic_filter_h_a4_arch; | gpl-3.0 |
freecores/hilbert_transformer | vhdl/analytic_filter_tb.vhd | 1 | 65741 | -- Testbench for Filters H_a1-4(z)
-- Uses a sine sweep as stimuli
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.analytic_filter_h_a1_pkg.all;
use work.analytic_filter_h_a2_pkg.all;
use work.analytic_filter_h_a3_pkg.all;
use work.analytic_filter_h_a4_pkg.all;
entity analytic_filter_tb is
generic(
clk_period : time := 10 ns;
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7; --delay of hilbert filter
data_width : integer := 16
);
end analytic_filter_tb;
architecture analytic_filter_tb_arch of analytic_filter_tb is
signal x : std_logic_vector(input_data_width-1 downto 0) := (others => '0'); --input
signal i,q : std_logic_vector(output_data_width-1 downto 0); --output
signal i_real,q_real : real;
signal x_real : real;
signal anal_data_i : std_logic_vector(input_data_width-1 downto 0);
signal clk : std_logic := '0';
signal rst : std_logic;
type filter_in_table is array (0 to 1034) of std_logic_vector(15 downto 0);
-- sine sweep
constant filter_in_force : filter_in_table :=
(
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F0D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"769F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7416"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7116"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6D93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"598B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"434B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"30CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2679"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"03D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA82"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D098"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C3D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B781"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ABCC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0F5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"882C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8353"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8092"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8220"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A450"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B334"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C445"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D731"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"00D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"167D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"403C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6336"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79DF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7205"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5174"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B2D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EAFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CFCB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B6A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8012"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D0C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1110"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3124"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E28"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7359"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"220B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B68F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"842D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9413"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AEA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F985"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"227F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6687"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7793"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"615E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"15ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E947"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A66"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A483"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2936"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"534A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"719F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B9C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D835"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8C4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8940"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A6C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"091C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D09"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"664B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6523"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"035B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E1D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9B7C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C958"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"030C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"690F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"788B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"570B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"217E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8896"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8107"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0791"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"44AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E20"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FF51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"906C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C4DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"489A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74CD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6387"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A59D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8327"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8789"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"707C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"644F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FB4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C665"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5729"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7596"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"427D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F660"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8977"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BD0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B06"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A1D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9488"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D62B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5AED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E39"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BAE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8655"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C1B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"179A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"60C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1349"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85C6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"237F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E59"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5081"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F944"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EFB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C29A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8602"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D4E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"352D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7775"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2F64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8916"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D217"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3543"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7890"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C26F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"843C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F00"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"61D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8033"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"14EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC1A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"859C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED52"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5449"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E7B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8906"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D8FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"45C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A53"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9396"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"875D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D710"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4658"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E908"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E756"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"837D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E0B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"750F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8172"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3EB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"510B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0C6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"713E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"08E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E571"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"814B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A26"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"396C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C308"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4281"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C529"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"467D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B354"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8155"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D40C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5535"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A08C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8849"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1D08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CB8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5075"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C953"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C86D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5095"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"185B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"980F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0BEE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5727"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"56B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2883"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FB5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA56"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FCD2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"75EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"592F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8047"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DA9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6570"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E5F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C370"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7649"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F920"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"850B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B641"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8770"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B187"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B487"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7879"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F96B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"583C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E66D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"805A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D490"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6885"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4CEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E69F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E264"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7383"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4DE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC86"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"26BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BBB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8978"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"582A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B19A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9051"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DA6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F580"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8031"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E808"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"798A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"374F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"666D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B2B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8002"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2138"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FB2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5952"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"957C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"40F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8951"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2ABE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DEC7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8351"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1905"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E31"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EDC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"803D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F9D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8029"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DE3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85E6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2B5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"766B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ED4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B229"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA1C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"704A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"873C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E01A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0912"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8009"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0F96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4244"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6557"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3584"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F357"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A999"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8484"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E22C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46A6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C6E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C98F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8128"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA1E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A57"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1CBE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7360"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B049"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"800E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"827E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"389D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6017"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"951D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D895"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E231"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9084"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C5B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE23"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4BEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0232"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B0C1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"599D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E00E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C54C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"32A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8007"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AB6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE54"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7671"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADC3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9454"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BBC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8598"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8028"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CF1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"886B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BDC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"91A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F8BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9BB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E834"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D22E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EC8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B630"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B696"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DFEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EE2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7478"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"946A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"001F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6B3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ACE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"157E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8350"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2D85"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"499B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8004"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FAE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8339"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5ED9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FC9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8F2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72B0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A58F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C59B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A306"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"89AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4EC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1EF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B44"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"71A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E742"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B180"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E35A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7293"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"22E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"480A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D32"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C20E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D464"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"772F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2019"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A616"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F287"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6601"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81BE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"931B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DDA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"851A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23B5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B5C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFB9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E0E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1468"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FC99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5935"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6382"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA22"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D72"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B13A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA2E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5754"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80E2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AF2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE14"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5063"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"004A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3703"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1C2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"98B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2CF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1858"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"911C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"209A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97C4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"94C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"31B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"186F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FAED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BEED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7243"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D485"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E527"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8411"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAC2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"17A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2C5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9C79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"895A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EEF4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CF8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8166"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7795"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1820"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8390"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EF30"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E46"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D97E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"878B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D64A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5955"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"883E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E51D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"912D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"614C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C747"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0762"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2AC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4D63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DBF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2933"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02E3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1BD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"53D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8197"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"34D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E456"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4142"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E55"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"96D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7928"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2524"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FB36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC0C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"68E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5992"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F19F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C016"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"553A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9949"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8148"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"908B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6240"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D45A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC9E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"275F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A64C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"663C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FAD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"77E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8307"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F94"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"861D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7417"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4F48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ECCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0732"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB3A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FA9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B8B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0));
begin
analytic_filter_inst : analytic_filter_h_a4 --change this to analytic_filter_h_ax to test other filters
generic map(
-- input_data_width => input_data_width, --uncomment this for analytic_filter_h_a1
-- output_data_width => output_data_width, --uncomment this for analytic_filter_h_a1
-- filter_delay_in_clks => filter_delay_in_clks --uncomment this for analytic_filter_h_a1
data_width => data_width --uncomment this for analytic_filter_h_a3-4
)
port map(
rst_i => rst,
clk_i => clk,
data_str_i => '1',
data_i => anal_data_i,
data_i_o => i,
data_q_o => q,
data_str_o => open
);
clk <= not clk after clk_period/2;
rst <= '1', '0' after 20 ns;
--choose scaling, not all filters have the full dynamic range
anal_data_i <= x;
-- anal_data_i <= std_logic_vector(shift_right(signed(x),1));
-- anal_data_i <= std_logic_vector(shift_right(signed(x),2));
x_real <= real(to_integer(signed(x)))/ 2.0**(input_data_width-1);
i_real <= real(to_integer(signed(i)))/ 2.0**(output_data_width-1);
q_real <= real(to_integer(signed(q)))/ 2.0**(output_data_width-1);
--choose imput stimuli:
-- x <= x"7FFF", x"0000" after 40 ns; --impulse response
-- x <= x"7FFF"; --step response
filter_in_gen: process
begin
x <= filter_in_force(0);
wait for clk_period*3;
x <= filter_in_force(1);
wait for clk_period;
for n in 0 to 1034 loop
if n + 2 <= 1034 then
x <= filter_in_force(n + 2);
end if;
wait for clk_period;
end loop;
assert false report "**** test complete. ****" severity note;
end process filter_in_gen;
end analytic_filter_tb_arch; | gpl-3.0 |
forflo/yodl | vhdlpp/vhdl_testfiles/block_header_decls.vhd | 2 | 697 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end adder;
architecture behv of adder is
signal result : std_logic_vector(n downto 0);
begin
fnord : block begin
-- the 3rd bit should be carry
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
end block fnord;
end behv;
| gpl-3.0 |
sneakypete81/atom-vhdl-entity-converter | spec/fixture/component/adder_indent_tab.vhd | 1 | 227 | component add
generic (
WIDTH : integer := 3;
HEIGHT : integer := 2
);
port (
clk : in std_logic;
in : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0)
);
end component add;
| gpl-3.0 |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_dff_simple.vhd | 1 | 420 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
if rising_edge(clock) then
A <= '0';
end if;
end process;
end behv;
| gpl-3.0 |
freecores/hilbert_transformer | vhdl/const_delay.vhd | 1 | 2593 | -- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package const_delay_pkg is
component const_delay
generic(
data_width : integer;
delay_in_clks : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end const_delay_pkg;
package body const_delay_pkg is
end const_delay_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity const_delay is
generic(
data_width : integer := 16;
delay_in_clks : integer := 10
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end const_delay;
architecture const_delay_arch of const_delay is
type register_line is array(0 to delay_in_clks-1) of std_logic_vector(data_width-1 downto 0);
type data_str_line is array(0 to delay_in_clks-1) of std_logic;
signal data_int : register_line;
signal data_str_int : data_str_line;
begin
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to delay_in_clks-1 loop
data_int(i) <= (others => '0');
data_str_int(i) <= '0';
end loop;
elsif clk_i'EVENT and clk_i = '1' then
data_int(0) <= data_i;
data_str_int(0) <= data_str_i;
for i in 0 to delay_in_clks-2 loop
data_int(i+1) <= data_int(i);
data_str_int(i+1) <= data_str_int(i);
end loop;
end if;
end process;
data_o <= data_int(delay_in_clks-1);
data_str_o <= data_str_int(delay_in_clks-1);
end const_delay_arch; | gpl-3.0 |
sneakypete81/atom-vhdl-entity-converter | spec/fixture/instance/adder_no_generics.vhd | 1 | 78 | add_i : add
port map (
clk => clk,
in => in,
output => output
);
| gpl-3.0 |
SoCdesign/EHA | RTL/Immortal_Chip/shift_register.vhd | 1 | 1051 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity shift_register is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end;
architecture behavior of shift_register is
signal shift_register_mem_out : std_logic_vector(REG_WIDTH-1 downto 0);
begin
process (clk, reset)
begin
if reset = '0' then
shift_register_mem_out <= (others => '0');
elsif clk'event and clk = '1' then
if shift = '1' then
shift_register_mem_out <= shift_register_mem_out (REG_WIDTH-2 downto 0) & '0';
else
shift_register_mem_out <= data_in or shift_register_mem_out;
end if;
end if;
end process;
data_out_parallel <= shift_register_mem_out;
data_out_serial <= shift_register_mem_out (REG_WIDTH-2);
end; | gpl-3.0 |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/new/PWM_Controller.vhd | 1 | 1394 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/16/2017 12:12:06 PM
-- Design Name:
-- Module Name: PWM_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PWM_Controller is
port(
iadc_sel : in std_logic;
iSW : in std_logic;
iData : in std_logic_vector(7 downto 0);
--iData2 : in std_logic_vector(7 downto 0);
oData : out std_logic_vector(7 downto 0)
);
end PWM_Controller;
architecture Behavioral of PWM_Controller is
begin
process(iadc_sel,iSW)
begin
if iadc_sel = '0' and iSW = '0' then
oData <= iData;
elsif iadc_sel = '1' and iSW = '1' then
oData <= iData;
else
oData <= "00000000";
end if;
end process;
end Behavioral;
| gpl-3.0 |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/Fault_injector.vhd | 13 | 1277 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; | gpl-3.0 |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/FIFO.vhd | 1 | 5396 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of FIFO is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(1 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal CTS_in, CTS_out: std_logic;
type FIFO_Mem_type is array (0 to 3) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_Mem : FIFO_Mem_type ;
TYPE STATE_TYPE IS (IDLE, READ_DATA);
SIGNAL HS_state_out,HS_state_in : STATE_TYPE;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
-- previous
-- router
-- -- ------------------------------------------
-- | | |
-- TX|--------->| RX Data_out|----> goes to Xbar and LBDR
-- | | |
-- RTS|--------->| DRTS FIFO read_en|<---- Comes from Arbiters (N,E,W,S,L)
-- | | (N,E,W,S,L)|
-- DCTS|<---------| CTS |
-- -- ------------------------------------------
--------------------------------------------------------------------------------------------
-- Hand shake protocol!
--
-- |<-Valid->|
-- | Data |
-- _____ _________ ______
-- RX _____X_________X______
-- DRTS _____|'''''''''|_____
-- CTS __________|''''|_______
--
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
HS_state_out <= IDLE;
read_pointer <= "00";
write_pointer <= "00";
CTS_out<='0';
FIFO_Mem<= (others => (others=>'0'));
elsif clk'event and clk = '1' then
HS_state_out <= HS_state_in;
write_pointer <= write_pointer_in;
if write_en = '1' then
--write into the memory
FIFO_Mem(conv_integer(write_pointer)) <= RX;
end if;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
Data_out <= FIFO_Mem(conv_integer(read_pointer));
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
CTS <= CTS_out;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer+1;
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer+1;
else
read_pointer_in <= read_pointer;
end if;
end process;
process(HS_state_out, full, DRTS, CTS_out) begin
case(HS_state_out) is
when IDLE =>
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_state_in <= READ_DATA;
CTS_in <= '1';
write_en <= '1';
else
HS_state_in <= IDLE;
CTS_in <= '0';
write_en <= '0';
end if;
when others => -- READ_DATA
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_state_in <= READ_DATA;
CTS_in <= '1';
write_en <= '1';
else
HS_state_in <= IDLE;
CTS_in <= '0';
write_en <= '0';
end if;
end case ;
end process;
process(write_pointer, read_pointer)begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
if write_pointer = read_pointer - 1 then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_scheduler.vhd | 1 | 7784 | --------------------------------------------------------------------------------
-- Scheduler for running 5 concurrent SHA1 calcs and outputting sequentially
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_scheduler is
port(
clk_i : in std_ulogic;
load_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 31)
);
end sha1_scheduler;
architecture RTL of sha1_scheduler is
component sha1_load
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_w_o : out w_input
);
end component;
component sha1_process_input
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end component;
component sha1_process_buffer
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end component;
signal w_load: w_input;
signal w_processed_input1: w_full;
signal w_processed_input2: w_full;
signal w_processed_input3: w_full;
signal w_processed_input4: w_full;
signal w_processed_input5: w_full;
signal w_processed_new: std_ulogic;
signal w_processed_buffer: w_output;
signal w_processed_buffer1: w_output;
signal w_processed_buffer2: w_output;
signal w_processed_buffer3: w_output;
signal w_processed_buffer4: w_output;
signal w_processed_buffer5: w_output;
signal w_buffer_valid1: std_ulogic;
signal w_buffer_valid2: std_ulogic;
signal w_buffer_valid3: std_ulogic;
signal w_buffer_valid4: std_ulogic;
signal w_buffer_valid5: std_ulogic;
signal w_pinput: w_input;
signal latch_pinput: std_ulogic_vector(0 to 4);
signal w_processed_valid: std_ulogic_vector(0 to 4);
signal i : integer range 0 to 16;
signal i_mux : integer range 0 to 4;
-- synthesis translate_off
signal test_sha1_process_input_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer0_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer_o : std_ulogic_vector(0 to 31);
signal test_sha1_load_o : std_ulogic_vector(0 to 31);
-- synthesis translate_on
begin
LOAD1: sha1_load port map (clk_i,rst_i,dat_i,sot_in,w_load);
--Alt: Use a generate statement
PINPUT1: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(0),w_processed_input1,w_processed_valid(0));
PBUFFER1: sha1_process_buffer port map (clk_i,rst_i,w_processed_input1,w_processed_valid(0),w_processed_valid(0),w_processed_buffer1,w_processed_buffer1,w_buffer_valid1);
PINPUT2: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(1),w_processed_input2,w_processed_valid(1));
PBUFFER2: sha1_process_buffer port map (clk_i,rst_i,w_processed_input2,w_processed_valid(1),w_processed_valid(1),w_processed_buffer2,w_processed_buffer2,w_buffer_valid2);
PINPUT3: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(2),w_processed_input3,w_processed_valid(2));
PBUFFER3: sha1_process_buffer port map (clk_i,rst_i,w_processed_input3,w_processed_valid(2),w_processed_valid(2),w_processed_buffer3,w_processed_buffer3,w_buffer_valid3);
PINPUT4: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(3),w_processed_input4,w_processed_valid(3));
PBUFFER4: sha1_process_buffer port map (clk_i,rst_i,w_processed_input4,w_processed_valid(3),w_processed_valid(3),w_processed_buffer4,w_processed_buffer4,w_buffer_valid4);
PINPUT5: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(4),w_processed_input5,w_processed_valid(4));
PBUFFER5: sha1_process_buffer port map (clk_i,rst_i,w_processed_input5,w_processed_valid(4),w_processed_valid(4),w_processed_buffer5,w_processed_buffer5,w_buffer_valid5);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
latch_pinput <= "00000";
i <= 0;
--Todo: start from 0 after testing
i_mux <= 0;
for x in 0 to 15 loop
w_pinput(x) <= "00000000000000000000000000000000";
end loop;
else
if i = 15 then
case i_mux is
when 0 => latch_pinput <= "10000";
when 1 => latch_pinput <= "01000";
when 2 => latch_pinput <= "00100";
when 3 => latch_pinput <= "00010";
when 4 => latch_pinput <= "00001";
end case;
w_pinput <= w_load;
i <= 0;
--i <= i + 1;
if i_mux = 4 then
i_mux <= 0;
else
i_mux <= i_mux + 1;
end if;
else
latch_pinput <= "00000";
i <= i + 1;
end if;
end if;
--Alt: Consider other conditionals
if w_processed_valid(0) = '1' then
w_processed_buffer <= w_processed_buffer1;
elsif w_processed_valid(1) = '1' then
w_processed_buffer <= w_processed_buffer2;
elsif w_processed_valid(2) = '1' then
w_processed_buffer <= w_processed_buffer3;
elsif w_processed_valid(3) = '1' then
w_processed_buffer <= w_processed_buffer4;
elsif w_processed_valid(4) = '1' then
w_processed_buffer <= w_processed_buffer5;
end if;
end if;
end process;
dat_1_o <= w_pinput(15);
-- synthesis translate_off
test_sha1_process_input_o <= w_processed_input1(16);
test_sha1_process_buffer0_o <= w_processed_buffer1(0);
test_sha1_process_buffer_o <= w_processed_buffer(0);
test_sha1_load_o <= w_load(15);
-- synthesis translate_on
end RTL; | gpl-3.0 |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_1/xbar.vhd | 4 | 1004 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= North_in;
when "00010" =>
Data_out <= East_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= South_in;
when others =>
Data_out <= Local_in;
end case;
end process;
end; | gpl-3.0 |
bruskajp/EE-316 | Project4/Vivado_NexysBoard/craddockEE316/craddockEE316.srcs/sources_1/imports/testFolder/multiplex.vhd | 1 | 786 | -- file: multiplex.vhd
-------------------------------------
-- n bit multiplexer
-- Shauna Rae
-- October 18, 1999
library ieee;
use ieee.std_logic_1164.all;
--define the entity of multiplex
entity multiplex is
generic (data_width : positive := 16);
port(select_line: in std_logic;
in_a, in_b: in std_logic_vector(data_width-1 downto 0);
output : out std_logic_vector(data_width-1 downto 0));
end multiplex;
architecture basic of multiplex is
begin
-- define a process which is dependent on select_line
multiplex_behaviour: process --(select_line)
begin
if select_line = '0' then -- select line zero select in_a
output <= in_a;
-- select line one select in_a as output
else
output <= in_b;
end if;
end process;
end basic; | gpl-3.0 |
Ana06/function-graphing-FPGA | KbdTxData.vhd | 2 | 10141 | ----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
-- http://www.computer-engINeerINg.org/ps2protocol/
--
-- 1) BrINg the Clock lINe low for at least 100 microseconds.
-- 2) BrINg the Data lINe low.
-- 3) Release the Clock lINe.
-- 4) Wait for the device to brINg the Clock lINe low.
-- 5) Set/reset the Data lINe to Tx_en the first data bit
-- 6) Wait for the device to brINg Clock high.
-- 7) Wait for the device to brINg Clock low.
-- 8) Repeat steps 5-7 for the other seven data bits and the parity bit
-- 9) Release the Data lINe.
-- 10) Wait for the device to brINg Data low.
-- 11) Wait for the device to brINg Clock low.
-- 12) Wait for the device to release Data and Clock
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity KbdTxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
END KbdTxData;
ARCHITECTURE Behavioral OF KbdTxData IS
TYPE state_type IS (reset,INit, clkLow,
startSEND,startbit,
bitshIFt,bitsEND,
parity,tempo_parity,
stopbit,akn,
DevRelease,ENDFSM);
SIGNAL state, next_state: state_type ;
SIGNAL cnt : std_logic_vector(12 DOWNTO 0):=(OTHERS=>'0');
SIGNAL startCount : std_logic:='0';
SIGNAL ENDCount : std_logic:='0';
SIGNAL shIFt : std_logic:='0';
SIGNAL ENDshIFt : std_logic:='0';
SIGNAL shIFtcnt : std_logic_vector(2 DOWNTO 0):=(OTHERS=>'0');
SIGNAL dataReg : std_logic_vector(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL INt_busy : std_logic;
SIGNAL INt_T_Clk : std_logic;
SIGNAL INt_T_Data : std_logic;
SIGNAL INt_KbdData : std_logic;
SIGNAL INt_KbdClk : std_logic;
BEGIN
Sequential: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
state <= INit;
ELSIF (clk='1' and clk'Event) THEN
state <= next_state;
END IF;
END PROCESS;
-- Counter
PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
cnt <= (OTHERS=>'0');
ENDCount <= '0';
ELSIF (clk = '1' and clk'Event) THEN
ENDCount <= '0';
cnt <= (OTHERS=>'0');
IF(startCount = '1') THEN
cnt <= cnt+'1';
IF (cnt = X"1388") THEN -- 100 us
cnt <= (OTHERS=>'0');
ENDCount <= '1';
END IF;
END IF;
END IF;
END PROCESS;
Dataproc:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
dataReg <= X"FF";
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (clk = '1' and clk'Event) THEN
IF (state = INit) THEN
dataReg <= data;
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (shIFtcnt = "111") THEN
shIFtcnt <= "000";
ENDshIFt <= '1';
ELSIF (shIFt = '1') THEN
ENDshIFt <= '0';
shIFtcnt <= shIFtcnt + '1';
dataReg <= dataReg(0) & dataReg(7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
CntrlFSM : PROCESS (state, kbd_clkf, kbd_dataf,ENDCount,Tx_en,ENDshIFt)
BEGIN
CASE state IS
WHEN reset =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= clkLow;
WHEN INit =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (Tx_en = '1') THEN
next_state <= clkLow;
ELSIF (Tx_en='0') THEN
next_state <= INit;
END IF;
WHEN clkLow =>
INt_busy <= '1';
INt_T_Clk <= '0';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '0';
IF (ENDCount = '1') THEN
startCount <= '0';
next_state <= startSEND;
ELSE
startCount <= '1';
next_state <= clkLow;
END IF;
WHEN startSEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= startbit;
ELSE
next_state <= startSEND;
END IF;
WHEN startbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= bitshIFt;
ELSE
next_state <= startbit;
END IF;
WHEN bitshIFt =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <='0';
IF (kbd_clkf = '1') THEN
next_state <= bitsEND;
ELSE
next_state <= bitshIFt;
END IF;
WHEN bitsEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <= '0';
IF (kbd_clkf = '1') THEN
shIFt <= '0';
next_state <= bitsEND;
ELSIF (ENDshIFt = '1') THEN
shIFt <= '0';
next_state <= parity;
ELSE
shIFt <= '1';
next_state <= bitshIFt;
END IF;
WHEN parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= tempo_parity;
ELSE
next_state <= parity;
END IF;
WHEN tempo_parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= stopbit;
ELSE
next_state <= tempo_parity;
END IF;
WHEN stopbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF kbd_clkf = '1' THEN
next_state <= akn;
ELSE
next_state <= stopbit;
END IF;
WHEN Akn =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF (kbd_dataf = '0') THEN
next_state <= DevRelease;
ELSE
next_state <= Akn;
END IF;
WHEN DevRelease =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (kbd_dataf = '1') THEN
next_state <= ENDFSM;
ELSE
next_state <= DevRelease;
END IF;
WHEN ENDFSM =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= INit;
END case;
END PROCESS;
OUTput: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
busy <= '0';
T_Clk <= '1';
T_Data <= '1';
KbdData <= '1';
KbdClk <= '1';
ELSIF (clk='1' and clk'Event) THEN
busy <= INt_busy;
T_Clk <= INt_T_Clk;
T_Data <= INt_T_Data;
KbdData <= INt_KbdData;
KbdClk <= INt_KbdClk;
END IF;
END PROCESS;
END Behavioral;
| gpl-3.0 |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/NI_channel.vhd | 1 | 5785 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity NI_channel is
generic (
DATA_WIDTH: integer := 32;
NI_DEPTH: integer:=16
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
TX: out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS, DCTS: in std_logic;
RTS,CTS: out std_logic
);
end NI_channel;
architecture behavior of NI_channel is
signal read_pointer, write_pointer, read_pointer_in: std_logic_vector(integer(ceil(log2(real(NI_DEPTH))))-1 downto 0);
signal full, empty: std_logic;
signal CB_write: std_logic;
signal CTS_in, CTS_out: std_logic;
type FIFO_Mem_type is array (0 to NI_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_Mem : FIFO_Mem_type ;
TYPE READ_STATE_TYPE IS (IDLE, READ_DATA);
SIGNAL HS_read_state_out, HS_read_state_in : READ_STATE_TYPE;
TYPE WRITE_STATE_TYPE IS (IDLE, WRITE_DATA);
SIGNAL HS_write_state_out,HS_write_state_in, HS_write_state_next : WRITE_STATE_TYPE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
--
-- PE router
-- -- ---- ---------------------------------- -- --
-- RX |<---------| TX RX |<---- | TX_L_R_?
-- DRTS|<---------| RTS DRTS |<---- | RTS_L_R_?
-- CTS |--------->| DCTS CTS |----> | DCTS_L_R_?
-- -- ---- ---------------------------------- -- --
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
process (clk, reset)begin
if reset = '0' then
HS_read_state_out <= IDLE;
HS_write_state_out <= IDLE;
read_pointer <= (others=>'0');
RTS_FF <= '0';
write_pointer <= (others=>'0');
FIFO_Mem <= (others => (others=>'0'));
CTS_out<= '0';
elsif clk'event and clk = '1' then
RTS_FF <= RTS_FF_in;
HS_read_state_out <= HS_read_state_in;
HS_write_state_out <= HS_write_state_next;
if (CB_write = '1' and full = '0')then
--write into the memory
-- update the write pointer
FIFO_Mem(conv_integer(write_pointer)) <= RX;
write_pointer <= write_pointer+ 1;
end if;
read_pointer <= read_pointer_in;
CTS_out<=CTS_in;
end if;
end process;
-- anything below here is pure combinational
TX <= FIFO_Mem(conv_integer(read_pointer));
RTS <= RTS_FF;
CTS <= CTS_out;
process(RTS_FF, empty, DCTS, read_pointer)begin
if (RTS_FF = '1' and DCTS='1' and empty = '0') then
read_pointer_in <= read_pointer+1;
else
read_pointer_in <= read_pointer;
end if;
end process;
process(RTS_FF, DCTS, HS_write_state_out, HS_write_state_in)begin
if RTS_FF = '1' and DCTS = '0' then
HS_write_state_next <= HS_write_state_out;
else
HS_write_state_next <= HS_write_state_in;
end if;
end process;
process(HS_write_state_out, RTS_FF, DCTS, empty)begin
if HS_write_state_out = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if empty = '0' then
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
else
RTS_FF_in <= '0';
end if;
end if ;
end process;
-- read from outside
process(HS_read_state_out, full, DRTS, CTS_out) begin
case(HS_read_state_out) is
when IDLE =>
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_read_state_in <= READ_DATA;
CTS_in <= '1';
CB_write <= '1';
else
HS_read_state_in <= IDLE;
CTS_in <= '0';
CB_write <= '0';
end if;
when others => -- READ_DATA
if CTS_out = '0' and DRTS = '1' and full ='0' then
HS_read_state_in <= READ_DATA;
CTS_in <= '1';
CB_write <= '1';
else
HS_read_state_in <= IDLE;
CTS_in <= '0';
CB_write <= '0';
end if;
end case ;
end process;
-- write to outside
process(HS_write_state_out, empty) begin
case(HS_write_state_out) is
when IDLE =>
if empty ='0' then
HS_write_state_in <= WRITE_DATA;
else
HS_write_state_in <= IDLE;
end if;
when others => -- WRITE_DATA
if empty ='0' then
HS_write_state_in <= WRITE_DATA;
else
HS_write_state_in <= IDLE;
end if;
end case ;
end process;
process(write_pointer, read_pointer)begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
if write_pointer = read_pointer - 1 then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 |
bruskajp/EE-316 | Project5/top_level.vhd | 1 | 20357 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 01:36:15 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
port(
clk_100mhz : in STD_LOGIC;
save_button_input : in STD_LOGIC;
ps2_clk : in std_logic;
ps2_data : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
tx : inout std_logic;
rx : inout std_logic;
potX : inout std_logic_vector(7 downto 0);
potY : inout std_logic_vector(7 downto 0);
VGA_H_SYNC : out std_logic;
VGA_V_SYNC : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0)
--usb_bt_input : in STD_LOGIC;
--keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
--poten_x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
--poten_y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
--usb_bt_output : out STD_LOGIC;
--lcd_output : out STD_LOGIC_VECTOR(7 downto 0); -- PUT BACK
--vga_output : out STD_LOGIC_VECTOR(11 downto 0);
--tricolor_lcd_output : out STD_LOGIC_VECTOR(11 downto 0); -- PUT BACK
);
end top_level;
architecture Behavioral of top_level is
-- RAM component
component blk_mem_gen_0
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR(16 downto 0);
dina : in STD_LOGIC_VECTOR(11 downto 0);
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(16 downto 0);
doutb : out STD_LOGIC_VECTOR(11 downto 0)
);
end component;
-- Game logic component
component game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end component;
-- USB/Bluetooth clock divider component
component clock_divider is
generic(count_max : INTEGER := 2); -- CHANGE VALUE
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
component sys_clk IS
GENERIC (
CONSTANT REF_CLK : integer := 100000000; -- 100.0 MHz
CONSTANT OUT_CLK : integer := 25000000);
PORT (
SIGNAL oCLK : INOUT std_logic;
SIGNAL iCLK : IN std_logic;
SIGNAL iRST : IN std_logic);
END component;
component vga_sync IS
GENERIC (
H_SYNC_TOTAL : INTEGER := 800;
H_PIXELS : INTEGER := 640;
H_SYNC_START : INTEGER := 659;
H_SYNC_WIDTH : INTEGER := 96;
V_SYNC_TOTAL : INTEGER := 525;
V_PIXELS : INTEGER := 480;
V_SYNC_START : INTEGER := 493;
V_SYNC_WIDTH : INTEGER := 2;
H_START : INTEGER := 699
);
PORT (
iCLK : IN STD_LOGIC;
iRST_N : IN STD_LOGIC;
iRed : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
iGreen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
iBlue : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
px : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
py : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_H_SYNC : OUT STD_LOGIC;
VGA_V_SYNC : OUT STD_LOGIC
--VGA_BLANK : OUT STD_LOGIC
);
END component;
component vga_out is
PORT ( iCLK : in STD_LOGIC;
px : in STD_LOGIC_VECTOR(9 DOWNTO 0);
py : in STD_LOGIC_VECTOR(9 DOWNTO 0);
potX : in STD_LOGIC_VECTOR(7 DOWNTO 0);
potY : in STD_LOGIC_VECTOR(7 DOWNTO 0);
color : in STD_LOGIC_VECTOR(11 downto 0);
red : out STD_LOGIC_VECTOR(3 DOWNTO 0);
green : out STD_LOGIC_VECTOR(3 DOWNTO 0);
blue : out STD_LOGIC_VECTOR(3 DOWNTO 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end component;
component i2c_user_logic is
Port (
clk : in std_logic;
busy : in std_logic;
data_rd : in std_logic_vector(7 downto 0);
ienable : in std_logic;
i2c_ena : out std_logic;
i2c_addr : out std_logic_vector(6 downto 0);
i2c_rw : out std_logic;
reset_n : out std_logic;
i2c_data_wr : out std_logic_vector(7 downto 0);
valid : out std_logic;
data16bit : out std_logic_vector(15 downto 0)
);
end component;
component i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 9600); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
end component;
component ps2_keyboard_to_ascii IS
GENERIC(
clk_freq : INTEGER := 100_000_000; --system clock frequency in Hz
ps2_debounce_counter_size : INTEGER := 9); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock input
ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard
ascii_new : OUT STD_LOGIC; --output flag indicating new ASCII value
ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --ASCII value
END component;
component uart is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
tx_out :out std_logic;
tx_empty :out std_logic;
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic
);
end component;
-- RAM signals
signal ram_addrb : STD_LOGIC_VECTOR(16 downto 0);
signal ram_doutb : STD_LOGIC_VECTOR(11 downto 0);
-- Game logic signals
signal gl_reset : STD_LOGIC;
signal gl_screen_size : STD_LOGIC;
signal gl_pen_width : STD_LOGIC_VECTOR(2 downto 0);
signal gl_x_pos, gl_y_pos : STD_LOGIC_VECTOR(7 downto 0);
signal gl_tricolor_led : STD_LOGIC_VECTOR(11 downto 0);
signal gl_usb_bt : STD_LOGIC_VECTOR(15 downto 0);
signal gl_color : STD_LOGIC_VECTOR(23 downto 0);
signal gl_ram_we : STD_LOGIC_VECTOR(0 downto 0);
signal gl_ram_val : STD_LOGIC_VECTOR(11 downto 0);
signal gl_ram_addr : STD_LOGIC_VECTOR(16 downto 0);
-- Potentionmeter interface signals
signal poten_x_pos : STD_LOGIC_VECTOR(7 downto 0);
signal poten_y_pos : STD_LOGIC_VECTOR(7 downto 0);
-- USB/Bluetooth signals
signal usb_bt_input_vector : STD_LOGIC_VECTOR(7 downto 0);
signal usb_bt_output_vector : STD_LOGIC_VECTOR(7 downto 0);
-- USB/Bluetooth clock divider signals
signal usb_bt_clk : STD_LOGIC;
-- Ryan's shit
signal reset_n : std_logic;
signal px : std_logic_vector(9 downto 0);
signal py : std_logic_vector(9 downto 0);
signal red : std_logic_vector(3 downto 0);
signal green : std_logic_vector(3 downto 0);
signal blue : std_logic_vector(3 downto 0);
signal i2cClk : std_logic;
signal i2c_ena : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_rw : std_logic;
signal i2c_reset : std_logic;
signal i2c_data_wr : std_logic_vector(7 downto 0);
signal vgaClk : std_logic;
signal busy : std_logic;
signal ack_error : std_logic;
signal ascii_code : std_logic_vector(6 downto 0);
signal full_ascii_code : std_logic_vector(7 downto 0);
signal ascii_new : std_logic;
signal valid : std_logic;
signal data_rd : std_logic_vector(7 downto 0);
signal data16bit : std_logic_vector(15 downto 0);
signal uartClk : std_logic;
signal uartClkEna: std_logic;
signal rx_data : std_logic_vector(7 downto 0);
begin
-- RAM port map
ram : blk_mem_gen_0
port map (
clka => clk_100mhz,
wea => gl_ram_we,
addra => gl_ram_addr,
dina => gl_ram_val,
clkb => clk_100mhz,
addrb => ram_addrb,
doutb => ram_doutb
);
full_ascii_code <= "0" & ascii_code;
-- Game logic port map
gl : game_logic
port map(
clk => clk_100mhz,
usb_bt_clk => usb_bt_clk,
save_button_input => save_button_input,
keyboard_input => full_ascii_code,
x_pos_input => potX,
y_pos_input => potY,
usb_bt_input => usb_bt_input_vector,
reset_output => gl_reset,
screen_size_output => gl_screen_size,
pen_width_output => gl_pen_width,
x_pos_output => gl_x_pos,
y_pos_output => gl_y_pos,
color_output => gl_color,
tricolor_led_output => gl_tricolor_led,
usb_bt_output => gl_usb_bt,
ram_we_output => gl_ram_we,
ram_val_output => gl_ram_val,
ram_addr_output => gl_ram_addr
);
-- USB/Bluetooth clock divider port map
usb_bt_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk_100mhz,
reset => '0',
clk_output => usb_bt_clk
);
-- Ryan's mess
reset_n <= not gl_reset;
process(clk_100mhz)
begin
if(rising_edge(clk_100mhz)) then
if(valid = '1') then
if(data16bit(12) = '0') then
potX <= data16bit(11 downto 4);
elsif(data16bit(12) = '1') then
potY <= data16bit(11 downto 4);
end if;
end if;
end if;
end process;
Inst_sys_clk : sys_clk
GENERIC map (
REF_CLK => 100000000, -- 100.0 MHz
OUT_CLK => 25000000)
PORT map (
oCLK => vgaClk,
iCLK => clk_100mhz,
iRST => gl_reset
);
Inst_i2c_clk : sys_clk
GENERIC map (
REF_CLK => 100000000, -- 100.0 MHz
OUT_CLK => 1000000)
PORT map (
oCLK => i2cClk,
iCLK => clk_100mhz,
iRST => gl_reset
);
Inst_uart_clk : sys_clk
GENERIC map (
REF_CLK => 100000000, -- 100.0 MHz
OUT_CLK => 115200)
PORT map (
oCLK => uartClk,
iCLK => clk_100mhz,
iRST => gl_reset
);
Inst_uartEna_clk : sys_clk
GENERIC map (
REF_CLK => 100000000, -- 100.0 MHz
OUT_CLK => 11520)
PORT map (
oCLK => uartClkEna,
iCLK => clk_100mhz,
iRST => gl_reset
);
Inst_vga_sync : vga_sync
GENERIC map (
H_SYNC_TOTAL => 800,
H_PIXELS => 640,
H_SYNC_START => 659,
H_SYNC_WIDTH => 96,
V_SYNC_TOTAL => 525,
V_PIXELS => 480,
V_SYNC_START => 493,
V_SYNC_WIDTH => 2,
H_START => 699)
PORT map (
iCLK => vgaClk,
iRST_N => reset_n,
iRed => red,
iGreen => green,
iBlue => blue,
px => px,
py => py,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_H_SYNC => VGA_H_SYNC,
VGA_V_SYNC => VGA_V_SYNC
--VGA_BLANK =>
);
Inst_vga_out : vga_out
PORT map(
iCLK => clk_100mhz,
px => px,
py => py,
potX => potX,
potY => potY,
color => ram_doutb,
red => red,
green => green,
blue => blue,
ram_addr_output => ram_addrb
);
Inst_i2c_user_logic : i2c_user_logic
Port map(
clk => clk_100mhz,
busy => busy,
ienable => '1',
data_rd => data_rd,
i2c_ena => i2c_ena,
i2c_addr => i2c_addr,
i2c_rw => i2c_rw,
reset_n => i2c_reset,
i2c_data_wr => i2c_data_wr,
valid => valid,
data16bit => data16bit
);
Inst_i2c_master : i2c_master
GENERIC map(
input_clk => 100_000_000, --input clock speed from user logic in Hz
bus_clk => 9600) --speed the i2c bus (scl) will run at in Hz
PORT map(
clk => clk_100mhz, --system clock
reset_n => i2c_reset, --active low reset
ena => i2c_ena, --latch in command
addr => i2c_addr, --address of target slave
rw => i2c_rw, --'0' is write, '1' is read
data_wr => i2c_data_wr, --data to write to slave
busy => busy, --indicates transaction in progress
data_rd => data_rd, --data read from slave
ack_error => ack_error, --flag if improper acknowledge from slave
sda => sda, --serial data output of i2c bus
scl => scl --serial clock output of i2c bus
);
Inst_ps2_keyboard_to_ascii : ps2_keyboard_to_ascii
GENERIC map(
clk_freq => 100_000_000, --system clock frequency in Hz
ps2_debounce_counter_size => 9) --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
PORT map(
clk => clk_100mhz, --system clock input
ps2_clk => ps2_clk, --clock signal from PS2 keyboard
ps2_data => ps2_data, --data signal from PS2 keyboard
ascii_new => ascii_new, --output flag indicating new ASCII value
ascii_code => ascii_code); --ASCII value
Inst_uart : uart
port map(
reset => gl_reset,
txclk => uartClk,
ld_tx_data => uartClkEna,
tx_data => gl_usb_bt(7 downto 0), -- FIX THIS (its actually 2 sets of commands)
tx_enable => '1',
tx_out => tx, --o
tx_empty => open, --o
rxclk => uartClk,
uld_rx_data => uartClkEna,
rx_data => usb_bt_input_vector, --o (7 downto 0)
rx_enable => '1',
rx_in => rx,
rx_empty => open --o
);
end Behavioral;
| gpl-3.0 |
Ana06/function-graphing-FPGA | puntos_muestra.vhd | 2 | 8881 | ----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:01:33 11/18/2013
-- Design Name:
-- Module Name: puntos_muestra - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end puntos_muestra;
architecture Behavioral of puntos_muestra is
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
--Tamaño de los coeficientes en la señal de salida del teclado
constant COEF : integer := 5;
constant NUM_COUNT : integer:= 4;
type matriz1 is array(0 to 32) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
type matriz2 is array(0 to 31) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
-- En función del caso utilizaremos uno de los siguientes muestreos de puntos (para más información consultar genera2.m)
constant puntos1 : matriz1 := (
"0000000000000000000000000",
"0000000000000001000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos2 : matriz2 := (
"0000000000000000000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos3 : matriz2 := (
"1111111111100000000000000",
"1111111111100010000000000",
"1111111111100100000000000",
"1111111111100110000000000",
"1111111111101000000000000",
"1111111111101010000000000",
"1111111111101100000000000",
"1111111111101110000000000",
"1111111111110000000000000",
"1111111111110010000000000",
"1111111111110100000000000",
"1111111111110110000000000",
"1111111111111000000000000",
"1111111111111010000000000",
"1111111111111100000000000",
"1111111111111110000000000",
"0000000000000010000000000",
"0000000000000100000000000",
"0000000000000110000000000",
"0000000000001000000000000",
"0000000000001010000000000",
"0000000000001100000000000",
"0000000000001110000000000",
"0000000000010000000000000",
"0000000000010010000000000",
"0000000000010100000000000",
"0000000000010110000000000",
"0000000000011000000000000",
"0000000000011010000000000",
"0000000000011100000000000",
"0000000000011110000000000",
"0000000000100000000000000");
signal punto: STD_LOGIC_VECTOR(DEC+ENT+NUM_COUNT-1 downto 0);
signal count: std_logic_vector(3 downto 0);
signal c3, c2,c1, cn1, cn2, cn3: std_logic_vector(COEF-1 downto 0);
signal puntoAux: std_logic_vector(20 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
begin
-- Obtenemos los coeficientes introducidos por el teclado, en valor absoluto
process(entradaTeclado)
begin
if entradaTeclado(34)='1' then c3 <= "00000" - entradaTeclado(34 downto 30);
else c3 <= entradaTeclado(34 downto 30);
end if;
if entradaTeclado(29)='1' then c2 <= "00000" - entradaTeclado(29 downto 25);
else c2 <= entradaTeclado(29 downto 25);
end if;
if entradaTeclado(24)='1' then c1 <= "00000" - entradaTeclado(24 downto 20);
else c1 <= entradaTeclado(24 downto 20);
end if;
if entradaTeclado(14)='1' then cn1<= "00000" - entradaTeclado(14 downto 10);
else cn1 <= entradaTeclado(14 downto 10);
end if;
if entradaTeclado(9)='1' then cn2 <= "00000" - entradaTeclado(9 downto 5);
else cn2 <= entradaTeclado(9 downto 5);
end if;
if entradaTeclado(4)='1' then cn3 <= "00000" - entradaTeclado(4 downto 0);
else cn3 <= entradaTeclado(4 downto 0);
end if;
end process;
-- En función de los coeficientes de la función, escogemos el count adecuado (reescalado del eje X)
-- (para más información consultar genera2.m)
pcount: process(c3, c2, c1, cn1, cn2, cn3, caso)
begin
if caso = "00" then
count <= "0000";
else
if c3>0 then
if cn3>0 then
count<="0010";
elsif cn2>0 then
if c3 > cn2(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
elsif cn1>0 then
count<="0001";
else
count<="0001";
end if;
elsif c2>0 then
if cn3>0 then
if cn3 > c2(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
elsif cn2>0 then
count<="0010";
elsif cn1>0 then
if c2 > cn1(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
else
count<="0010";
end if;
elsif c1>0 then
if cn3>0 then
count<="0011";
elsif cn2>0 then
if cn2 > c1(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
else
count<="0010";
end if;
else
if cn3>0 then
count<="0100";
elsif cn2>0 then
count<="0011";
elsif cn1>0 then
count<="0010";
else
count<="0000";
end if;
end if;
end if;
end process pcount;
sincrono: process (clk, reset, enable)
begin
if reset = '1' then
estado <= (others => '0');
elsif clk'event and clk = '1' then
if enable = '1' then
estado <= estado_sig;
elsif retro_muestra = '1'
then estado <= numPuntos-1;
end if;
end if;
end process sincrono;
maquina_estados: process(estado, caso, numPuntos)
begin
if estado = "0000000" then
fin <= '1';
else
fin <= '0';
end if;
if caso = "00" then
punto <= puntos1(conv_integer(unsigned(estado)));
elsif caso = "01" then
punto <= puntos2(conv_integer(unsigned(estado)));
else
punto <= puntos3(conv_integer(unsigned(estado)));
end if;
if estado = numPuntos-1 then
estado_sig <= (others => '0');
fin <= '1';
else
estado_sig <= estado + 1;
fin <= '0';
end if;
end process maquina_estados;
-- En función del count (nos indica la potencia de 2 por la cual tenemos que multiplicar los puntos de muestra),
--elegimos el subvector que nos interesa
puntoAux <= punto(DEC+ENT+NUM_COUNT-1-conv_integer(count) downto NUM_COUNT-conv_integer(count));
punto_o <= puntoAux;
-- Escala x: en el caso normal, 1 unidad equivale a 2^(count-3), por lo que count_o representará este exponente
-- En el caso de solo tomar números positivos (logaritmo), debido al reescalado de los puntos, ahora 1 unidad
-- representará la mitad que en el caso anterior
with caso select
count_o <= count-3 when "10", --eje central
count-4 when others;--eje en la izquierda (log)
end Behavioral;
| gpl-3.0 |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_1/LBDR.vhd | 3 | 3137 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 |
mgiacomini/mips-pipeline | ADD_PC.vhd | 2 | 1387 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 20:00
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ADD_PC IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ADD_PC;
ARCHITECTURE ARC_ADD_PC OF ADD_PC IS
CONSTANT PC_INCREMENT : UNSIGNED(31 DOWNTO 0):= X"00000004";
BEGIN
OUT_A <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) + PC_INCREMENT);
END ARC_ADD_PC;
| gpl-3.0 |
mgiacomini/mips-pipeline | TB_MAIN_PROCESSOR.vhd | 2 | 2119 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_MAIN_PROCESSOR IS
END TB_MAIN_PROCESSOR;
ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAIN_PROCESSOR
PORT(
CLK : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAIN_PROCESSOR PORT MAP (
CLK => CLK,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RESET <= '1';
wait for 10 ns;
RESET <= '0';
WAIT;
end process;
END;
| gpl-3.0 |
mgiacomini/mips-pipeline | INST.vhd | 2 | 4867 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:14
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY INST IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END INST;
ARCHITECTURE ARC_INST OF INST IS
--DEVE SER 0 TO 255 O ARRAY PARA FACILITAR A LEITURA DO PROGRAMA EM ORDEM CRESCENTE
TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PROGRAM : MEMORY := (X"3C010002",X"20220004",X"01095024", X"01485025" ,X"014a5020",X"01285022",X"0149582a",X"00004820",X"11490002",X"01284820",X"08100006",X"ae2a0000",X"8e300000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000" );
BEGIN
--O FATOR - X"00400000" DEVIDO AO INCIO DAS INSTRUES NO SOFTWARE MARS
OUT_A <= PROGRAM(TO_INTEGER((UNSIGNED(IN_A) - X"00400000") SRL 2));
END ARC_INST;
| gpl-3.0 |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sim_ztex.vhd | 1 | 5800 | --------------------------------------------------------------------------------
-- sim_ztex.vhd
-- Simulation testbench for ztex_wrapper
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha1_pkg.all;
library std;
use std.textio.all;
entity sim_ztex is
end sim_ztex;
architecture SIM of sim_ztex is
component ztex_wrapper
port(
rst_i : in std_logic; --RESET
cs_i : in std_logic; --CS
cont_i : in std_logic; --CONT
clk_i : in std_logic; --IFCLK
dat_i : in unsigned(0 to 7); --FD
dat_o : out unsigned(0 to 7); --pc
SLOE : out std_logic; --SLOE
SLRD : out std_logic; --SLRD
SLWR : out std_logic; --SLWR
FIFOADR0 : out std_logic; --FIFOADR0
FIFOADR1 : out std_logic; --FIFOADR1
PKTEND : out std_logic; --PKTEND
FLAGA : in std_logic; --FLAGA EP2 FIFO Empty flag (FLAGA)
FLAGB : in std_logic --FLAGB
);
end component;
signal i: integer range 0 to 65535;
signal rst_i: std_logic := '0';
signal cs_i: std_logic := '0';
signal cont_i: std_logic := '0';
signal clk_i: std_logic := '0';
signal dat_i: unsigned(0 to 7);
signal dat_o: unsigned(0 to 7);
signal SLOE: std_logic;
signal SLRD: std_logic;
signal SLWR: std_logic;
signal FIFOADR0: std_logic;
signal FIFOADR1: std_logic;
signal PKTEND: std_logic;
signal FLAGA: std_logic;
signal FLAGB: std_logic;
type t_char_file is file of character;
--type t_byte_arr is unsigned(0 to 7);
signal read_arr_byte : handshake_data;
signal start_mk: mk_data;
signal end_mk: mk_data;
constant clock_period : time := 1 ns;
begin
ZTEX1: ztex_wrapper port map (rst_i, cs_i, cont_i, clk_i,
dat_i, dat_o,
SLOE, SLRD, SLWR, FIFOADR0, FIFOADR1, PKTEND, FLAGA, FLAGB);
stim_proc: process
file file_handshake : t_char_file open read_mode is "wpa2-psk-linksys.hccap";
file file_handshake2 : t_char_file open read_mode is "wpa2-psk-linksys.hccap";
variable char_buffer : character;
begin
rst_i <= '0';
cs_i <= '1';
i <= 0;
start_mk(0) <= "00110001"; --0x31, char 1
start_mk(1) <= "00110000";
start_mk(2) <= "00110000";
start_mk(3) <= "00110000";
start_mk(4) <= "00110000";
start_mk(5) <= "00110000";
start_mk(6) <= "00110000";
start_mk(7) <= "00110000";
start_mk(8) <= "00110000";
start_mk(9) <= "00110001";
end_mk(0) <= "00110001"; --0x31, char 1
end_mk(1) <= "00110000";
end_mk(2) <= "00110000";
end_mk(3) <= "00110000";
end_mk(4) <= "00110000";
end_mk(5) <= "00110000";
end_mk(6) <= "00110000";
end_mk(7) <= "00110011";
end_mk(8) <= "00110000";
end_mk(9) <= "00110000";
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
while not endfile(file_handshake) loop
read(file_handshake, char_buffer);
dat_i <= to_unsigned(character'pos(char_buffer), 8);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
file_close(file_handshake);
for x in 0 to 9 loop
dat_i <= start_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
for x in 0 to 9 loop
dat_i <= end_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
--Do it all again
while SLOE = '0' loop
wait until rising_edge(clk_i);
end loop;
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
while not endfile(file_handshake2) loop
read(file_handshake2, char_buffer);
dat_i <= to_unsigned(character'pos(char_buffer), 8);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
file_close(file_handshake2);
for x in 0 to 9 loop
dat_i <= start_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
for x in 0 to 9 loop
dat_i <= end_mk(x);
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
--ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end SIM; | gpl-3.0 |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_2/SHMU.vhd | 1 | 8238 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet_E_0, healthy_packet_E_0, faulty_packet_S_0, healthy_packet_S_0, faulty_packet_L_0, healthy_packet_L_0: in std_logic;
faulty_packet_W_1, healthy_packet_W_1, faulty_packet_S_1, healthy_packet_S_1, faulty_packet_L_1, healthy_packet_L_1: in std_logic;
faulty_packet_E_2, healthy_packet_E_2, faulty_packet_N_2, healthy_packet_N_2, faulty_packet_L_2, healthy_packet_L_2: in std_logic;
faulty_packet_W_3, healthy_packet_W_3, faulty_packet_N_3, healthy_packet_N_3, faulty_packet_L_3, healthy_packet_L_3: in std_logic
);
end SHMU;
architecture behavior of SHMU is
type SHM_type is array (0 to network_size*network_size-1) of std_logic_vector(router_fault_info_width-1 downto 0); --memory
signal SHM : SHM_type ;
signal Healthy_N_0, Healthy_E_0, Healthy_W_0, Healthy_S_0, Healthy_L_0: std_logic;
signal Healthy_N_1, Healthy_E_1, Healthy_W_1, Healthy_S_1, Healthy_L_1: std_logic;
signal Healthy_N_2, Healthy_E_2, Healthy_W_2, Healthy_S_2, Healthy_L_2: std_logic;
signal Healthy_N_3, Healthy_E_3, Healthy_W_3, Healthy_S_3, Healthy_L_3: std_logic;
signal Intermittent_N_0, Intermittent_E_0, Intermittent_W_0, Intermittent_S_0, Intermittent_L_0: std_logic;
signal Intermittent_N_1, Intermittent_E_1, Intermittent_W_1, Intermittent_S_1, Intermittent_L_1: std_logic;
signal Intermittent_N_2, Intermittent_E_2, Intermittent_W_2, Intermittent_S_2, Intermittent_L_2: std_logic;
signal Intermittent_N_3, Intermittent_E_3, Intermittent_W_3, Intermittent_S_3, Intermittent_L_3: std_logic;
signal Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: std_logic;
signal Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: std_logic;
signal Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: std_logic;
signal Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: std_logic;
component counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty:out std_logic
);
end component;
begin
-- these are the signals that do not actually exist because of the topology
Faulty_N_0 <= '0';
Faulty_W_0 <= '0';
Faulty_N_1 <= '0';
Faulty_E_1 <= '0';
Faulty_S_2 <= '0';
Faulty_W_2 <= '0';
Faulty_S_3 <= '0';
Faulty_E_3 <= '0';
CT_0_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_0, Healthy_packet => healthy_packet_E_0,
Healthy => Healthy_E_0, Intermittent => Intermittent_E_0, Faulty => Faulty_E_0);
CT_0_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_0, Healthy_packet => healthy_packet_S_0,
Healthy => Healthy_S_0, Intermittent => Intermittent_S_0, Faulty => Faulty_S_0);
CT_0_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_0, Healthy_packet => healthy_packet_L_0,
Healthy => Healthy_L_0, Intermittent => Intermittent_L_0, Faulty => Faulty_L_0);
------------------------------------------------------------------------------------------------------------
CT_1_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_1, Healthy_packet => healthy_packet_W_1,
Healthy => Healthy_W_1, Intermittent => Intermittent_W_1, Faulty => Faulty_W_1);
CT_1_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_1, Healthy_packet => healthy_packet_S_1,
Healthy => Healthy_S_1, Intermittent => Intermittent_S_1, Faulty => Faulty_S_1);
CT_1_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_1, Healthy_packet => healthy_packet_L_1,
Healthy => Healthy_L_1, Intermittent => Intermittent_L_1, Faulty => Faulty_L_1);
------------------------------------------------------------------------------------------------------------
CT_2_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_2, Healthy_packet => healthy_packet_N_2,
Healthy => Healthy_N_2, Intermittent => Intermittent_N_2, Faulty => Faulty_N_2);
CT_2_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_2, Healthy_packet => healthy_packet_E_2,
Healthy => Healthy_E_2, Intermittent => Intermittent_E_2, Faulty => Faulty_E_2);
CT_2_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_2, Healthy_packet => healthy_packet_L_2,
Healthy => Healthy_L_2, Intermittent => Intermittent_L_2, Faulty => Faulty_L_2);
------------------------------------------------------------------------------------------------------------
CT_3_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_3, Healthy_packet => healthy_packet_N_3,
Healthy => Healthy_N_3, Intermittent => Intermittent_N_3, Faulty => Faulty_N_3);
CT_3_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_3, Healthy_packet => healthy_packet_W_3,
Healthy => Healthy_W_3, Intermittent => Intermittent_W_3, Faulty => Faulty_W_3);
CT_3_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_3, Healthy_packet => healthy_packet_L_3,
Healthy => Healthy_L_3, Intermittent => Intermittent_L_3, Faulty => Faulty_L_3);
process(clk, reset)begin
if reset = '0' then
SHM <= (others => (others => '0'));
elsif clk'event and clk = '1' then
SHM(0) <= Faulty_N_0 & Faulty_E_0 & Faulty_W_0 & Faulty_S_0 & Faulty_L_0;
SHM(1) <= Faulty_N_1 & Faulty_E_1 & Faulty_W_1 & Faulty_S_1 & Faulty_L_1;
SHM(2) <= Faulty_N_2 & Faulty_E_2 & Faulty_W_2 & Faulty_S_2 & Faulty_L_2;
SHM(3) <= Faulty_N_3 & Faulty_E_3 & Faulty_W_3 & Faulty_S_3 & Faulty_L_3;
end if;
end process;
END; | gpl-3.0 |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/ztex_wrapper.vhd | 1 | 6632 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use work.sha1_pkg.all;
entity ztex_wrapper is
port(
fd : inout std_logic_vector(15 downto 0);
CS : in std_logic;
IFCLK : in std_logic;
--FXCLK : in std_logic;
--sck_i : in std_logic;
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR : out std_logic_vector(1 downto 0);
FLAGA : in std_logic; --PF
FLAGB : in std_logic; --Full
FLAGC : in std_logic; --Empty
PKTEND : out std_logic;
RESET : in std_logic;
RUN : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ztex_wrapper;
architecture RTL of ztex_wrapper is
COMPONENT fx2_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END COMPONENT;
signal fd_buf : std_logic_vector(15 downto 0);
signal fd_in : std_logic_vector(15 downto 0);
signal fd_out : std_logic_vector(15 downto 0);
signal sloe_buf: std_ulogic;
signal slrd_buf: std_ulogic;
signal slwr_buf: std_ulogic;
signal pktend_buf: std_ulogic;
signal fifoadr_buf: std_logic_vector(1 downto 0);
--FIFOS
signal in_fifo_wr_en: std_ulogic;
signal in_fifo_rd_en: std_ulogic;
signal in_fifo_full: std_ulogic;
signal in_fifo_empty: std_ulogic;
signal in_fifo_almost_empty: std_ulogic;
signal out_fifo_wr_en: std_ulogic;
signal out_fifo_rd_en: std_ulogic;
signal out_fifo_full: std_ulogic;
signal out_fifo_empty: std_ulogic;
signal out_fifo_almost_empty: std_ulogic;
signal direction: std_ulogic;
--Data
signal datablock: ssid_data;
type state_type is (STATE_ERROR,
STATE_READY,
STATE_INPUT,
STATE_READ_INPUT,
STATE_READ_PROGRESS,
STATE_WORKING,
STATE_FINISH_FAIL,
STATE_FINISH_SUCCEED
);
type cmd_type is (CMD_WAIT, --00
CMD_WRITE, --01
CMD_READ, --10
CMD_ERROR --11
);
type data_type is (DATA_NULL, --00
DATA_SSID, --01
DATA_MK, --10
DATA_ERROR --11
);
signal state : state_type := STATE_ERROR;
signal command : cmd_type;
signal datatype : data_type;
signal dataaddr : integer range 0 to 35;
signal data : std_logic_vector(7 downto 0);
begin
SLOE <= sloe_buf when CS = '1' else 'Z';
SLRD <= slrd_buf when CS = '1' else 'Z';
SLWR <= slwr_buf when CS = '1' else 'Z';
FIFOADR <= fifoadr_buf when CS = '1' else "ZZ";
PKTEND <= pktend_buf when CS = '1' else 'Z'; --Unused
fd <= fd_out when CS = '1' and direction = '0' else (others => 'Z');
fifoadr_buf <= "10" when direction = '1' else "00";
sloe_buf <= '0' when direction = '1' else '1';
slrd_buf <= '0' when direction = '1' and FLAGC = '1' else '1'; --Input and FX2 not empty
--slwr_buf <= '0' when direction = '0' else '1';
--FX2 Flow control
direction <= '0' when
out_fifo_empty = '0' and
FLAGB = '1' else
'1';
pktend_buf <= '0' when
out_fifo_almost_empty = '1' and
out_fifo_rd_en = '1' else
'1';
in_fifo_wr_en <= '1' when
direction = '1' and
CS = '1' and
flagc = '1' else
'0';
slwr_buf <= '0' when
out_fifo_rd_en = '1' and
flagb = '1' else
'1';
in_fifo : fx2_fifo port map (
rst => RESET,
wr_clk => IFCLK,
rd_clk => IFCLK,
din => fd,
wr_en => in_fifo_wr_en,
rd_en => in_fifo_rd_en,
dout => fd_in,
full => in_fifo_full,
empty => in_fifo_empty,
almost_empty => in_fifo_almost_empty
);
out_fifo : fx2_fifo port map (
rst => RESET,
wr_clk => IFCLK,
rd_clk => IFCLK,
din => fd_buf,
wr_en => out_fifo_wr_en,
rd_en => out_fifo_rd_en,
dout => fd_out,
full => out_fifo_full,
empty => out_fifo_empty,
almost_empty => out_fifo_almost_empty
);
ztex_comm: process(IFCLK, RESET)
begin
if RESET = '1' then
fd_buf <= X"ce5d";
in_fifo_rd_en <= '1';
out_fifo_rd_en <= '0';
state <= STATE_READY;
elsif IFCLK'event and IFCLK = '1' then
if in_fifo_empty = '0' then
if fd_in(15 downto 14) = "00" then
command <= CMD_WAIT;
elsif fd_in(15 downto 14) = "01" then
command <= CMD_WRITE;
elsif fd_in(15 downto 14) = "10" then
command <= CMD_READ;
else
command <= CMD_ERROR;
end if;
if fd_in(13 downto 12) = "00" then
datatype <= DATA_NULL;
elsif fd_in(13 downto 12) = "01" then
datatype <= DATA_SSID;
elsif fd_in(13 downto 12) = "10" then
datatype <= DATA_MK;
else
datatype <= DATA_ERROR;
end if;
dataaddr <= to_integer(unsigned(fd_in(11 downto 8)));
data <= fd_in(7 downto 0);
else
command <= CMD_WAIT;
end if;
if state = STATE_READY then
out_fifo_wr_en <= '0';
if command = CMD_WRITE then
datablock(dataaddr) <= unsigned(data);
elsif command = CMD_READ then
out_fifo_wr_en <= '1';
fd_buf <= fd_in(15 downto 8) & std_logic_vector(datablock(dataaddr));
end if;
elsif state = STATE_READ_INPUT then
state <= STATE_READY;
end if;
--Todo fix for multiple clock domains
if direction = '0' then
out_fifo_rd_en <= not out_fifo_rd_en;
end if;
end if;
end process ztex_comm;
end RTL;
| gpl-3.0 |
SoCdesign/EHA | RTL/Credit_Based/Credit_Based_FC/ParityChecker_packet_detector.vhd | 4 | 2664 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end parity_checker_packet_detector;
architecture behavior of parity_checker_packet_detector is
signal xor_all: std_logic;
signal fault_out, fault_out_in: std_logic;
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
type state_type IS (Idle, Header_flit, Body_flit, Tail_flit);
SIGNAL state_out, state_in : state_type;
begin
-- sequential process
process(reset, clk)begin
if reset = '0' then
state_out <= Idle;
fault_out <= '0';
elsif clk'event and clk = '1' then
state_out <= state_in;
fault_out <= fault_out_in;
end if;
end process;
--anything bellow this is combinatorial
-- this part is the typical parity
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out_in <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out_in <= '1';
end if;
end process;
-- FSM for packet health detection
process(flit_type, fault_out, state_out, valid_in)
begin
faulty_packet <= '0';
healthy_packet <= '0';
--if valid_in = '1' then
case(state_out) is
when Idle =>
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
when Header_flit =>
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
else
state_in <= state_out;
end if;
else
state_in <= Idle;
faulty_packet <= '1';
end if;
when Body_flit =>
if fault_out = '0' then
if flit_type = "100" then
state_in <= Tail_flit;
else
state_in <= state_out;
end if;
else
state_in <= Idle;
faulty_packet <= '1';
end if;
when Tail_flit =>
state_in <= Idle;
if fault_out = '0' then
healthy_packet <= '1';
else
faulty_packet <= '1';
end if;
when others => state_in <= state_out;
end case;
--else
-- state_in <= state_out;
--end if;
end process;
end;
| gpl-3.0 |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/imports/Downloads/TTL_Serial_Display.vhd | 1 | 3183 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TTL_Serial_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
Tx : out STD_LOGIC);
end TTL_Serial_Display;
architecture Behavioral of TTL_Serial_Display is
signal DIV : unsigned(15 DOWNTO 0) := X"0000";
--Signals for StateMachine:
type stateType is range 0 to 10;
Signal Sel : integer range 0 to 11;
Signal Q : std_logic ;
signal CS : stateType;
--Signals for Splitter:
signal X1,X2,X3,X4 : std_logic_vector (3 downto 0);
signal extend : std_logic_vector (3 downto 0);
signal baud_en : std_logic;
signal HEX2_Data1 : std_logic_vector (7 downto 0);
signal HEX2_Data2 : std_logic_vector (7 downto 0);
signal HEX2_Data3 : std_logic_vector (7 downto 0);
signal HEX2_Data4 : std_logic_vector (7 downto 0);
signal LUT_Data : std_logic_vector (7 downto 0);
BEGIN
LUTConversion:
Process(Hex_IN)
begin
X1 <= Hex_IN(15 downto 12);
X2 <= Hex_IN(11 downto 8);
X3 <= Hex_IN(7 downto 4);
X4 <= Hex_IN(3 downto 0);
extend <= "0000";
end process;
Process(X1, X2, X3, X4)
begin
HEX2_Data1 <= extend & X1;
HEX2_Data2 <= extend & X2;
HEX2_Data3 <= extend & X3;
HEX2_Data4 <= extend & X4;
end process;
LUTMux:
process (Sel)
begin
if (Sel = 0) then
LUT_Data <= X"76";
elsif (Sel = 1) then
LUT_Data <= X"76";
elsif (Sel = 2) then
LUT_Data <= X"76";
elsif (Sel = 3) then
LUT_Data <= X"76";
elsif (Sel = 4) then
LUT_Data <= X"79";
elsif (Sel = 5) then
LUT_Data <= X"00";
elsif (Sel = 6) then
LUT_Data <= X"7A";
elsif (Sel = 7) then
LUT_Data <= X"FF";
elsif (Sel = 8) then
LUT_Data <= HEX2_Data1;
elsif (Sel = 9) then
LUT_Data <= HEX2_Data2;
elsif (Sel = 10) then
LUT_Data <= HEX2_Data3;
elsif (Sel = 11) then
LUT_Data <= HEX2_Data4;
end if;
end process;
StateMachine:
--code pulled from Ring_Counter.vhd
process(iCLK)
begin
if rising_edge(iCLK) then
if DIV >= X"28B1" then
DIV <= X"0000";
baud_en <= '1';
else
DIV <= DIV +1;
baud_en <= '0';
end if;
end if;
end process;
process (CS, iCLK, baud_en)
begin
if rising_edge(iCLK) and baud_en = '1' then
case CS is
when 0 =>
Q <= '0';
CS <= 1;
when 1 =>
Q <= LUT_Data(0);
CS <= 2;
when 2 =>
Q <= LUT_Data(1);
CS <= 3;
when 3 =>
Q <= LUT_Data(2);
CS <= 4;
when 4 =>
Q <= LUT_Data(3);
CS <= 5;
when 5 =>
Q <= LUT_Data(4);
CS <= 6;
when 6 =>
Q <= LUT_Data(5);
CS <= 7;
when 7 =>
Q <= LUT_Data(6);
CS <= 8;
when 8 =>
Q <= LUT_Data(7);
CS <= 9;
when 9 =>
Q <= '1';
CS <= 10;
if (Sel < 11) then
Sel <= Sel+1;
else
Sel <= 8;
end if;
when 10 =>
Q <= '0';
CS <= 1;
end case;
end if;
end process;
Tx <= Q;
end Behavioral;
| gpl-3.0 |
SoCdesign/EHA | RTL/Hand_Shaking/Hand_Shaking_FC/Fault_injector.vhd | 2 | 1183 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (data_in(i) and not sta_1 and not sta_0) or (mask(i) and sta_1);
end generate;
end; | gpl-3.0 |
SoCdesign/EHA | RTL/Hand_Shaking/Checkers/Control_part_checkers/Handshaking_FC/LBDR_checkers/RTL_and_Synthesis/LBDR_pseudo.vhd | 1 | 2839 | -- Copyright (C) 2016 Siavoosh Payandeh, Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end LBDR_pseudo;
architecture behavior of LBDR_pseudo is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else -- Body flit
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; | gpl-3.0 |
SoCdesign/EHA | RTL/Fault_Management/SHMU_prototype/version_1/network_parity_FI_2x2.vhd | 1 | 21480 | --Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_0, CTS_L_0: out std_logic;
DRTS_L_0, DCTS_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_1, CTS_L_1: out std_logic;
DRTS_L_1, DCTS_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_2, CTS_L_2: out std_logic;
DRTS_L_2, DCTS_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_3, CTS_L_3: out std_logic;
DRTS_L_3, DCTS_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
-- Declaring router component
component router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size : integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(4 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty:out std_logic
);
end component;
component SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: in std_logic;
Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: in std_logic;
Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: in std_logic;
Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal DCTS_N_0, DCTS_E_0, DCTS_w_0, DCTS_S_0: std_logic;
signal DCTS_N_1, DCTS_E_1, DCTS_w_1, DCTS_S_1: std_logic;
signal DCTS_N_2, DCTS_E_2, DCTS_w_2, DCTS_S_2: std_logic;
signal DCTS_N_3, DCTS_E_3, DCTS_w_3, DCTS_S_3: std_logic;
signal DRTS_N_0, DRTS_E_0, DRTS_W_0, DRTS_S_0: std_logic;
signal DRTS_N_1, DRTS_E_1, DRTS_W_1, DRTS_S_1: std_logic;
signal DRTS_N_2, DRTS_E_2, DRTS_W_2, DRTS_S_2: std_logic;
signal DRTS_N_3, DRTS_E_3, DRTS_W_3, DRTS_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal CTS_N_0, CTS_E_0, CTS_w_0, CTS_S_0: std_logic;
signal CTS_N_1, CTS_E_1, CTS_w_1, CTS_S_1: std_logic;
signal CTS_N_2, CTS_E_2, CTS_w_2, CTS_S_2: std_logic;
signal CTS_N_3, CTS_E_3, CTS_w_3, CTS_S_3: std_logic;
signal RTS_N_0, RTS_E_0, RTS_W_0, RTS_S_0: std_logic;
signal RTS_N_1, RTS_E_1, RTS_W_1, RTS_S_1: std_logic;
signal RTS_N_2, RTS_E_2, RTS_W_2, RTS_S_2: std_logic;
signal RTS_N_3, RTS_E_3, RTS_W_3, RTS_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal faulty_packet_N_0, faulty_packet_E_0, faulty_packet_W_0, faulty_packet_S_0, faulty_packet_L_0: std_logic;
signal faulty_packet_N_1, faulty_packet_E_1, faulty_packet_W_1, faulty_packet_S_1, faulty_packet_L_1: std_logic;
signal faulty_packet_N_2, faulty_packet_E_2, faulty_packet_W_2, faulty_packet_S_2, faulty_packet_L_2: std_logic;
signal faulty_packet_N_3, faulty_packet_E_3, faulty_packet_W_3, faulty_packet_S_3, faulty_packet_L_3: std_logic;
signal healthy_packet_N_0, healthy_packet_E_0, healthy_packet_W_0, healthy_packet_S_0, healthy_packet_L_0: std_logic;
signal healthy_packet_N_1, healthy_packet_E_1, healthy_packet_W_1, healthy_packet_S_1, healthy_packet_L_1: std_logic;
signal healthy_packet_N_2, healthy_packet_E_2, healthy_packet_W_2, healthy_packet_S_2, healthy_packet_L_2: std_logic;
signal healthy_packet_N_3, healthy_packet_E_3, healthy_packet_W_3, healthy_packet_S_3, healthy_packet_L_3: std_logic;
signal Healthy_N_0, Healthy_E_0, Healthy_W_0, Healthy_S_0, Healthy_L_0: std_logic;
signal Healthy_N_1, Healthy_E_1, Healthy_W_1, Healthy_S_1, Healthy_L_1: std_logic;
signal Healthy_N_2, Healthy_E_2, Healthy_W_2, Healthy_S_2, Healthy_L_2: std_logic;
signal Healthy_N_3, Healthy_E_3, Healthy_W_3, Healthy_S_3, Healthy_L_3: std_logic;
signal Intermittent_N_0, Intermittent_E_0, Intermittent_W_0, Intermittent_S_0, Intermittent_L_0: std_logic;
signal Intermittent_N_1, Intermittent_E_1, Intermittent_W_1, Intermittent_S_1, Intermittent_L_1: std_logic;
signal Intermittent_N_2, Intermittent_E_2, Intermittent_W_2, Intermittent_S_2, Intermittent_L_2: std_logic;
signal Intermittent_N_3, Intermittent_E_3, Intermittent_W_3, Intermittent_S_3, Intermittent_L_3: std_logic;
signal Faulty_N_0, Faulty_E_0, Faulty_W_0, Faulty_S_0, Faulty_L_0: std_logic;
signal Faulty_N_1, Faulty_E_1, Faulty_W_1, Faulty_S_1, Faulty_L_1: std_logic;
signal Faulty_N_2, Faulty_E_2, Faulty_W_2, Faulty_S_2, Faulty_L_2: std_logic;
signal Faulty_N_3, Faulty_E_3, Faulty_W_3, Faulty_S_3, Faulty_L_3: std_logic;
begin
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
SHMU_unit: SHMU
generic map(router_fault_info_width => 5,network_size => 2)
port map( reset => reset,
clk => clk,
Faulty_N_0 => Faulty_N_0, Faulty_E_0 => Faulty_E_0, Faulty_W_0 => Faulty_W_0, Faulty_S_0 => Faulty_S_0, Faulty_L_0 => Faulty_L_0,
Faulty_N_1 => Faulty_N_1, Faulty_E_1 => Faulty_E_1, Faulty_W_1 => Faulty_W_1, Faulty_S_1 => Faulty_S_1, Faulty_L_1 => Faulty_L_1,
Faulty_N_2 => Faulty_N_2, Faulty_E_2 => Faulty_E_2, Faulty_W_2 => Faulty_W_2, Faulty_S_2 => Faulty_S_2, Faulty_L_2 => Faulty_L_2,
Faulty_N_3 => Faulty_N_3, Faulty_E_3 => Faulty_E_3, Faulty_W_3 => Faulty_W_3, Faulty_S_3 => Faulty_S_3, Faulty_L_3 => Faulty_L_3
);
CT_0_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_0, Healthy_packet => healthy_packet_N_0,
Healthy => Healthy_N_0, Intermittent => Intermittent_N_0, Faulty => Faulty_N_0);
CT_0_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_0, Healthy_packet => healthy_packet_E_0,
Healthy => Healthy_E_0, Intermittent => Intermittent_E_0, Faulty => Faulty_E_0);
CT_0_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_0, Healthy_packet => healthy_packet_W_0,
Healthy => Healthy_W_0, Intermittent => Intermittent_W_0, Faulty => Faulty_W_0);
CT_0_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_0, Healthy_packet => healthy_packet_S_0,
Healthy => Healthy_S_0, Intermittent => Intermittent_S_0, Faulty => Faulty_S_0);
CT_0_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_0, Healthy_packet => healthy_packet_L_0,
Healthy => Healthy_L_0, Intermittent => Intermittent_L_0, Faulty => Faulty_L_0);
------------------------------------------------------------------------------------------------------------
CT_1_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_1, Healthy_packet => healthy_packet_N_1,
Healthy => Healthy_N_1, Intermittent => Intermittent_N_1, Faulty => Faulty_N_1);
CT_1_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_1, Healthy_packet => healthy_packet_E_1,
Healthy => Healthy_E_1, Intermittent => Intermittent_E_1, Faulty => Faulty_E_1);
CT_1_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_1, Healthy_packet => healthy_packet_W_1,
Healthy => Healthy_W_1, Intermittent => Intermittent_W_1, Faulty => Faulty_W_1);
CT_1_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_1, Healthy_packet => healthy_packet_S_1,
Healthy => Healthy_S_1, Intermittent => Intermittent_S_1, Faulty => Faulty_S_1);
CT_1_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_1, Healthy_packet => healthy_packet_L_1,
Healthy => Healthy_L_1, Intermittent => Intermittent_L_1, Faulty => Faulty_L_1);
------------------------------------------------------------------------------------------------------------
CT_2_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_2, Healthy_packet => healthy_packet_N_2,
Healthy => Healthy_N_2, Intermittent => Intermittent_N_2, Faulty => Faulty_N_2);
CT_2_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_2, Healthy_packet => healthy_packet_E_2,
Healthy => Healthy_E_2, Intermittent => Intermittent_E_2, Faulty => Faulty_E_2);
CT_2_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_2, Healthy_packet => healthy_packet_W_2,
Healthy => Healthy_W_2, Intermittent => Intermittent_W_2, Faulty => Faulty_W_2);
CT_2_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_2, Healthy_packet => healthy_packet_S_2,
Healthy => Healthy_S_2, Intermittent => Intermittent_S_2, Faulty => Faulty_S_2);
CT_2_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_2, Healthy_packet => healthy_packet_L_2,
Healthy => Healthy_L_2, Intermittent => Intermittent_L_2, Faulty => Faulty_L_2);
------------------------------------------------------------------------------------------------------------
CT_3_N: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_N_3, Healthy_packet => healthy_packet_N_3,
Healthy => Healthy_N_3, Intermittent => Intermittent_N_3, Faulty => Faulty_N_3);
CT_3_E: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_E_3, Healthy_packet => healthy_packet_E_3,
Healthy => Healthy_E_3, Intermittent => Intermittent_E_3, Faulty => Faulty_E_3);
CT_3_W: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_W_3, Healthy_packet => healthy_packet_W_3,
Healthy => Healthy_W_3, Intermittent => Intermittent_W_3, Faulty => Faulty_W_3);
CT_3_S: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_S_3, Healthy_packet => healthy_packet_S_3,
Healthy => Healthy_S_3, Intermittent => Intermittent_S_3, Faulty => Faulty_S_3);
CT_3_L: counter_threshold_classifier generic map(counter_depth => 8, healthy_counter_threshold => 20, faulty_counter_threshold => 1)
port map ( reset => reset,
clk => clk,
faulty_packet => faulty_packet_L_3, Healthy_packet => healthy_packet_L_3,
Healthy => Healthy_L_3, Intermittent => Intermittent_L_3, Faulty => Faulty_L_3);
-- instantiating the routers
R_0: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>0, Rxy_rst => 60, Cx_rst => 10, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_0, DCTS_E_0, DCTS_W_0, DCTS_S_0, DCTS_L_0,
DRTS_N_0, DRTS_E_0, DRTS_W_0, DRTS_S_0, DRTS_L_0,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
RTS_N_0, RTS_E_0, RTS_W_0, RTS_S_0, RTS_L_0,
CTS_N_0, CTS_E_0, CTS_w_0, CTS_S_0, CTS_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
faulty_packet_N_0, faulty_packet_E_0, faulty_packet_W_0, faulty_packet_S_0, faulty_packet_L_0,
healthy_packet_N_0, healthy_packet_E_0, healthy_packet_W_0, healthy_packet_S_0, healthy_packet_L_0);
R_1: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>1, Rxy_rst => 60, Cx_rst => 12, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_1, DCTS_E_1, DCTS_W_1, DCTS_S_1, DCTS_L_1,
DRTS_N_1, DRTS_E_1, DRTS_W_1, DRTS_S_1, DRTS_L_1,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
RTS_N_1, RTS_E_1, RTS_W_1, RTS_S_1, RTS_L_1,
CTS_N_1, CTS_E_1, CTS_w_1, CTS_S_1, CTS_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
faulty_packet_N_1, faulty_packet_E_1, faulty_packet_W_1, faulty_packet_S_1, faulty_packet_L_1,
healthy_packet_N_1, healthy_packet_E_1, healthy_packet_W_1, healthy_packet_S_1, healthy_packet_L_1);
R_2: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>2, Rxy_rst => 60, Cx_rst => 3, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_2, DCTS_E_2, DCTS_W_2, DCTS_S_2, DCTS_L_2,
DRTS_N_2, DRTS_E_2, DRTS_W_2, DRTS_S_2, DRTS_L_2,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
RTS_N_2, RTS_E_2, RTS_W_2, RTS_S_2, RTS_L_2,
CTS_N_2, CTS_E_2, CTS_w_2, CTS_S_2, CTS_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
faulty_packet_N_2, faulty_packet_E_2, faulty_packet_W_2, faulty_packet_S_2, faulty_packet_L_2,
healthy_packet_N_2, healthy_packet_E_2, healthy_packet_W_2, healthy_packet_S_2, healthy_packet_L_2);
R_3: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>3, Rxy_rst => 60, Cx_rst => 5, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_3, DCTS_E_3, DCTS_W_3, DCTS_S_3, DCTS_L_3,
DRTS_N_3, DRTS_E_3, DRTS_W_3, DRTS_S_3, DRTS_L_3,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
RTS_N_3, RTS_E_3, RTS_W_3, RTS_S_3, RTS_L_3,
CTS_N_3, CTS_E_3, CTS_w_3, CTS_S_3, CTS_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
faulty_packet_N_3, faulty_packet_E_3, faulty_packet_W_3, faulty_packet_S_3, faulty_packet_L_3,
healthy_packet_N_3, healthy_packet_E_3, healthy_packet_W_3, healthy_packet_S_3, healthy_packet_L_3);
-- instantiating the Fault fault_injector
-- vertical FIs
FI_0_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_0,
address => FI_Add_0_2,
sta_0 => sta0_0_2,
sta_1 => sta1_0_2,
data_out => RX_N_2
);
FI_2_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_2,
address => FI_Add_2_0,
sta_0 => sta0_2_0,
sta_1 => sta1_2_0,
data_out => RX_S_0
);
FI_1_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_1,
address => FI_Add_1_3,
sta_0 => sta0_1_3,
sta_1 => sta1_1_3,
data_out => RX_N_3
);
FI_3_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_3,
address => FI_Add_3_1,
sta_0 => sta0_3_1,
sta_1 => sta1_3_1,
data_out => RX_S_1
);
-- horizontal FIs
FI_0_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_0,
address => FI_Add_0_1,
sta_0 => sta0_0_1,
sta_1 => sta1_0_1,
data_out => RX_W_1
);
FI_1_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_1,
address => FI_Add_1_0,
sta_0 => sta0_1_0,
sta_1 => sta1_1_0,
data_out => RX_E_0
);
FI_2_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_2,
address => FI_Add_2_3,
sta_0 => sta0_2_3,
sta_1 => sta1_2_3,
data_out => RX_W_3
);
FI_3_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_3,
address => FI_Add_3_2,
sta_0 => sta0_3_2,
sta_1 => sta1_3_2,
data_out => RX_E_2
);
---------------------------------------------------------------
-- binding the routers together
-- vertical handshakes
-- connecting router: 0 to router: 2 and vice versa
DRTS_N_2 <= RTS_S_0;
DCTS_S_0 <= CTS_N_2;
DRTS_S_0 <= RTS_N_2;
DCTS_N_2 <= CTS_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
DRTS_N_3 <= RTS_S_1;
DCTS_S_1 <= CTS_N_3;
DRTS_S_1 <= RTS_N_3;
DCTS_N_3 <= CTS_S_1;
-------------------
-- horizontal handshakes
-- connecting router: 0 to router: 1 and vice versa
DRTS_E_0 <= RTS_W_1;
DCTS_W_1 <= CTS_E_0;
DRTS_W_1 <= RTS_E_0;
DCTS_E_0 <= CTS_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
DRTS_E_2 <= RTS_W_3;
DCTS_W_3 <= CTS_E_2;
DRTS_W_3 <= RTS_E_2;
DCTS_E_2 <= CTS_W_3;
-------------------
end;
| gpl-3.0 |
JarrettR/FPGA-Cryptoparty | FPGA/hdl/sha1_process_input.vhd | 1 | 3751 | --------------------------------------------------------------------------------
-- After input has been loaded, run calcs to fill up entire message digest
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_process_input is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end sha1_process_input;
architecture RTL of sha1_process_input is
signal w: w_full;
signal w_con: w_full;
signal w_hold: w_input;
-- synthesis translate_off
signal test_word_1: std_ulogic_vector(0 to 31);
signal test_word_2: std_ulogic_vector(0 to 31);
signal test_word_3: std_ulogic_vector(0 to 31);
signal test_word_4: std_ulogic_vector(0 to 31);
signal test_word_5: std_ulogic_vector(0 to 31);
-- synthesis translate_on
signal i : integer range 0 to 79;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
--Todo: decide if reset is even wanted
--for x in 0 to 15 loop
-- w_hold(x) <= "00000000000000000000000000000000";
--end loop;
else
if load_i = '1' then
--Alt: Type-casting instead of using loop
for x in 0 to 15 loop
w(x) <= w_hold(x);
end loop;
i <= 16; --i + 1;
valid_o <= '0';
elsif i < 16 then
i <= i + 1;
valid_o <= '0';
else
w(i) <= (w_con(i - 3)(1 to 31) & w_con(i - 3)(0)) XOR
(w_con(i - 8)(1 to 31) & w_con(i - 8)(0)) XOR
(w_con(i - 14)(1 to 31) & w_con(i - 14)(0)) XOR
(w_con(i - 16)(1 to 31) & w_con(i - 16)(0));
if i = 79 then
i <= 0;
--valid_o <= '1';
elsif i = 16 then
i <= i + 1;
valid_o <= '1';
else
i <= i + 1;
valid_o <= '0';
end if;
end if;
end if;
end if;
end process;
--Alt: merge functions of dat_w_o and w_con using inout port
dat_w_o <= w;
w_hold <= dat_i;
w_con <= w;
-- synthesis translate_off
test_word_1 <= w_con(16);
test_word_2 <= w_con(17);
test_word_3 <= w_con(18);
test_word_4 <= w_con(78);
test_word_5 <= w_con(79);
-- synthesis translate_on
end RTL; | gpl-3.0 |
freecores/usb_fpga_1_15 | examples/usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.vhd | 17 | 3116 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
| gpl-3.0 |
freecores/usb_fpga_1_15 | examples/usb-fpga-1.11/1.11c/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
ibm2030/IBM2030 | FMD2030_5-03D.vhd | 1 | 9132 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Manual Controls - Front panel switches Display, Store & Reset
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ManualControls IS
port
(
-- Inputs
E_SW_SEL_MAIN_STG,E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
E_CY_STOP_SMPL : IN STD_LOGIC; -- 03C
SEL_CHNL_DATA_XFER : IN STD_LOGIC; -- 12D
POWER_ON_RESET : IN STD_LOGIC; -- 14A
LOAD_KEY_SW : IN STD_LOGIC; -- 03C
CLOCK_OFF,CLOCK_ON : IN STD_LOGIC; -- 08A
WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC; -- 05D
READ_ECHO_1,READ_ECHO_2 : IN STD_LOGIC; -- 05D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_AUX_RD_CALL : IN STD_LOGIC; -- 12C
SEL_WR_CALL : IN STD_LOGIC; -- 12C
ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC; -- 04A
MAN_DSPLY_GUV_HUV : IN STD_LOGIC; -- 12C
CPU_WR_PWR : IN STD_LOGIC; -- 04D
LOAD_KEY_INLK : IN STD_LOGIC; -- 03C
POWER_OFF_SW : IN STD_LOGIC; -- 03C
IJ_SEL_SW,UV_SEL_SW : IN STD_LOGIC; -- 04C
SEL_AUX_WR_CALL : IN STD_LOGIC; -- 12C
USE_R : IN STD_LOGIC; -- 04D
SEL_T1 : IN STD_LOGIC;
CU_SALS : IN STD_LOGIC_VECTOR(0 to 1);
-- Switches
SW_DSPLY, SW_STORE,SW_SYS_RST : IN STD_LOGIC;
-- Outputs
MACH_RST_SW,MACH_RST_1,MACH_RST_3,MACH_RST_4,MACH_RST_5,MACH_RST_6,SYSTEM_RST_SW : OUT STD_LOGIC; -- Various
STG_MEM_SEL : OUT STD_LOGIC; -- 08D,04D,05B,06C
USE_MAN_DECODER_PWR : OUT STD_LOGIC; -- 04C,05C,05B
USE_MANUAL_DECODER : OUT STD_LOGIC; -- 04D,05B,04C,10C,07C,11C,05C
ALLOW_MAN_OPERATION : OUT STD_LOGIC; -- 03C,04A
MANUAL_DISPLAY : OUT STD_LOGIC; -- 06C,12C
MAN_STOR_OR_DSPLY : OUT STD_LOGIC; -- 04D,04A,06B,07B
MAN_STORE : OUT STD_LOGIC; -- 01C,06A,04B,06B,06C,01C,06A,04C
MAN_STORE_PWR : OUT STD_LOGIC; -- 05C,08B,06C,07B
STORE_S_REG_RST : OUT STD_LOGIC; -- 07B
CPU_SET_ALLOW_WR_LCH : OUT STD_LOGIC; -- 06C
MAN_RD_CALL : OUT STD_LOGIC; -- 05D,04D
GT_MAN_SET_MN : OUT STD_LOGIC; -- 07B
AUX_WRITE_CALL : OUT STD_LOGIC; -- 04B
ALLOW_WRITE : OUT STD_LOGIC; -- 05D,04A,06C,07A,04D,12C
ALLOW_WR_DLYD : OUT STD_LOGIC; -- 03A,04A,04D,12D,05D,03C,04B,06C,03B,04A
MANUAL_OPERATION : OUT STD_LOGIC; -- 03C
MAN_WRITE_CALL : OUT STD_LOGIC; -- 05D
STORE_R : OUT STD_LOGIC; -- 06C
-- Clocks
CONV_OSC : IN STD_LOGIC;
T1,T2 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ManualControls;
ARCHITECTURE FMD OF ManualControls IS
signal AC1D4 : STD_LOGIC;
signal WRITE_ECHO,READ_ECHO : STD_LOGIC;
signal MAN_RD_INLK : STD_LOGIC;
signal MAN_RD_CALL_LCH : STD_LOGIC;
signal MAN_WR_CALL : STD_LOGIC;
signal MAN_WR_CALL_RST : STD_LOGIC;
signal sMACH_RST_SW,sMACH_RST_3,sSYSTEM_RST_SW : STD_LOGIC;
signal sSTG_MEM_SEL : STD_LOGIC;
signal sUSE_MANUAL_DECODER : STD_LOGIC;
signal sALLOW_MAN_OPERATION : STD_LOGIC;
signal sMANUAL_DISPLAY : STD_LOGIC;
signal sMAN_STOR_OR_DSPLY : STD_LOGIC;
signal sMAN_STORE,sMAN_STORE2 : STD_LOGIC;
signal sSTORE_S_REG_RST : STD_LOGIC;
signal sCPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal sMAN_RD_CALL : STD_LOGIC;
signal sALLOW_WRITE : STD_LOGIC;
signal sALLOW_WR : STD_LOGIC;
signal sSTORE_R : STD_LOGIC;
signal UMD_LCH_Set,UMD_LCH_Reset,MD_LCH_Set,MS_LCH_Set,AW_LCH_Set,AW_LCH_Reset,
MW_LCH_Set,MW_LCH_Reset,MRC_LCH_Set,MRC_LCH_Reset,SR_LCH_Set,SR_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-03D
-- USE MAN DECODER
sSTG_MEM_SEL <= E_SW_SEL_MAIN_STG or E_SW_SEL_AUX_STG; -- AC1H3
STG_MEM_SEL <= sSTG_MEM_SEL;
sALLOW_MAN_OPERATION <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CLOCK_OFF); -- AC1C4,AC1G3 ?? Removed a NOT here
ALLOW_MAN_OPERATION <= sALLOW_MAN_OPERATION;
UMD_LCH_Set <= (sALLOW_MAN_OPERATION and SW_DSPLY) or (sALLOW_MAN_OPERATION and SW_STORE);
UMD_LCH_Reset <= E_CY_STOP_SMPL or sMACH_RST_3;
UMD_LCH: entity work.FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4
USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER;
USE_MAN_DECODER_PWR <= not E_CY_STOP_SMPL and sUSE_MANUAL_DECODER; -- AC1J4
-- MAN DSPLY
AC1D4 <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CONV_OSC); -- AC1G2,AC1D4 -- Inverter removed ??
MD_LCH_Set <= CLOCK_OFF and SW_DSPLY and AC1D4;
MD_LCH: entity work.FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ??
MANUAL_DISPLAY <= sMANUAL_DISPLAY;
-- MAN STORE R
sSTORE_S_REG_RST <= not CLOCK_ON and SW_STORE; -- AC1J6
STORE_S_REG_RST <= sSTORE_S_REG_RST;
MS_LCH_Set <= AC1D4 and sSTORE_S_REG_RST;
MS_LCH: entity work.FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5
MAN_STORE <= sMAN_STORE;
-- MAN_STORE_PWR <= sMAN_STORE; -- AC1F3 -- Need to delay this a bit
MAN_STORE_DELAY: entity work.AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3
MAN_STORE2_DELAY: entity work.AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3
sMAN_STOR_OR_DSPLY <= sMANUAL_DISPLAY or sMAN_STORE; -- AC1J2,AC1F3
MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY;
-- SYS RST
sSYSTEM_RST_SW <= SW_SYS_RST;
SYSTEM_RST_SW <= sSYSTEM_RST_SW;
sMACH_RST_SW <= SW_SYS_RST or POWER_ON_RESET or LOAD_KEY_SW;
MACH_RST_SW <= sMACH_RST_SW;
sMACH_RST_3 <= sMACH_RST_SW;
MACH_RST_1 <= sMACH_RST_3;
MACH_RST_3 <= sMACH_RST_3;
MACH_RST_4 <= sMACH_RST_3;
MACH_RST_5 <= sMACH_RST_3;
MACH_RST_6 <= sMACH_RST_3;
WRITE_ECHO <= WRITE_ECHO_1 or WRITE_ECHO_2; -- AA1J4
READ_ECHO <= READ_ECHO_1 or READ_ECHO_2; -- AA1K4
MAN_WR_CALL_RST <= WRITE_ECHO or sMACH_RST_3; -- AC1H3
sCPU_SET_ALLOW_WR_LCH <= (sMAN_STOR_OR_DSPLY and READ_ECHO) or (CPU_READ_PWR and T2); -- AA1K4 Wire-OR of negated signals
CPU_SET_ALLOW_WR_LCH <= sCPU_SET_ALLOW_WR_LCH;
-- ALLOW WR
AW_LCH_Set <= sCPU_SET_ALLOW_WR_LCH or SEL_AUX_RD_CALL;
AW_LCH_Reset <= sMACH_RST_3 or SEL_WR_CALL or MAN_WR_CALL or (ROAR_RESTT_STOR_BYPASS and RECYCLE_RST) or (CPU_WR_PWR and T2);
ALLOW_WRITE_LCH: entity work.FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3
ALLOW_WRITE <= sALLOW_WRITE;
DELAY_ALLOW_WR : entity work.AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7
ALLOW_WR_DLYD <= sALLOW_WR;
-- MAN WR CALL
MW_LCH_Set <= (sALLOW_WR and LOAD_KEY_INLK) or (sALLOW_WR and sSYSTEM_RST_SW) or (sALLOW_WR and POWER_OFF_SW) or (sMAN_STOR_OR_DSPLY and READ_ECHO);
MW_LCH_Reset <= CLOCK_ON or MAN_WR_CALL_RST;
MW_LCH: entity work.FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5
-- MAN RD INLK
MAN_RD_INLK_FL: entity work.FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4
-- MAN RD CALL
MRC_LCH_Set <= sSTG_MEM_SEL and not MAN_RD_INLK and sMAN_STOR_OR_DSPLY;
MRC_LCH_Reset <= not sMAN_STOR_OR_DSPLY or READ_ECHO;
MAN_RD_CALL_FL: entity work.FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2
sMAN_RD_CALL <= MAN_RD_CALL_LCH and not sALLOW_WR; -- AC1J2
MAN_RD_CALL <= sMAN_RD_CALL;
GT_MAN_SET_MN <= (MAN_RD_CALL_LCH and sUSE_MANUAL_DECODER and not sALLOW_WR) or
(sMANUAL_DISPLAY and IJ_SEL_SW and not sALLOW_WR) or
(sMANUAL_DISPLAY and UV_SEL_SW and not sALLOW_WR)
or MAN_DSPLY_GUV_HUV; -- AC1H4,AC1G3
AUX_WRITE_CALL <= (CPU_WR_PWR and T2) or SEL_AUX_WR_CALL; -- AA1K4,AA1C3
MANUAL_OPERATION <= sMAN_RD_CALL or MAN_WR_CALL or MAN_WR_CALL_RST or READ_ECHO;
-- STORE R
SR_LCH_Set <= MAN_WR_CALL or (T1 and USE_R);
SR_LCH_Reset <= SEL_T1 or (T1 and not CU_SALS(0) and CU_SALS(1));
SR_LCH: entity work.FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C
STORE_R <= sSTORE_R;
MAN_WRITE_CALL <= not READ_ECHO and MAN_WR_CALL and sSTORE_R; -- AC1G3
END FMD;
| gpl-3.0 |
ibm2030/IBM2030 | FMD2030_5-08A1.vhd | 1 | 7899 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08A1.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock generator - 4 phase (T1,T2,T3,T4 and P1,P2,P3,P4)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add registers to all clock outputs and delay rising edge of Px and Tx clocks
---------------------------------------------------------------------------
library IEEE;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Gates_package.all;
use work.all;
entity Clock is Port (
-- Clock stuff
CLOCK_IN : in std_logic;
T1,T2,T3,T4 : out std_logic;
P1,P2,P3,P4 : out std_logic;
OSC_T_LINE : out std_logic; -- 12A
M_CONV_OSC : out std_logic; -- 03C
P_CONV_OSC : out std_logic; -- 03D,03C
M_CONV_OSC_2 : out std_logic; -- 03C
CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B
CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D
CLOCK_START : in std_logic; -- 03C
MACH_RST_3 : in std_logic; -- 03D
Sw_Slow : in std_logic -- '1' to run slow
);
end Clock;
architecture FMD of Clock is
-- Following 2 lines to run clock at 5.33MHz (standard)
-- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0);
subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
constant RATIOFast : DividerSize := "00000000000000000000001000"; -- 5 gives 10MHz => 720ns cycle
-- Following 2 lines to run clock at 5Hz
constant RATIOSlow : DividerSize := "00100010010101010001000000"; -- 5M gives 10Hz => 720ms cycle
constant ZERO : DividerSize := (others=>'0');
constant ONE : DividerSize := (0=>'1',others=>'0');
signal DIVIDER : DividerSize := (others=>'0');
signal DIVIDER_MAX : DividerSize;
signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0';
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
signal P1D,P2D,P3D,P4D : STD_LOGIC;
signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A, N_OSC : STD_LOGIC;
begin
-- Divide the 50MHz FPGA clock down
-- 1.5us storage cycle means T1-4 takes 750ns, or 1.33MHz
-- The clock to generate the four phases is therefore 2.66MHz
-- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used
DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast;
OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0';
N_OSC <= not OSC;
process (CLOCK_IN)
begin
if CLOCK_IN'event and CLOCK_IN='1' then
if DIVIDER>=DIVIDER_MAX then
DIVIDER <= ZERO;
else
DIVIDER <= DIVIDER + ONE;
end if;
end if;
end process;
-- AC1K6,AC1C6 Probably have to re-do this lot to get it work
--SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4);
--SETS(2) <= DLYD_OSC not CLK(4) and CLK(1);
--SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2);
--SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1';
--RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1';
--RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1';
--RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1';
--RSTS(4) <= OSC and CLK(1);
--FLV(SETS,RSTS,CLK); -- AC1C6
-- The following process forms a ring counter
-- MACH_RST_3 forces the counter to 0001
-- If CLOCK_START is false, the counter stays at 0001
-- When CLOCK_START goes true, the counter cycles through
-- 0001 0001 0001 1001 1100 0110 0011 1001 1100 ....
-- When CLOCK_START subsequently goes false, the sequence continues
-- until reaching 0011, after which it stays at 0001
-- ... 1001 1100 0110 0011 0001 0001 0001 ...
-- The original counter used a level-triggered implementation, driven by
-- both levels of the OSC signal. Here it is easier to make it edge triggered
-- which requires a clock of twice the frequency, hence OSC2
process (OSC2, MACH_RST_3, CLOCK_START)
begin
if OSC2'event and OSC2='1' then
if OSC='0' then -- OSC Rising edge: +P1 (P4=1 & START) -P3 (P4=1) or -P1 +P3 (P2=1)
OSC <= '1';
if CLK(2)='1' or MACH_RST_3='1' then
CLK(1) <= '0';
elsif CLOCK_START='1' and CLK(4)='1' then
CLK(1) <= '1';
end if;
if CLK(4)='1' or MACH_RST_3='1' then
CLK(3) <= '0';
elsif CLK(2)='1' then
CLK(3) <= '1';
end if;
else -- OSC Falling edge: +P2 -P4 (P1=1) or -P2 +P4 (P3=1)
OSC <= '0';
if CLK(3)='1' or MACH_RST_3='1' then
CLK(2) <= '0';
elsif CLK(1)='1' then
CLK(2) <= '1';
end if;
if CLK(3)='1' or MACH_RST_3='1' then
CLK(4) <= '1';
elsif CLK(1)='1' then
CLK(4) <= '0';
end if;
end if;
end if;
end process;
OSC_T_LINEA <= OSC; -- AC1B6
OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSCD : FDCE port map(D=>N_OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); -- AC1C6
M_DLYD_OSC <= not OSC; -- AC1C6
DLYN_OSC <= OSC; -- AC1C6
-- P1 <= CLK(1);
-- P2 <= CLK(2);
-- P3 <= CLK(3);
-- P4 <= CLK(4);
-- Delay the rising edge of each P pulse to ensure that the T pulses never overlap
P1DLY: entity DelayRisingEdgeX port map (D=>CLK(1),CLK=>CLOCK_IN,Q=>P1D);
P2DLY: entity DelayRisingEdgeX port map (D=>CLK(2),CLK=>CLOCK_IN,Q=>P2D);
P3DLY: entity DelayRisingEdgeX port map (D=>CLK(3),CLK=>CLOCK_IN,Q=>P3D);
P4DLY: entity DelayRisingEdgeX port map (D=>CLK(4),CLK=>CLOCK_IN,Q=>P4D);
T1A <= P4D and P1D;
T2A <= P1D and P2D;
T3A <= P2D and P3D;
T4A <= P3D and P4D;
T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_OFFA <= not CLOCK_ONA;
CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P_CONV_OSCA <= OSC and CLOCK_OFFA;
P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSC_2A <= not(P_CONV_OSCA);
M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
end FMD;
| gpl-3.0 |
ibm2030/IBM2030 | ibm2030-switches.vhd | 1 | 22125 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-switches.vhd
-- Creation Date: 21:49:37 20/01/2010
-- Description:
-- 360/30 Front Panel switch handling
-- Some switches are provided by the pushbuttons and sliders on the S3BOARD
-- Rotary switches are connected externally with a mixture of scanning and
-- discrete inputs. In all cases the "Process" position is not connected so
-- omitting the switches entirely allows the system to run normally.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.01 2010-07-20
-- [LJW] Add Switch connection information, no functional change
--
--
-- Func Port Pin Conn A2 A B C D E F G H J AC E' ROS Rate Check
-- Ground 1 - - - - - - - - - - - - - -
-- +5V 2 - - - - - - - - - - - - - -
-- +3.3V Vcco 3 - - - - - - - - - - C C C C
-- Hex0 pa_io1 E6 4 * * * * * * * * * # - - - -
-- Hex1 pa_io2 D5 5 * * * * * * * * * # - - - -
-- Hex2 pa_io3 C5 6 * * * * * * * * * # - - - -
-- Hex3 pa_io4 D6 7 * * * * * * * * * # - - - -
-- ScanA pa_io5 C6 8 S - - - - - - - - - - - - -
-- ScanB pa_io6 E7 9 - S - - - - - - - - - - - -
-- ScanC pa_io7 C7 10 - - S - - - - - - - - - - -
-- ScanD pa_io8 D7 11 - - - S - - - - - - - - - -
-- ScanE pa_io9 C8 12 - - - - S - - - - - - - - -
-- ScanF pa_io10 D8 13 - - - - - S - - - - - - - -
-- ScanG pa_io11 C9 14 - - - - - - S - - - - - - -
-- ScanH pa_io12 D10 15 - - - - - - - S - - - - - -
-- ScanJ pa_io13 A3 16 - - - - - - - - S - - - - -
-- ScanAC pa_io14 B4 17 - - - - - - - - - S - - - -
-- E_Inner pa_io15 A4 18 - - - - - - - - - - * - - -
-- E_Outer pa_io16 B5 19 - - - - - - - - - - * - - -
-- ROS InhCFStop pa_io17 A5 20 - - - - - - - - - - - * - -
-- ROS Scan pa_io18 B6 21 - - - - - - - - - - - * - -
-- Rate_InstrStep ma2_db0 B7 22 - - - - - - - - - - - - * -
-- Rate_SingleCyc ma2_db1 A7 23 - - - - - - - - - - - - * -
-- Check_Diag ma2_db2 B8 24 - - - - - - - - - - - - - *
-- Check_Disable ma2_db3 A8 25 - - - - - - - - - - - - - *
-- Check_Stop ma2_db4 A9 26 - - - - - - - - - - - - - *
-- Check_Restart ma2_db5 B10 27 - - - - - - - - - - - - - *
--
-- * = Hex0,1,2,3 inputs have diodes from each of the 9 hex-encoded switches A-J (A to switch, K to FPGA, total 36 diodes)
-- # = The Address Compare switch (AC) is 10-position, unencoded, with diodes to perform the 0-9 encoding (total 15 diodes)
-- S = Scan output to switch common (one output at a time goes high to scan)
-- C = Common connection for non-scanned switches
-- Switch E' is the selector switch which is part of switch E and selects the inner, middle or outer rings
-- The "Proc" positions of the ROS, Rate and Check switches are not connected - if no switches are present then these 3 and the AC switch default to "Proc"
-- The "Middle" position of the E selector switch is not connected - the default is therefore the MS/LS ring
-- Pulldowns are provided by the FPGA input
--
-- Most of the remaining switches are connected to the on-board pushbuttons and slide switches:
-- Reset
-- Start
-- Stop
-- Load
-- Lamp Test
-- ROAR Reset
-- Display
-- Store
-- Check Reset
-- Set IC
-- Interrupt
-- Fast/Slow clock control
-- Two switches are not used:
-- Power Off
-- Timer Interrupt
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switches is
Port ( -- Raw switch inputs: (These can be modified to suit the board being used)
SwA_scan : out STD_LOGIC;
SwB_scan : out STD_LOGIC;
SwC_scan : out STD_LOGIC;
SwD_scan : out STD_LOGIC;
SwE_scan : out STD_LOGIC;
SwF_scan : out STD_LOGIC;
SwG_scan : out STD_LOGIC;
SwH_scan : out STD_LOGIC;
SwJ_scan : out STD_LOGIC;
SwAC_scan : out STD_LOGIC; -- Address Compare
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
SW_E_Inner, SW_E_Outer : in STD_LOGIC;
RawSw_Proc_Inh_CF_Stop, RawSw_Proc_Scan : in STD_LOGIC; -- ROS Control
RawSw_Rate_Single_Cycle, RawSw_Rate_Instruction_Step : in STD_LOGIC; -- Rate
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Scanned switch inputs - MAX7318 connections
SCL : out STD_LOGIC;
SDA : inout STD_LOGIC;
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
status_lamps : in STD_LOGIC_VECTOR(4 downto 0);
-- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
SwAP,SwBP,SwCP,SwDP,SwFP,SwGP,SwHP,SwJP : out STD_LOGIC;
SwE : out E_SW_BUS_Type;
Sw_PowerOff, Sw_Interrupt, Sw_Load : out STD_LOGIC; -- Right-hand pushbuttons
Sw_SystemReset, Sw_RoarReset, Sw_Start, Sw_SetIC, Sw_CheckReset,
Sw_Stop, Sw_IntTmr, Sw_Store, Sw_LampTest, Sw_Display : out STD_LOGIC; -- Left-hand pushbuttons
Sw_Proc_Inh_CF_Stop, Sw_Proc_Proc, Sw_Proc_Scan : out STD_LOGIC; -- ROS Control
Sw_Rate_Single_Cycle, Sw_Rate_Instruction_Step, Sw_Rate_Process : out STD_LOGIC; -- Rate
Sw_Chk_Chk_Restart, Sw_Chk_Diagnostic, Sw_Chk_Stop, Sw_Chk_Process, Sw_Chk_Disable : out STD_LOGIC; -- Check Control
Sw_ROAR_RESTT,Sw_ROAR_RESTT_WITHOUT_RST,Sw_EARLY_ROAR_STOP,Sw_ROAR_STOP, Sw_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_SYNC,Sw_ADDR_COMP_PROC,Sw_SAR_DLYD_STOP,Sw_SAR_STOP,Sw_SAR_RESTART : out STD_LOGIC; -- Address Compare
-- 1kHz clock signal
Clock1ms : out STD_LOGIC;
-- 50Hz Timer signal
Timer : out STD_LOGIC
);
end switches;
architecture Behavioral of switches is
subtype debounce is std_logic_vector(0 to 3);
signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal counter1k : std_logic_vector(15 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw,SwE_combined : std_logic_vector(3 downto 0) := "0000";
signal UseInner,UseMid,UseOuter : Boolean;
signal SwAC,SwAC_combined : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
RawSw_Display : STD_LOGIC; -- Right-hand pushbuttons
signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceSystemReset, debounceRoarReset, debounceStart, debounceSetIC, debounceCheckReset,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0';
signal sClock1ms : std_logic := '0';
signal max7318_switches : std_logic_vector(0 to 63);
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin
max7318 : entity panel_Switches port map (
clk => clk,
SCL => SCL,
SDA => SDA,
LEDs => status_lamps,
Switches => max7318_switches -- If the MAX7318 is not present, this vector should be all zero
);
Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk)
begin
if (rising_edge(clk)) then
if counter=sample then
if scan="0000" then SwA <= Hex_in or max7318_switches(12 to 15); SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in or max7318_switches(16 to 19); SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in or max7318_switches(20 to 23); SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in or max7318_switches(24 to 27); SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in or max7318_switches(36 to 39); end if;
if scan="0101" then SwF <= Hex_in or max7318_switches(28 to 31); SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in or max7318_switches(40 to 43); SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in or max7318_switches(44 to 47); SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in or max7318_switches(48 to 51); SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in or max7318_switches(4 to 7); end if;
end if;
if counter=divider then
counter<=(others=>'0');
if scan="1001" then
scan <= "0000";
else
scan <= scan + 1;
end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & (rawSw_Interrupt or max7318_switches(53));
debounceLoad <= debounceLoad(1 to 3) & (rawSw_Load or max7318_switches(52));
debounceSystemReset <= debounceSystemReset(1 to 3) & (rawSw_SystemReset or max7318_switches(63));
debounceRoarReset <= debounceRoarReset(1 to 3) & (rawSw_RoarReset or max7318_switches(61));
debounceStart <= debounceStart(1 to 3) & (rawSw_Start or max7318_switches(56));
debounceSetIC <= debounceSetIC(1 to 3) & (rawSw_SetIC or max7318_switches(60));
debounceCheckReset <= debounceCheckReset(1 to 3) & (rawSw_CheckReset or max7318_switches(58));
debounceStop <= debounceStop(1 to 3) & (rawSw_Stop or max7318_switches(55));
debounceIntTmr <= debounceIntTmr(1 to 3) & (rawSw_IntTmr or max7318_switches(62));
debounceStore <= debounceStore(1 to 3) & (rawSw_Store or max7318_switches(59));
debounceLampTest <= debounceLampTest(1 to 3) & (rawSw_LampTest or max7318_switches(57));
debounceDisplay <= debounceDisplay(1 to 3) & (rawSw_Display or max7318_switches(54));
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
if (debounceSystemReset = "0000") then Sw_SystemReset <= '0'; else if (debounceSystemReset = "1111") then Sw_SystemReset <= '1'; end if; end if;
if (debounceRoarReset = "0000") then Sw_RoarReset <= '0'; else if (debounceRoarReset = "1111") then Sw_RoarReset <= '1'; end if; end if;
if (debounceStart = "0000") then Sw_Start <= '0'; else if (debounceStart = "1111") then Sw_Start <= '1'; end if; end if;
if (debounceSetIC = "0000") then Sw_SetIC <= '0'; else if (debounceSetIC = "1111") then Sw_SetIC <= '1'; end if; end if;
if (debounceCheckReset = "0000") then Sw_CheckReset <= '0'; else if (debounceCheckReset = "1111") then Sw_CheckReset <= '1'; end if; end if;
if (debounceStop = "0000") then Sw_Stop <= '0'; else if (debounceStop = "1111") then Sw_Stop <= '1'; end if; end if;
if (debounceIntTmr = "0000") then Sw_IntTmr <= '0'; else if (debounceIntTmr = "1111") then Sw_IntTmr <= '1'; end if; end if;
if (debounceStore = "0000") then Sw_Store <= '0'; else if (debounceStore = "1111") then Sw_Store <= '1'; end if; end if;
if (debounceLampTest = "0000") then Sw_LampTest <= '0'; else if (debounceLampTest = "1111") then Sw_LampTest <= '1'; end if; end if;
if (debounceDisplay = "0000") then Sw_Display <= '0'; else if (debounceDisplay = "1111") then Sw_Display <= '1'; end if; end if;
if (timerCounter = divider100) then
timerOut <= not timerOut;
Timer <= timerOut;
timerCounter <= (others=>'0');
else
timerCounter <= timerCounter + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
Clock1kHz : process(clk)
begin
if (rising_edge(clk)) then
if counter1k = divider2000 then
counter1k <= (others => '0');
sClock1ms <= not sClock1ms;
else
counter1k <= counter1k + 1;
end if;
end if;
end process;
Clock1ms <= sClock1ms;
SwA_scan <= '1' when scan="0000" else '0';
SwB_scan <= '1' when scan="0001" else '0';
SwC_scan <= '1' when scan="0010" else '0';
SwD_scan <= '1' when scan="0011" else '0';
SwE_scan <= '1' when scan="0100" else '0';
SwF_scan <= '1' when scan="0101" else '0';
SwG_scan <= '1' when scan="0110" else '0';
SwH_scan <= '1' when scan="0111" else '0';
SwJ_scan <= '1' when scan="1000" else '0';
SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring
UseInner <= (SW_E_INNER='1' or max7318_switches(34)='1');
UseMid <= SW_E_INNER='0' and max7318_switches(34)='0' and SW_E_OUTER='0' and max7318_switches(35)='0';
UseOuter <= (SW_E_OUTER='1' or max7318_switches(35)='1');
SwE_combined <= SwE_raw or max7318_switches(36 to 39);
SwE.I_SEL <= '1' when SwE_combined="0000" and UseInner else '0';
SwE.J_SEL <= '1' when SwE_combined="0001" and UseInner else '0';
SwE.U_SEL <= '1' when SwE_combined="0010" and UseInner else '0';
SwE.V_SEL <= '1' when SwE_combined="0011" and UseInner else '0';
SwE.L_SEL <= '1' when SwE_combined="0100" and UseInner else '0';
SwE.T_SEL <= '1' when SwE_combined="0101" and UseInner else '0';
SwE.D_SEL <= '1' when SwE_combined="0110" and UseInner else '0';
SwE.R_SEL <= '1' when SwE_combined="0111" and UseInner else '0';
SwE.S_SEL <= '1' when SwE_combined="1000" and UseInner else '0';
SwE.G_SEL <= '1' when SwE_combined="1001" and UseInner else '0';
SwE.H_SEL <= '1' when SwE_combined="1010" and UseInner else '0';
SwE.FI_SEL <= '1' when SwE_combined="1011" and UseInner else '0';
SwE.FT_SEL <= '1' when SwE_combined="1100" and UseInner else '0';
-- Mid ring
SwE.MS_SEL <= '1' when SwE_combined="0000" and UseMid else '0';
SwE.LS_SEL <= '1' when SwE_combined="0001" and UseMid else '0';
-- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_combined="0000" and UseOuter else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_combined="0001" and UseOuter else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_combined="0010" and UseOuter else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_combined="0011" and UseOuter else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_combined="0100" and UseOuter else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_combined="0101" and UseOuter else '0';
SwE.Q_SEL <= '1' when SwE_combined="0110" and UseOuter else '0';
SwE.C_SEL <= '1' when SwE_combined="0111" and UseOuter else '0';
SwE.F_SEL <= '1' when SwE_combined="1000" and UseOuter else '0';
SwE.TT_SEL <= '1' when SwE_combined="1001" and UseOuter else '0';
SwE.TI_SEL <= '1' when SwE_combined="1010" and UseOuter else '0';
SwE.JI_SEL <= '1' when SwE_combined="1011" and UseOuter else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare
SwAC_combined <= SwAC or max7318_switches(4 to 7);
Sw_ADDR_COMP_PROC <= '1' when SwAC_combined="0000" else '0';
Sw_SAR_DLYD_STOP <= '1' when SwAC_combined="0001" else '0';
Sw_SAR_STOP <= '1' when SwAC_combined="0010" else '0';
Sw_SAR_RESTART <= '1' when SwAC_combined="0011" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC_combined="0100" else '0';
Sw_ROAR_RESTT <= '1' when SwAC_combined="0101" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC_combined="0110" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC_combined="0111" else '0';
Sw_ROAR_STOP <= '1' when SwAC_combined="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC_combined="1001" else '0';
-- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' or max7318_switches(0)='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' and max7318_switches(0 to 1)="00" else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' or max7318_switches(1)='1' else '0';
-- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' or max7318_switches(3)='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' and max7318_switches(2 to 3)="00" else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' or max7318_switches(2)='1' else '0';
-- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' or max7318_switches(11)='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' or max7318_switches(8)='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' or max7318_switches(10)='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' and max7318_switches(8 to 11)="0000"else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' or max7318_switches(9)='1' else '0';
-- Unimplemented switches
RawSw_PowerOff <= '0';
-- Pushbuttons
RawSw_SystemReset <= pb(0);
RawSw_Start <= pb(1);
RawSw_Load <= pb(2);
RawSw_Stop <= pb(3);
-- Slide switches
RawSw_IntTmr <= sw(0);
RawSw_Display <= sw(1);
RawSw_Store <= sw(2);
RawSw_Interrupt <= sw(3);
RawSw_RoarReset <= sw(4);
RawSw_SetIC <= sw(5);
RawSw_CheckReset <= sw(6);
RawSw_LampTest <= sw(7);
end behavioral;
| gpl-3.0 |
ibm2030/IBM2030 | panel_LEDs.vhd | 1 | 10199 | ---------------------------------------------------------------------------
-- Copyright © 2015 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: panel_LEDs.vhd
-- Creation Date: 16:08:00 16/06/2015
-- Description:
-- 360/30 Front Panel LED lamp drivers
-- This drives 256 front panel LEDs via Maxim SPI/I2C multiplexed drivers
-- There are two options:
-- MAX7219 8 x 8 multiplexed LEDs
-- MAX7951 Charlieplexed LEDs
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity panel_LEDs is
Generic (
Clock_divider : integer := 25; -- Default for 50MHz clock is 2, for 25MHz = 40ns = 20ns + 20ns. 25 gives 2MHz.
Number_LEDs : integer := 256
);
Port ( -- Lamp input vector
LEDs : in std_logic_vector(0 to Number_LEDs-1);
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Driver outputs
MAX7219_CLK : out std_logic;
MAX7219_DIN : out std_logic; -- LEDs 00-3F
MAX7219_LOAD : out std_logic; -- Data latched on rising edge
MAX6951_CLK : out std_logic;
MAX6951_DIN : out std_logic; --
MAX6951_CS0 : out std_logic; -- LEDs 00-3F Data latched on rising edge
MAX6951_CS1 : out std_logic; -- LEDs 40-7F Data latched on rising edge
MAX6951_CS2 : out std_logic; -- LEDs 80-BF Data latched on rising edge
MAX6951_CS3 : out std_logic -- LEDs C0-FF Data latched on rising edge
);
end panel_LEDs;
architecture Behavioral of panel_LEDs is
signal clk_out : std_logic := '0';
signal shift_reg64 : std_logic_vector(63 downto 0);
signal reg_counter : integer range 0 to 11 := 0;
signal bit_counter16 : integer range 0 to 16 := 0;
signal bit_counter64 : integer range 0 to 64 := 0;
-- MAX7219 data is 8b address and 8b data
-- Address is:
-- 00 No-op (unused)
-- 01 Digit 0 (in position 0)
-- ...
-- 08 Digit 7 (in position 7)
-- 09 Decode mode (fixed 00 in position 8)
-- 0A Intensity (fixed at 0F in position 9)
-- 0B Scan limit (fixed at 07 in position 10)
-- 0C Shutdown (fixed at 01 in position 11)
-- 0F Display test (fixed at 00 in position 12)
type registers7219 is array(0 to 3,0 to 12) of std_logic_vector(15 downto 0);
signal max7219_vector : registers7219 :=
(
0 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
1 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
2 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
),
3 => (
0 => "0000000100000000",
1 => "0000001000000000",
2 => "0000001100000000",
3 => "0000010000000000",
4 => "0000010100000000",
5 => "0000011000000000",
6 => "0000011100000000",
7 => "0000100000000000",
8 => "0000100100000000",
9 => "0000101000001111",
10 => "0000101100000111",
11 => "0000110000000001",
12 => "0000111100000000"
)
);
-- MAX6951 data is 8b Address and 8b Data
-- Address is:
-- 00 No-op (unused)
-- 01 Decode mode (fixed at default)
-- 02 Intensity (fixed at 0F in position 8)
-- 03 Scan limit (fixed at 07 in position 9)
-- 04 Configuration (fixed at 01 in position 10)
-- 07 Display test (fixed at 00 in position 11)
-- 60 Digit 0 (in position 0)
-- ...
-- 67 Digit 7 (in position 0)
type registers6951 is array(0 to 3,0 to 11) of std_logic_vector(15 downto 0);
signal max6951_vector : registers6951 :=
(
0 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
1 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
2 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
),
3 => (
0 => "0110000000000000",
1 => "0110000100000000",
2 => "0110001000000000",
3 => "0110001100000000",
4 => "0110010000000000",
5 => "0110010100000000",
6 => "0110011000000000",
7 => "0110011100000000",
8 => "0000001000001111",
9 => "0000001100000111",
10 => "0000010000000001",
11 => "0000011100000000"
)
);
begin
gen_clk : process (clk) is
variable divider : integer := Clock_divider;
begin
if rising_edge(clk) then
if (divider=0) then
divider := Clock_divider;
clk_out <= not clk_out;
MAX7219_CLK <= not clk_out;
MAX6951_CLK <= not clk_out;
else
divider := divider - 1;
end if;
end if;
end process;
max7219 : process (clk_out) is
begin
if falling_edge(clk_out) then
if bit_counter64=0 then
bit_counter64 <= 64;
case reg_counter is
when 0 to 7 =>
-- Mapping is:
-- b7 = DP = XX7
-- b6 = A = XX0
-- b5 = B = XX1
-- b4 = C = XX2
-- b3 = D = XX3
-- b2 = E = XX4
-- b1 = F = XX5
-- b0 = G = XX6
shift_reg64 <=
max7219_vector(3,reg_counter)(15 downto 8) & LEDs(reg_counter*8+192+7) & LEDs(reg_counter*8+192 to reg_counter*8+192+6) &
max7219_vector(2,reg_counter)(15 downto 8) & LEDs(reg_counter*8+128+7) & LEDs(reg_counter*8+128 to reg_counter*8+128+6) &
max7219_vector(1,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 64+7) & LEDs(reg_counter*8+ 64 to reg_counter*8+ 64+6) &
max7219_vector(0,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 0+7) & LEDs(reg_counter*8+ 0 to reg_counter*8+ 0+6);
when others =>
shift_reg64 <=
max7219_vector(3,reg_counter) &
max7219_vector(2,reg_counter) &
max7219_vector(1,reg_counter) &
max7219_vector(0,reg_counter);
end case;
if reg_counter=12 then
reg_counter <= 0;
else
reg_counter <= reg_counter + 1;
end if;
MAX7219_DIN <= '0';
MAX7219_Load <= '1';
else
bit_counter64 <= bit_counter64 - 1;
shift_reg64 <= shift_reg64(62 downto 0) & '0';
MAX7219_DIN <= shift_reg64(63);
MAX7219_Load <= '0';
end if;
end if;
end process;
max6951 : process (clk_out) is
variable dev_counter : integer range 0 to 3 := 3;
variable reg_counter : integer range 0 to 11 := 0;
variable bit_counter : integer range 0 to 16 := 16;
variable shift_reg : std_logic_vector(16 downto 0);
begin
if falling_edge(clk_out) then
if bit_counter=0 then
bit_counter := 16;
case reg_counter is
when 0 to 7 =>
shift_reg := '0' & max6951_vector(dev_counter,reg_counter)(15 downto 8) & LEDs(dev_counter*64+reg_counter*8 to dev_counter*64+reg_counter*8+7);
when others =>
shift_reg := '0' & max6951_vector(dev_counter,reg_counter);
end case;
if reg_counter=11 then
if dev_counter=0 then
dev_counter := 3;
else
dev_counter := dev_counter - 1;
end if;
reg_counter := 0;
else
reg_counter := reg_counter + 1;
end if;
else
bit_counter := bit_counter - 1;
shift_reg := shift_reg(15 downto 0) & '0';
end if;
if bit_counter=16 then
MAX6951_CS0 <= '1';
MAX6951_CS1 <= '1';
MAX6951_CS2 <= '1';
MAX6951_CS3 <= '1';
else
if dev_counter=0 then
MAX6951_CS0 <= '0';
else
MAX6951_CS0 <= '1';
end if;
if dev_counter=1 then
MAX6951_CS1 <= '0';
else
MAX6951_CS1 <= '1';
end if;
if dev_counter=2 then
MAX6951_CS2 <= '0';
else
MAX6951_CS2 <= '1';
end if;
if dev_counter=3 then
MAX6951_CS3 <= '0';
else
MAX6951_CS3 <= '1';
end if;
end if;
MAX6951_DIN <= shift_reg(16);
end if;
end process;
end behavioral;
| gpl-3.0 |
freecores/usb_fpga_1_15 | examples/usb-fpga-2.16/2.16b/mmio/fpga/ucecho.vhd | 4 | 3683 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 |
freecores/usb_fpga_1_15 | examples/usb-fpga-1.2/intraffic/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
ibm2030/IBM2030 | FMD2030_5-08C.vhd | 1 | 6564 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Multiplexor Channel registers FO & FB
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Revise XH & XL BU latches amd MPX_INTRPT signal
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PH;
use work.FLVL;
entity MpxFOFB is
Port ( MPX_ROS_LCH : in STD_LOGIC;
S_REG_0 : in STD_LOGIC;
SET_FW : in STD_LOGIC;
S_REG_1 : in STD_LOGIC;
S_REG_2 : in STD_LOGIC;
T3 : in STD_LOGIC;
CK_SALS : in STD_LOGIC_VECTOR (0 to 3);
PK_SALS : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
MACH_RST_SET_LCH : in STD_LOGIC;
SALS_CS : in STD_LOGIC_VECTOR (0 to 3);
SALS_SA : in STD_LOGIC;
CK_0_PWR : in STD_LOGIC;
R_REG : in STD_LOGIC_VECTOR (0 to 8);
T1,T2 : in STD_LOGIC;
XXH : out STD_LOGIC;
XH : out STD_LOGIC;
XL : out STD_LOGIC;
FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC;
FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC;
SUPPR_CTRL_LCH : out STD_LOGIC;
OP_OUT_SIG : out STD_LOGIC;
MPX_OPN_LT_GATE : out STD_LOGIC;
MACH_RST_MPX : out STD_LOGIC;
MPX_INTRPT : out STD_LOGIC;
SX1_MASK : out STD_LOGIC;
EXT_TRAP_MASK_ON : out STD_LOGIC;
SX2_MASK : out STD_LOGIC;
FAK : out STD_LOGIC;
SET_BUS_O_CTRL_LCH : out STD_LOGIC;
MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8);
clk : in STD_LOGIC);
end MpxFOFB;
architecture FMD of MpxFOFB is
signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC;
signal XXH_IN,XH_IN,XL_IN : STD_LOGIC;
signal XXHBU,XHBU,XLBU : STD_LOGIC;
signal sMACH_RST_MPX : STD_LOGIC;
signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
alias KP is PK_SALS;
signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC;
signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
begin
-- XL, XH and XXL bits and backup
XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU);
XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH);
X_SET <= T3SET or sMACH_RST_MPX;
XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
XXH <= sXXH;
XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
-- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH);
XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
XH <= sXH;
XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
-- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH);
XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
XL <= sXL;
-- MPX Flags
T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3));
sMACH_RST_MPX <= MACH_RST_SET_LCH;
MACH_RST_MPX <= sMACH_RST_MPX;
CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2;
CHNL_L <= sMACH_RST_MPX or CK11XX;
MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP);
FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP;
CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2;
OPN_L <= sMACH_RST_MPX or CKX11X;
MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH);
FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH;
CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2;
SUPPR_L <= sMACH_RST_MPX or CK1X1X;
SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH);
SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH;
CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2;
OUT_L <= sMACH_RST_MPX or CKX1X1;
OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG);
OP_OUT_SIG <= not notOP_OUT_SIG;
MPX_OPN_LT_GATE <= CKX11X;
-- External Interrupt Masks
-- ?? Should the R_REG bits be inverted before use?
CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask;
SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);
-- MPX BUS OUT REGISTER
sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA;
FAK <= sFAK;
sSET_BUS_O_CTRL <= sFAK and CK_0_PWR;
SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL;
BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O
BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1);
MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG);
end FMD;
| gpl-3.0 |
TUCircle/homework | VHDL/Aufgabe4.4.vhdl | 2 | 573 | --Aufgabe 4.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_4 is
port(x: in STD_LOGIC_VECTOR(4 downto 1);
y: out STD_LOGIC);
end entity;
architecture test of Aufgabe4_4 is
begin
process(x)
variable z: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
--Bereich links oben
z(0) := x(1) and x(2);
z(1) := x(1) or x(2);
if x(3) = '0' then
z(2) := z(0);
else
z(2) := z(1);
end if;
--Abtastregister
if RISING_EDGE(x(4)) then
y <= z(2);
end if;
end process;
end architecture;
| gpl-3.0 |
nanomolina/MIPS | DATAPATH/imem.vhd | 3 | 2427 | -------------------------------------------------------------------------------
--
-- Title : imem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : imem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria ROM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo puede contener hasta 64
-- instrucciones (palabras) de 32 bits(aunque podria direccionar mas memoria)
-- Inicialmente, al salir de reset, carga en la memoria el archivo MIPS_SOFT_FILE
-- con el programa a ejecutar.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
--library WORK;
--use WORK.components.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(5 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is
constant MAX_BOUND: Integer := 64;
constant MIPS_SOFT_FILE: string := "mips_pipeline.dat";
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable index, result: integer;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to MAX_BOUND-1 loop -- set all contents low
mem(conv_integer(i)) := CONV_STD_LOGIC_VECTOR(0, 32);
end loop;
index := 0;
FILE_OPEN(mem_file, MIPS_SOFT_FILE, READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch)-character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch)-character'pos('a')+10;
else report "Format error on line " & integer'image(index)
severity error;
end if;
end loop;
mem(index) := CONV_STD_LOGIC_VECTOR(result, 32);
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(CONV_INTEGER(a));
wait on a;
end loop;
end process;
end;
| gpl-3.0 |
TUCircle/homework | VHDL/Aufgabe4.3.vhdl | 2 | 740 | --Aufgabe 4.3
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_3 is
port(a: in UNSIGNED(3 downto 0);
b: in UNSIGNED(3 downto 0);
s: in STD_LOGIC_VECTOR(1 DOWNTO 0);
y: out UNSIGNED(3 downto 0));
end entity;
architecture test of Aufgabe4_3 is
begin
process(a,b,s)
variable v0,v1,v2,v3,v4: UNSIGNED(3 downto 0);
begin
--Linker Bereich + Oben Rechts
v0 := a and b;
v1 := a or b;
if s(0) = '0' then
v2 := v0;
v3 := a;
else
v2 := v1;
v3 := not(a);
end if;
--Addierer / Links Unten
v4 := v3 + b;
if s(1) = '0' then
y <= v2;
else
y <= v4;
end if;
end process;
end architecture;
| gpl-3.0 |
nanomolina/MIPS | DATAPATH/datapath.vhd | 1 | 3065 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.components.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end entity;
architecture BH of datapath is
signal DUMPS, PCSrc, ZEROs : std_logic;
signal PC1, PCNext, PC_T, PCOut, INSTRUCTION,
PCPlus4, SrcA, PCJump, QUATRO,
PCBranch, SignImm, SrcB, Result,
RD1, RD2, AD1, AD2, ReadData, WriteData, ALUResult : std_logic_vector(31 downto 0);
signal SIGNIN : std_logic_vector(15 downto 0);
signal A1, A2, A3, IMEMIN : std_logic_vector(5 downto 0);
signal instr5_1, instr5_2, instr5_3, instr5_4, WriteReg : std_logic_vector(4 downto 0);
begin
ADDER1: adder port map(
a => PCOut,
b => QUATRO,
y => PCPlus4
);
ADDER2: adder port map(
a => AD1 ,
b => PCPlus4,
y => PCBranch
);
FLOPR1: flopr port map(
d => PC1 ,
rst => reset,
clk => clk,
q => PCOut
);
MUX2_1: mux2 port map(
d0 => PCPlus4,
d1 => PCBranch,
s => PCSrc,
y => PCNext
);
MUX2_2: mux2 port map(
d0 => PCNext,
d1 => PCJump,
s => Jump,
y => PC1
);
MUX2_3: mux2 port map(
d0 => WriteData,
d1 => SignImm,
s => AluSrc,
y => SrcB
);
MUX2_4: mux2 port map(
d0 => ALUResult,
d1 => ReadData,
s => MemToReg,
y => Result
);
MUX2_5: mux2 generic map(
MAX => 5
)
port map(
d0 => instr5_1,
d1 => instr5_2,
s => RegDst,
y => WriteReg
);
IMEM1: imem port map(
a => IMEMIN,
rd => INSTRUCTION
);
REGFILE1: regfile port map(
ra1 => instr5_3,
ra2 => instr5_4,
wa3 => WriteReg,
wd3 => Result,
we3 => RegWrite,
clk => clk,
rd1 => SrcA,
rd2 => WriteData
);
SIGNEXT: sign port map(
a => SIGNIN,
y => SignImm
);
ALU1: alu port map(
a => SrcA,
b => SrcB,
alucontrol => AluControl,
result => ALUResult,
zero => ZEROs
);
SL2a: sl2 port map(
a => SignImm,
y => AD1
);
DMEM1: dmem port map(
a => ALUResult,
wd => WriteData,
clk => clk,
we => MemWrite,
rd => ReadData,
dump => DUMPS
);
QUATRO <= x"00000004"; --REVISAR!!!
PCJump <= PCPlus4(31 downto 28) & INSTRUCTION(25 downto 0) & "00";
PCSrc <= Branch and ZEROs;
IMEMIN <= PCOut(7 downto 2);
instr5_1 <= INSTRUCTION(20 downto 16);
instr5_2 <= INSTRUCTION(15 downto 11);
instr5_3 <= INSTRUCTION(25 downto 21);
instr5_4 <= INSTRUCTION(20 downto 16);
SIGNIN <= INSTRUCTION(15 downto 0);
instr <= INSTRUCTION;
pc <= PCOut;
end architecture;
| gpl-3.0 |
phst/flycheck | test/resources/language/vhdl.vhd | 4 | 48 | entity syntax_error is
end entity syntax_error
| gpl-3.0 |
nanomolina/MIPS | PIPELINE/datapath.vhd | 1 | 5014 | library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity;
architecture arq_datapath of datapath is
component fetch
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end component;
component decode
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end component;
component execute
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc : in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end component;
component memory
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end component;
component writeback
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end component;
signal PcBranchM_s, InstrF_s, PCF_s, PCPlus4F_s,
InstrD_s,RD2E_s, RD1E_s, SignImmE_s,
AluOutM_s, WriteDataM_s, ReadDataW_s,
ResultW_s : std_logic_vector(31 downto 0);
signal ZeroM_s, PcSrcM_s : std_logic;
signal A3_s, RtE_s, RdE_s : std_logic_vector(4 downto 0);
begin
Fetch1: fetch port map(
jumpM => Jump,
PcSrcM => PCSrcM_s, --changing
clk => clk,
reset => reset,
PcBranchM => PCBranchM_s,
InstrF => InstrD_s, --changing
PCF => pc,
PCPlus4F => PCPlus4F_s --changing
);
Decode1: decode port map(
A3 => A3_s, --changing
InstrD => InstrD_s, --changing
Wd3 => ResultW_s,
RegWrite => RegWrite,
clk => clk,
RtD => RtE_s,
RdD => RdE_s,
SignImmD => SignImmE_s,
RD1D => RD1E_s,
RD2D => RD2E_s
);
Execute1: execute port map(
RD1E => RD1E_s, --changing
RD2E => RD2E_s,
PCPlus4E => PCPlus4F_s,
SignImmE => SignImmE_s, --changing
RtE => RtE_s, --changing
RdE => RdE_s,
RegDst => RegDst,
AluSrc => AluSrc,
AluControl => AluControl,
WriteRegE => A3_s,
ZeroE => ZeroM_s,
AluOutE => AluOutM_s,
WriteDataE => WriteDataM_s,
PCBranchE => PCBranchM_s
);
Memory1: memory port map(
AluOutM => AluOutM_s, --changing
WriteDataM => WriteDataM_s, --changing
ZeroM => ZeroM_s, --changing
MemWrite => MemWrite,
Branch => Branch,
clk => clk,
dump => dump,
ReadDataM => ReadDataW_s,
PCSrcM => PCSrcM_s --Posee el mismo nombre (posible conflicto futuro) illak:Para nada!
);
WriteBack1: writeback port map(
AluOutW => AluOutM_s, --changing
ReadDataW => ReadDataW_s, --changing
MemToReg => MemToReg,
ResultW => ResultW_s --changing
);
instr <= instrD_s;
end arq_datapath;
| gpl-3.0 |
nanomolina/MIPS | PIPELINE/flopr.vhd | 3 | 439 | library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
| gpl-3.0 |
nanomolina/MIPS | PIPELINE/memory.vhd | 2 | 1083 | library ieee;
use ieee.std_logic_1164.all;
entity memory is
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end entity;
architecture e_arq of memory is
component dmem
port (
a, wd: in std_logic_vector (31 downto 0);
clk,we: in std_logic;
rd: out std_logic_vector (31 downto 0);
dump: in std_logic);
end component;
signal temp1: std_logic_vector(31 downto 0);
signal temp2: std_logic_vector(31 downto 0);
begin
temp1 <= "0000000000000000" & AluOutM(31 downto 16);
temp2 <= "0000000000000000" & WriteDataM(31 downto 16);
dmem1: dmem port map(
a => temp1,
wd => temp2,
clk => clk,
we => MemWrite,
rd => ReadDataM, --salida
dump => dump);
PCSrcM <= ZeroM and Branch; --salida
end architecture;
| gpl-3.0 |
nanomolina/MIPS | prueba/sl2.vhd | 3 | 372 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity sl2 is
port(
a: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0)
);
end entity;
architecture bh of sl2 is
begin
process(a)
begin
y <= a(29 downto 0) & "00";
end process;
end bh;
| gpl-3.0 |
nanomolina/MIPS | prueba/decode.vhd | 2 | 1374 | library ieee;
use ieee.std_logic_1164.all;
entity decode is
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end entity;
architecture d_arq of decode is
component regfile
port (
ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0));
end component;
component sign
port (
a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end component;
begin
regfile1: regfile port map(
ra1 => InstrD(25 downto 21),
ra2 => InstrD(20 downto 16),
wa3 => A3,
wd3 => Wd3,
we3 => RegWrite,
clk => clk,
rd1 => RD1D, --salida
rd2 => RD2D); --salida
sign1: sign port map(
a => InstrD(15 downto 0),
y => SignImmD); --salida
RtD <= InstrD(20 downto 16); --salida
RdD <= InstrD(15 downto 11); --salida
end architecture;
| gpl-3.0 |
nanomolina/MIPS | prueba/datapath.vhd | 1 | 13001 | library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity;
architecture arq_datapath of datapath is
component fetch
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end component;
component decode
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end component;
component execute
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc : in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end component;
component memory
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end component;
component writeback
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end component;
component IF_ID
port(
clk : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
pcplus4_in : in std_logic_vector(31 downto 0);
instr_out : out std_logic_vector(31 downto 0);
pcplus4_out : out std_logic_vector(31 downto 0)
);
end component;
component ID_EX
port(
RtD_in : in std_logic_vector(4 downto 0);
RdD_in : in std_logic_vector(4 downto 0);
SignImm_in : in std_logic_vector(31 downto 0);
RD1_in : in std_logic_vector(31 downto 0);
RD2_in : in std_logic_vector(31 downto 0);
PCPlus4_in : in std_logic_vector(31 downto 0);
MemToReg_in:in std_logic;
MemWrite_in:in std_logic;
Branch_in:in std_logic;
AluSrc_in:in std_logic;
RegDst_in:in std_logic;
RegWrite_in:in std_logic;
Jump_in:in std_logic;
alucontrol_in: in std_logic_vector (2 downto 0);
clk : in std_logic;
PCPlus4_out : out std_logic_vector(31 downto 0);
MemToReg_out:out std_logic;
MemWrite_out:out std_logic;
Branch_out:out std_logic;
AluSrc_out:out std_logic;
RegDst_out:out std_logic;
RegWrite_out:out std_logic;
Jump_out:out std_logic;
alucontrol_out: out std_logic_vector (2 downto 0);
RtD_out : out std_logic_vector(4 downto 0);
RdD_out : out std_logic_vector(4 downto 0);
SignImm_out : out std_logic_vector(31 downto 0);
RD1_out : out std_logic_vector(31 downto 0);
RD2_out : out std_logic_vector(31 downto 0)
);
end component;
component EX_MEM
port(
Zero_in : in std_logic;
AluOut_in : in std_logic_vector(31 downto 0);
WriteData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
PCBranch_in : in std_logic_vector(31 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Jump_in: in std_logic;
Branch_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Jump_out: out std_logic;
Branch_out: out std_logic;
Zero_out : out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
WriteData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0);
PCBranch_out : out std_logic_vector(31 downto 0)
);
end component;
component MEM_WB
port(
AluOut_in : in std_logic_vector(31 downto 0);
ReadData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
ReadData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0)
);
end component;
signal PCBranchE_out_s, InstrF_out_s, InstrIFID_out_s , PCF_s, PCPlus4F_out_s,
PCPlus4IFID_out_s, RD2D_out_s,RD2IDEX_out_s, RD1D_out_s,RD1IDEX_out_s,
SignImmD_out_s,SignImmIDEX_out_s,
AluOutE_out_s,AluOutEXMEM_out_s, WriteDataE_out_s,WriteDataEXMEM_out_s, ReadDataM_out_s,
ReadDataMEMWB_out_s,PCPlus4IDEX_out_s,
ResultW_s, PCBranchEXMEM_out_s, AluOutMEMWB_out_s: std_logic_vector(31 downto 0);
signal ZeroE_out_s,ZeroEXMEM_out_s, PcSrcM_s,MemToRegIDEX_out_s, MemToRegEXMEM_out_s,
MemToRegMEMWB_out_s,MemWriteIDEX_out_s,BranchIDEX_out_s,BranchEXMEM_out_s,
AluSrcIDEX_out_s,RegDstIDEX_out_s,RegWriteIDEX_out_s,RegWriteEXMEM_out_s,
RegWriteMEMEB_out_s,JumpIDEX_out_s, JumpEXMEM_out_s,MemWriteEXMEM_out_s: std_logic;
signal A3E_out_s,A3EXMEM_out_s,A3MEMWB_out_s, RtD_out_s, RtIDEX_out_s, RdD_out_s, RdIDEX_out_s: std_logic_vector(4 downto 0);
signal AluControlIDEX_out_s: std_logic_vector(2 downto 0);
begin
Fetch1: fetch port map(
jumpM => JumpEXMEM_out_s,
PcSrcM => PcSrcM_s,
clk => clk,
reset => reset,
PcBranchM => PCBranchEXMEM_out_s,
InstrF => InstrF_out_s,
PCF => pc,
PCPlus4F => PCPlus4F_out_s
);
IF_ID1: IF_ID port map(
clk => clk,
instr_in => InstrF_out_s,
pcplus4_in => PCPlus4F_out_s,
instr_out => InstrIFID_out_s,
pcplus4_out => PCPlus4IFID_out_s
);
Decode1: decode port map(
A3 => A3MEMWB_out_s,
InstrD => InstrIFID_out_s,
Wd3 => ResultW_s,
RegWrite => RegWriteMEMEB_out_s,
clk => clk,
RtD => RtD_out_s,
RdD => RdD_out_s,
SignImmD => SignImmD_out_s,
RD1D => RD1D_out_s,
RD2D => RD2D_out_s
);
ID_EX1: ID_EX port map(
RtD_in => RtD_out_s,
RdD_in => RdD_out_s,
SignImm_in => SignImmD_out_s,
RD1_in => RD1D_out_s,
RD2_in => RD2D_out_s,
PCPlus4_in => PCPlus4IFID_out_s,
MemToReg_in => MemToReg,
MemWrite_in => MemWrite,
Branch_in => Branch,
AluSrc_in => AluSrc,
RegDst_in => RegDst,
RegWrite_in => RegWrite,
Jump_in => Jump,
alucontrol_in => AluControl,
clk => clk,
PCPlus4_out => PCPlus4IDEX_out_s,
MemToReg_out => MemToRegIDEX_out_s,
MemWrite_out => MemWriteIDEX_out_s,
Branch_out => BranchIDEX_out_s,
AluSrc_out => AluSrcIDEX_out_s,
RegDst_out => RegDstIDEX_out_s,
RegWrite_out => RegWriteIDEX_out_s,
Jump_out => JumpIDEX_out_s,
alucontrol_out => AluControlIDEX_out_s,
RtD_out => RtIDEX_out_s,
RdD_out => RdIDEX_out_s,
SignImm_out => SignImmIDEX_out_s,
RD1_out => RD1IDEX_out_s,
RD2_out => RD2IDEX_out_s
);
Execute1: execute port map(
RD1E => RD1IDEX_out_s,
RD2E => RD2IDEX_out_s,
PCPlus4E => PCPlus4IDEX_out_s,
SignImmE => SignImmIDEX_out_s,
RtE => RtIDEX_out_s,
RdE => RdIDEX_out_s,
RegDst => RegDstIDEX_out_s,
AluSrc => AluSrcIDEX_out_s,
AluControl => AluControlIDEX_out_s,
WriteRegE => A3E_out_s,
ZeroE => ZeroE_out_s,
AluOutE => AluOutE_out_s,
WriteDataE => WriteDataE_out_s,
PCBranchE => PCBranchE_out_s
);
EX_MEM1: EX_MEM port map(
Zero_in => ZeroE_out_s,
AluOut_in => AluOutE_out_s,
WriteData_in => WriteDataE_out_s,
WriteReg_in => A3E_out_s,
PCBranch_in => PCBranchE_out_s,
RegWrite_in => RegWriteIDEX_out_s,
MemToReg_in => MemToRegIDEX_out_s,
MemWrite_in => MemWriteIDEX_out_s,
Jump_in => JumpIDEX_out_s,
Branch_in => BranchIDEX_out_s,
clk => clk,
RegWrite_out => RegWriteEXMEM_out_s,
MemToReg_out => MemToRegEXMEM_out_s,
MemWrite_out => MemWriteEXMEM_out_s,
Jump_out => JumpEXMEM_out_s,
Branch_out => BranchEXMEM_out_s,
Zero_out => ZeroEXMEM_out_s,
AluOut_out => AluOutEXMEM_out_s,
WriteData_out => WriteDataEXMEM_out_s,
WriteReg_out => A3EXMEM_out_s,
PCBranch_out => PCBranchEXMEM_out_s
);
Memory1: memory port map(
AluOutM => AluOutEXMEM_out_s,
WriteDataM => WriteDataEXMEM_out_s,
ZeroM => ZeroEXMEM_out_s,
MemWrite => MemWriteEXMEM_out_s,
Branch => BranchEXMEM_out_s,
clk => clk,
dump => dump,
ReadDataM => ReadDataM_out_s,
PCSrcM => PCSrcM_s
);
MEM_WB1: MEM_WB port map(
AluOut_in => AluOutEXMEM_out_s,
ReadData_in => ReadDataM_out_s,
WriteReg_in => A3EXMEM_out_s,
RegWrite_in => RegWriteEXMEM_out_s,
MemToReg_in => MemToRegEXMEM_out_s,
clk => clk,
RegWrite_out => RegWriteMEMEB_out_s,
MemToReg_out => MemToRegMEMWB_out_s,
AluOut_out => AluOutMEMWB_out_s,
ReadData_out => ReadDataMEMWB_out_s,
WriteReg_out => A3MEMWB_out_s
);
WriteBack1: writeback port map(
AluOutW => AluOutEXMEM_out_s,
ReadDataW => ReadDataMEMWB_out_s,
MemToReg => MemToRegMEMWB_out_s,
ResultW => ResultW_s
);
instr <= InstrF_out_s;
end architecture;
| gpl-3.0 |
mzakharo/usb-de2-fpga | src/devreq.vhd | 1 | 11651 | -- devreq.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- USB 2.0 Device Request handler
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. Handles control endpoint requests sent by the USB Host
-- 2. Sends USB Descriptors, defined in usb_inc.vhd to the host
-- 4. Can be used to implement Vendor Specific Device Requests
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.usb_inc.all;
use work.isp_hal.all;
package devreq_inc is -- component declaration package
type devreq_in_t is record
hal : drv_iface_out_t;
req : device_request_t;
req_rdy : bit;
end record;
type devreq_out_t is record
hal : drv_iface_in_t;
done : bit;
configured : bit;
end record;
component devreq is
port(
clk : in std_logic;
reset : in std_logic;
d : in devreq_in_t;
q : out devreq_out_t);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.devreq_inc.all;
use work.usb_inc.all;
use work.isp_hal.all;
use work.isp_inc.all;
entity devreq is
port(
clk : in std_logic;
reset : in std_logic;
d : in devreq_in_t;
q : out devreq_out_t);
end devreq;
architecture handler of devreq is
type not_reset_t is record
hal : drv_iface_in_t;
tx_greater : signed(8 downto 0);
tx_len : std_logic_vector(7 downto 0);
descr_len : unsigned(7 downto 0);
cnt : unsigned(4 downto 0);
inline : bit_vector(2 downto 0);
tmpcnt : unsigned(4 downto 0);
neq : bit;
end record;
type state_t is (idle , decode, dev_descr, conf_descr, zero, stall, set_addr, wait_ready);
constant dev_len : integer := byte_deviceDescriptor(CRD_devDesc)'length; --bits
constant conf_len : integer := CRD_Full_Desc'length; --bits
--length of functions
constant fsend_ep_len : integer := 2;
constant fdev_len : integer := dev_len / 2 / 8;
constant fconf_len : integer := conf_len /2 /8;
constant fstall_len : integer := 2;
constant fvalid_len : integer := 1;
constant fset_addr_len : integer := 2;
--total number of functions
constant func_states : integer := fsend_ep_len + fdev_len + fconf_len + fstall_len + fvalid_len + fset_addr_len;
type reg_t is record
nr : not_reset_t;
state : state_t;
shift : bit_vector(func_states downto 0);
configured : bit;
end record;
signal r, rin : reg_t;
function swap( constant word : in std_logic_vector(0 to 15) ) return std_logic_vector is
begin
return( word(8 to 15) & word(0 to 7));
end function swap;
begin --architecture
comb : process(r,d)
variable v : reg_t;
constant fsend_ep_start : integer := 0;
alias r_fsend_ep : bit_vector(fsend_ep_len -1 downto 0) is r.shift(fsend_ep_len -1 + fsend_ep_start downto fsend_ep_start);
alias v_fsend_ep : bit_vector(fsend_ep_len- 1 downto 0) is v.shift(fsend_ep_len -1 + fsend_ep_start downto fsend_ep_start);
constant fdev_start : integer := fsend_ep_len + fsend_ep_start;
alias r_fdev_descr : bit_vector(fdev_len-1 downto 0) is r.shift(fdev_len -1 + fdev_start downto fdev_start);
alias v_fdev_descr : bit_vector(fdev_len-1 downto 0) is v.shift(fdev_len -1 + fdev_start downto fdev_start);
constant fconf_start : integer := fdev_len + fdev_start;
alias r_fconf_descr : bit_vector(fconf_len-1 downto 0) is r.shift(fconf_len -1 + fconf_start downto fconf_start);
alias v_fconf_descr : bit_vector(fconf_len-1 downto 0) is v.shift(fconf_len -1 + fconf_start downto fconf_start);
constant fstall_start : integer := fconf_len + fconf_start;
alias r_fstall : bit_vector(fstall_len-1 downto 0) is r.shift(fstall_len -1 + fstall_start downto fstall_start);
alias v_fstall : bit_vector(fstall_len-1 downto 0) is v.shift(fstall_len -1 + fstall_start downto fstall_start);
constant fvalid_start : integer := fstall_len + fstall_start;
constant fset_addr_start : integer := fvalid_len + fvalid_start;
alias r_fset_addr : bit_vector(fset_addr_len-1 downto 0) is r.shift(fset_addr_len -1 + fset_addr_start downto fset_addr_start);
alias v_fset_addr : bit_vector(fset_addr_len-1 downto 0) is v.shift(fset_addr_len -1 + fset_addr_start downto fset_addr_start);
type func_data_t is array(func_states - 1 downto 0) of data_t;
type func_cmd_t is array(func_states - 1 downto 0) of cmd_t;
variable datas : func_data_t;
variable cmds : func_cmd_t;
begin
--parameters
v := r;
case r.state is
when idle =>
if (d.req_rdy = '1') then
v.state := decode ;
end if;
v.configured := '0';
when decode =>
--INFO: not checking bRequestType - assuming all requests are USB_STANDARD request types
if (d.req.bRequest(3 downto 0) = GET_DESCRIPTOR and d.req.wValue(11 downto 8) = desc_DEVICE) then
v.state := dev_descr;
elsif (d.req.bRequest(3 downto 0) = GET_DESCRIPTOR and d.req.wValue(11 downto 8) = desc_CONFIGURATION) then
v.state := conf_descr;
elsif (d.req.bRequest(3 downto 0) = SET_CONFIGURATION) then
v.state := zero;
v.configured := '1';
elsif (d.req.bRequest(3 downto 0) = SET_ADDRESS) then
v.state := set_addr;
else
v.state := stall;
end if;
v.nr.inline := (others => '0');
v.nr.descr_len :=to_unsigned(0, 8);
when dev_descr => v.state := wait_ready;
v_fsend_ep(0) := '1';
v.nr.descr_len :=to_unsigned((dev_len / 8), 8);
v.nr.inline(0) := '1';
when conf_descr => v.state := wait_ready;
v.nr.descr_len :=to_unsigned((conf_len / 8), 8);
v_fsend_ep(0) := '1';
v.nr.inline(1) := '1';
when zero => v.state := wait_ready;
v_fsend_ep(0) := '1';
v.nr.inline(2) := '1';
when stall => v.state := wait_ready;
v_fstall(0) := '1';
when set_addr => v.state := wait_ready;
v_fset_addr(0) := '1';
v.nr.inline(2) := '1';
when wait_ready =>
if r.shift(func_states) = '1' then
v.state := idle;
end if;
end case;
q.done <= r.shift(func_states);
q.configured <= r.configured and r.shift(func_states);
--output length to send for desc_DEVICE
v.nr.tx_greater := ('0' & signed(d.req.wLength(7 downto 0)) - ('0' & signed(r.nr.descr_len)) ); --INFO: max length supported : 0xFF
if (r.nr.tx_greater(r.nr.tx_greater'high) = '1') then --wLength < sizeof(desc_DEVICE)
v.nr.tx_len := d.req.wLength( 7 downto 1) & '0'; -- force even transactions - just to make the code simpler for now.
else
v.nr.tx_len := std_logic_vector(r.nr.descr_len);
end if;
if (unsigned(to_stdlogicvector(r_fsend_ep)) /= 0) then
v.nr.tmpcnt := unsigned(r.nr.tx_len(5 downto 1)); --divide by 2
else
v.nr.tmpcnt := r.nr.cnt;
end if;
if (r.nr.cnt /= 0) then
v.nr.neq := '1';
else
v.nr.neq := '0';
end if;
--function shift register
if(d.hal.rdy = '1') then
v_fsend_ep := (r_fsend_ep sll 1);
v_fsend_ep(0) := v_fsend_ep(0) or r_fset_addr(r_fset_addr'high);
--inline functions
v_fdev_descr(v_fdev_descr'low) := r_fsend_ep(r_fsend_ep'high) and r.nr.inline(0);
v_fconf_descr(v_fconf_descr'low) := r_fsend_ep(r_fsend_ep'high) and r.nr.inline(1);
v.nr.cnt := r.nr.tmpcnt - 1; -- descriptor words left to send
for i in v_fdev_descr'high downto 1 loop
v_fdev_descr(i) := r_fdev_descr(i - 1) and r.nr.neq;
end loop;
for i in v_fconf_descr'high downto 1 loop
v_fconf_descr(i) := r_fconf_descr(i - 1) and r.nr.neq;
end loop;
v_fstall := (r_fstall sll 1);
v_fset_addr := (r_fset_addr sll 1);
v.shift(fvalid_start) := ((r.nr.inline(0) or r.nr.inline(1)) and not(v.nr.neq))
or (r_fsend_ep(r_fsend_ep'high) and r.nr.inline(2));
end if;
if(d.hal.rdy = '1') then
v.shift(func_states) := r.shift(fvalid_start) or r_fstall(r_fstall'high);
else
v.shift(func_states) := '0';
end if;
--initialize temporary outputs
for i in 0 to (func_states - 1) loop
cmds(i) := (others => '0');
datas(i) := (others => '0');
end loop;
--function code start
if (r.shift(fsend_ep_start) = '1') then
cmds(fsend_ep_start) := otg_wr_cmd;
datas(fsend_ep_start) := Wr_Buffer & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fsend_ep_start + 1) = '1') then
cmds(fsend_ep_start + 1) := otg_wr;
datas(fsend_ep_start+ 1) := x"00" & r.nr.tx_len;
end if;
for i in 0 to r_fdev_descr'high loop
if (r.shift(fdev_start + i) = '1' )then
cmds(fdev_start + i) := otg_wr;
datas(fdev_start + i) := swap(byte_deviceDescriptor(CRD_devDesc)( i*16 to (i+1)*16 - 1)) ;
end if;
end loop;
for i in 0 to r_fconf_descr'high loop
if (r.shift(fconf_start + i) = '1' )then
cmds(fconf_start + i) := otg_wr;
datas(fconf_start + i) := swap(CRD_Full_Desc( i*16 to (i+1)*16 - 1));
end if;
end loop;
if (r.shift(fstall_start) = '1') then
cmds(fstall_start) := otg_wr_cmd;
datas(fstall_start) := EPSTS_STALL & EPINDEX4EP0_CONTROL_OUT;
end if;
if (r.shift(fstall_start + 1) = '1') then
cmds(fstall_start + 1) := otg_wr_cmd;
datas(fstall_start+ 1) := EPSTS_STALL & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fvalid_start) = '1') then
cmds(fstall_start + 1) := otg_wr_cmd;
datas(fstall_start+ 1) := Validate & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fset_addr_start) = '1') then
cmds(fset_addr_start) := otg_wr_cmd;
datas(fset_addr_start) := Wr_DcAddress;
end if;
if (r.shift(fset_addr_start + 1) = '1') then
cmds(fset_addr_start + 1) := otg_wr;
datas(fset_addr_start + 1) := x"0080" or d.req.wValue;
end if;
--function code end
--assign temporary outputs to real outputs
v.nr.hal.data := (others => '0');
v.nr.hal.cmd := (others => '0');
for i in 0 to (func_states - 1) loop
v.nr.hal.cmd := v.nr.hal.cmd or cmds(i);
v.nr.hal.data := v.nr.hal.data or datas(i);
end loop;
--and finally
q.hal.cmd <= r.nr.hal.cmd;
q.hal.data <= r.nr.hal.data;
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.state <= idle;
r.shift <= (others => '0');
r.configured <= '0';
elsif rising_edge(clk) then
r.shift <= rin.shift;
r.state <= rin.state;
r.configured <= rin.configured;
end if;
end process;
seq_nrst : process
begin
wait until rising_edge(clk);
r.nr <= rin.nr;
end process;
end architecture;
| gpl-3.0 |
RowdyRajan/GestureControlInterfaceCapstone | usb_component.vhd | 1 | 2445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out std_logic := '1';
USB_RD_N : out std_logic := '1';
USB_RST_N : out std_logic := '1';
USB_CS_N : out std_logic := '1';
USB_INT0 : in std_logic; -- Irq 0 DC
USB_INT1 : in std_logic; -- Irq 1 HC
-- Avalon Memory-Mapped-Slave interface Device Controller (DC)
avs_dc_address : in std_logic;
avs_dc_writedata : in std_logic_vector(15 downto 0);
avs_dc_write_n : in std_logic;
avs_dc_read_n : in std_logic;
avs_dc_CS_n : in std_logic;
avs_dc_readdata : out std_logic_vector(15 downto 0);
avs_dc_irq : out std_logic;
-- Avalon Memory-Mapped-Slave interface Host Controller (HC)
-- Probably will not use this interface.
avs_hc_address : in std_logic;
avs_hc_writedata : in std_logic_vector(15 downto 0);
avs_hc_write_n : in std_logic;
avs_hc_read_n : in std_logic;
avs_hc_CS_n : in std_logic;
avs_hc_readdata : out std_logic_vector(15 downto 0);
avs_hc_irq : out std_logic
);
end usb;
architecture connections of usb is
begin
-- Send interrupt from DE2 connection to proper controller
avs_dc_irq <= USB_INT0;
avs_hc_irq <= USB_INT1;
-- Two cases possible, using the host controller or the device controller.
-- Currently this does not full function for the Host Controller (HC) but we
-- do not need it for our project. I do intend to make the architecture generalized later
--Device controller signals
USB_DATA <= avs_dc_writedata when avs_dc_write_n = '0' else (others => 'Z'); -- Only does device controller
avs_dc_readdata <= USB_DATA when avs_dc_read_n = '0' else (others => 'Z');
avs_hc_readdata <= USB_DATA when avs_hc_read_n = '0' else (others => 'Z');
USB_CS_N <= '1' when avs_dc_CS_n = '0' and avs_hc_CS_n = '0' else '0';
USB_ADDR(0) <= '1';
USB_ADDR(1) <= avs_dc_address;
USB_RD_N <= avs_dc_read_n; --Just Ignoring the HC controller right now.
USB_WR_N <= avs_dc_write_n;
USB_RST_N <= reset_n;
end architecture connections;
-- If chip_select_n == 1
-- I could probably have processes for chip select for toggling between HC and DC
-- but for now i'm less than interested when I havent gotten DC working
| gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/clock_control/clock_control_inst.vhd | 1 | 432 | component clock_control is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component clock_control;
u0 : component clock_control
port map (
inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
ena => CONNECTED_TO_ena, -- .ena
outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
);
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 7 | 20294 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd | 7 | 17071 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_wr_demux;
-------------------------------------------------------------------------------
entity axi_sg_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_skid2mm_buf;
architecture implementation of axi_sg_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_sg_v4_1_2.axi_sg_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_ddiv_29_no_dsp_64/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd | 24 | 10812 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qQi3Y4JwXl7Wn1bhw/jkWXomzcSGtpscU8oJ2LP5BaQ4u6xazRA/mCI7R7F7nM8pFppzcZaDXNDE
awD47nPbZg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XEx6ZQwv4Vw0EbtXfrnFwRRFXeTMxOSVFFjSp4WS2rNJPGaN9nwYF1MaeUImPm4WplW12OharfDq
Bd4u1MUCQQngaNAVq+qRFAvic1cEd9UAgV4uPUwUSymN6YFqFEFkBe61gVOGTL52kYCmFP5vOloO
dikNZ7RmkwcL7Ou/YYw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UywbMvtnenvwrN54J6TLUnt5D0ugRYGbxGf5WbHCK4A1QpEpAfm4/GMahChLWJyd4co3Sz7iyKnH
pF9fGrDxABF6+XgD+gYwW23LAy4Oeb9L0L1aN751j4eBb+SD/nc7Bvs8/PkG8AEiUh9nBX5X8YRG
y6Rb3Rd/oLAqNh8W+hPkvGvBFD04EpmUO8rwABNMEgzx5Xy8UXIXF2/AM7g88q21LLpqxJfNMKwc
6gETTRFn2W/DccvMkQI7J7x9xQ6JV6mIj8jQumxc8qNgDnzszgiyVxNRBCbBRnwlMks8aj9jaN+c
Q9ZuNT/eHVXIa0PtrhWx3BPMD5whsOfdpvUEtw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IBlJOJ+ArISdfMfaRPeRQ6J3iITR2w063jCi0nfoo8xkZyikCIgC9XnNEXDlcFlFoTYVTWN/pOxk
4QfAUNIYHfGqxHDX5K+igT3JRGAbHW05TeT9Sz1Tz76BTL6nuYHgWbYb3HeB+sQkWjFalZjk90K9
XOlFLMcGKo/KZGkFFlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UEgDruV4ZmeVXnBh8PLE5PuwbRj5lmOC7K+F+X4e7otBgmXMWFiIeN9GvRB5AtCI3/1G6zC73gYH
FO1FlbS2tVmG3nSzVkxcIbEL+1KFosqyivHaeWvPOnefymg/10sYhtvZO5E9oVciuYijzF2w37f1
+4YL/FQqMk/yNEOV2k/YRjnqc95iWqQ5vwJ7EAAYrnHnFINWKUvk3N1gH1DwIaBkwK3QG8wkmtAX
tNp4c+AqLhfwpZ56BFnB83iDMJP8wmqSaW72Ckgh0dX309k5OA2Zw6uWUoRzYaEgJQgRL7ARYuPh
p4NJLaGXoIG5duhfCAO8zu+TZ49OCwwXulwm7w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Dzk2duxGRZEP8sfvf9eFwJMWv7R8u0eFXVvb80PbacYDJR7yK9uh327PG+jja/aceEUlDK9iE6LC
gHnAhFB+s2L7gbIN5CB2gJ0O/y7NGTy9/CsMTLlUlECbh3egIAKJ4XZKfIxn7KP1Sb+n2k7aQe6H
FXUgDSit0mOXHhQbzQUUynd81PYcQDMSRTrNLn6L7GsMV/N4KrCegZhOpHfzOVEhHkkMpIWSGBt4
0gsZSXY4FhbaybuBSsYhSiZIPMLy3FxEgJQeZbHMHTyJaibx6UrTayI4VnRP4BA2lHpY4yqhwdrI
qYhnt3+HhAvJgqexSmEUJ4YIMZSxSGHLYZZeHg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
tW2/X7vSNTSNWTm7mZMxJdbdpKlStwr1I2qOFJ5Ka5TPzAVTCBLrYL4wfzEsW2WiYzahzut11iu7
5bkkJT+XY+nnYDeLNaq9oZiKa46GbDQij9eBRfPL4WutrsGLOo3fvXshpE7s1cbaUjni1PDq4wTh
EL9JQf19Q/tfUTIS8l2q1O3vfHO7sJmfhdqmHl5Ktimz7VNjbz0rvZ0uRl7uilTFub2TEM3GRc3t
TMRCiEOxxRqThe2a/cipcAUKtFv86RhNvsViCgkdnfM6o106htfeD0j5NVgDahXmjWbUdjtrsbwN
YcVuy++v85Qz68E2AepsHg7f66vVNbL9/SP2KMfSqE9doHIhDKbDuAbWNcDI2VTZLUYOmJ5Kw2FZ
d0/JLJDBOaokoqSI/DvDiIGhFRiDl9+6XMZAgGdte8G20M9Ps147hkc92w2z+yFvg4U2jnSgbJqa
ZYmykyqv7agwv+czqNxVQZNfu43fgyaSYzQ6w8nZQSG4nR3fn+n0l3QiM49Zm3fpQrGVHx/Qnj/o
M9aWaHGtNPFQtvMkQNas7JoGWH5BQdt+AaCsqkzwUEvVBPrMBH9CH02yNe9P4K/RNDZxKJr/RKOV
Tv9k6pR947oH8Gr2d2IohTh+TvADSbtOYLaynJWRI8AvI1zXGI5dhE7Bw/9a6t2RilvNyhVvifpT
wOwEXl5vEBTnNR/aZTzoebQxh+DylXdXEFEIx7vauRyWlaqw3lKTZ+AJUxfu7+JY+12iBie0TbIV
TbGcYlPmwlW6CdESmqPhpY4fn1asS6Y6Z8p276/LDQRhBO1ou7XUwTdFt4eJnRYGA6OEYk8hYE0d
/7uRv9iH2WfgiOLjEoLfZULxKDaTrD+yyYjxmlmy4RJZXZ+N1yx7HKT3PYQebQ4LJ49CzIHIFhEm
vw3JXv/e9BoYvNFyOyW37841mVjZ5kmhMgSN7qxfD4yxDZIjbZvja1l5gPjf2cksl0f6MNmJUQMm
Npb4QspTvctQM3Xs0RReGW8rsGx87jdkIZtyyMtrBh8eHYizh+XHOSShcmjZHI3QhhXUu9mUAt9P
NKyadBOAsnhGz8wmcsTXdQJLhb9I/m5eZHrZWn3O+rkZ1dWfTPZMvAPcqsZ/TK3UPBtlE2slkuJa
LMw0829WNWRTfc+DQbnqoMc0HZaXi8HvWlPy17QBDxyHDy77ldoKQ6NqUyjtzx1QjshPz86DCpOp
F7shN2NVyl4ZxfLfwqfuhvKjx1PhHOuP0OShsQHF4lxChiecG31o1IajAytfNo59/ophgMucatc7
3U+HM+arslNmzOF+cLdT4xVKZnja7dmacQVTJxb+QQ+V3RchUpF8rRNxWnT7BzgyBKWKG031xiCW
vRy4T9/URmISo8gRJBUKfg0hwpWMeTneh23Jc1K1rNv3n4BM4Tn8LIGWl89/MTHpc2NTS3F+mH/h
gyXNYdFnO2zHCkGNV7kE/m6EtJ7FE3p2TfOE13ru++DKSStPiYEXE9ZjCeYQ/tUNzPAv9plO2NeB
gjpIUuasbCXp+u9w4aF+yNZh2XZ5myOdGjLcmFXgkOUO7pg7cGafAMkjhc6N9WJymPsQDF+O67k4
XYC9f41zr0ZeBAOkoHb53CDEAvhlwO6Iy3GArzY/P0QA6QJW639o2eRJefKiQj1KE1/VMoEVmAxV
6s0K3d0gcVCbuzZ787mNPNCqga+WVjvPcpXQtxTbDz0/FcmygGIe+CnlJfA2yyg66O9rEfRvh9B2
dNafVldov+knrH3S2tr+Wosc0wNZ4zkTpEJjSCKSLUG/bBR181QOEmeuVc1zf36hGPYjkIFcuvQ5
PBThUx8XIKXTp+NpQ0QDr+k9CuuBu0Yd81j8xgeA1iFttygeOX66Xlrc712S7f0kqBaHDS+s9xyC
4vo0nfQhWmGchTFEfTAouehpfP5B139UtAA6KP4bRxHTT1OY2Ea9UiZzp/P/nn4r4DuZQyGQec7D
HX6maHIJjDcqo8WHES7PJFp4VDmj993iZEG7WV/oWFKwlx/zXCquUIq5zs3YGg7yilvtPOu3iWJC
/luNGDe/2DfDz+wg8U1veMIVxxB6XOEHlbUF1d5KbR/nW5bpuwUm4gZZ4FBVf/LlZA+FLXnz24Ht
btgYnVzanXTje+kI9DPtbo5SMb/Yj/a86ZX8lNPd8NlD5JTGfJVF1Drz2xT9VVwc53CmuDBa8/oq
tmhFOPSgdBCGA6dJ7FpC1/lOPDrvsqQFlhmVId+9nI82su1VULN5ShNRxcJ4e5rtAq9Klc1hRa7t
7DLJLE1mYFT2vOWEtJs0GPbvv+xFPmLe5LgQJ8IPAhQnPUFRJiQ3V6V65+ynkk0g61N7kA4juK9J
BoL/UgzJacoH4VQ7NwPN5QtLP10i1jjwjyMdRCcTEC+vYbPHjKCuY0ReXBplVQrHfugz+XxK7Aa5
WqwRinPKKz5kfac/AXqvVc920JbOk0PtolAduXFB8PLvoCkysjPXVlbd8GB2vye88GnnjL/Rgxj7
BRJyBjoxq7ADd/t1+hJf63m0nvnzlcLBOQsJl0LroOL0w3IZ5B686FlLCwnvUgQggWy4C1yLTjbF
djm44zxEyXb2PlEo5Pc9uPHd9vggLOS6+BHSaDTgfWDvcwy8aR7LAOLR51affr5GAIuuK8ukNsrz
Z+O4Sc5Gi1WFQ7wcdTq6VaTyccFNguYk/2kkFsgO5BfJCuf8IQFGAijoQQE6V4Czy2FR4dYmSxCI
nnR8LKYk/jKvcaNL+OQHsyWgmftYGvKeKGQIAyVNbo6k6jC+6/qRfhm9BYIYrEZBAOA4bWaNkYCB
zau4xGVKDC4MdR9K695wiLa49antO2UuTQyArAieV7uAG63lpGZ8/BnRhOpu1QSoxmKll6gbTtxV
tcp+1AK6btonR4zTinHNnh4n8Wsrd8C7HADR1+jr3QNWDWxEjEDNxDh7JcKH625h/dHDkdfpgGCN
gjXtJ3PQN4fWnRgX8RXYeoF6fEHGtpfP7zsWHdSqx7IYvPHRLE/kzWYS1DdPj3DVOkPuRrXWk3yc
0xOWx77YXV1NX5bgGol50tV35AA6BGDsp+hmigsuYp1GQBazPbeZBvq6aKd/NlAAN4aigeiKQ8hk
jUsXPyP7ReERwP3dU79+bPyWAxPOITt8ID2j8s6witX2TIam01RttDgW8C/0hdQn1kTWN9JH+5yS
fr82DzHAxoEMqicCcDByJywl8+MM6U6HsQXwQZS62S2fvEMA1cZ1jnNjb73P9zP5ozEEKlwIViav
rw/3OEJPBwQtiH7Y5OzqCu5sRcw5LrdI/PqC7Zbu6hClcF7G6BIivy3S7JLdvZESOz07EIYmtdHd
Gq5aTZcLoJDIJQweutlvw7t55cthv3hEOFPwC/Q4AVZTPfhvsBCnChyfTr81BhT5P0RO4qv3Wtwd
ZjmPqYd8ySxElussVSO+P5BVPO3Mz7Q59/Y50ePAJkPakOd9qR5bmVGOKconjMYsD5hVfyIYkmu/
m9xjPUEN0qGzgE5bHpag7cHV3N1yRR2UN4VDSl9Gd1VbpT+hEHzCbWd6Gk/m3BPHOYqW8krSn9Wx
4bZmV7v51c715VCHCRu0t8866ApmIwFTJLbKyiINqKJgq39ZhZIPN5awtwpZ1YEEtaqUg9seeboC
fQpIHD/vXMUp/qi3TEFGTrItnJEwahEv+PKAeTlHuL/S5ibCxMP8vL5F3Dljy0kI5odFDgIjJZqe
x9y41RnFluPgWqZHJU2HdL9M6VLUc15NIKEjFXBhac5bbsomP8YcD+hBQseXvPr7gaLI3IYh+GSh
YHUhCZMw1daobXLGIHhYznaf3x78Xkp9wAltmQgI4TxYBVzenjssbn30S+cEYZZbgZ2dmqwF8uZp
n9IDIIvWY7arh0DWHVh19nfVVIkpaDHoOT89G0jkzbVLEUDibcypPfJICXESIG7hoiXOxyQd5kzf
Wt7UzSxbV+sqyaBvtJWKyePJFDIV6ycfhN3DdzdyBUeG/z2H3Sd+jmC23Ftqp/qUMpoinctKcxDy
rYzSUAjFLR7C438nxw5/zkDv6WLnl/1IsnRPA7NhKYZhdbTC5JMFy71aJgmOtyc3Vew3RjCLdUIL
BdEjV06WE7p3z83+2WtrJjwQ1xwYCDxMAmQbvrunqWDJrucStxDQC8FEjNYTtn/IMR1CEL8XB9os
2GjZAOlhgLXOG1wMl0ezNmCOKPDwaUvRVHhLxy+LSpA1YdpJDSWQBUcPNvJWItHGpkIT1HBGDmSe
TpemSP1uAF6kHJmzPornufCSO76cAA2myPK0iwbazNhh3na5l2Kw/tUWrQgaPIyODYeC4sOF9v/+
qPXAof8cdUcX5uzpqeaw0w7xN3gf7PYyD/a3Ce/Z/zbVx/xpyCtmbXJwnFy72816pXdN7EgTPAo6
ziRdKUefSJWrYbkzAnTM5NdFtPC323OgdWz/Sn+bzBePwe/fWJmkGYl7KGHXCyi051HZl3kZcX0m
gtN7impQpOhdV4UqAtHAw6jatSmf77tPkdGfMPoodclpvOGAelju43kxPdpV4J55qzDDiBtPhU/R
pMnwbhEGDcxqWaTdNDMj6MLferdIpqMtX25biYIVS+r2XlbV4I1C+HrPM7E16jtMtFPQTiiE4J94
gLzZRk4f8tMrPUJffJTnxdROtLp5fZDBOTKAXO4qiRYny14MhgTzTRn7Sli0WSlabDCTYfs78IEt
UP46WZQhO5+BYaPgqbGssAAGag2ndG335AcXwAHjLWIGs6FtjWCwPw8GnrjjWVxDpKROCWKgzkFI
dYn1tyAFANDnaD69BGE5i57r/IMwkrSDOUkEpfclqIIV3xCULa5OPzBi4G4dyhraDF4dWPkWVUU1
MxhCrRKZxRSV4mwW9PrfnQU6D36g1mmbmihWDXtsFwXcUqHkxPGvwa49ww4LdxIVaWKtVUM8G1c0
2SiohVcwrIj3UQekyLv6jLTHObwmfuPU//jesduS9iBVAAt89gzrwY8RuND1TtEZXLXaZj/cVIoW
zqBozMJUELWjy5MkaOyk92i2ChuWcMICGV26H/YOyQjJnoEvZsBQdpw5aen0gBUG0AzPlEgJDChv
KHCc/LyNFrqn/zbDnOE0fFKKIgfcXlNahX1NvEXlPWVTPEjKu+Ak42krBFVzbL4qlYSO/62gHpv+
u0wh/a5F6XZsR6diYZt92Kut5+OzxsjUW3VrL462Qt4z3RHjtFvF1mfxNagQBSCfnPKf+1gtCG6Z
xG9bHNkc+NRry3KVp7Ykv8xzBzCTvDeAKHcYmxj6D5UCb1fV4L0uS+gRQOhN23oPe+/wYVzhsWG1
YpMnLA5dVwktLGZywArletpW/86R+DTta48WOzpC5J7fTwflWGpSSydi3hqbrKk2t2BFiSoHuz1K
+Uc9Noz5Hlo7ziO99BuJowVS2lpvLvg3BqMS8PVyT2xH/MHfXB93iVSdsE8SsrIU3PWzpDp2CC1s
Gpq6t0xrOSC12kQ3SjXVWXQK3qqWfNL8IUqtwFFMAhKZTcJQv5dQ7dkR49vxCeQ+9KmhXkxJXYiZ
c+3QXHMFvT4ReUu5aFsPPL4/EB5km9li9fybffsdo7WTaGdem/Z0H/SwkvAGpzWT23vcdLlOAU5Q
E4JkWpjf18UZZG8/CfitgMM+QdHFYFPdtg5VLKIPCsuVT+oRrZ15kUY62JGlYr0vUzcQG/8VwJlP
EJtPPFQqWy0dujfPIC3m4Lrq+LbkMSIg0ub2oxQvK1nDtId2pSyt5gyKgHkOmiI8QcKgeNUHxWIT
BNata3sAEYnC97QRiEBPw6DCQG+QyKldL6JLX+sOcwgW7N0oiNL2PArqwY/JnqeQ3GE767BgKLjg
c6ooEwHSXSnwg4IOhtIzL+HGmbeGCD4mFTlBsMGR44GylKXwwhDkqdcA2rbPaqC4T6gt4U2Uv5Fe
37aSDf7nmpHTv+EfMsprO+7g7xN15Ldzzt/l7uPEVISMIz5ajSZwLWQp9DzX4M8AXBydbSMT3w1h
2+NAcYSFLeY+ALpkbOkFIeZCr5PFL46Hy7nzuuJGoyHU7dn+CpMf1MRqNqcOVXT33R2Cs/x64MIu
xHOAIwHrLd1EoE5C6lXqKDZtNFeELeTUsHh9qQN5kbpM6F3Z42A5kHu5iwhQSIYlHHywXecDE/70
Birt/+PhIe0E3tuoM15+KmwiNZBd8cO4nTV5sH79Zjymk5KdGew1BdAoqqAGGIips7r0xeTSaVoS
VEtDOev7nQ9RWdKrWVQ41SMDcMGkgefs8hNfc4td5TCxbIIG/QI1qj/XmO4sODCy8gBNNvcM1AoF
VJtNnZYQyaO1SBE76wrxNnI3SpbkgW8egFWyFA6i+obeeKYvKJuhu4btjtSZm9Y2VbI4TBbOP0V/
vRZuT3qQJpS3Dau6+95NFXOfLyNOZpXHWKk+xjX4u2+R7bAkPm1o71JmKukQz7muLYJsbZZFadie
hLMscshTeE3f2gvjx705PEAo7dF7N/izVfzenagXOJVY5Vo2NkuLwdg1uutY3OtUrj2TfAFhoYXG
nPnyEfWjI8V8coj0EWpT1JZw2ZOfznV5Ys/nuUTZ+7UESVBqE4zJOW2xPcuwFCemd5EktnXWE8Jo
CYr6RnJsHvjubEBRNABaDBKciH9t9B1+0RfZAExCP7aKIOoIzYedNGRdcyRNFbNYNgnCszlfSoqX
uNk0aE29wnKpXlO9SccHlsas8C9OW++s3LmX1ML6Bd/tzDJSBth++TDQBCpQXmXY5amymPjyKt36
Wcy5ruQW2bOkCVpvKHsdNPerJvytV8sO0O6S+Ycqhx7NYln0W6XWMC5UKaHHTR53dflvoDt24Mxv
8rQ1NUkAfV2ZfdhorMqa1xjBkitsHzCq1EpZLV9gtERI7H/sCIWBxbak0hGYed66+zACanFm0fZr
ISyFDVJ3mImjQnFlS1M7ebQALxFL/TL11xRFb+zib2+x+6lXBxbZZD8O547NIgxEqY9sQvm/TNhp
3yk4aEA1T7GpteJ0sJVRR4bt2tfDq9/VX5UZ+CZXezfrWs4S0epp6B5dZdCZaPE8S2qNslCmHQCs
3KJOfjM0x6meWx6W+25DdsFbFrDauis4yeliFMIUWAlbGgb0uo/jHTX89ferjP3SdbOJVK3CGFdw
KCTBC8xhwoDY5POA0LIioTRCc9ndNvponAoOipQIQQZEg723JFR+T2Ik0Av+mDO2I+d4kuWzywb2
gk2bLUw0VlSsBM7Sz0q94jqsSU+3VL/pORBaCNswLzWgspcnPEaK4+JktBgqtYBv47q0+uK3QAGF
lbi/q41uz4GUV5OrRVFU07ANF0zgFrLaZ7UNSkYwoXJosGSsewaj9kNOi3jZc98NLxW46t1INhLp
OE0zHwQnGFBqs2a7a7nUrkOJOcMMLOLKXh8mpK/yE9H78Ia4So2OKxmtjI7I1uqgiY/mlZ5zGlcU
wtY2GUW/kh+SyMYKqEblK1ab9vCyZupiwBrZfVpdiNwRkCU+Ek2ykf3/OrEQDLwLpGeFcuACiXEx
USTa7xbbkYtBUP63m/jKmaf2UUOE2Y6aerrwdifxOsQpW1E+FTbj0pE+1dgt29qhA+tc/66nM/jy
oSU1NhTq/gokjzxIAK1RB6NCxQnX6jdrQ2dGq0ASEEKh6Jl8GRjijmGDw4iZDRXfyJYHfGmaoQ/s
OpbSATBF11gABSUp5hhSzxRaOTUqV+0Ti4V1TWK1//KKYua9vnXJCWGK950p9uLaWhmiCM9Gw5zr
WMF096gmV1RIRiQOFxseuzQkVqB2oYa7YJdp8FGKQENvZpLSsJ09plDqEXW5HtKu58kfsHnowR/+
hA==
`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd | 4 | 44262 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_scc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_9.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32));
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_9.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | cpu_dbus_connect.vhd | 1 | 3109 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Tue Nov 7 19:42:31 2017
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 2
-- Master address width: 32
-- Slave address width: 26
-- Port size: 32
-- Port granularity: 8
-- Entity name: cpu_dbus_connect
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e cpu_dbus_connect 1 2 32 26 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity cpu_dbus_connect is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(31 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(25 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_sel_o: out std_logic_vector(3 downto 0);
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(25 downto 2);
m1_dat_o: out std_logic_vector(31 downto 0);
m1_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of cpu_dbus_connect is
signal select_slave: std_logic_vector(2 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal adr_mux: std_logic_vector(31 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
sel_mux<=s0_sel_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="001" when adr_mux(31 downto 26)="000000" else
"010" when adr_mux(31 downto 26)="000001" else
"100"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_sel_o<=sel_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(cyc_mux and stb_mux and select_slave(2)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_gpio_0_0/synth/design_SWandHW_standalone_axi_gpio_0_0.vhd | 1 | 10202 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SWandHW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SWandHW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SWandHW_standalone_axi_gpio_0_0_arch OF design_SWandHW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SWandHW_standalone_axi_gpio_0_0_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_pkg.vhd | 8 | 23668 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
package axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
--constant NUM_REG_TOTAL : integer := 18;
--constant NUM_REG_TOTAL : integer := 23;
constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers
--constant NUM_REG_PER_CHANNEL : integer := 6;
constant NUM_REG_PER_CHANNEL : integer := 12;
constant NUM_REG_PER_S2MM : integer := 120;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_SA_INDEX : integer := 6;
constant MM2S_SA2_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant RESERVED_24_INDEX : integer := 9;
constant MM2S_LENGTH_INDEX : integer := 10;
constant RESERVED_2C_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_DA_INDEX : integer := 18;
constant S2MM_DA2_INDEX : integer := 19;
constant RESERVED_50_INDEX : integer := 20;
constant RESERVED_54_INDEX : integer := 21;
--constant S2MM_LENGTH_INDEX : integer := 22;
constant S2MM_LENGTH_INDEX : integer := 142;
constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00
constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04
constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08
constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C
constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10
constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14
constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18
constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C
constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20
constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24
constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28
-- Following was reserved, now is used for SG xCache and xUser
constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C
constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30
constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34
constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38
constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C
constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40
constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44
constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034
constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C
constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50
constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54
constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58
-- New registers for S2MM channels
constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70
constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74
constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78
constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C
constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90
constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94
constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98
constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C
constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0
constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4
constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8
constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC
constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0
constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4
constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8
constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC
constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0
constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4
constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8
constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC
constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110
constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114
constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118
constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C
constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130
constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134
constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138
constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C
constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150
constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154
constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158
constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C
constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170
constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174
constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178
constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C
constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190
constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194
constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198
constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C
constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0
constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4
constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8
constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC
constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0
constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4
constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8
constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC
constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0
constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4
constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8
constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC
constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210
constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214
constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218
constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C
constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230
constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234
constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238
constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_KH_BIT : integer := 3;
constant CYCLIC_BIT : integer := 4;
--constant DMACR_RESERVED3_BIT : integer := 3;
--constant DMACR_RESERVED4_BIT : integer := 4;
constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_RESERVED6_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_dma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width ( dwidth : integer;
burst_size: integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
-- coverage off
return 0;
-- coverage on
end if;
end;
end package body axi_dma_pkg;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/fifo_generator_v13_0/simulation/fifo_generator_vhdl_beh.vhd | 15 | 465879 | -------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_vhdl_beh.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_vhdl_beh.vhd
-- |
-- +-fifo_generator_v13_0_1_conv
-- |
-- +-fifo_generator_v13_0_1_bhv_as
-- |
-- +-fifo_generator_v13_0_1_bhv_ss
-- |
-- +-fifo_generator_v13_0_1_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE wr_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pntr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_pntr_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
wdci_proc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
END IF;
END PROCESS wdci_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
rd_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
rd_pntr_q <= rd_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & rd_pntr_wr_d1;
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
wr_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
wr_pntr_q <= wr_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & wr_pntr_rd1;
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_wdc: PROCESS(WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
END IF; -- WR_CLK
END PROCESS proc_wdc;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
--overflow_i <= (wr_rst_i OR full_comb) AND WR_EN after C_TCQ;
overflow_i <= (full_comb) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
--underflow_i <= (rd_rst_i OR empty_comb) and RD_EN after C_TCQ;
underflow_i <= (empty_comb) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)AND C_EN_SAFETY_CKT =0) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv0_safety: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT =1) GENERATE
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rd_rst_i, RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rd_rst_i = '1') THEN
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' ) THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
--ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0_safety;
gv1_nsafety: IF (NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) ) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1_nsafety;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_misc.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic_vector;
false_case : std_logic_vector)
RETURN std_logic_vector IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
running_result := conv_std_logic_vector(value,bitwidth);
RETURN running_result;
END int_2_std_logic_vector;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
CONSTANT DO_ALL_ZERO : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT RST_VAL : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
CONSTANT RST_VALUE : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= if_then_else(C_USE_DOUT_RST = 1, RST_VAL, DO_ALL_ZERO);
CONSTANT IS_ASYMMETRY : integer :=if_then_else((C_WR_PNTR_WIDTH /= C_RD_PNTR_WIDTH),1,0);
CONSTANT C_GRTR_PNTR_WIDTH : integer :=if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH),C_WR_PNTR_WIDTH,C_RD_PNTR_WIDTH);
CONSTANT LESSER_WIDTH : integer
:=if_then_else((C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH),
C_WR_PNTR_WIDTH,
C_RD_PNTR_WIDTH);
CONSTANT DIFF_MAX_RD : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT DIFF_MAX_WR : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL read_allow_dc : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
SIGNAL srst_wrst_busy : std_logic := '0';
SIGNAL srst_rrst_busy : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := RST_VALUE;
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL wr_point_d2 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_pntr_temp : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL width_gt1 : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing AE and AF
-------------------------------------------------------------------------------
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing RD_DATA_COUNT WR_DATA_COUNT
-------------------------------------------------------------------------------
SIGNAL count_dc : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0) := int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
SIGNAL one : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
SIGNAL ratio : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
--gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
srst_rrst_busy <= SRST OR RD_RST_BUSY;
srst_wrst_busy <= SRST OR WR_RST_BUSY;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
srst_rrst_busy <= '0';
srst_wrst_busy <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
BEGIN
ALMOST_FULL <= almost_full_i;
END GENERATE gaf_ss;
gafn_ss: IF (C_HAS_ALMOST_FULL = 0 AND C_PROG_FULL_TYPE <= 2 AND C_PROG_EMPTY_TYPE <= 2) GENERATE
BEGIN
ALMOST_FULL <= '0';
END GENERATE gafn_ss;
EMPTY <= empty_i;
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
BEGIN
ALMOST_EMPTY <= almost_empty_i;
END GENERATE gae_ss;
gaen_ss: IF (C_HAS_ALMOST_EMPTY = 0) GENERATE
BEGIN
ALMOST_EMPTY <= '0';
END GENERATE gaen_ss;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
gen_read_allow_for_dc_fwft: IF(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0) GENERATE
read_allow_dc <= RD_EN_USER AND (NOT USER_EMPTY_FB);
END GENERATE gen_read_allow_for_dc_fwft;
gen_read_allow_for_dc_std: IF(NOT(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0)) GENERATE
read_allow_dc <= read_allow;
END GENERATE gen_read_allow_for_dc_std;
wrptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (CLK'event AND CLK = '1') THEN
-- user_empty_fb_d1 <= USER_EMPTY_FB;
user_empty_fb_d1 <= empty_i;
IF (user_empty_fb_d1 = '0' AND empty_i = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_i = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_i = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_i = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
gpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr <= rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gtrim;
comp1 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (adj_rd_pntr_wr = wr_pntr) ELSE '0';
gf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_eq_rp;
-- Write data width is bigger than read data width
-- Write depth is smaller than read depth
-- One write could be equal to 2 or 4 or 8 reads
gf_asym: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_full <= comp1 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_full <= (comp0 AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gf_asym;
gf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_gt_rp;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
fcomp2 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "10")) ELSE '0';
gaf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_eq_rp;
gaf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_afull <= fcomp2 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_afull <= (comp1 AND (NOT write_allow) AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gaf_wp_lt_rp;
gaf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= ((comp0 OR comp1 OR fcomp2) AND read_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_gt_rp;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
pad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE pad;
trim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE trim;
ecomp1 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (adj_wr_pntr_rd = rd_pntr) ELSE '0';
ge_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_eq_rp;
ge_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_lt_rp;
ge_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_empty <= ecomp1 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_empty <= ecomp0 AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE ge_wp_gt_rp;
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate data_count_int flags for RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rd_depth_gt_wr: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
SIGNAL decr_by_one : std_logic := '0';
SIGNAL incr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
decr_by_one <= read_allow_dc;
incr_by_ratio <= write_allow;
cntr: PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF decr_by_one = '1' THEN
IF incr_by_ratio = '0' THEN
count_dc <= count_dc - one AFTER C_TCQ;
ELSE
count_dc <= count_dc - one + ratio AFTER C_TCQ;
END IF;
ELSE
IF incr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc + ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
rd_data_count_int <= count_dc;
wr_data_count_int <= count_dc(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE rd_depth_gt_wr;
wr_depth_gt_rd: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
SIGNAL incr_by_one : std_logic := '0';
SIGNAL decr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
incr_by_one <= write_allow;
decr_by_ratio <= read_allow_dc;
cntr: PROCESS (CLK, RST)
BEGIN
IF (rst_i = '1' ) THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy='1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF incr_by_one = '1' THEN
IF decr_by_ratio = '0' THEN
count_dc <= count_dc + one AFTER C_TCQ;
ELSE
count_dc <= count_dc + one - ratio AFTER C_TCQ;
END IF;
ELSE
IF decr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc - ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
wr_data_count_int <= count_dc;
rd_data_count_int <= count_dc(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE wr_depth_gt_rd;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
ecomp2 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "10")) ELSE '0';
gae_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND (NOT read_allow));
END GENERATE gae_wp_eq_rp;
gae_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= ((ecomp0 OR ecomp1 OR ecomp2) AND write_allow);
END GENERATE gae_wp_lt_rp;
gae_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_aempty <= ecomp2 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_aempty <= ecomp1 AND (NOT read_allow) AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE gae_wp_gt_rp;
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
-------------------------------------------------------------------------------
-- synchronous FIFO using linked lists
-------------------------------------------------------------------------------
gnll_cc_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
FIFO_PROC : PROCESS (CLK, rst_i, wr_pntr)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF CLK'event AND CLK = '1' THEN
IF srst_wrst_busy = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
ELSE
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_wr_d1 after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
wr_point_d2 <= wr_point_d1 after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_i /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --srst
END IF; --CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
IF (rst_i = '1' OR srst_rrst_busy = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
END IF;
IF rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 )AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF CLK'event AND CLK = '1' THEN
-- ELSE
IF (srst_rrst_busy= '1') THEN
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 ) AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
IF srst_rrst_busy = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSE
-- Delay the read pointer before passing to CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_rd1 after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (RD_EN = '1') THEN
IF empty_i /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --srst
END IF; --CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
END GENERATE gnll_cc_fifo;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_max : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_wr_pntr_rd_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_max : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
SIGNAL full_reg : std_logic := '0';
SIGNAL rst_full_ff_reg1 : std_logic := '0';
SIGNAL rst_full_ff_reg2 : std_logic := '0';
SIGNAL carry : std_logic := '0';
CONSTANT WR_RD_RATIO_I_PF : integer := if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH), (C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH), 0);
CONSTANT WR_RD_RATIO_PF : integer := 2**WR_RD_RATIO_I_PF;
-- CONSTANT WR_RD_RATIO_I_PE : integer := if_then_else((C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH), (C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH), 0);
-- CONSTANT WR_RD_RATIO_PE : integer := 2**WR_RD_RATIO_I_PE;
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
--CONSTANT EXTRA_WORDS : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2,
-- (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT EXTRA_WORDS_PF : integer := 2*WR_RD_RATIO_PF;
--CONSTANT EXTRA_WORDS_PE : integer := 2*WR_RD_RATIO_PE;
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
diff_pntr_pe_max <= DIFF_MAX_RD;
dif_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
write_only <= write_allow AND NOT read_allow;
read_only <= read_allow AND NOT write_allow;
END GENERATE dif_pntr_sym;
dif_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
gpf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(write_allow);
write_only <= write_allow AND NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)));
END GENERATE gpf_wp_lt_rp;
gpf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)));
write_only<= write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(read_allow);
END GENERATE gpf_wp_gt_rp;
END GENERATE dif_pntr_asym;
dif_cal_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
write_only_q <= '0';
read_only_q <= '0';
diff_pntr_reg1 <= (OTHERS => '0');
diff_pntr_pe_reg1 <= (OTHERS => '0');
diff_pntr_reg2 <= (OTHERS => '0');
diff_pntr_pe_reg2 <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
read_only_q <= '0' AFTER C_TCQ;
diff_pntr_pe_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe_reg2 <= (OTHERS => '0');
END IF;
IF (srst_wrst_busy = '1') THEN
write_only_q <= '0' AFTER C_TCQ;
diff_pntr_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_reg2 <= (OTHERS => '0');
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr + "1" AFTER C_TCQ;
ELSE
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
diff_pntr <= diff_pntr_reg1(C_WR_PNTR_WIDTH-1 downto 0);
diff_pntr_pe <= diff_pntr_pe_reg1(C_RD_PNTR_WIDTH-1 downto 0);
END GENERATE dif_cal_pntr_sym;
dif_cal_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
adj_wr_pntr_rd_asym(C_RD_PNTR_WIDTH downto 1) <= adj_wr_pntr_rd;
adj_wr_pntr_rd_asym(0) <= '1';
rd_pntr_asym(C_RD_PNTR_WIDTH downto 1) <= not(rd_pntr);
rd_pntr_asym(0) <= '1';
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
diff_pntr_pe_asym <= (OTHERS => '0');
full_reg <= '0';
rst_full_ff_reg1 <= '1';
rst_full_ff_reg2 <= '1';
diff_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
rst_full_ff_reg1 <= '1' AFTER C_TCQ;
rst_full_ff_reg2 <= '1' AFTER C_TCQ;
full_reg <= '0' AFTER C_TCQ;
diff_pntr_pe_asym <= (OTHERS => '0') AFTER C_TCQ;
END IF;
IF (srst_wrst_busy = '1') THEN
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
rst_full_ff_reg1 <= RST_FULL_FF AFTER C_TCQ;
rst_full_ff_reg2 <= rst_full_ff_reg1 AFTER C_TCQ;
full_reg <= full_i AFTER C_TCQ;
diff_pntr_pe_asym <= adj_wr_pntr_rd_asym + rd_pntr_asym AFTER C_TCQ;
IF (full_i = '0') THEN
diff_pntr <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
carry <= (NOT(OR_REDUCE(diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1))));
diff_pntr_pe <= diff_pntr_pe_max when (full_reg = '1' AND rst_full_ff_reg2 = '0' AND carry = '1' ) else diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1);
END GENERATE dif_cal_pntr_asym;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '0') THEN
IF ((diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((diff_pntr) < C_PF_ASSERT_VAL ) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1' AND C_HAS_RST = 1) THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN='0') THEN
IF (conv_integer(diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < C_PF_NEGATE_VAL) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH)WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < pf_assert_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF(conv_integer(diff_pntr) < pf_negate_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (diff_pntr_pe <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (diff_pntr_pe > (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > (C_PE_NEGATE_VAL) ) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_assert_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= (pe_assert_val)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_negate_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= (WR_RST_BUSY OR full_i) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= (RD_RST_BUSY OR empty_i) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_wrst_busy = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_rrst_busy = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 0) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 1) GENERATE
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
PROCESS ( CLK )
BEGIN
rst_delayed_sft1 <= rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rst_i, CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rst_i = '1') THEN
valid_d1 <= '0' after C_TCQ;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
valid_d1 <= valid_i after C_TCQ;
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , CLK )
BEGIN
IF (rst_delayed_sft4 = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
--ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
--valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv1;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
--END GENERATE gnll_fifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v13_0_1_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0';
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0) := (OTHERS => '0')
);
END fifo_generator_v13_0_1_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST OR WR_RST_BUSY OR RD_RST_BUSY;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
CONSTANT INVALID : std_logic_vector (1 downto 0) := "00";
CONSTANT STAGE1_VALID : std_logic_vector (1 downto 0) := "10";
CONSTANT STAGE2_VALID : std_logic_vector (1 downto 0) := "01";
CONSTANT BOTH_STAGES_VALID : std_logic_vector (1 downto 0) := "11";
SIGNAL curr_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
SIGNAL next_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
BEGIN
proc_fwft_fsm : PROCESS ( curr_fwft_state, RD_EN, FIFOEMPTY)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
IF (FIFOEMPTY = '0') THEN
next_fwft_state <= STAGE1_VALID;
ELSE --FIFOEMPTY = '1'
next_fwft_state <= INVALID;
END IF;
WHEN STAGE1_VALID =>
IF (FIFOEMPTY = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSE -- FIFOEMPTY = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN STAGE2_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= INVALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= STAGE1_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '0') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- FIFOEMPTY = '1' AND RD_EN = '0'
next_fwft_state <= STAGE2_VALID;
END IF;
WHEN BOTH_STAGES_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- RD_EN = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN OTHERS =>
next_fwft_state <= INVALID;
END CASE;
END PROCESS proc_fwft_fsm;
proc_fsm_reg: PROCESS (rd_rst_i, RD_CLK)
BEGIN
IF (rd_rst_i = '1') THEN
curr_fwft_state <= INVALID;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
curr_fwft_state <= INVALID AFTER C_TCQ;
ELSE
curr_fwft_state <= next_fwft_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_fsm_reg;
proc_regen: PROCESS (curr_fwft_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
STAGE2_REG_EN <= '0';
WHEN STAGE1_VALID =>
STAGE2_REG_EN <= '1';
WHEN STAGE2_VALID =>
STAGE2_REG_EN <= '0';
WHEN BOTH_STAGES_VALID =>
IF (RD_EN = '1') THEN
STAGE2_REG_EN <= '1';
ELSE
STAGE2_REG_EN <= '0';
END IF;
WHEN OTHERS =>
STAGE2_REG_EN <= '0';
END CASE;
END PROCESS proc_regen;
VALID_STAGES <= curr_fwft_state;
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
glat0_nsafety: if C_EN_SAFETY_CKT=0 GENERATE
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_nsafety;
glat0_safety: if C_EN_SAFETY_CKT=1 GENERATE
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN -- PROCESS regout_lat0
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2 ) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2 AND rst_delayed_sft4 = '1') THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1' and rd_rst_i = '0') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_safety;
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_as;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v13_0_1_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic;
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
SIGNAL wr_rst_busy_i : std_logic := '0';
SIGNAL rd_rst_busy_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL almost_full_i : std_logic ;
SIGNAL prog_full_i : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal rst_2_sync_safety : std_logic := '0';
signal clk_2_sync : std_logic := '0';
signal clk_2_sync_safety : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1) OR (C_MEMORY_TYPE = 4)) GENERATE
fgss : fifo_generator_v13_0_1_bhv_ss
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => if_then_else(C_MEMORY_TYPE = 4, 1, C_MEMORY_TYPE),
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RD_EN_USER => rd_en_delayed,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => almost_full_i,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => prog_full_i,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v13_0_1_bhv_as
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => almost_full_i,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => prog_full_i,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
ALMOST_FULL <= almost_full_i;
PROG_FULL <= prog_full_i;
WR_RST_I_OUT <= wr_rst_i;
RD_RST_I_OUT <= rd_rst_i;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
SIGNAL sbiterr_fwft : STD_LOGIC := '0';
SIGNAL dbiterr_fwft : STD_LOGIC := '0';
SIGNAL rd_en_to_fwft_fifo : STD_LOGIC := '0';
SIGNAL dout_fwft : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fwft : STD_LOGIC := '0';
SIGNAL valid_stages_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL stage2_reg_en_i : STD_LOGIC := '0';
BEGIN
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_to_fwft_fifo,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_fwft,
USERVALID => valid_p0_out,
USEREMPTY => empty_fwft,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => sbiterr_fwft,
USERDBITERR => dbiterr_fwft,
STAGE2_REG_EN => stage2_reg_en_i,
VALID_STAGES => valid_stages_i
);
gberr_non_pkt_fifo: IF (C_FIFO_TYPE /= 1) GENERATE
VALID <= valid_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
SBITERR <= sbiterr_fwft;
DBITERR <= dbiterr_fwft;
dout_p0_out <= dout_fwft;
rd_en_to_fwft_fifo <= rd_en_delayed;
empty_p0_out <= empty_fwft;
END GENERATE gberr_non_pkt_fifo;
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
grd_en_npkt: IF (C_FIFO_TYPE /= 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
END GENERATE grd_en_npkt;
grd_en_pkt: IF (C_FIFO_TYPE = 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND (NOT valid_p0_out);
END GENERATE ngfwft_rd;
END GENERATE grd_en_pkt;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF ((srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
EMPTY <= empty_p0_out;
gpkt_fifo_fwft: IF (C_FIFO_TYPE = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_plus1 : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_reg : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL eop_at_stage2 : STD_LOGIC := '0';
SIGNAL ram_pkt_empty : STD_LOGIC := '0';
SIGNAL ram_pkt_empty_d1 : STD_LOGIC := '0';
SIGNAL pkt_ready_to_read : STD_LOGIC := '0';
SIGNAL fwft_stage1_valid : STD_LOGIC := '0';
SIGNAL fwft_stage2_valid : STD_LOGIC := '0';
SIGNAL rd_en_2_stage2 : STD_LOGIC := '0';
SIGNAL ram_wr_en_pkt_fifo : STD_LOGIC := '0';
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL dummy_wr_eop : STD_LOGIC := '0';
SIGNAL ram_rd_en_compare : STD_LOGIC := '0';
SIGNAL partial_packet : STD_LOGIC := '0';
SIGNAL wr_rst_fwft_pkt_fifo : STD_LOGIC := '0';
SIGNAL stage1_eop : STD_LOGIC := '0';
SIGNAL stage1_eop_d1 : STD_LOGIC := '0';
SIGNAL rd_en_fifo_in_d1 : STD_LOGIC := '0';
BEGIN
wr_rst_fwft_pkt_fifo <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
-- Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
-- When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
-- When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
-- write packet count
gdummy_wr_eop: IF (C_AXI_TYPE = 0) GENERATE
SIGNAL packet_empty_wr : std_logic := '1';
BEGIN
proc_dummy_wr_eop: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
partial_packet <= '0';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
partial_packet <= '0' AFTER C_TCQ;
ELSE
IF (almost_full_i = '1' AND ram_wr_en_pkt_fifo = '1' AND packet_empty_wr = '1' AND din_delayed(0) = '0') THEN
partial_packet <= '1' AFTER C_TCQ;
ELSE
IF (partial_packet = '1' AND din_delayed(0) = '1' AND ram_wr_en_pkt_fifo = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS proc_dummy_wr_eop;
dummy_wr_eop <= almost_full_i AND ram_wr_en_pkt_fifo AND packet_empty_wr AND (NOT din_delayed(0)) AND (NOT partial_packet);
-- Synchronize the packet EMPTY in WR clock domain to generate the dummy WR_EOP
gpkt_empty_sync: IF (C_COMMON_CLOCK = 0) GENERATE
TYPE pkt_empty_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE-1) OF STD_LOGIC;
SIGNAL pkt_empty_sync : pkt_empty_array := (OTHERS => '1');
BEGIN
proc_empty_sync: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
pkt_empty_sync <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
pkt_empty_sync <= pkt_empty_sync(1 to C_SYNCHRONIZER_STAGE-1) & empty_p0_out AFTER C_TCQ;
END IF;
END PROCESS proc_empty_sync;
packet_empty_wr <= pkt_empty_sync(0);
END GENERATE gpkt_empty_sync;
gnpkt_empty_sync: IF (C_COMMON_CLOCK = 1) GENERATE
packet_empty_wr <= empty_p0_out;
END GENERATE gnpkt_empty_sync;
END GENERATE gdummy_wr_eop;
proc_stage1_eop: PROCESS (rst_fwft, CLK_INT)
BEGIN
IF (rst_fwft = '1') THEN
stage1_eop_d1 <= '0';
rd_en_fifo_in_d1 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
stage1_eop_d1 <= '0' AFTER C_TCQ;
rd_en_fifo_in_d1 <= '0' AFTER C_TCQ;
ELSE
stage1_eop_d1 <= stage1_eop AFTER C_TCQ;
rd_en_fifo_in_d1 <= rd_en_fifo_in AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_stage1_eop;
stage1_eop <= dout_fifo_out(0) WHEN (rd_en_fifo_in_d1 = '1') ELSE stage1_eop_d1;
ram_wr_en_pkt_fifo <= wr_en_delayed AND (NOT FULL_int);
wr_eop <= ram_wr_en_pkt_fifo AND ((din_delayed(0) AND (NOT partial_packet)) OR dummy_wr_eop);
ram_rd_en_compare <= stage2_reg_en_i AND stage1_eop;
pkt_fifo_fwft : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => 2 -- Enable low latency fwft logic
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_delayed,
FIFOEMPTY => pkt_ready_to_read,
FIFODATA => dout_fwft,
FIFOSBITERR => sbiterr_fwft,
FIFODBITERR => dbiterr_fwft,
USERDATA => dout_p0_out,
USERVALID => OPEN,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => OPEN,
USERUNDERFLOW => OPEN,
RAMVALID => OPEN, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_2_stage2,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR,
STAGE2_REG_EN => OPEN,
VALID_STAGES => OPEN
);
pkt_ready_to_read <= NOT ((ram_pkt_empty NOR empty_fwft) AND ((valid_stages_i(0) AND valid_stages_i(1)) OR eop_at_stage2));
rd_en_to_fwft_fifo <= NOT empty_fwft AND rd_en_2_stage2;
pregsm : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
eop_at_stage2 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (stage2_reg_en_i = '1') THEN
eop_at_stage2 <= stage1_eop AFTER C_TCQ;
END IF;
END IF;
END PROCESS pregsm;
-----------------------------------------------------------------------------
-- Write and Read Packet Count
-----------------------------------------------------------------------------
proc_wr_pkt_cnt: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
wr_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (wr_eop = '1') THEN
wr_pkt_count <= wr_pkt_count + int_2_std_logic_vector(1,C_WR_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_wr_pkt_cnt;
grss_pkt_cnt : IF C_COMMON_CLOCK = 1 GENERATE
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count <= (OTHERS => '0');
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH);
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
rd_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
ELSIF (stage2_reg_en_i = '1' AND stage1_eop = '1') THEN
rd_pkt_count <= rd_pkt_count + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
rd_pkt_count_plus1 <= rd_pkt_count_plus1 + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (SRST='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
ELSE
IF ((rd_pkt_count = wr_pkt_count) AND wr_eop = '1') THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count_plus1 = wr_pkt_count) AND wr_eop = '0' AND almost_full_i = '0' AND ram_rd_en_compare = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS proc_pkt_empty;
END GENERATE grss_pkt_cnt;
gras_pkt_cnt : IF C_COMMON_CLOCK = 0 GENERATE
TYPE wr_pkt_cnt_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pkt_count_q : wr_pkt_cnt_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pkt_count_b2g : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_pkt_count_rd : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
proc_wr_pkt_cnt_b2g: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_b2g <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_pkt_count_b2g <= wr_pkt_count AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_b2g;
-- Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
proc_wr_pkt_cnt_rd: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_q <= (OTHERS => (OTHERS => '0'));
wr_pkt_count_rd <= (OTHERS => '0');
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
wr_pkt_count_q <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-2 DOWNTO 0) & wr_pkt_count_b2g AFTER C_TCQ;
wr_pkt_count_rd <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-1) AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_rd;
rd_pkt_count <= rd_pkt_count_reg + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH)
WHEN (stage1_eop = '1') ELSE rd_pkt_count_reg;
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count_reg <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (rd_en_fifo_in = '1') THEN
rd_pkt_count_reg <= rd_pkt_count AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty_as : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (rd_pkt_count /= wr_pkt_count_rd) THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count = wr_pkt_count_rd) AND stage2_reg_en_i = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_pkt_empty_as;
END GENERATE gras_pkt_cnt;
END GENERATE gpkt_fifo_fwft;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
SIGNAL rst_active : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event and WR_CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_active after C_TCQ;
END IF;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
gsrst : IF (C_HAS_SRST = 1) GENERATE
gcc_srst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
g8s_cc_srst: IF (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus") GENERATE
SIGNAL wr_rst_reg : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (wr_rst_reg = '0' AND srst_delayed = '1') THEN
wr_rst_reg <= '1';
ELSE
IF (wr_rst_reg = '1') THEN
wr_rst_reg <= '0';
ELSE
wr_rst_reg <= wr_rst_reg;
END IF;
END IF;
END IF;
END PROCESS;
rst_i <= wr_rst_reg;
rd_rst_busy <= wr_rst_reg;
rd_rst_busy_i <= wr_rst_reg;
wr_rst_busy <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
wr_rst_busy_i <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
rst_full_ff_i <= wr_rst_reg;
rst_full_gen_i <= rst_active_i WHEN (C_FULL_FLAGS_RST_VAL = 1) ELSE '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= srst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= wr_rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE g8s_cc_srst;
END GENERATE gcc_srst;
END GENERATE gsrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
rst_2_sync_safety <= RST WHEN (C_ENABLE_RST_SYNC = 1) ELSE RD_RST;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
clk_2_sync_safety <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE RD_CLK;
grst_safety_ckt: IF (C_EN_SAFETY_CKT = 1 AND C_INTERFACE_TYPE = 0) GENERATE
SIGNAL rst_d1_safety : STD_LOGIC := '1';
SIGNAL rst_d2_safety : STD_LOGIC := '1';
SIGNAL rst_d3_safety : STD_LOGIC := '1';
SIGNAL rst_d4_safety : STD_LOGIC := '1';
SIGNAL rst_d5_safety : STD_LOGIC := '1';
SIGNAL rst_d6_safety : STD_LOGIC := '1';
SIGNAL rst_d7_safety : STD_LOGIC := '1';
BEGIN
prst: PROCESS (rst_2_sync_safety, clk_2_sync_safety)
BEGIN
IF (rst_2_sync_safety = '1') THEN
rst_d1_safety <= '1';
rst_d2_safety <= '1';
rst_d3_safety <= '1';
rst_d4_safety <= '1';
rst_d5_safety <= '1';
rst_d6_safety <= '1';
rst_d7_safety <= '1';
ELSIF (clk_2_sync_safety'event AND clk_2_sync_safety = '1') THEN
rst_d1_safety <= '0' AFTER C_TCQ;
rst_d2_safety <= rst_d1_safety AFTER C_TCQ;
rst_d3_safety <= rst_d2_safety AFTER C_TCQ;
rst_d4_safety <= rst_d3_safety AFTER C_TCQ;
rst_d5_safety <= rst_d4_safety AFTER C_TCQ;
rst_d6_safety <= rst_d5_safety AFTER C_TCQ;
rst_d7_safety <= rst_d6_safety AFTER C_TCQ;
END IF;
END PROCESS prst;
assert_safety: PROCESS (rst_d7_safety, wr_en)
BEGIN
IF(rst_d7_safety = '1' AND wr_en = '1') THEN
assert false
report "A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled"
severity warning;
END IF;
END PROCESS assert_safety;
END GENERATE grst_safety_ckt;
grstd1 : IF ((C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0)) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
SIGNAL rst_d4 : STD_LOGIC := '1';
SIGNAL rst_d5 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_d4 <= '1';
rst_d5 <= '1';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_d4 <= rst_d3 AFTER C_TCQ;
rst_d5 <= rst_d4 AFTER C_TCQ;
END IF;
END PROCESS prst;
g_nsafety_ckt: IF ((C_EN_SAFETY_CKT = 0) ) GENERATE
rst_full_gen_i <= rst_d3;
END GENERATE g_nsafety_ckt;
g_safety_ckt: IF (C_EN_SAFETY_CKT = 1 ) GENERATE
rst_full_gen_i <= rst_d5;
END GENERATE g_safety_ckt;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v13_0_1_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v13_0_1_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE state IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_misc.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_vhdl_beh IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex7";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_PIPELINE_REG : integer := 0;
C_POWER_SAVING_MODE : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- AXI Built-in FIFO Primitive Type
-- 512x36, 1kx18, 2kx9, 4kx4, etc
C_PRIM_FIFO_TYPE_WACH : string := "512x36";
C_PRIM_FIFO_TYPE_WDCH : string := "512x36";
C_PRIM_FIFO_TYPE_WRCH : string := "512x36";
C_PRIM_FIFO_TYPE_RACH : string := "512x36";
C_PRIM_FIFO_TYPE_RDCH : string := "512x36";
C_PRIM_FIFO_TYPE_AXIS : string := "512x36";
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
SLEEP : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END fifo_generator_vhdl_beh;
ARCHITECTURE behavioral OF fifo_generator_vhdl_beh IS
COMPONENT fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
-- CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
-- CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
CONSTANT TFF : time := 100 ps;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : bin2gray
-----------------------------------------------------------------------------
-- This function receives a binary value, and returns the associated
-- graycoded value.
FUNCTION bin2gray (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := indata(I) XOR indata(I+1);
END LOOP;
RETURN tmp_value;
END bin2gray;
-----------------------------------------------------------------------------
-- FUNCTION : gray2bin
-----------------------------------------------------------------------------
-- This function receives a gray-coded value, and returns the associated
-- binary value.
FUNCTION gray2bin (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := XOR_REDUCE(indata(length-1 DOWNTO I));
END LOOP;
RETURN tmp_value;
END gray2bin;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
SIGNAL axi_rs_rst : std_logic := '0';
CONSTANT IS_V8 : INTEGER := if_then_else((C_FAMILY = "virtexu"),1,0);
CONSTANT IS_K8 : INTEGER := if_then_else((C_FAMILY = "kintexu"),1,0);
CONSTANT IS_A8 : INTEGER := if_then_else((C_FAMILY = "artixu"),1,0);
CONSTANT IS_VM : INTEGER := if_then_else((C_FAMILY = "virtexuplus"),1,0);
CONSTANT IS_KM : INTEGER := if_then_else((C_FAMILY = "kintexuplus"),1,0);
CONSTANT IS_ZNQU : INTEGER := if_then_else((C_FAMILY = "zynquplus"),1,0);
CONSTANT IS_8SERIES : INTEGER := if_then_else((IS_V8 = 1 OR IS_K8 = 1 OR IS_A8 = 1 OR IS_VM = 1 OR IS_ZNQU = 1 OR IS_KM = 1),1,0);
BEGIN
inverted_reset <= NOT S_ARESETN;
gaxi_rs_rst: IF (C_INTERFACE_TYPE > 0 AND (C_AXIS_TYPE = 1 OR C_WACH_TYPE = 1 OR
C_WDCH_TYPE = 1 OR C_WRCH_TYPE = 1 OR C_RACH_TYPE = 1 OR C_RDCH_TYPE = 1)) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (inverted_reset, S_ACLK)
BEGIN
IF (inverted_reset = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
rst_d1 <= '0' AFTER TFF;
rst_d2 <= rst_d1 AFTER TFF;
END IF;
END PROCESS prst;
axi_rs_rst <= rst_d2;
END GENERATE gaxi_rs_rst;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
SIGNAL wr_data_count_in : std_logic_vector (C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
signal full_i : std_logic := '0';
signal empty_i : std_logic := '0';
signal WR_RST_INT : std_logic := '0';
signal RD_RST_INT : std_logic := '0';
begin
inst_conv_fifo: fifo_generator_v13_0_1_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => full_i,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_i,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => wr_data_count_in,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR,
WR_RST_BUSY => WR_RST_BUSY,
RD_RST_BUSY => RD_RST_BUSY,
WR_RST_I_OUT => WR_RST_INT,
RD_RST_I_OUT => RD_RST_INT
);
FULL <= full_i;
EMPTY <= empty_i;
fifo_ic_adapter: IF (C_HAS_DATA_COUNTS_AXIS = 3) GENERATE
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL rd_eop : STD_LOGIC := '0';
SIGNAL data_read : STD_LOGIC := '0';
SIGNAL w_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_wr_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_rd_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt : std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_w_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
SIGNAL r_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE w_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0);
SIGNAL w_q : w_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
BEGIN
wr_eop <= WR_EN AND not(full_i);
rd_eop <= RD_EN AND not(empty_i);
-- Write Packet count logic
proc_w_cnt: PROCESS (WR_CLK, WR_RST_INT)
BEGIN
IF (WR_RST_INT = '1') THEN
w_cnt <= (OTHERS => '0');
ELSIF (WR_CLK = '1' AND WR_CLK'EVENT) THEN
IF (wr_eop = '1') THEN
w_cnt <= w_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_w_cnt;
-- Convert Write Packet count to Grey
pw_gc : PROCESS (WR_CLK, WR_RST_INT)
BEGIN
if (WR_RST_INT = '1') then
w_cnt_gc <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
w_cnt_gc <= bin2gray(w_cnt, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1' AND C_HAS_RST = 1) THEN
w_q(i) <= (OTHERS => '0');
ELSIF RD_CLK'EVENT AND RD_CLK = '1' THEN
w_q(i) <= w_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
w_q(0) <= w_cnt_gc;
w_cnt_gc_asreg_last <= w_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pw_rd_bin : PROCESS (RD_CLK, RD_RST_INT)
BEGIN
if (RD_RST_INT = '1') then
w_cnt_rd <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_rd_bin;
-- Read Packet count logic
proc_r_cnt: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
r_cnt <= (OTHERS => '0');
ELSIF (RD_CLK = '1' AND RD_CLK'EVENT) THEN
IF (rd_eop = '1') THEN
r_cnt <= r_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_r_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_w_cnt_rd_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= w_cnt_rd;
r_inv_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= not r_cnt;
p_cry: PROCESS (rd_eop)
BEGIN
IF (rd_eop = '0') THEN
adj_w_cnt_rd_pad(0) <= '1';
r_inv_pad(0) <= '1';
ELSE
adj_w_cnt_rd_pad(0) <= '0';
r_inv_pad(0) <= '0';
END IF;
END PROCESS p_cry;
p_sub: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
d_cnt_pad <= (OTHERS=>'0');
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad AFTER TFF;
END IF;
END PROCESS p_sub;
d_cnt <= d_cnt_pad(log2roundup(C_WR_DEPTH) DOWNTO 1);
WR_DATA_COUNT <= d_cnt;
END GENERATE fifo_ic_adapter;
fifo_icn_adapter: IF (C_HAS_DATA_COUNTS_AXIS /= 3) GENERATE
WR_DATA_COUNT <= wr_data_count_in;
END GENERATE fifo_icn_adapter;
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
SIGNAL axis_dc : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_rst_busy_axis : STD_LOGIC := '0';
SIGNAL rd_rst_busy_axis : STD_LOGIC := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 0) GENERATE
gwe_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_wr_en <= S_AXIS_TVALID AND axis_s_axis_tready;
END GENERATE gwe_pkt;
gwe: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gwe;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 0) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 0) GENERATE
gre_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_rd_en <= M_AXIS_TREADY AND axis_m_axis_tvalid;
END GENERATE gre_pkt;
gre_npkt: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gre_npkt;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 0) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
SIGNAL axis_wr_rst : STD_LOGIC := '0';
SIGNAL axis_rd_rst : STD_LOGIC := '0';
BEGIN
axis_we <= axis_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE axis_wr_en AND S_ACLK_EN;
axis_re <= axis_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE axis_rd_en AND M_ACLK_EN;
axisf : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 2 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 11 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => if_then_else(C_APPLICATION_TYPE_AXIS = 1,1,0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else(C_APPLICATION_TYPE_AXIS = 1,0,C_APPLICATION_TYPE_AXIS),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_we,
RD_EN => axis_re,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
EMPTY => axis_empty,
ALMOST_FULL => axis_almost_full,
PROG_FULL => AXIS_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXIS_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => axis_dc,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR,
WR_RST_BUSY => wr_rst_busy_axis,
RD_RST_BUSY => rd_rst_busy_axis,
WR_RST_I_OUT => axis_wr_rst,
RD_RST_I_OUT => axis_rd_rst
);
g8s_axis_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_axis_rdy: IF (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13) GENERATE
axis_s_axis_tready <= NOT (axis_full OR wr_rst_busy_axis);
END GENERATE g8s_bi_axis_rdy;
g8s_nbi_axis_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13)) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g8s_nbi_axis_rdy;
END GENERATE g8s_axis_rdy;
g7s_axis_rdy: IF (IS_8SERIES = 0) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g7s_axis_rdy;
--axis_m_axis_tvalid <= NOT axis_empty WHEN (C_APPLICATION_TYPE_AXIS /= 1) ELSE NOT axis_empty AND axis_pkt_read;
gnaxis_pkt_fifo: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_m_axis_tvalid <= NOT axis_empty;
END GENERATE gnaxis_pkt_fifo;
S_AXIS_TREADY <= axis_s_axis_tready;
M_AXIS_TVALID <= axis_m_axis_tvalid;
gaxis_pkt_fifo_cc: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 1) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_wr_eop_d1 : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_cnt : INTEGER := 0;
SIGNAL axis_pkt_read : STD_LOGIC := '0';
BEGIN
axis_m_axis_tvalid <= NOT axis_empty AND axis_pkt_read;
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_read <= '0';
axis_wr_eop_d1 <= '0';
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
axis_wr_eop_d1 <= axis_wr_eop;
IF (axis_rd_eop = '1' AND (axis_pkt_cnt = 1) AND axis_wr_eop_d1 = '0') THEN
axis_pkt_read <= '0' AFTER TFF;
ELSIF ((axis_pkt_cnt > 0) OR (axis_almost_full = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
-- Packet count logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_cnt <= 0;
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop_d1 = '1' AND axis_rd_eop = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt + 1 AFTER TFF;
ELSIF (axis_rd_eop = '1' AND axis_wr_eop_d1 = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt - 1 AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gaxis_pkt_fifo_cc;
gaxis_pkt_fifo_ic: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 0) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_read : STD_LOGIC := '0';
SIGNAL axis_wpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_rpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_axis_wpkt_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
SIGNAL rpkt_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE wpkt_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0);
SIGNAL wpkt_q : wpkt_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
SIGNAL axis_af_q : axis_af_array := (OTHERS => (OTHERS => '0'));
SIGNAL axis_af_rd : std_logic_vector(0 DOWNTO 0) := (others => '0');
BEGIN
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_pkt_read <= '0';
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1' AND (conv_integer(diff_pkt_cnt) = 1)) THEN
axis_pkt_read <= '0' AFTER TFF;
-- Asserting packet read at the same time when the packet is written is not considered because it causes
-- packet FIFO handshake violation when the packet size is just 2 data beat and each write is separated
-- by more than 2 clocks. This causes the first data to come out at the FWFT stage making the actual FIFO
-- empty and leaving the first stage FWFT stage with no data, and when the last data is written, it
-- actually makes the valid to be high for a clock and de-asserts immediately as the written data will
-- take two clocks to appear at the FWFT output. This situation is a violation of packet FIFO, where
-- TVALID should not get de-asserted in between the packet transfer.
ELSIF ((conv_integer(diff_pkt_cnt) > 0) OR (axis_af_rd(0) = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
axis_m_axis_tvalid <= (NOT axis_empty) AND axis_pkt_read;
-- Write Packet count logic
proc_wpkt_cnt: PROCESS (S_ACLK, axis_wr_rst)
BEGIN
IF (axis_wr_rst = '1') THEN
axis_wpkt_cnt <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop = '1') THEN
axis_wpkt_cnt <= axis_wpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_wpkt_cnt;
-- Convert Write Packet count to Grey
pwpkt_gc : PROCESS (S_ACLK, axis_wr_rst)
BEGIN
if (axis_wr_rst = '1') then
axis_wpkt_cnt_gc <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
wpkt_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
wpkt_q(i) <= wpkt_q(i-1) AFTER TFF;
END IF;
END PROCESS;
-- af_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => 1
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => axis_af_q(i-1),
-- Q => axis_af_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
axis_af_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
axis_af_q(i) <= axis_af_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
wpkt_q(0) <= axis_wpkt_cnt_gc;
axis_wpkt_cnt_gc_asreg_last <= wpkt_q(C_SYNCHRONIZER_STAGE);
axis_af_q(0)(0) <= axis_almost_full;
axis_af_rd <= axis_af_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pwpkt_rd_bin : PROCESS (M_ACLK, axis_rd_rst)
BEGIN
if (axis_rd_rst = '1') then
axis_wpkt_cnt_rd <= (OTHERS => '0');
ELSIF (M_ACLK'event AND M_ACLK = '1') THEN
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_rd_bin;
-- Read Packet count logic
proc_rpkt_cnt: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_rpkt_cnt <= (OTHERS => '0');
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1') THEN
axis_rpkt_cnt <= axis_rpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_rpkt_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_axis_wpkt_cnt_rd_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= axis_wpkt_cnt_rd;
rpkt_inv_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= not axis_rpkt_cnt;
pkt_cry: PROCESS (axis_rd_eop)
BEGIN
IF (axis_rd_eop = '0') THEN
adj_axis_wpkt_cnt_rd_pad(0) <= '1';
rpkt_inv_pad(0) <= '1';
ELSE
adj_axis_wpkt_cnt_rd_pad(0) <= '0';
rpkt_inv_pad(0) <= '0';
END IF;
END PROCESS pkt_cry;
pkt_sub: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
diff_pkt_cnt_pad <= (OTHERS=>'0');
ELSIF M_ACLK'event AND M_ACLK = '1' THEN
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad AFTER TFF;
END IF;
END PROCESS pkt_sub;
diff_pkt_cnt <= diff_pkt_cnt_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1);
END GENERATE gaxis_pkt_fifo_ic;
gdc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 1 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
SIGNAL axis_dc_pkt_fifo : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_dc_pkt_fifo <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_we = '1' AND axis_re = '0') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo + "1" AFTER TFF;
ELSIF (axis_we = '0' AND axis_re = '1') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo - "1" AFTER TFF;
END IF;
END IF;
END PROCESS;
AXIS_DATA_COUNT <= axis_dc_pkt_fifo;
END GENERATE gdc_pkt;
gndc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 0 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
AXIS_DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc_pkt;
gdc: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
AXIS_DATA_COUNT <= axis_dc;
END GENERATE gdc;
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= S_AXIS_TVALID WHEN (C_HAS_SLAVE_CE = 0) ELSE S_AXIS_TVALID AND S_ACLK_EN;
axis_re <= M_AXIS_TREADY WHEN (C_HAS_MASTER_CE = 0) ELSE M_AXIS_TREADY AND M_ACLK_EN;
axis_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => axis_we,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => axis_re
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 2) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout_pkt : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
SIGNAL awvalid_en : std_logic := '0';
SIGNAL awready_pkt : std_logic := '0';
SIGNAL wdch_we : STD_LOGIC := '0';
SIGNAL wr_rst_busy_wach : std_logic := '0';
SIGNAL wr_rst_busy_wdch : std_logic := '0';
SIGNAL wr_rst_busy_wrch : std_logic := '0';
SIGNAL rd_rst_busy_wach : std_logic := '0';
SIGNAL rd_rst_busy_wdch : std_logic := '0';
SIGNAL rd_rst_busy_wrch : std_logic := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWQOS_OFFSET - C_AXI_REGION_WIDTH, AWQOS_OFFSET);
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 3 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE /= 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET) <= S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
gwach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wach_din(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET) <= S_AXI_AWID;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
END GENERATE gwach_din3;
gwach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_AWID <= (OTHERS => '0');
END GENERATE gwach_din4;
gwach_din5: IF (C_AXI_TYPE = 1) GENERATE
wach_din(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET) <= S_AXI_AWREGION;
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach_din5;
gwach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_AWREGION <= (OTHERS => '0');
END GENERATE gwach_din6;
wach_din(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET) <= S_AXI_AWADDR;
wach_din(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET) <= S_AXI_AWLEN;
wach_din(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET) <= S_AXI_AWSIZE;
wach_din(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET) <= S_AXI_AWBURST;
wach_din(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET) <= S_AXI_AWLOCK;
wach_din(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET) <= S_AXI_AWCACHE;
wach_din(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET) <= S_AXI_AWPROT;
wach_din(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET) <= S_AXI_AWQOS;
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET) <= S_AXI_WUSER;
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
gwdch_din3: IF (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
wdch_din(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET) <= S_AXI_WID;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
END GENERATE gwdch_din3;
gwdch_din4: IF NOT (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
M_AXI_WID <= (OTHERS => '0');
END GENERATE gwdch_din4;
wdch_din(WID_OFFSET-1 DOWNTO WDATA_OFFSET) <= S_AXI_WDATA;
wdch_din(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET) <= S_AXI_WSTRB;
wdch_din(0) <= S_AXI_WLAST;
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
M_AXI_WLAST <= wdch_dout(0);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET) <= M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
gwrch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wrch_din(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET) <= M_AXI_BID;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
END GENERATE gwrch_din3;
gwrch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_BID <= (OTHERS => '0');
END GENERATE gwrch_din4;
wrch_din(BID_OFFSET-1 DOWNTO BRESP_OFFSET) <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 0) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 0) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 0) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 0) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 0) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 0) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 0) GENERATE
gpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= awready_pkt AND awvalid_en;
END GENERATE;
gnpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 0) GENERATE
gaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
END GENERATE gaxi_mm_wach_rd_en2;
gnaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gnaxi_mm_wach_rd_en2;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 0) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 0) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 0) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 0) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
SIGNAL wach_we : STD_LOGIC := '0';
SIGNAL wach_re : STD_LOGIC := '0';
BEGIN
wach_we <= wach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wach_wr_en AND S_ACLK_EN;
wach_re <= wach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wach_rd_en AND M_ACLK_EN;
axi_wach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 2 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 11 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_WACH = 1),0,C_APPLICATION_TYPE_WACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_we,
RD_EN => wach_re,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
DIN => wach_din,
DOUT => wach_dout_pkt,
FULL => wach_full,
EMPTY => wach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AW_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AW_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR,
WR_RST_BUSY => wr_rst_busy_wach,
RD_RST_BUSY => rd_rst_busy_wach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wach_rdy: IF (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13) GENERATE
wach_s_axi_awready <= NOT (wach_full OR wr_rst_busy_wach);
END GENERATE g8s_bi_wach_rdy;
g8s_nbi_wach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13)) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g8s_nbi_wach_rdy;
END GENERATE g8s_wach_rdy;
g7s_wach_rdy: IF (IS_8SERIES = 0) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g7s_wach_rdy;
wach_m_axi_awvalid <= NOT wach_empty;
S_AXI_AWREADY <= wach_s_axi_awready;
gawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL awvalid_pkt : STD_LOGIC := '0';
BEGIN
awvalid_pkt <= wach_m_axi_awvalid AND awvalid_en;
wach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_dout_pkt,
S_VALID => awvalid_pkt,
S_READY => awready_pkt,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gawvld_pkt_fifo;
gnawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
M_AXI_AWVALID <= wach_m_axi_awvalid;
wach_dout <= wach_dout_pkt;
END GENERATE gnawvld_pkt_fifo;
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
SIGNAL wdch_re : STD_LOGIC := '0';
BEGIN
wdch_we <= wdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wdch_wr_en AND S_ACLK_EN;
wdch_re <= wdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wdch_rd_en AND M_ACLK_EN;
axi_wdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 2 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 11 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_we,
RD_EN => wdch_re,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
EMPTY => wdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_W_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_W_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR,
WR_RST_BUSY => wr_rst_busy_wdch,
RD_RST_BUSY => rd_rst_busy_wdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wdch_rdy: IF (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13) GENERATE
wdch_s_axi_wready <= NOT (wdch_full OR wr_rst_busy_wdch);
END GENERATE g8s_bi_wdch_rdy;
g8s_nbi_wdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13)) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g8s_nbi_wdch_rdy;
END GENERATE g8s_wdch_rdy;
g7s_wdch_rdy: IF (IS_8SERIES = 0) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g7s_wdch_rdy;
wdch_m_axi_wvalid <= NOT wdch_empty;
S_AXI_WREADY <= wdch_s_axi_wready;
M_AXI_WVALID <= wdch_m_axi_wvalid;
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
SIGNAL wrch_we : STD_LOGIC := '0';
SIGNAL wrch_re : STD_LOGIC := '0';
BEGIN
wrch_we <= wrch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE wrch_wr_en AND M_ACLK_EN;
wrch_re <= wrch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wrch_rd_en AND S_ACLK_EN;
axi_wrch : fifo_generator_v13_0_1_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 2 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 11 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_we,
RD_EN => wrch_re,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
EMPTY => wrch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_B_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_B_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR,
WR_RST_BUSY => wr_rst_busy_wrch,
RD_RST_BUSY => rd_rst_busy_wrch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
wrch_s_axi_bvalid <= NOT wrch_empty;
g8s_wrch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wrch_rdy: IF (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13) GENERATE
wrch_m_axi_bready <= NOT (wrch_full OR wr_rst_busy_wrch);
END GENERATE g8s_bi_wrch_rdy;
g8s_nbi_wrch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13)) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g8s_nbi_wrch_rdy;
END GENERATE g8s_wrch_rdy;
g7s_wrch_rdy: IF (IS_8SERIES = 0) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g7s_wrch_rdy;
S_AXI_BVALID <= wrch_s_axi_bvalid;
M_AXI_BREADY <= wrch_m_axi_bready;
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
gaxi_pkt_fifo_wr: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
BEGIN
txn_count_en_up <= wdch_s_axi_wready AND wdch_we AND wdch_din(0);
txn_count_en_down <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
gaxi_mm_cc_pkt_wr: IF (C_COMMON_CLOCK = 1) GENERATE
proc_wr_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (txn_count_en_up = '1' AND txn_count_en_down = '0') THEN
wr_pkt_count <= wr_pkt_count + conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
ELSIF (txn_count_en_down = '1' AND txn_count_en_up = '0') THEN
wr_pkt_count <= wr_pkt_count - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
END IF;
END IF;
END PROCESS proc_wr_txn_cnt;
awvalid_en <= '1' WHEN (wr_pkt_count > conv_std_logic_vector(0,C_WR_PNTR_WIDTH_WDCH)) ELSE '0';
END GENERATE gaxi_mm_cc_pkt_wr;
END GENERATE gaxi_pkt_fifo_wr;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout_pkt : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
SIGNAL arvalid_en : std_logic := '0';
SIGNAL arready_pkt : std_logic := '0';
SIGNAL rdch_re : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rach : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rdch : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rach : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rdch : STD_LOGIC := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARQOS_OFFSET - C_AXI_REGION_WIDTH,ARQOS_OFFSET);
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE /= 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET) <= S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
grach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rach_din(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET) <= S_AXI_ARID;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
END GENERATE grach_din3;
grach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_ARID <= (OTHERS => '0');
END GENERATE grach_din4;
grach_din5: IF (C_AXI_TYPE = 1) GENERATE
rach_din(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET) <= S_AXI_ARREGION;
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach_din5;
grach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_ARREGION <= (OTHERS => '0');
END GENERATE grach_din6;
rach_din(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET) <= S_AXI_ARADDR;
rach_din(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET) <= S_AXI_ARLEN;
rach_din(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET) <= S_AXI_ARSIZE;
rach_din(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET) <= S_AXI_ARBURST;
rach_din(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET) <= S_AXI_ARLOCK;
rach_din(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET) <= S_AXI_ARCACHE;
rach_din(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET) <= S_AXI_ARPROT;
rach_din(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET) <= S_AXI_ARQOS;
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET) <= M_AXI_RUSER;
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
grdch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rdch_din(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET) <= M_AXI_RID;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
END GENERATE grdch_din3;
grdch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_RID <= (OTHERS => '0');
END GENERATE grdch_din4;
rdch_din(RID_OFFSET-1 DOWNTO RDATA_OFFSET) <= M_AXI_RDATA;
rdch_din(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET) <= M_AXI_RRESP;
rdch_din(0) <= M_AXI_RLAST;
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
S_AXI_RLAST <= rdch_dout(0);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 0) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 0) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 0) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 0) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 0) GENERATE
gpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= arready_pkt AND arvalid_en;
END GENERATE;
gnpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 0) GENERATE
gaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
END GENERATE gaxi_mm_rach_rd_en2;
gnaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE gnaxi_mm_rach_rd_en2;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 0) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 0) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
SIGNAL rach_we : STD_LOGIC := '0';
SIGNAL rach_re : STD_LOGIC := '0';
BEGIN
rach_we <= rach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rach_wr_en AND S_ACLK_EN;
rach_re <= rach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rach_rd_en AND M_ACLK_EN;
axi_rach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 2 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 11 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_RACH = 1),0,C_APPLICATION_TYPE_RACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_we,
RD_EN => rach_re,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
DIN => rach_din,
DOUT => rach_dout_pkt,
FULL => rach_full,
EMPTY => rach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AR_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AR_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR,
WR_RST_BUSY => wr_rst_busy_rach,
RD_RST_BUSY => rd_rst_busy_rach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_rach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rach_rdy: IF (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13) GENERATE
rach_s_axi_arready <= NOT (rach_full OR wr_rst_busy_rach);
END GENERATE g8s_bi_rach_rdy;
g8s_nbi_rach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13)) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g8s_nbi_rach_rdy;
END GENERATE g8s_rach_rdy;
g7s_rach_rdy: IF (IS_8SERIES = 0) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g7s_rach_rdy;
rach_m_axi_arvalid <= NOT rach_empty;
S_AXI_ARREADY <= rach_s_axi_arready;
gaxi_arvld: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL arvalid_pkt : STD_LOGIC := '0';
BEGIN
arvalid_pkt <= rach_m_axi_arvalid AND arvalid_en;
rach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_dout_pkt,
S_VALID => arvalid_pkt,
S_READY => arready_pkt,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE gaxi_arvld;
gnaxi_arvld: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
M_AXI_ARVALID <= rach_m_axi_arvalid;
rach_dout <= rach_dout_pkt;
END GENERATE gnaxi_arvld;
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
SIGNAL rdch_we : STD_LOGIC := '0';
BEGIN
rdch_we <= rdch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE rdch_wr_en AND M_ACLK_EN;
rdch_re <= rdch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rdch_rd_en AND S_ACLK_EN;
axi_rdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 2 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 11 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_we,
RD_EN => rdch_re,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
EMPTY => rdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_R_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_R_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR,
WR_RST_BUSY => wr_rst_busy_rdch,
RD_RST_BUSY => rd_rst_busy_rdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
rdch_s_axi_rvalid <= NOT rdch_empty;
g8s_rdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rdch_rdy: IF (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13) GENERATE
rdch_m_axi_rready <= NOT (rdch_full OR wr_rst_busy_rdch);
END GENERATE g8s_bi_rdch_rdy;
g8s_nbi_rdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13)) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g8s_nbi_rdch_rdy;
END GENERATE g8s_rdch_rdy;
g7s_rdch_rdy: IF (IS_8SERIES = 0) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g7s_rdch_rdy;
S_AXI_RVALID <= rdch_s_axi_rvalid;
M_AXI_RREADY <= rdch_m_axi_rready;
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
gaxi_pkt_fifo_rd: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL rd_burst_length : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_free_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_committed_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
SIGNAL rdch_rd_ok : STD_LOGIC := '0';
SIGNAL accept_next_pkt : STD_LOGIC := '0';
SIGNAL decrement_val : INTEGER := 0;
BEGIN
rd_burst_length <= ('0' & rach_dout_pkt(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET)) + conv_std_logic_vector(1,9);
accept_next_pkt <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
rdch_rd_ok <= rdch_re AND rdch_s_axi_rvalid;
arvalid_en <= '1' WHEN (rd_fifo_free_space >= rd_burst_length) ELSE '0';
gaxi_mm_cc_pkt_rd: IF (C_COMMON_CLOCK = 1) GENERATE
rd_fifo_free_space <= conv_std_logic_vector(C_WR_DEPTH_RDCH-conv_integer(rd_fifo_committed_space),C_WR_PNTR_WIDTH_RDCH+1);
decrement_val <= 1 WHEN (rdch_rd_ok = '1') ELSE 0;
proc_rd_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
rd_fifo_committed_space <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (accept_next_pkt = '1') THEN
-- Subtract 1 if read happens on read data FIFO while adding ARLEN
rd_fifo_committed_space <= rd_fifo_committed_space + conv_std_logic_vector((conv_integer(rd_burst_length) - decrement_val), C_WR_PNTR_WIDTH_RDCH+1);
ELSIF (rdch_rd_ok = '1') THEN
-- Subtract 1 whenever read happens on read data FIFO
rd_fifo_committed_space <= rd_fifo_committed_space - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_RDCH+1);
END IF;
END IF;
END PROCESS proc_rd_txn_cnt;
END GENERATE gaxi_mm_cc_pkt_rd;
END GENERATE gaxi_pkt_fifo_rd;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fdiv_14_no_dsp_32.vhd | 6 | 12691 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fdiv_14_no_dsp_32;
ARCHITECTURE ANN_ap_fdiv_14_no_dsp_32_arch OF ANN_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fdiv_14_no_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd | 19 | 4781 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | spi/spimaster.vhd | 1 | 6908 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| A rudimentary SPI master peripheral |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spimaster is
port ( clk : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(2 downto 0);
cpu_wait : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable : in std_logic;
req_read : in std_logic;
req_write : in std_logic;
slave_cs : out std_logic;
slave_clk : out std_logic;
slave_mosi : out std_logic;
slave_miso : in std_logic
);
end spimaster;
-- registers:
-- base+0 -- chip select control; bit 0 is slave_cs
-- base+1 -- status register; bit 0 indicates "transmitter busy"
-- base+2 -- transmitter: write a byte here, starts SPI bus transaction
-- base+3 -- receiver: last byte received (updated on each transation)
-- base+4 -- clock divider: clk counts from 0 to whatever is in this register before proceeding
--
-- Note that if an SPI transfer is underway already the CPU will be
-- forced to wait until it completes before any register can be
-- read or written. This is very convenient as it means you can
-- just read or write bytes without checking the status register.
architecture Behavioral of spimaster is
-- start up in idle state
signal slave_cs_register : std_logic := '1';
signal slave_clk_register : std_logic := '1';
signal slave_mosi_register: std_logic := '0';
signal data_out_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal data_in_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal busy_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal clk_divide_target : unsigned(7 downto 0) := (others => '0');
signal clk_divide_value : unsigned(7 downto 0) := (others => '0');
signal cpu_was_idle : std_logic := '1';
-- cpu visible registers
signal chip_select_out : std_logic_vector(7 downto 0);
signal status_data_out : std_logic_vector(7 downto 0);
signal data_out_enable : std_logic;
begin
chip_select_out <= "0000000" & slave_cs_register;
status_data_out <= "0000000" & busy_sr(7);
cpu_wait <= busy_sr(7);
--TH: Added logic to expose data to bus only when it is really needed
-- I think it wastes energy when uneccesary signal value changes are avoided
data_out_enable <= req_read and not busy_sr(7);
with cpu_address&data_out_enable select
data_out <=
chip_select_out when "0001",
status_data_out when "0011",
data_out_sr when "0101",
data_in_sr when "0111",
std_logic_vector(clk_divide_target) when "1001",
(others=>'0') when others;
slave_cs <= slave_cs_register;
slave_clk <= slave_clk_register;
slave_mosi <= slave_mosi_register;
spimaster_proc: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
slave_cs_register <= '1';
slave_clk_register <= '1';
slave_mosi_register <= '0';
data_out_sr <= (others => '0');
data_in_sr <= (others => '0');
busy_sr <= (others => '0');
clk_divide_target <= (others => '0');
clk_divide_value <= (others => '0');
cpu_was_idle <= '1';
else
-- divide down input clk to get 2 * spi clk
clk_divide_value <= clk_divide_value + 1;
if clk_divide_value = clk_divide_target then
clk_divide_value <= to_unsigned(0, 8);
end if;
if busy_sr(7) = '1' then
if clk_divide_value = clk_divide_target then
-- we're in the midst of a transaction! whoo!
if slave_clk_register = '1' then
-- clk is high; next cycle will be falling edge of clk
slave_clk_register <= '0';
slave_mosi_register <= data_out_sr(7);
-- shift data out
data_out_sr <= data_out_sr(6 downto 0) & '0';
else
-- clk is low; next cycle will be rising edge of clk
slave_clk_register <= '1';
-- shift busy
busy_sr <= busy_sr(6 downto 0) & '0';
-- latch data in
data_in_sr <= data_in_sr(6 downto 0) & slave_miso;
end if;
end if;
end if;
if enable = '1' and req_write = '1' then
if busy_sr(7) = '0' and cpu_was_idle = '1' then
cpu_was_idle <= '0';
case cpu_address is
when "000" =>
slave_cs_register <= data_in(0);
when "010" =>
-- only allow writes when transmitter is idle
data_out_sr <= data_in;
busy_sr <= (others => '1');
when "100" =>
clk_divide_target <= unsigned(data_in);
when others => -- no change
end case;
else
cpu_was_idle <= cpu_was_idle;
end if;
else
cpu_was_idle <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fdiv_14_no_dsp_32/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd | 24 | 9340 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/vhdl/ANN_ST_WandB.vhd | 7 | 3065 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 6560
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 6560;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_WandB is
component ANN_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_WandB_ram_U : component ANN_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_ST_WandB.vhd | 7 | 3065 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 6560
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 6560;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_WandB is
component ANN_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_WandB_ram_U : component ANN_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 |
bonfireprocessor/bonfire-soc | obsolete/papro_lpc.vhd | 1 | 2849 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Sat Feb 18 19:01:47 2017
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 2
-- Master address width: 26
-- Slave address width: 8
-- Port size: 8
-- Port granularity: 8
-- Entity name: papro_lpc
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e papro_lpc 1 2 26 8 8 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity papro_lpc is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(25 downto 0);
s0_dat_i: in std_logic_vector(7 downto 0);
s0_dat_o: out std_logic_vector(7 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(7 downto 0);
m0_dat_o: out std_logic_vector(7 downto 0);
m0_dat_i: in std_logic_vector(7 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(7 downto 0);
m1_dat_o: out std_logic_vector(7 downto 0);
m1_dat_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of papro_lpc is
signal select_slave: std_logic_vector(2 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal adr_mux: std_logic_vector(25 downto 0);
signal wdata_mux: std_logic_vector(7 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(7 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="001" when adr_mux(25 downto 8)="000000000000000000" else
"010" when adr_mux(25 downto 8)="000000000000000001" else
"100"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(cyc_mux and stb_mux and select_slave(2)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_afifo_autord.vhd | 7 | 15525 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_p_uOut.vhd | 4 | 4111 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/synth/ANN_ap_fmul_2_max_dsp_32.vhd | 6 | 12689 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd | 4 | 90840 | -------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_skid_buf.vhd | 13 | 18142 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_sg_skid_buf;
architecture implementation of axi_sg_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fcmp_0_no_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd | 24 | 10163 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YdBG68RFwokFzFKR7nrliDOlnj+kk1DIHHuLOj0ERcmliOs+5nUCq2+I7g3RQADo/tw/5hYyhBvA
zkhz98SR0w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j+3SDUDDyQpwaJ4UUg1tCPqwSzhuWj7b+1nfm4NSTDcl723o9USSuBxoK+76BYb4n4RIJlaApOB1
xNyJ3TdKE3+cTmvo0JV4qZ/XJHZylmoeBz0Fa0FUE6qNsZHsOrUGeTkEzZcF/sKG+/yE9U7pWoo2
Vf/+czWAwGAF78M7eU0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHFWCJwUkRx0aWaiHT7rUDSuriVubrVt+dyN4XxebufJxmziEPnQW6R0Shvp3t9Rs28T0a6gDRTE
Yey998iArVO7WMLyPrC3VVfJAlUGA4SKXhclRes7vUyAWd942ytCM7CkgL8iKyxoTg6xgfAfb1bS
qKlQxP6Oh4UUMDF+wHj+TqR8Ri90ha2TKZ3vmzrYqXnqSsrUSiRPehahCB1EUZH03X39IWPBz/gL
jGMIzAwNsIFGk7JDXQ1D3yAeTLNRd0NJcbaXnRrczJd53QGhqk8FqQ8ewybUbV9d8utygp25BGSo
JL4M04pk4WhIMGjsQFVvSMt/b7bkXT5sNjgvEw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j4+Cq5t9jDH4b+tKONxSAQvUQSuEe6vmG/Fza6ThabY69JhhPiAIpyWkTk3pwrTii4y4QnUfomhd
SpT3nUMfy+A+uQihmL10hDFp3fMr/mfz4mde6CKmvH7NBA3c08FvVPiEDiRWg9D4PMn2iWzltZXB
4rCaDADltHHwoyn39vQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rVRC062BQnogimrJCqwTEd8ZOGC7aEi0dcp+jm3FwXnyuOU7ngEQ72N9ueAz6dcDQv3DZdlM5Zpu
mki8lLpfaQs1vszYHih3xmyOKcPdFqNb7otiQtmfyooFn6V5ZzK3hmaEFLqj6FRatAy4p2bTO2IO
DA4XayojNrn5+ADoj7yOj5hGWjrRbETfJQITMA+za7Lsu3ffroRuir2hOhDcPmOAKk0H+lG5J1/3
RGecNjZ6Px0gG+x+xDpWTFC6jSut/l9G+mYe7pWxhvOjNbfbpsKsCOeVD+NqT73v3Y/PYgd0cpBf
50bH+PiZYS93G80CmpaHUds75mMSCwIL/D9CJw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JPTsEMu7ivOCw+Wjrjiy3x7HTmU1csA0FSpSPA+aeDgUayQeahYc14vUAhzbnZvlrLWhUndZeDwo
3cAy7kv7lvuDgocp3TSVIEbRQbQQWEnF+lxyUk5f0XyY/eVMSaOdgfv7M/nPZJE52DlORF+IQ2B5
avNqsEHw/CM8qQX5A8/J21vVstkC1xfP6MseeK4nr+VBWZve6RaXZD+6i7X+GWzwfH0yO1tffjCQ
H2lhqG43HLBWd55LVB1ZVs7xPRYuRyrN4FLml3VvHtEXu8GA90OPGbzeuJuoiHDz5lmGgVEy6uNR
6ovEb87b8tpmnAZWAth8fcRz2a8gu2NtJmEg+g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
lHJV8fpNPaAZNP6iIPw0amUkAWeoac9F6Mn9lqxif19WHqLYLbQfJDRFOYN3pCmfdj64L9W/N1Ow
zUiFQ1Qn+/Po9LRxFhRjke+zlOLKcgmrz8Wsv/OJc4VSamOJ3dkTyGAaIz6iZjWAIfa3F20xboAz
QXBZHDMkFizWW6XCIBYurqj2WtAKSTo+Bn8syqerOb95UCNUITtoJ+4Ks9EWEUZ1S3AZ55HmtpfK
LybQ1/3Y6BdftkTr+jYn82lsEtYcZAhoxy4mD9Xafm1r7qcWxCRWhADW8LcZuOzFjH2Ppfz0ekQ4
2RYH0EMznWeFwuD9Zw9al80EuiW9Ua2WZSWij+5Tz+ria8QZ8bK6Wy/0J/+TX0BK6W8eBFVDLS7O
ync3GB+NMqTQa+CrDizkGVwKy0xiLspHkFF7qbRo1Hobt+3IBuFY1TLxGyaw/4iAp3TlQK9tLrYr
mCrBNRY0VvxkATuvpzYLQohRxqSd0kaY8gB1TeioNqP9mbysOa5WhVoasQAm9ZFO3dpzn1gk9Y+T
TjFjIzBsbELJlGenqcnZHlRY/zkuHXLnEqe+u2rsDfvD52AVJ9cr38Rb8Kk/Bc+eT3XZgrJ2bHlo
th4a75jw6wpEW2XabxTuE9rrlu5wY0Y5yfnNT6L8hi9URS5Q6N7eogvyGgppZktebcu7KlH6m9WM
RzYA8VNFwZSyXztX6Cml6BCcjERze9zHEznyaBoF3+uq9Y+bKpo037rLMDFhNOAyWcTdQF+w3+1n
KL28hwybFXjHjPlMiKdQU/Y/JkLDGzmLwVIi1C4NPJAfwGK8m+o2AEt9ZqGuGQPmiDqyNb4alRCL
/cjQHSIBx/BLHlpgwyPdS3hvGL6AbsaF3iErUBofmAzgXdo6/go0WkB6rBoqzxSiNPXRcVMdkdLV
u9XE02h/IvPQHWPB2e5LkoP+CT9iqF/JLaBwpQrG0fTxo+Pyyihl4h+o7b8gi164OJHTuKvGXWkI
bWaWaAEJ/CUXa5YjptXRicoW79TOwOwr5+95Eg/LpJayX7kZJgzqSISA7s0wo5URvsGmo7m3pz6E
p8pSfsWN3yJdPaes1adJkdbFzSNPw3SM9zgX22XZpW8U5DkQPGTu1TnRPxP6ZrNFOsBY2vvWj8F8
lYYVtw3LyGjW/YZwpB6V2QIureUbc1B96PTdnfqNr51/yVeuJEvkIEDSiu8MVJY2EJb/lEymD+w5
my/QRktpsR1KpFBklwnU3sXrUM51EjMfa9+yUaLN0R46kkkyLO+zb/DyHrXKeTY7rEYNUQnJpbGz
meMs+Rg+STAh/W+qQJyyJuz2tmxJI3bQPxl/1VFukYQJ/jdjgQfv1k8dtAdhobqLfO7bKwAzyz1h
y8bVBoEPWhzP2/Y0Z+B/JzRqvPpjNjs/Tx2M+ct09FolbxbskWvJt/Sesoh8Q9jDdhyZYGGuFyu7
55NK2jVYDt31YiVx9crEtLQ2lTyxm3erg1ez7Y36EwakRCFAZluocIeR9JgZ7js0LfdhbzzPe71b
p8e26QIF4Aycf8RSTejeav3/rzqyNmod6d4MH5LQ9ELziIcO1aBFcqFh8DHPN2CuoCVfnc3U0Tzi
DxpnXeBY4A+Rhe6uyu+byxuKNXvODb65fpFW/anQGkuEC+tp10XTq+6e5C/U/vPz+Gj1WFJrrzNp
k6xQH7s2GhF3tQ5W8ohJ7uvz8rpgis2QhreFJq9lhYSd+KJdaba1jZ+hAkIfJupdX4kMwfsxm/wn
5fnROcs+fMh7EwCbCSKuhNUiSx09OgudttRQGJSMABuUtsQzk7zX2PD6mY1cHynlp5dysZGXewqR
nAlJUuOAVbI73ZgG6dFCaVvbtgFGA+nf165ezt8VAamFVk5QnQHLdeLIhcp1AZQnH/ZjcMDl4oPl
pfLeOGUawoXtbdVURjICdFtJ8q6ChzsSDCMxuoF31FuXwP5pnGryzLiDuSnu2HHkoxIMcigxnyLD
TtefsxEwHLN+hVCrPCAAdNSIhddZ3bYiPk7lAMiv6BCxYDZGS9ZCM1cOSyucG7h3RdnQwg3A5uXO
SfaNEJlHtDMx4cucuENWxdybS+2ncYQF6fj1Fu0V7pYaYxViGda3gUhogY92s6649b5YAxESFyjg
lc5N9ZnOvQwpLzq9YKo4gfuXOJ1ZwbFPC7AsJpLI5RE97q78ajbqUqL7Aty67J63isNL8rkyQYWE
Q8su5MdBrzNeuGr8ExqF9PauDPluq/uTXAjfmCq6YUZotPV+6wKQSTYMSB1DuH4GXoRhGGIrwLH1
bgHNSWJr22pAZ8WoeHCvA774DRXPCDLHcKwBWLn3bQaIr8s76UTM61ii4eQ4/BOQhOOOW8UJFhXn
jDhByLQ2cRVkFIvNSCT20uFXwmV0zg2ba2tqO39eTBzRw8khvUsEExT0pHCemE3O1YCaFr5vBwSw
e1vxC3+AgIKIoKRU5pabirpjYeBT1+suWRwh4N4S344al5vL38TbuZG/o97tM0SZrDK8w+43gZzI
65yq4JKALCnx6NEIcqdMUvTq+wyyyt1g12c0dVUGGLQNaqiTWFOeCSI9UUKKGVQ3B8KSH6AhxeYS
gV0vNz1Q6oSp37/8qp5WCug8iMTcJc8byxf2ta84Ia1hJVN0LAQt2bKmCbEHgTLZ993g/8Qzkiq2
iaS78ZCzGRr39mWx/xl5KV3Zkfy/sz3/g5q4Zgwm4GvsHF4g6XBURE85FbMAikPLMhFFO3ebUSkH
u+DMoyuRqqmBkP8JxlkF/TaeIvZVHPXTKQ2j/zPsyAfWNMpnGu9ZKDsKuFP09SuaYYiPI6ev2l7S
SiyDxNSIiVR5xXoInO/7+nftScRIrAlDV5PMsbNryxPAgDF66zwrR7+PGs6HPt8WCuZ0uceYjl8J
D1yUA+BKkPDWCYsOEs9ABg/uRQFXVpYsg4SkW+tzw1u9gx5oa3nG2a/gNa1jei7maAG8AJC12obj
JCMCqAOVSP9yRjtQ0KBl6cJomFkQMSJcAKnpTAgRrB4TMUst34Nyxfum9b/Vel39/WXD0A6DjJ1f
O1q+SJQH7BQw/af+vLthdAhLxJIu2kY18gVfROWqP7/0a3ud0aHh78wWa9tQOg4f7EzgYx24L8gp
8ilAHOxg5iqw4RiWt4x0ocLVU+SdILKDjjyXuMxK2aBnKvr0h13NtMVUvF5CGDkwKrbmVQ64ZLHG
r4WGgqkzI3CuRFcarI5OOuRfoIUf6mK0nv3TbhGvr4Xilg1QxK/dRqQe8AziO+mKWAKZIWSBR0fE
nPvKHUkg9PB27PqPxrOOJa1qO5orSG5FB9QtWdL4BgqPU1+dYkFzbAKpXKcBqUMfS+Q16ptdxyi6
30j2PHUkM1JyVp+oIczWGmV/YiPXuQZ+cUdDu31IURvGmju6L0S60cAzthhROczysBr+HeRkgtP4
U4szYmOHC+iu7RSCV0Q8qDfwtD80Mex4aNknYed7U5MP/6OFRZOLnuguS5ARJ9JR6+ONnQSXv/Rw
X5RN3pWpjbrjKqRAodrXJDDbajJaP2BxEcoZhSlRh2mXa9iZsI4k+rjdAAZQc0Ql9dkz9nQ+kNXC
myXMN7A/mc4cipHUnwZgVNseIm1rijaOWeQ0p1MSprxEJ3azfcY6GGRB89N0b0F64mZG9UOnfwzW
HUZf+IGwIDR7YiC+HbfZ9mYjJCn69uocWOjkUxZxTqprwQlYNBKXWQ3k5OWUUpliRoqFc/IFqu0l
FPdgsXNBKqPf2VryDrVfOkFH09w0kvUVFsTmbz1Q/dYjC+fvcjTm42eJ666ZRDnDO2FQo/e7He02
MhjiRxK0rD1LNaaXhHbdPrASFi0X82oyukdFm6aNpJUN/SOySZL8qmpWlirog/IOk8c8A366IBif
16NM+F22rwqKszcVSIyfj1s3VmpAvCS26+8SsqLHlIB2fF6VCbd+MkaHVVkXj+GN8SuYtm3LOyyX
trRlhI6Ra+FlZzFaegz46OsCY+lTZ5RNAdfsY/aERCq0s01Jl6/7E60w86UwoI7yb/0B5T0jI3Fh
GqgJbDaPUHd8GXADlEhjI5Y1aSIeMtnvDv0ih9YaGOIKaeFwG4dlxHCp7JZTXotzvqFQSTEeI9UA
Zw+wrBaH4U5J+jk/v0M6VM23FFGstcJUaajfs+1bKITYr2fVpM0U7D/O34NgE4xz6bFCaKmwcrJp
IotEIMaBWWhLsAx4pTBtI4FQf6NmV6UNkQMRkXXDI1Fns3ooL2vZKgV5ZI9FrOOzTOtHdOuPTNwb
xHywEkliqIQYMRQxjwlDzluAW0JOEL+1MZuxN+WYJGVy1KmDDx6k1uhGuU16PxIymfjq4NdhuBXk
0SZPsfHMW20nhmyTH8t4s8b5UpuCujzMHS30yDiVltFfmyEdGOZC1TDJ8G0ylFxAgfBNbagk/sec
W1tQLmq4HKrPJP9quRzDgVLkqvurF9/LKtwLyNIrgEy6MjY+gNip9JlOYTOM8aW0RqB5zqb75H0j
MrRKei3vBC4uMjByhL3vqfMlyAwOuLD55ON5fPVmnNPHdNcbKnpWsxSIJvPIIZ8uenIgK+Jqm19C
G0yxkWS4Mh0cS31CnCErCbdqRTN0Y9xvd8smrHLDnhO/FbFznpwAFsdpVr2wFeKZ9nxXD18548DL
NtFXoVGX1H6xivhMOLPVJk6O8F3VZz75sKlrPfpEjZNGb027y7XXqV9DSuATDNHqi4PIJ8tsxTZ3
3xCV0k/rDCNyUAtF9PcxAD0hM/B88jFWemIuImWu9NIhDB8IOPDbiRz9tfisL7TovI5GP9WDO9kR
06IADYSMvcCK7YOfHqkRit2EoYt7q0Uvt7aTC3floc+PMFqhxH+KNFcjPG20xyY37lATb38gf0N+
t5KK27ggPyu+o3PET1N5bq1FO7eg9BnAokyrfBFiYasqW4w7qQ9znWCmOX6iBuy5nPh06XAYdyNs
uLlR7ordHKC8/AfHlMR4Bq/3Yq0Ysm3WGjIjT1RljdvuOCDh+Nnt+dAny0rFHPnW1XYszTQaz6CU
Ugh/tZuWAaEWvkJkqprxA0IdmNaWwaTgCpdOOT5llUxqK2DkvTUkFNlOK7YkS2Z+pJTt/dGfwGsI
vAaRBq4Ks1FoQd4DYG2tTmksrKn96Fj+jKPO1WoWYnmauqVa/WSMMy4m0XV+e1CoN+sT1kbsP+u+
RRDWq0TNi46P5m/tNwjzQmghzBEko22Wx30R+rSRbq31290qulNeZ4o7+jQ0xNVoedLJNIFzgkBq
YsH2SFXtallxUfZdA+TiVTXFAnO9KN5+LFteu2PrwJ3wXWpIViUx0mNbqtDmA5DMGvm8fc54mxde
sa66svggXx4jggmRS5YHRhadubTPJMwH1+XIDCpWFlJA1bMM+KpjBgPo0CysgjheKzuXXlKCrF98
0whmmFm9AAFNUaESjbi30jQfa5XK0Z6H0GVO0FRP96TS4ICjxldUUJny5s4Ys0/zjDbR+e2vGePj
Gtoqz4Gi4HUNLJbsI0fHFgSt1iRjHL2Ol+LUKqhyax+y/eToEHOMoYZffBpyXSo5mgnkXDlM/yRz
2X3YBnNhVLr5o1KrKzgxES/kii8MNq3h/OUBnvsB/vfJHxnoZ+IQnuNaFWUxgFYrMlRdWeCCL1VJ
+XMcKoePJGVheIGGbxRPYi6GxVj7nD5WXFy6P5QlrdgKDlGRhdwgsw2OH62kikx684AN+8A8hTCu
Fw0wr/EvRLvSXc5X8BX0graSdvQTcy7MBv6ENfe7dWyhY3z+boFPwUPj9D9/fjJRnxvjbe6oLTcH
Ggiz1j0yvtVdzRs+K4+Wx2uMcc84mndMKb8ojPHwqwhaK+iL/D6nDwA1hGkcFAG/CbS0XlqxyIi/
KYfga8bJGO55q6FZ/2KnEFb5ozzM+P11rJFHapGV6prtyxxnHN+MJ0JGNNNAHt2qDXwNa9gM+eAx
WG9Fxtb1Qa2KoRJ2OZvR06RT5L1It4N7qiVdhlsr9hzdnsGdrC1BASzVxEhCboQrLArBE8wL0aU/
Nw3y2AEWRcHyQL+Mv249kj9WDlMdCzZbk3udlmdxrk49b6MsW6zrDWgfDVDvCxNbmwe4r9gM0SM0
q3mHwDnwiQkflQsEYclcswKlGlDaxgeZ+zBQwYwqi1cs5go5VA5Eq8ndenu+NFTFef4Kx0aOO7YK
5dM5sC0puyAl/oniVzrKRJ+DnETU86QFAAa2N4CpCAvsodb3s83cfkSOJacDGXzL2bZhamYWVYYu
Md2jMrM85u+LlHAWzQ0LqCTkI0O8W0ssK1jX6m2maaxUv1TC6B3a2erW2xV/RkbyX1Q5aOfkDVu7
/vJk2mqGjgIgr/uq6fN+xO7G02X2EUki3yCrYpboRnnCjHm/hOhcoL1RXwpy0JrnFaCw9S69f05Z
niYpcjQ+dCT20+BCNb+GufFYvcJ3mb4oCtEb6HOIw4SVjTfTNOzfPn8v+QBdD059+Byd45Upm60r
Pqw397KrE8GRgs0O9/bcGhVUHMnVPBJjHoIs+o4x0IrAezuyhhfgOz6RqZtgxcp9DWHUNGWJCmeu
kUZdyWIb69TywZFNyenWcmMS7BrEsdAbemoenmWxcT/F7mhtuoNFV/dVSc+JnKJV2jKXk43Apa4z
YgiTTro34u3MnS6vMqGgdwcnEshVBfU7hUcZJhRMsWd2faQTKZfAQWZujNJCRY7rUAwtOUq0pPth
XCJKKapx59tbD6sN+H97jH+UBDis519y7Vk4A/h6qKdzAAYDk+8L1sbxiLpuJvy8EyK+iEqpN99s
+l2yfzz3q+pQ/mZ1t/Gh1lFiL75mshwsWRRNpySkiPrhnqtsp1sjlbzcfCRSUcIHmFkS7sZ2++ET
uZM+1C1TKMusoriq3YjBtzTSOosS2MygpZwFQURuwGReUtNS+Iy26g9gHnvptGXKUaXMMTGsJbPg
p7eIse1WY+6t0NbFTw0K0BPKhWXHTNPE8jAOZa51gGFVo5xoW54GZe98yQYviChEvLWNaU+ARwFP
K4REOg7KOIz4dEu93rSUs8ns1KaaECbV9dXLXe/EnNLYnxUaXcjRjCmBEHaHdu58fu5i+gpgNyA8
UisuaIUgtRCq/eu3ejkwvCkt0bdlvuHq6GWcqFuZuAvFz+GHJTLqtWC2tnbq7RScINiOvf4fRCgK
XxwNaiGxAr+4waSppxQ4TY9TWCTB1F0JQP49nPGJ6JUgUA==
`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_ddiv_29_no_dsp_64/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd | 24 | 10163 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YdBG68RFwokFzFKR7nrliDOlnj+kk1DIHHuLOj0ERcmliOs+5nUCq2+I7g3RQADo/tw/5hYyhBvA
zkhz98SR0w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j+3SDUDDyQpwaJ4UUg1tCPqwSzhuWj7b+1nfm4NSTDcl723o9USSuBxoK+76BYb4n4RIJlaApOB1
xNyJ3TdKE3+cTmvo0JV4qZ/XJHZylmoeBz0Fa0FUE6qNsZHsOrUGeTkEzZcF/sKG+/yE9U7pWoo2
Vf/+czWAwGAF78M7eU0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHFWCJwUkRx0aWaiHT7rUDSuriVubrVt+dyN4XxebufJxmziEPnQW6R0Shvp3t9Rs28T0a6gDRTE
Yey998iArVO7WMLyPrC3VVfJAlUGA4SKXhclRes7vUyAWd942ytCM7CkgL8iKyxoTg6xgfAfb1bS
qKlQxP6Oh4UUMDF+wHj+TqR8Ri90ha2TKZ3vmzrYqXnqSsrUSiRPehahCB1EUZH03X39IWPBz/gL
jGMIzAwNsIFGk7JDXQ1D3yAeTLNRd0NJcbaXnRrczJd53QGhqk8FqQ8ewybUbV9d8utygp25BGSo
JL4M04pk4WhIMGjsQFVvSMt/b7bkXT5sNjgvEw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j4+Cq5t9jDH4b+tKONxSAQvUQSuEe6vmG/Fza6ThabY69JhhPiAIpyWkTk3pwrTii4y4QnUfomhd
SpT3nUMfy+A+uQihmL10hDFp3fMr/mfz4mde6CKmvH7NBA3c08FvVPiEDiRWg9D4PMn2iWzltZXB
4rCaDADltHHwoyn39vQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rVRC062BQnogimrJCqwTEd8ZOGC7aEi0dcp+jm3FwXnyuOU7ngEQ72N9ueAz6dcDQv3DZdlM5Zpu
mki8lLpfaQs1vszYHih3xmyOKcPdFqNb7otiQtmfyooFn6V5ZzK3hmaEFLqj6FRatAy4p2bTO2IO
DA4XayojNrn5+ADoj7yOj5hGWjrRbETfJQITMA+za7Lsu3ffroRuir2hOhDcPmOAKk0H+lG5J1/3
RGecNjZ6Px0gG+x+xDpWTFC6jSut/l9G+mYe7pWxhvOjNbfbpsKsCOeVD+NqT73v3Y/PYgd0cpBf
50bH+PiZYS93G80CmpaHUds75mMSCwIL/D9CJw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JPTsEMu7ivOCw+Wjrjiy3x7HTmU1csA0FSpSPA+aeDgUayQeahYc14vUAhzbnZvlrLWhUndZeDwo
3cAy7kv7lvuDgocp3TSVIEbRQbQQWEnF+lxyUk5f0XyY/eVMSaOdgfv7M/nPZJE52DlORF+IQ2B5
avNqsEHw/CM8qQX5A8/J21vVstkC1xfP6MseeK4nr+VBWZve6RaXZD+6i7X+GWzwfH0yO1tffjCQ
H2lhqG43HLBWd55LVB1ZVs7xPRYuRyrN4FLml3VvHtEXu8GA90OPGbzeuJuoiHDz5lmGgVEy6uNR
6ovEb87b8tpmnAZWAth8fcRz2a8gu2NtJmEg+g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
lHJV8fpNPaAZNP6iIPw0amUkAWeoac9F6Mn9lqxif19WHqLYLbQfJDRFOYN3pCmfdj64L9W/N1Ow
zUiFQ1Qn+/Po9LRxFhRjke+zlOLKcgmrz8Wsv/OJc4VSamOJ3dkTyGAaIz6iZjWAIfa3F20xboAz
QXBZHDMkFizWW6XCIBYurqj2WtAKSTo+Bn8syqerOb95UCNUITtoJ+4Ks9EWEUZ1S3AZ55HmtpfK
LybQ1/3Y6BdftkTr+jYn82lsEtYcZAhoxy4mD9Xafm1r7qcWxCRWhADW8LcZuOzFjH2Ppfz0ekQ4
2RYH0EMznWeFwuD9Zw9al80EuiW9Ua2WZSWij+5Tz+ria8QZ8bK6Wy/0J/+TX0BK6W8eBFVDLS7O
ync3GB+NMqTQa+CrDizkGVwKy0xiLspHkFF7qbRo1Hobt+3IBuFY1TLxGyaw/4iAp3TlQK9tLrYr
mCrBNRY0VvxkATuvpzYLQohRxqSd0kaY8gB1TeioNqP9mbysOa5WhVoasQAm9ZFO3dpzn1gk9Y+T
TjFjIzBsbELJlGenqcnZHlRY/zkuHXLnEqe+u2rsDfvD52AVJ9cr38Rb8Kk/Bc+eT3XZgrJ2bHlo
th4a75jw6wpEW2XabxTuE9rrlu5wY0Y5yfnNT6L8hi9URS5Q6N7eogvyGgppZktebcu7KlH6m9WM
RzYA8VNFwZSyXztX6Cml6BCcjERze9zHEznyaBoF3+uq9Y+bKpo037rLMDFhNOAyWcTdQF+w3+1n
KL28hwybFXjHjPlMiKdQU/Y/JkLDGzmLwVIi1C4NPJAfwGK8m+o2AEt9ZqGuGQPmiDqyNb4alRCL
/cjQHSIBx/BLHlpgwyPdS3hvGL6AbsaF3iErUBofmAzgXdo6/go0WkB6rBoqzxSiNPXRcVMdkdLV
u9XE02h/IvPQHWPB2e5LkoP+CT9iqF/JLaBwpQrG0fTxo+Pyyihl4h+o7b8gi164OJHTuKvGXWkI
bWaWaAEJ/CUXa5YjptXRicoW79TOwOwr5+95Eg/LpJayX7kZJgzqSISA7s0wo5URvsGmo7m3pz6E
p8pSfsWN3yJdPaes1adJkdbFzSNPw3SM9zgX22XZpW8U5DkQPGTu1TnRPxP6ZrNFOsBY2vvWj8F8
lYYVtw3LyGjW/YZwpB6V2QIureUbc1B96PTdnfqNr51/yVeuJEvkIEDSiu8MVJY2EJb/lEymD+w5
my/QRktpsR1KpFBklwnU3sXrUM51EjMfa9+yUaLN0R46kkkyLO+zb/DyHrXKeTY7rEYNUQnJpbGz
meMs+Rg+STAh/W+qQJyyJuz2tmxJI3bQPxl/1VFukYQJ/jdjgQfv1k8dtAdhobqLfO7bKwAzyz1h
y8bVBoEPWhzP2/Y0Z+B/JzRqvPpjNjs/Tx2M+ct09FolbxbskWvJt/Sesoh8Q9jDdhyZYGGuFyu7
55NK2jVYDt31YiVx9crEtLQ2lTyxm3erg1ez7Y36EwakRCFAZluocIeR9JgZ7js0LfdhbzzPe71b
p8e26QIF4Aycf8RSTejeav3/rzqyNmod6d4MH5LQ9ELziIcO1aBFcqFh8DHPN2CuoCVfnc3U0Tzi
DxpnXeBY4A+Rhe6uyu+byxuKNXvODb65fpFW/anQGkuEC+tp10XTq+6e5C/U/vPz+Gj1WFJrrzNp
k6xQH7s2GhF3tQ5W8ohJ7uvz8rpgis2QhreFJq9lhYSd+KJdaba1jZ+hAkIfJupdX4kMwfsxm/wn
5fnROcs+fMh7EwCbCSKuhNUiSx09OgudttRQGJSMABuUtsQzk7zX2PD6mY1cHynlp5dysZGXewqR
nAlJUuOAVbI73ZgG6dFCaVvbtgFGA+nf165ezt8VAamFVk5QnQHLdeLIhcp1AZQnH/ZjcMDl4oPl
pfLeOGUawoXtbdVURjICdFtJ8q6ChzsSDCMxuoF31FuXwP5pnGryzLiDuSnu2HHkoxIMcigxnyLD
TtefsxEwHLN+hVCrPCAAdNSIhddZ3bYiPk7lAMiv6BCxYDZGS9ZCM1cOSyucG7h3RdnQwg3A5uXO
SfaNEJlHtDMx4cucuENWxdybS+2ncYQF6fj1Fu0V7pYaYxViGda3gUhogY92s6649b5YAxESFyjg
lc5N9ZnOvQwpLzq9YKo4gfuXOJ1ZwbFPC7AsJpLI5RE97q78ajbqUqL7Aty67J63isNL8rkyQYWE
Q8su5MdBrzNeuGr8ExqF9PauDPluq/uTXAjfmCq6YUZotPV+6wKQSTYMSB1DuH4GXoRhGGIrwLH1
bgHNSWJr22pAZ8WoeHCvA774DRXPCDLHcKwBWLn3bQaIr8s76UTM61ii4eQ4/BOQhOOOW8UJFhXn
jDhByLQ2cRVkFIvNSCT20uFXwmV0zg2ba2tqO39eTBzRw8khvUsEExT0pHCemE3O1YCaFr5vBwSw
e1vxC3+AgIKIoKRU5pabirpjYeBT1+suWRwh4N4S344al5vL38TbuZG/o97tM0SZrDK8w+43gZzI
65yq4JKALCnx6NEIcqdMUvTq+wyyyt1g12c0dVUGGLQNaqiTWFOeCSI9UUKKGVQ3B8KSH6AhxeYS
gV0vNz1Q6oSp37/8qp5WCug8iMTcJc8byxf2ta84Ia1hJVN0LAQt2bKmCbEHgTLZ993g/8Qzkiq2
iaS78ZCzGRr39mWx/xl5KV3Zkfy/sz3/g5q4Zgwm4GvsHF4g6XBURE85FbMAikPLMhFFO3ebUSkH
u+DMoyuRqqmBkP8JxlkF/TaeIvZVHPXTKQ2j/zPsyAfWNMpnGu9ZKDsKuFP09SuaYYiPI6ev2l7S
SiyDxNSIiVR5xXoInO/7+nftScRIrAlDV5PMsbNryxPAgDF66zwrR7+PGs6HPt8WCuZ0uceYjl8J
D1yUA+BKkPDWCYsOEs9ABg/uRQFXVpYsg4SkW+tzw1u9gx5oa3nG2a/gNa1jei7maAG8AJC12obj
JCMCqAOVSP9yRjtQ0KBl6cJomFkQMSJcAKnpTAgRrB4TMUst34Nyxfum9b/Vel39/WXD0A6DjJ1f
O1q+SJQH7BQw/af+vLthdAhLxJIu2kY18gVfROWqP7/0a3ud0aHh78wWa9tQOg4f7EzgYx24L8gp
8ilAHOxg5iqw4RiWt4x0ocLVU+SdILKDjjyXuMxK2aBnKvr0h13NtMVUvF5CGDkwKrbmVQ64ZLHG
r4WGgqkzI3CuRFcarI5OOuRfoIUf6mK0nv3TbhGvr4Xilg1QxK/dRqQe8AziO+mKWAKZIWSBR0fE
nPvKHUkg9PB27PqPxrOOJa1qO5orSG5FB9QtWdL4BgqPU1+dYkFzbAKpXKcBqUMfS+Q16ptdxyi6
30j2PHUkM1JyVp+oIczWGmV/YiPXuQZ+cUdDu31IURvGmju6L0S60cAzthhROczysBr+HeRkgtP4
U4szYmOHC+iu7RSCV0Q8qDfwtD80Mex4aNknYed7U5MP/6OFRZOLnuguS5ARJ9JR6+ONnQSXv/Rw
X5RN3pWpjbrjKqRAodrXJDDbajJaP2BxEcoZhSlRh2mXa9iZsI4k+rjdAAZQc0Ql9dkz9nQ+kNXC
myXMN7A/mc4cipHUnwZgVNseIm1rijaOWeQ0p1MSprxEJ3azfcY6GGRB89N0b0F64mZG9UOnfwzW
HUZf+IGwIDR7YiC+HbfZ9mYjJCn69uocWOjkUxZxTqprwQlYNBKXWQ3k5OWUUpliRoqFc/IFqu0l
FPdgsXNBKqPf2VryDrVfOkFH09w0kvUVFsTmbz1Q/dYjC+fvcjTm42eJ666ZRDnDO2FQo/e7He02
MhjiRxK0rD1LNaaXhHbdPrASFi0X82oyukdFm6aNpJUN/SOySZL8qmpWlirog/IOk8c8A366IBif
16NM+F22rwqKszcVSIyfj1s3VmpAvCS26+8SsqLHlIB2fF6VCbd+MkaHVVkXj+GN8SuYtm3LOyyX
trRlhI6Ra+FlZzFaegz46OsCY+lTZ5RNAdfsY/aERCq0s01Jl6/7E60w86UwoI7yb/0B5T0jI3Fh
GqgJbDaPUHd8GXADlEhjI5Y1aSIeMtnvDv0ih9YaGOIKaeFwG4dlxHCp7JZTXotzvqFQSTEeI9UA
Zw+wrBaH4U5J+jk/v0M6VM23FFGstcJUaajfs+1bKITYr2fVpM0U7D/O34NgE4xz6bFCaKmwcrJp
IotEIMaBWWhLsAx4pTBtI4FQf6NmV6UNkQMRkXXDI1Fns3ooL2vZKgV5ZI9FrOOzTOtHdOuPTNwb
xHywEkliqIQYMRQxjwlDzluAW0JOEL+1MZuxN+WYJGVy1KmDDx6k1uhGuU16PxIymfjq4NdhuBXk
0SZPsfHMW20nhmyTH8t4s8b5UpuCujzMHS30yDiVltFfmyEdGOZC1TDJ8G0ylFxAgfBNbagk/sec
W1tQLmq4HKrPJP9quRzDgVLkqvurF9/LKtwLyNIrgEy6MjY+gNip9JlOYTOM8aW0RqB5zqb75H0j
MrRKei3vBC4uMjByhL3vqfMlyAwOuLD55ON5fPVmnNPHdNcbKnpWsxSIJvPIIZ8uenIgK+Jqm19C
G0yxkWS4Mh0cS31CnCErCbdqRTN0Y9xvd8smrHLDnhO/FbFznpwAFsdpVr2wFeKZ9nxXD18548DL
NtFXoVGX1H6xivhMOLPVJk6O8F3VZz75sKlrPfpEjZNGb027y7XXqV9DSuATDNHqi4PIJ8tsxTZ3
3xCV0k/rDCNyUAtF9PcxAD0hM/B88jFWemIuImWu9NIhDB8IOPDbiRz9tfisL7TovI5GP9WDO9kR
06IADYSMvcCK7YOfHqkRit2EoYt7q0Uvt7aTC3floc+PMFqhxH+KNFcjPG20xyY37lATb38gf0N+
t5KK27ggPyu+o3PET1N5bq1FO7eg9BnAokyrfBFiYasqW4w7qQ9znWCmOX6iBuy5nPh06XAYdyNs
uLlR7ordHKC8/AfHlMR4Bq/3Yq0Ysm3WGjIjT1RljdvuOCDh+Nnt+dAny0rFHPnW1XYszTQaz6CU
Ugh/tZuWAaEWvkJkqprxA0IdmNaWwaTgCpdOOT5llUxqK2DkvTUkFNlOK7YkS2Z+pJTt/dGfwGsI
vAaRBq4Ks1FoQd4DYG2tTmksrKn96Fj+jKPO1WoWYnmauqVa/WSMMy4m0XV+e1CoN+sT1kbsP+u+
RRDWq0TNi46P5m/tNwjzQmghzBEko22Wx30R+rSRbq31290qulNeZ4o7+jQ0xNVoedLJNIFzgkBq
YsH2SFXtallxUfZdA+TiVTXFAnO9KN5+LFteu2PrwJ3wXWpIViUx0mNbqtDmA5DMGvm8fc54mxde
sa66svggXx4jggmRS5YHRhadubTPJMwH1+XIDCpWFlJA1bMM+KpjBgPo0CysgjheKzuXXlKCrF98
0whmmFm9AAFNUaESjbi30jQfa5XK0Z6H0GVO0FRP96TS4ICjxldUUJny5s4Ys0/zjDbR+e2vGePj
Gtoqz4Gi4HUNLJbsI0fHFgSt1iRjHL2Ol+LUKqhyax+y/eToEHOMoYZffBpyXSo5mgnkXDlM/yRz
2X3YBnNhVLr5o1KrKzgxES/kii8MNq3h/OUBnvsB/vfJHxnoZ+IQnuNaFWUxgFYrMlRdWeCCL1VJ
+XMcKoePJGVheIGGbxRPYi6GxVj7nD5WXFy6P5QlrdgKDlGRhdwgsw2OH62kikx684AN+8A8hTCu
Fw0wr/EvRLvSXc5X8BX0graSdvQTcy7MBv6ENfe7dWyhY3z+boFPwUPj9D9/fjJRnxvjbe6oLTcH
Ggiz1j0yvtVdzRs+K4+Wx2uMcc84mndMKb8ojPHwqwhaK+iL/D6nDwA1hGkcFAG/CbS0XlqxyIi/
KYfga8bJGO55q6FZ/2KnEFb5ozzM+P11rJFHapGV6prtyxxnHN+MJ0JGNNNAHt2qDXwNa9gM+eAx
WG9Fxtb1Qa2KoRJ2OZvR06RT5L1It4N7qiVdhlsr9hzdnsGdrC1BASzVxEhCboQrLArBE8wL0aU/
Nw3y2AEWRcHyQL+Mv249kj9WDlMdCzZbk3udlmdxrk49b6MsW6zrDWgfDVDvCxNbmwe4r9gM0SM0
q3mHwDnwiQkflQsEYclcswKlGlDaxgeZ+zBQwYwqi1cs5go5VA5Eq8ndenu+NFTFef4Kx0aOO7YK
5dM5sC0puyAl/oniVzrKRJ+DnETU86QFAAa2N4CpCAvsodb3s83cfkSOJacDGXzL2bZhamYWVYYu
Md2jMrM85u+LlHAWzQ0LqCTkI0O8W0ssK1jX6m2maaxUv1TC6B3a2erW2xV/RkbyX1Q5aOfkDVu7
/vJk2mqGjgIgr/uq6fN+xO7G02X2EUki3yCrYpboRnnCjHm/hOhcoL1RXwpy0JrnFaCw9S69f05Z
niYpcjQ+dCT20+BCNb+GufFYvcJ3mb4oCtEb6HOIw4SVjTfTNOzfPn8v+QBdD059+Byd45Upm60r
Pqw397KrE8GRgs0O9/bcGhVUHMnVPBJjHoIs+o4x0IrAezuyhhfgOz6RqZtgxcp9DWHUNGWJCmeu
kUZdyWIb69TywZFNyenWcmMS7BrEsdAbemoenmWxcT/F7mhtuoNFV/dVSc+JnKJV2jKXk43Apa4z
YgiTTro34u3MnS6vMqGgdwcnEshVBfU7hUcZJhRMsWd2faQTKZfAQWZujNJCRY7rUAwtOUq0pPth
XCJKKapx59tbD6sN+H97jH+UBDis519y7Vk4A/h6qKdzAAYDk+8L1sbxiLpuJvy8EyK+iEqpN99s
+l2yfzz3q+pQ/mZ1t/Gh1lFiL75mshwsWRRNpySkiPrhnqtsp1sjlbzcfCRSUcIHmFkS7sZ2++ET
uZM+1C1TKMusoriq3YjBtzTSOosS2MygpZwFQURuwGReUtNS+Iy26g9gHnvptGXKUaXMMTGsJbPg
p7eIse1WY+6t0NbFTw0K0BPKhWXHTNPE8jAOZa51gGFVo5xoW54GZe98yQYviChEvLWNaU+ARwFP
K4REOg7KOIz4dEu93rSUs8ns1KaaECbV9dXLXe/EnNLYnxUaXcjRjCmBEHaHdu58fu5i+gpgNyA8
UisuaIUgtRCq/eu3ejkwvCkt0bdlvuHq6GWcqFuZuAvFz+GHJTLqtWC2tnbq7RScINiOvf4fRCgK
XxwNaiGxAr+4waSppxQ4TY9TWCTB1F0JQP49nPGJ6JUgUA==
`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0.vhd | 24 | 10163 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YdBG68RFwokFzFKR7nrliDOlnj+kk1DIHHuLOj0ERcmliOs+5nUCq2+I7g3RQADo/tw/5hYyhBvA
zkhz98SR0w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j+3SDUDDyQpwaJ4UUg1tCPqwSzhuWj7b+1nfm4NSTDcl723o9USSuBxoK+76BYb4n4RIJlaApOB1
xNyJ3TdKE3+cTmvo0JV4qZ/XJHZylmoeBz0Fa0FUE6qNsZHsOrUGeTkEzZcF/sKG+/yE9U7pWoo2
Vf/+czWAwGAF78M7eU0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHFWCJwUkRx0aWaiHT7rUDSuriVubrVt+dyN4XxebufJxmziEPnQW6R0Shvp3t9Rs28T0a6gDRTE
Yey998iArVO7WMLyPrC3VVfJAlUGA4SKXhclRes7vUyAWd942ytCM7CkgL8iKyxoTg6xgfAfb1bS
qKlQxP6Oh4UUMDF+wHj+TqR8Ri90ha2TKZ3vmzrYqXnqSsrUSiRPehahCB1EUZH03X39IWPBz/gL
jGMIzAwNsIFGk7JDXQ1D3yAeTLNRd0NJcbaXnRrczJd53QGhqk8FqQ8ewybUbV9d8utygp25BGSo
JL4M04pk4WhIMGjsQFVvSMt/b7bkXT5sNjgvEw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j4+Cq5t9jDH4b+tKONxSAQvUQSuEe6vmG/Fza6ThabY69JhhPiAIpyWkTk3pwrTii4y4QnUfomhd
SpT3nUMfy+A+uQihmL10hDFp3fMr/mfz4mde6CKmvH7NBA3c08FvVPiEDiRWg9D4PMn2iWzltZXB
4rCaDADltHHwoyn39vQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rVRC062BQnogimrJCqwTEd8ZOGC7aEi0dcp+jm3FwXnyuOU7ngEQ72N9ueAz6dcDQv3DZdlM5Zpu
mki8lLpfaQs1vszYHih3xmyOKcPdFqNb7otiQtmfyooFn6V5ZzK3hmaEFLqj6FRatAy4p2bTO2IO
DA4XayojNrn5+ADoj7yOj5hGWjrRbETfJQITMA+za7Lsu3ffroRuir2hOhDcPmOAKk0H+lG5J1/3
RGecNjZ6Px0gG+x+xDpWTFC6jSut/l9G+mYe7pWxhvOjNbfbpsKsCOeVD+NqT73v3Y/PYgd0cpBf
50bH+PiZYS93G80CmpaHUds75mMSCwIL/D9CJw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JPTsEMu7ivOCw+Wjrjiy3x7HTmU1csA0FSpSPA+aeDgUayQeahYc14vUAhzbnZvlrLWhUndZeDwo
3cAy7kv7lvuDgocp3TSVIEbRQbQQWEnF+lxyUk5f0XyY/eVMSaOdgfv7M/nPZJE52DlORF+IQ2B5
avNqsEHw/CM8qQX5A8/J21vVstkC1xfP6MseeK4nr+VBWZve6RaXZD+6i7X+GWzwfH0yO1tffjCQ
H2lhqG43HLBWd55LVB1ZVs7xPRYuRyrN4FLml3VvHtEXu8GA90OPGbzeuJuoiHDz5lmGgVEy6uNR
6ovEb87b8tpmnAZWAth8fcRz2a8gu2NtJmEg+g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
lHJV8fpNPaAZNP6iIPw0amUkAWeoac9F6Mn9lqxif19WHqLYLbQfJDRFOYN3pCmfdj64L9W/N1Ow
zUiFQ1Qn+/Po9LRxFhRjke+zlOLKcgmrz8Wsv/OJc4VSamOJ3dkTyGAaIz6iZjWAIfa3F20xboAz
QXBZHDMkFizWW6XCIBYurqj2WtAKSTo+Bn8syqerOb95UCNUITtoJ+4Ks9EWEUZ1S3AZ55HmtpfK
LybQ1/3Y6BdftkTr+jYn82lsEtYcZAhoxy4mD9Xafm1r7qcWxCRWhADW8LcZuOzFjH2Ppfz0ekQ4
2RYH0EMznWeFwuD9Zw9al80EuiW9Ua2WZSWij+5Tz+ria8QZ8bK6Wy/0J/+TX0BK6W8eBFVDLS7O
ync3GB+NMqTQa+CrDizkGVwKy0xiLspHkFF7qbRo1Hobt+3IBuFY1TLxGyaw/4iAp3TlQK9tLrYr
mCrBNRY0VvxkATuvpzYLQohRxqSd0kaY8gB1TeioNqP9mbysOa5WhVoasQAm9ZFO3dpzn1gk9Y+T
TjFjIzBsbELJlGenqcnZHlRY/zkuHXLnEqe+u2rsDfvD52AVJ9cr38Rb8Kk/Bc+eT3XZgrJ2bHlo
th4a75jw6wpEW2XabxTuE9rrlu5wY0Y5yfnNT6L8hi9URS5Q6N7eogvyGgppZktebcu7KlH6m9WM
RzYA8VNFwZSyXztX6Cml6BCcjERze9zHEznyaBoF3+uq9Y+bKpo037rLMDFhNOAyWcTdQF+w3+1n
KL28hwybFXjHjPlMiKdQU/Y/JkLDGzmLwVIi1C4NPJAfwGK8m+o2AEt9ZqGuGQPmiDqyNb4alRCL
/cjQHSIBx/BLHlpgwyPdS3hvGL6AbsaF3iErUBofmAzgXdo6/go0WkB6rBoqzxSiNPXRcVMdkdLV
u9XE02h/IvPQHWPB2e5LkoP+CT9iqF/JLaBwpQrG0fTxo+Pyyihl4h+o7b8gi164OJHTuKvGXWkI
bWaWaAEJ/CUXa5YjptXRicoW79TOwOwr5+95Eg/LpJayX7kZJgzqSISA7s0wo5URvsGmo7m3pz6E
p8pSfsWN3yJdPaes1adJkdbFzSNPw3SM9zgX22XZpW8U5DkQPGTu1TnRPxP6ZrNFOsBY2vvWj8F8
lYYVtw3LyGjW/YZwpB6V2QIureUbc1B96PTdnfqNr51/yVeuJEvkIEDSiu8MVJY2EJb/lEymD+w5
my/QRktpsR1KpFBklwnU3sXrUM51EjMfa9+yUaLN0R46kkkyLO+zb/DyHrXKeTY7rEYNUQnJpbGz
meMs+Rg+STAh/W+qQJyyJuz2tmxJI3bQPxl/1VFukYQJ/jdjgQfv1k8dtAdhobqLfO7bKwAzyz1h
y8bVBoEPWhzP2/Y0Z+B/JzRqvPpjNjs/Tx2M+ct09FolbxbskWvJt/Sesoh8Q9jDdhyZYGGuFyu7
55NK2jVYDt31YiVx9crEtLQ2lTyxm3erg1ez7Y36EwakRCFAZluocIeR9JgZ7js0LfdhbzzPe71b
p8e26QIF4Aycf8RSTejeav3/rzqyNmod6d4MH5LQ9ELziIcO1aBFcqFh8DHPN2CuoCVfnc3U0Tzi
DxpnXeBY4A+Rhe6uyu+byxuKNXvODb65fpFW/anQGkuEC+tp10XTq+6e5C/U/vPz+Gj1WFJrrzNp
k6xQH7s2GhF3tQ5W8ohJ7uvz8rpgis2QhreFJq9lhYSd+KJdaba1jZ+hAkIfJupdX4kMwfsxm/wn
5fnROcs+fMh7EwCbCSKuhNUiSx09OgudttRQGJSMABuUtsQzk7zX2PD6mY1cHynlp5dysZGXewqR
nAlJUuOAVbI73ZgG6dFCaVvbtgFGA+nf165ezt8VAamFVk5QnQHLdeLIhcp1AZQnH/ZjcMDl4oPl
pfLeOGUawoXtbdVURjICdFtJ8q6ChzsSDCMxuoF31FuXwP5pnGryzLiDuSnu2HHkoxIMcigxnyLD
TtefsxEwHLN+hVCrPCAAdNSIhddZ3bYiPk7lAMiv6BCxYDZGS9ZCM1cOSyucG7h3RdnQwg3A5uXO
SfaNEJlHtDMx4cucuENWxdybS+2ncYQF6fj1Fu0V7pYaYxViGda3gUhogY92s6649b5YAxESFyjg
lc5N9ZnOvQwpLzq9YKo4gfuXOJ1ZwbFPC7AsJpLI5RE97q78ajbqUqL7Aty67J63isNL8rkyQYWE
Q8su5MdBrzNeuGr8ExqF9PauDPluq/uTXAjfmCq6YUZotPV+6wKQSTYMSB1DuH4GXoRhGGIrwLH1
bgHNSWJr22pAZ8WoeHCvA774DRXPCDLHcKwBWLn3bQaIr8s76UTM61ii4eQ4/BOQhOOOW8UJFhXn
jDhByLQ2cRVkFIvNSCT20uFXwmV0zg2ba2tqO39eTBzRw8khvUsEExT0pHCemE3O1YCaFr5vBwSw
e1vxC3+AgIKIoKRU5pabirpjYeBT1+suWRwh4N4S344al5vL38TbuZG/o97tM0SZrDK8w+43gZzI
65yq4JKALCnx6NEIcqdMUvTq+wyyyt1g12c0dVUGGLQNaqiTWFOeCSI9UUKKGVQ3B8KSH6AhxeYS
gV0vNz1Q6oSp37/8qp5WCug8iMTcJc8byxf2ta84Ia1hJVN0LAQt2bKmCbEHgTLZ993g/8Qzkiq2
iaS78ZCzGRr39mWx/xl5KV3Zkfy/sz3/g5q4Zgwm4GvsHF4g6XBURE85FbMAikPLMhFFO3ebUSkH
u+DMoyuRqqmBkP8JxlkF/TaeIvZVHPXTKQ2j/zPsyAfWNMpnGu9ZKDsKuFP09SuaYYiPI6ev2l7S
SiyDxNSIiVR5xXoInO/7+nftScRIrAlDV5PMsbNryxPAgDF66zwrR7+PGs6HPt8WCuZ0uceYjl8J
D1yUA+BKkPDWCYsOEs9ABg/uRQFXVpYsg4SkW+tzw1u9gx5oa3nG2a/gNa1jei7maAG8AJC12obj
JCMCqAOVSP9yRjtQ0KBl6cJomFkQMSJcAKnpTAgRrB4TMUst34Nyxfum9b/Vel39/WXD0A6DjJ1f
O1q+SJQH7BQw/af+vLthdAhLxJIu2kY18gVfROWqP7/0a3ud0aHh78wWa9tQOg4f7EzgYx24L8gp
8ilAHOxg5iqw4RiWt4x0ocLVU+SdILKDjjyXuMxK2aBnKvr0h13NtMVUvF5CGDkwKrbmVQ64ZLHG
r4WGgqkzI3CuRFcarI5OOuRfoIUf6mK0nv3TbhGvr4Xilg1QxK/dRqQe8AziO+mKWAKZIWSBR0fE
nPvKHUkg9PB27PqPxrOOJa1qO5orSG5FB9QtWdL4BgqPU1+dYkFzbAKpXKcBqUMfS+Q16ptdxyi6
30j2PHUkM1JyVp+oIczWGmV/YiPXuQZ+cUdDu31IURvGmju6L0S60cAzthhROczysBr+HeRkgtP4
U4szYmOHC+iu7RSCV0Q8qDfwtD80Mex4aNknYed7U5MP/6OFRZOLnuguS5ARJ9JR6+ONnQSXv/Rw
X5RN3pWpjbrjKqRAodrXJDDbajJaP2BxEcoZhSlRh2mXa9iZsI4k+rjdAAZQc0Ql9dkz9nQ+kNXC
myXMN7A/mc4cipHUnwZgVNseIm1rijaOWeQ0p1MSprxEJ3azfcY6GGRB89N0b0F64mZG9UOnfwzW
HUZf+IGwIDR7YiC+HbfZ9mYjJCn69uocWOjkUxZxTqprwQlYNBKXWQ3k5OWUUpliRoqFc/IFqu0l
FPdgsXNBKqPf2VryDrVfOkFH09w0kvUVFsTmbz1Q/dYjC+fvcjTm42eJ666ZRDnDO2FQo/e7He02
MhjiRxK0rD1LNaaXhHbdPrASFi0X82oyukdFm6aNpJUN/SOySZL8qmpWlirog/IOk8c8A366IBif
16NM+F22rwqKszcVSIyfj1s3VmpAvCS26+8SsqLHlIB2fF6VCbd+MkaHVVkXj+GN8SuYtm3LOyyX
trRlhI6Ra+FlZzFaegz46OsCY+lTZ5RNAdfsY/aERCq0s01Jl6/7E60w86UwoI7yb/0B5T0jI3Fh
GqgJbDaPUHd8GXADlEhjI5Y1aSIeMtnvDv0ih9YaGOIKaeFwG4dlxHCp7JZTXotzvqFQSTEeI9UA
Zw+wrBaH4U5J+jk/v0M6VM23FFGstcJUaajfs+1bKITYr2fVpM0U7D/O34NgE4xz6bFCaKmwcrJp
IotEIMaBWWhLsAx4pTBtI4FQf6NmV6UNkQMRkXXDI1Fns3ooL2vZKgV5ZI9FrOOzTOtHdOuPTNwb
xHywEkliqIQYMRQxjwlDzluAW0JOEL+1MZuxN+WYJGVy1KmDDx6k1uhGuU16PxIymfjq4NdhuBXk
0SZPsfHMW20nhmyTH8t4s8b5UpuCujzMHS30yDiVltFfmyEdGOZC1TDJ8G0ylFxAgfBNbagk/sec
W1tQLmq4HKrPJP9quRzDgVLkqvurF9/LKtwLyNIrgEy6MjY+gNip9JlOYTOM8aW0RqB5zqb75H0j
MrRKei3vBC4uMjByhL3vqfMlyAwOuLD55ON5fPVmnNPHdNcbKnpWsxSIJvPIIZ8uenIgK+Jqm19C
G0yxkWS4Mh0cS31CnCErCbdqRTN0Y9xvd8smrHLDnhO/FbFznpwAFsdpVr2wFeKZ9nxXD18548DL
NtFXoVGX1H6xivhMOLPVJk6O8F3VZz75sKlrPfpEjZNGb027y7XXqV9DSuATDNHqi4PIJ8tsxTZ3
3xCV0k/rDCNyUAtF9PcxAD0hM/B88jFWemIuImWu9NIhDB8IOPDbiRz9tfisL7TovI5GP9WDO9kR
06IADYSMvcCK7YOfHqkRit2EoYt7q0Uvt7aTC3floc+PMFqhxH+KNFcjPG20xyY37lATb38gf0N+
t5KK27ggPyu+o3PET1N5bq1FO7eg9BnAokyrfBFiYasqW4w7qQ9znWCmOX6iBuy5nPh06XAYdyNs
uLlR7ordHKC8/AfHlMR4Bq/3Yq0Ysm3WGjIjT1RljdvuOCDh+Nnt+dAny0rFHPnW1XYszTQaz6CU
Ugh/tZuWAaEWvkJkqprxA0IdmNaWwaTgCpdOOT5llUxqK2DkvTUkFNlOK7YkS2Z+pJTt/dGfwGsI
vAaRBq4Ks1FoQd4DYG2tTmksrKn96Fj+jKPO1WoWYnmauqVa/WSMMy4m0XV+e1CoN+sT1kbsP+u+
RRDWq0TNi46P5m/tNwjzQmghzBEko22Wx30R+rSRbq31290qulNeZ4o7+jQ0xNVoedLJNIFzgkBq
YsH2SFXtallxUfZdA+TiVTXFAnO9KN5+LFteu2PrwJ3wXWpIViUx0mNbqtDmA5DMGvm8fc54mxde
sa66svggXx4jggmRS5YHRhadubTPJMwH1+XIDCpWFlJA1bMM+KpjBgPo0CysgjheKzuXXlKCrF98
0whmmFm9AAFNUaESjbi30jQfa5XK0Z6H0GVO0FRP96TS4ICjxldUUJny5s4Ys0/zjDbR+e2vGePj
Gtoqz4Gi4HUNLJbsI0fHFgSt1iRjHL2Ol+LUKqhyax+y/eToEHOMoYZffBpyXSo5mgnkXDlM/yRz
2X3YBnNhVLr5o1KrKzgxES/kii8MNq3h/OUBnvsB/vfJHxnoZ+IQnuNaFWUxgFYrMlRdWeCCL1VJ
+XMcKoePJGVheIGGbxRPYi6GxVj7nD5WXFy6P5QlrdgKDlGRhdwgsw2OH62kikx684AN+8A8hTCu
Fw0wr/EvRLvSXc5X8BX0graSdvQTcy7MBv6ENfe7dWyhY3z+boFPwUPj9D9/fjJRnxvjbe6oLTcH
Ggiz1j0yvtVdzRs+K4+Wx2uMcc84mndMKb8ojPHwqwhaK+iL/D6nDwA1hGkcFAG/CbS0XlqxyIi/
KYfga8bJGO55q6FZ/2KnEFb5ozzM+P11rJFHapGV6prtyxxnHN+MJ0JGNNNAHt2qDXwNa9gM+eAx
WG9Fxtb1Qa2KoRJ2OZvR06RT5L1It4N7qiVdhlsr9hzdnsGdrC1BASzVxEhCboQrLArBE8wL0aU/
Nw3y2AEWRcHyQL+Mv249kj9WDlMdCzZbk3udlmdxrk49b6MsW6zrDWgfDVDvCxNbmwe4r9gM0SM0
q3mHwDnwiQkflQsEYclcswKlGlDaxgeZ+zBQwYwqi1cs5go5VA5Eq8ndenu+NFTFef4Kx0aOO7YK
5dM5sC0puyAl/oniVzrKRJ+DnETU86QFAAa2N4CpCAvsodb3s83cfkSOJacDGXzL2bZhamYWVYYu
Md2jMrM85u+LlHAWzQ0LqCTkI0O8W0ssK1jX6m2maaxUv1TC6B3a2erW2xV/RkbyX1Q5aOfkDVu7
/vJk2mqGjgIgr/uq6fN+xO7G02X2EUki3yCrYpboRnnCjHm/hOhcoL1RXwpy0JrnFaCw9S69f05Z
niYpcjQ+dCT20+BCNb+GufFYvcJ3mb4oCtEb6HOIw4SVjTfTNOzfPn8v+QBdD059+Byd45Upm60r
Pqw397KrE8GRgs0O9/bcGhVUHMnVPBJjHoIs+o4x0IrAezuyhhfgOz6RqZtgxcp9DWHUNGWJCmeu
kUZdyWIb69TywZFNyenWcmMS7BrEsdAbemoenmWxcT/F7mhtuoNFV/dVSc+JnKJV2jKXk43Apa4z
YgiTTro34u3MnS6vMqGgdwcnEshVBfU7hUcZJhRMsWd2faQTKZfAQWZujNJCRY7rUAwtOUq0pPth
XCJKKapx59tbD6sN+H97jH+UBDis519y7Vk4A/h6qKdzAAYDk+8L1sbxiLpuJvy8EyK+iEqpN99s
+l2yfzz3q+pQ/mZ1t/Gh1lFiL75mshwsWRRNpySkiPrhnqtsp1sjlbzcfCRSUcIHmFkS7sZ2++ET
uZM+1C1TKMusoriq3YjBtzTSOosS2MygpZwFQURuwGReUtNS+Iy26g9gHnvptGXKUaXMMTGsJbPg
p7eIse1WY+6t0NbFTw0K0BPKhWXHTNPE8jAOZa51gGFVo5xoW54GZe98yQYviChEvLWNaU+ARwFP
K4REOg7KOIz4dEu93rSUs8ns1KaaECbV9dXLXe/EnNLYnxUaXcjRjCmBEHaHdu58fu5i+gpgNyA8
UisuaIUgtRCq/eu3ejkwvCkt0bdlvuHq6GWcqFuZuAvFz+GHJTLqtWC2tnbq7RScINiOvf4fRCgK
XxwNaiGxAr+4waSppxQ4TY9TWCTB1F0JQP49nPGJ6JUgUA==
`protect end_protected
| gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_1/hdl/vhdl/ANN_mul_mul_7ns_14s_14_1.vhd | 7 | 1533 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
port (
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(14 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
signal a_cvt: unsigned(7 - 1 downto 0);
signal b_cvt: signed(14 - 1 downto 0);
signal p_cvt: signed(14 - 1 downto 0);
begin
a_cvt <= unsigned(a);
b_cvt <= signed(b);
p_cvt <= signed (resize(unsigned (signed ('0' & a_cvt) * signed (b_cvt)), 14));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_mul_mul_7ns_14s_14_1 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of ANN_mul_mul_7ns_14s_14_1 is
component ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_mul_mul_7ns_14s_14_1_DSP48_0_U : component ANN_mul_mul_7ns_14s_14_1_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 |
Rookfighter/aes-ss17 | tutorial/ledblinker.vhd | 1 | 1002 | -- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LED blinking module
entity ledblinker is
port (clk: in std_logic; -- clock, rising edge
led: out std_logic); -- LED status, active high
end entity ledblinker;
architecture behavioral of ledblinker is
-- define length of counter
constant CNTLEN: natural := 24;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
signal led_int: std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if unsigned(cnt) = 12000000 then
cnt <= (others => '0');
led_int <= not led_int;
else
cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
led <= led_int;
end architecture behavioral;
| gpl-3.0 |
1995parham/FPGA-Homework | HW-1/src/p4-5/t-flipflop.vhd | 1 | 665 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 04-03-2016
-- Module Name: t-flipflop.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity t_flipflop is
port( t, clk : in std_logic;
q, q_bar : out std_logic);
end entity;
architecture behavioral of t_flipflop is
signal buff : std_logic := '0';
begin
q <= buff;
q_bar <= not buff;
process (clk)
begin
if clk'event and clk = '1' and t = '1' then
buff <= not buff;
end if;
end process;
end architecture;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers.vhd | 3 | 59747 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop Finite State Machine (FSM)
--
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in,
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig,
health_info => health_info_sig,
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info => err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info => err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info => err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info => err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info => err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info => err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info => err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info => err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info => err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info => err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change
);
fault_info <= fault_info_sig;
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- Anything below here is pure combinational.
-- Control part (Logic for checking how we should give credit to previous node, whether it is real or fake credit)
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
-- Data-path related part (party calculation)
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
-- Data-path related part (parity checking)
process(valid_in, RX, xor_all)begin
fault_info_sig <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_info_sig <= '1';
end if;
end process;
-- Mixture of data-path related and control part
process(RX, faulty_packet_out, fault_info_sig, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, RX, valid_in)begin
-- this is the default value of the memory!
-- Writing to the corresponding location where write pointer is pointing to (in the FIFO slots)
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
-- Some default values (some sort of initialization, also used for avoiding latch(es) ??)
fault_info_sig <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_info_sig = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_info_sig = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_info_sig = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
-- Control part of FIFO (reading the corresponding location based on where read pointer is pointing to in FIFO slots)
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
-- Control part of FIFO
-- read enable signal computation logic (based on grants from arbiters (allocator) and empty signal)
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
-- Control part of FIFO (write pointer update logic (rotate left one-bit))
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
-- Control part of FIFO (read pointer update logic (rotate left one-bit))
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
-- Control part of FIFO (more or less, although because of fault_out, it is also a bit related to the data-path part)
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_info_sig) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_info_sig = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
-- Control part of FIFO (Empty and Full signals computation logic)
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Processor_NI/NI.vhd | 3 | 19778 | ---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10 -- the current node's address
); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end; --entity NI
architecture logic of NI is
-- packet format:
-- the parity bit is calculated by the NI and the processor has no control over it
-- flit type is generated by the NI and process has no control over it
-- header flit
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit |
-- '----------------------------------------------------------------------'
-- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it)
-- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0)
-- body flit 1
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PACKET LENGTH | PACKET ID |parity bit |
-- '----------------------------------------------------------------------'
-- PACEKT ID is determined and added by the NI (the processor has no control over it)
-- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14)
-- other body flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- Tail flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
begin
process(clk, enable, write_byte_enable)
begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= (others=>'0');
state <= IDLE;
packet_counter_out <= (others=>'0');
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en)
begin
storage_in <= storage ;
valid_data_in <= valid_data;
if enable = '1' and address = NI_reserved_data_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1'then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out)
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT;
packet_length_counter_in <= ("0000" & FIFO_Data_out(23 downto 16))-1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - "000000000001";
if packet_length_counter_out = "000000000010" then
state_in <= TAIL_FLIT;
else
state_in <= BODY_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = NI_reserved_data_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = NI_reserved_data_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = NI_flag_address then
data_read <= flag_register;
elsif old_address = NI_counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & "000000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
| gpl-3.0 |
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