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EliasLuiz/TCC | Leon3/lib/gaisler/uart/apbuart.vhd | 1 | 21003 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
stop : std_ulogic; -- 0: one stop bit, 1: two stop bits
tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty
break : std_ulogic; -- break detected
breakirqen : std_ulogic; -- generate irq when break has been received
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
irqpend : std_ulogic; -- pending irq for delayed rx irq
delayirqen : std_ulogic; -- enable delayed rx irq
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(sbits-1 downto 0);
brate : std_logic_vector(sbits-1 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0');
constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0');
constant fifozero : fifo := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs :=
(rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0',
paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1',
tsempty => '1', stop => '0', tsemptyirqen => '0', break => '0', breakirqen => '0',
ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'),
rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero,
rshift => (others => '0'), tshift => (others => '1'), thold => fifozero,
irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle,
txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0',
tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'),
txd => '1', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'),
rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero,
rcnt => rcntzero, tcnt => rcntzero);
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(sbits-1 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(sbits-1) and not r.scaler(sbits-1);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(15) := r.stop;
rdata(14) := r.tsemptyirqen;
rdata(13) := r.delayirqen;
rdata(12) := r.breakirqen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(sbits-1 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.stop := apbi.pwdata(15);
v.tsemptyirqen := apbi.pwdata(14);
v.delayirqen := apbi.pwdata(13);
v.breakirqen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
if (r.rxtick and r.delayirqen) = '1' then
v.irqcnt := v.irqcnt + 1;
end if;
if r.irqcnt(5 downto 4) = "11" then
v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost !
v.irqpend := '0';
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stopbit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := '0' & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.stop = '1' then
v.txstate := stopbit;
else
v.txstate := idle;
end if;
end if;
when stopbit =>
if r.txtick = '1' then
v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if r.delayirqen = '0' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
end if;
if rxd = '1' then
if r.delayirqen = '1' then
v.irqpend := r.rirqen; v.irqcnt := (others => '0');
end if;
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then
v.break := '1';
v.irq := v.irq or r.breakirqen;
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
if (r.rfifoirqen and r.rxen and rhalffull) = '1' then
v.irqpend := '0';
end if;
end if;
v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty);
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break;
v.tsempty := RES.tsempty; v.stop := RES.stop; v.txen := RES.txen; v.rxen := RES.rxen;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
v.rcnt := RES.rcnt; v.tcnt := RES.tcnt;
v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr;
v.rraddr := RES.rraddr; v.traddr := RES.traddr;
v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend;
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= (others => '0');
uarto.scaler(sbits-1 downto 0) <= r.scaler;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
uarto.flow <= '0';
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.ctsn <= rin.ctsn;
r.rxf <= rin.rxf;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq) & ", scaler bits " & tost(sbits));
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/leon3s.vhd | 1 | 6790 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3sl150/config.vhd | 1 | 6961 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/dcom.vhd | 1 | 5672 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom
-- File: dcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DSU Communications module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libdcom.all;
entity dcom is
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end;
architecture struct of dcom is
type dcom_state_type is (idle, addr1, read1, read2, write1, write2);
type reg_type is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
len : std_logic_vector(5 downto 0);
write : std_ulogic;
clen : std_logic_vector(1 downto 0);
state : dcom_state_type;
hresp : std_logic_vector(1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ((others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), idle, (others => '0'));
signal r, rin : reg_type;
begin
comb : process(dmao, rst, uarto, ahbi, r)
variable v : reg_type;
variable enable : std_ulogic;
variable newlen : std_logic_vector(5 downto 0);
variable vuarti : dcom_uart_in_type;
variable vdmai : ahb_dma_in_type;
variable newaddr : std_logic_vector(31 downto 2);
begin
v := r;
vuarti.read := '0'; vuarti.write := '0'; vuarti.data := r.data(31 downto 24);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010"; vdmai.busy := '0';
vdmai.address := r.addr; vdmai.wdata := ahbdrivedata(r.data);
vdmai.write := r.write; vdmai.irq := '0';
-- save hresp
if dmao.ready = '1' then v.hresp := ahbi.hresp; end if;
-- address incrementer
newlen := r.len - 1;
newaddr := r.addr(31 downto 2) + 1;
case r.state is
when idle => -- idle state
v.clen := "00";
if uarto.dready = '1' then
if uarto.data(7) = '1' then v.state := addr1; end if;
v.write := uarto.data(6); v.len := uarto.data(5 downto 0);
vuarti.read := '1';
end if;
when addr1 => -- receive address
if uarto.dready = '1' then
v.addr := r.addr(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then
if r.write = '1' then v.state := write1; else v.state := read1; end if;
end if;
when read1 => -- read AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.data := ahbreadword(dmao.rdata); v.state := read2;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
when read2 => -- send read-data on uart
if uarto.thempty = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.write := '1'; v.clen := r.clen + 1;
if (r.clen(1) and not v.clen(1)) = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := read1; end if;
end if;
end if;
when write1 => -- receive write-data
if uarto.dready = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then v.state := write2; end if;
when write2 => -- write AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := write1; end if;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
when others =>
v.state := idle; v.write := '0';
end case;
if (not RESET_ALL) and (uarto.lock and rst) = '0' then
v.state := RES.state; v.write := RES.write;
end if;
rin <= v; dmai <= vdmai; uarti <= vuarti;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (uarto.lock and rst) = '0' then
r <= RES;
end if;
end if;
end process;
end;
| gpl-3.0 |
hoglet67/CoPro6502 | src/CoPro6809.vhd | 1 | 11973 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CoPro6809 is
port (
-- GOP Signals
fastclk : in std_logic;
tp : out std_logic_vector(8 downto 2);
test : out std_logic_vector(6 downto 1);
sw : in std_logic_vector(2 downto 1);
fcs : out std_logic;
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end CoPro6809;
architecture BEHAVIORAL of CoPro6809 is
component dcm_49_16
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component tuberom_6809
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component cpu09
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(7 downto 0);
irq : in std_logic;
firq : in std_logic;
nmi : in std_logic;
halt : in std_logic;
hold : in std_logic;
vma : out std_logic;
lic_out : out std_logic;
ifetch : out std_logic;
opfetch : out std_logic;
ba : out std_logic;
bs : out std_logic;
addr : out std_logic_vector(15 downto 0);
rw : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
component tube
port(
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data : inout std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdnw : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- drq : out std_logic;
-- dackb : in std_logic;
p_addr : in std_logic_vector(2 downto 0);
p_cs_b : in std_logic;
p_data_in : in std_logic_vector(7 downto 0);
p_data_out : out std_logic_vector(7 downto 0);
p_rdnw : in std_logic;
p_phi2 : in std_logic;
p_rst_b : out std_logic;
p_nmi_b : inout std_logic;
p_irq_b : inout std_logic
);
end component;
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_16M00 : std_logic;
signal phi0 : std_logic;
signal phi1 : std_logic;
signal phi2 : std_logic;
signal phi3 : std_logic;
signal cpu_clken : std_logic;
signal clken_counter : std_logic_vector (3 downto 0);
signal bootmode : std_logic;
signal RSTn : std_logic;
signal bs : std_logic;
signal ba : std_logic;
signal vma : std_logic;
signal ifetch : std_logic;
signal opfetch : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_R_W_n : std_logic;
signal cpu_addr_int : std_logic_vector (15 downto 0);
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_sync : std_logic;
signal cpu_NMI_sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_dcm_49_16 : dcm_49_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_tuberom : tuberom_6809 port map (
CLK => clk_16M00,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
Inst_cpu09: cpu09 PORT MAP(
clk => phi2, -- E clock input (falling edge)
rst => not RSTn, -- reset input (active high)
vma => vma, -- valid memory address (active high)
lic_out => open, -- last instruction cycle (active high)
ifetch => ifetch, -- instruction fetch cycle (active high)
opfetch => opfetch, -- opcode fetch (active high)
ba => ba, -- bus available (high on sync wait or DMA grant)
bs => bs, -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr => cpu_addr_int, -- address bus output
rw => cpu_R_W_n, -- read not write output
data_out => cpu_dout, -- data bus output
data_in => cpu_din, -- data bus input
irq => cpu_NMI_sync, -- interrupt request input (active high)
firq => cpu_IRQ_sync, -- fast interrupt request input (active high)
nmi => '0', -- non maskable interrupt request input (active high)
halt => '0', -- halt input (active high) grants DMA
hold => '0' -- hold input (active high) extend bus cycle
);
-- Remap the hardware vectors from 0xFFFx to 0xFEFx
cpu_addr <= cpu_addr_int when bs = '0'
else cpu_addr_int(15 downto 9) & '0' & cpu_addr_int(7 downto 0);
inst_tube: tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => p_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => phi2,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
p_cs_b <= '0' when vma = '1' and cpu_addr(15 downto 4) = "111111101110" else '1';
rom_cs_b <= '0' when vma = '1' and cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
ram_cs_b <= '0' when vma = '1' and p_cs_b = '1' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1";
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and Phi2);
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr(15 downto 0);
ram_data <= cpu_dout when cpu_R_W_n = '0' else "ZZZZZZZZ";
fcs <= '1';
testpr : process(sw)
begin
if (sw(1) = '1' and sw(2) = '1') then
test(6) <= opfetch and Phi0;
test(5) <= cpu_addr(11);
test(4) <= cpu_addr(10);
test(3) <= cpu_addr(9);
test(2) <= cpu_addr(8);
test(1) <= cpu_addr(7);
tp(8) <= cpu_addr(6);
tp(7) <= cpu_addr(5);
tp(6) <= cpu_addr(4);
tp(5) <= cpu_addr(3);
tp(4) <= cpu_addr(2);
tp(3) <= cpu_addr(1);
tp(2) <= cpu_addr(0);
-- test(6) <= CPU_NMI_n;
-- test(5) <= cpu_wr_n;
-- if h_addr(2 downto 0) = "101" and h_cs_b = '0' then
-- test(4) <= '1';
-- else
-- test(4) <= '0';
-- end if;
-- if cpu_addr(2 downto 0) = "101" and p_cs_b = '0' then
-- test(3) <= '1';
-- else
-- test(3) <= '0';
-- end if;
-- test(2) <= clk_6M00;
-- test(1) <= cpu_dout(7);
-- tp(8) <= cpu_dout(6);
-- tp(7) <= cpu_dout(5);
-- tp(6) <= cpu_dout(4);
-- tp(5) <= cpu_dout(3);
-- tp(4) <= cpu_dout(2);
-- tp(3) <= cpu_dout(1);
-- tp(2) <= cpu_dout(0);
else
test(6) <= phi2; -- 12
test(5) <= vma; -- 11
test(4) <= bs; -- 10
test(3) <= ba; -- 9
test(2) <= cpu_R_W_n; -- 8
test(1) <= rom_cs_b; -- 7
tp(8) <= RSTn; -- 6
tp(7) <= ram_wr_int; -- 5
tp(6) <= ram_oe_int; -- 4
tp(5) <= p_cs_b; -- 3
tp(4) <= CPU_IRQ_n; -- 2
tp(3) <= CPU_NMI_n; -- 1
tp(2) <= bootmode; -- 0
end if;
end process;
sync_gen : process(phi2, RSTn)
begin
if RSTn = '0' then
cpu_NMI_sync <= '0';
cpu_IRQ_sync <= '0';
elsif rising_edge(phi2) then
cpu_NMI_sync <= not cpu_NMI_n;
cpu_IRQ_sync <= not cpu_IRQ_n;
end if;
end process;
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_16M00, RSTn)
begin
if RSTn = '0' then
bootmode <= '1';
elsif rising_edge(clk_16M00) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
-- 4MHz
-- cpu_clken active on cycle 0, 4, 8, 12
-- address/data changes on cycle 1, 5, 9, 13
-- phi0 active on cycle 1..2
-- phi1 active on cycle 2..3
-- phi2 active on cycle 3..4
-- phi3 active on cycle 4..5
-- alternative
-- phi0 active on cycle 1
-- phi1 active on cycle 2
-- phi2 active on cycle 3
-- phi3 active on cycle 4
--------------------------------------------------------
clk_gen : process(clk_16M00)
begin
if rising_edge(clk_16M00) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0) and clken_counter(1);
--phi0 <= not clken_counter(1);
phi0 <= cpu_clken;
phi1 <= phi0;
phi2 <= phi1;
phi3 <= phi2;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/cypress/ssram/cy7c1380d.vhd | 4 | 26441 | --***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/gencomp/tech.in.vhd | 2 | 356 | -- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_TRANSTECH : integer := CFG_TRANS_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/vm2413/AttackTableMul.vhd | 2 | 2413 | --
-- AttackTableMul.vhd
-- Envelope attack shaping table for VM2413
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity AttackTableMul is
port(
i0 : in std_logic_vector( 7 downto 0 ); -- ³µ 8bit (® 0bit, ¬ 8bit)
i1 : in std_logic_vector( 7 downto 0 ); -- t« 8bit (® 8bit)
o : out std_logic_vector( 13 downto 0 ) -- t«14bit (® 8bit, ¬ 6bit)
);
end entity;
architecture rtl of AttackTableMul is
signal w_mul : std_logic_vector( 16 downto 0 );
begin
w_mul <= ('0' & i0) * i1;
o <= w_mul( 15 downto 2 ); -- bit16 Í bit15 Ư¶ÈÌÅJbgBbit1`0 (¬) ÍØèÌÄB
end architecture;
| gpl-3.0 |
hoglet67/AtomBusMon | src/MC6809CpuMonLX9.vhd | 2 | 7579 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonLX9.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMonLX9
--Device: XC3S250E/XC3S500E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for LX9
);
port (
clock : in std_logic;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test : out std_logic;
-- 6809/6809E mode selection
-- Jumper is between pins B1 and D1
-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
EMode_n : in std_logic;
--6809 Signals
PIN33 : inout std_logic;
PIN34 : inout std_logic;
PIN35 : inout std_logic;
PIN36 : inout std_logic;
PIN38 : inout std_logic;
PIN39 : in std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMonLX9;
architecture behavioral of MC6809CpuMonLX9 is
signal clk_count : std_logic_vector(1 downto 0);
signal quadrature : std_logic_vector(1 downto 0);
signal clock7_3728 : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal E : std_logic;
signal Q : std_logic;
signal DMA_n_BREQ_n : std_logic;
signal MRDY : std_logic;
signal TSC : std_logic;
signal LIC : std_logic;
signal AVMA : std_logic;
signal BUSY : std_logic;
signal XTAL : std_logic;
signal EXTAL : std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
wrapper : entity work.MC6809CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
-- Fast clock
clock => clock,
-- Quadrature clocks
E => E,
Q => Q,
--6809 Signals
DMA_n_BREQ_n => DMA_n_BREQ_n,
-- 6809E Sig
TSC => TSC,
LIC => LIC,
AVMA => AVMA,
BUSY => BUSY,
-- Signals common to both 6809 and 6809E
RES_n => RES_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n,
FIRQ_n => FIRQ_n,
HALT_n => HALT_n,
BS => BS,
BA => BA,
R_W_n => R_W_n,
Addr => Addr,
Data => Data,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2
);
-- Pins whose functions are dependent on "E" mode
PIN33 <= BUSY when EMode_n = '0' else 'Z';
DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
PIN34 <= 'Z' when EMode_n = '0' else E;
E <= PIN34 when EMode_n = '0' else quadrature(1);
PIN35 <= 'Z' when EMode_n = '0' else Q;
Q <= PIN35 when EMode_n = '0' else quadrature(0);
PIN36 <= AVMA when EMode_n = '0' else 'Z';
MRDY <= '1' when EMode_n = '0' else PIN36;
PIN38 <= LIC when EMode_n = '0' else 'Z';
EXTAL <= '0' when EMode_n = '0' else PIN38;
TSC <= PIN39 when EMode_n = '0' else '0';
XTAL <= '0' when EMode_n = '0' else PIN39;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-- Quadrature clock generator, unused in 6809E mode
quadrature_gen : process(EXTAL)
begin
if rising_edge(EXTAL) then
if (MRDY = '1') then
if (quadrature = "00") then
quadrature <= "01";
elsif (quadrature = "01") then
quadrature <= "11";
elsif (quadrature = "11") then
quadrature <= "10";
else
quadrature <= "00";
end if;
end if;
end if;
end process;
-- Seperate piece of circuitry that emits a 7.3728MHz clock
inst_dcm1 : entity work.DCM1 port map(
CLKIN_IN => clock,
CLK0_OUT => clock7_3728,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
clk_gen : process(clock7_3728)
begin
if rising_edge(clock7_3728) then
clk_count <= clk_count + 1;
end if;
end process;
end behavioral;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/ram/ssdram256Mb.vhd | 2 | 10135 | -------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ssdram256Mb is
generic (
freq_g : integer := 100
);
port (
clock_i : in std_logic;
reset_i : in std_logic;
refresh_i : in std_logic := '1';
-- Static RAM bus
addr_i : in std_logic_vector(24 downto 0); -- 32MB
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
cs_i : in std_logic;
oe_i : in std_logic;
we_i : in std_logic;
-- SD-RAM ports
mem_cke_o : out std_logic;
mem_cs_n_o : out std_logic;
mem_ras_n_o : out std_logic;
mem_cas_n_o : out std_logic;
mem_we_n_o : out std_logic;
mem_udq_o : out std_logic;
mem_ldq_o : out std_logic;
mem_ba_o : out std_logic_vector( 1 downto 0);
mem_addr_o : out std_logic_vector(12 downto 0);
mem_data_io : inout std_logic_vector(15 downto 0)
);
end entity;
architecture Behavior of ssdram256Mb is
constant SdrCmd_de_c : std_logic_vector(3 downto 0) := "1111"; -- deselect
constant SdrCmd_xx_c : std_logic_vector(3 downto 0) := "0111"; -- no operation
constant SdrCmd_rd_c : std_logic_vector(3 downto 0) := "0101"; -- read
constant SdrCmd_wr_c : std_logic_vector(3 downto 0) := "0100"; -- write
constant SdrCmd_ac_c : std_logic_vector(3 downto 0) := "0011"; -- activate
constant SdrCmd_pr_c : std_logic_vector(3 downto 0) := "0010"; -- precharge all
constant SdrCmd_re_c : std_logic_vector(3 downto 0) := "0001"; -- refresh
constant SdrCmd_ms_c : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set
-- SD-RAM control signals
signal SdrCmd_s : std_logic_vector(3 downto 0);
signal SdrBa_s : std_logic_vector(1 downto 0);
signal SdrUdq_s : std_logic;
signal SdrLdq_s : std_logic;
signal SdrAdr_s : std_logic_vector(12 downto 0);
signal SdrDat_s : std_logic_vector(15 downto 0);
signal ram_req_s : std_logic;
signal ram_ack_s : std_logic;
signal ram_addr_s : std_logic_vector(24 downto 0);
signal ram_din_s : std_logic_vector( 7 downto 0);
signal ram_dout_s : std_logic_vector( 7 downto 0);
signal ram_we_s : std_logic;
begin
-- Detect request
process (reset_i, clock_i)
variable pcs_v : std_logic_vector(1 downto 0);
variable acess_v : std_logic;
begin
if reset_i = '1' then
data_o <= (others => '1');
ram_we_s <= '0';
ram_req_s <= '0';
pcs_v := "00";
elsif rising_edge(clock_i) then
if ram_req_s = '1' and ram_ack_s = '1' then
if ram_we_s = '0' then
data_o <= ram_dout_s;
end if;
ram_req_s <= '0';
end if;
if pcs_v = "01" then
ram_addr_s <= addr_i;
ram_req_s <= '1';
if we_i = '1' then
ram_din_s <= data_i;
ram_we_s <= '1';
else
ram_we_s <= '0';
end if;
end if;
acess_v := cs_i and (oe_i or we_i);
pcs_v := pcs_v(0) & acess_v;
end if;
end process;
----------------------------
process (clock_i)
type typSdrRoutine_t is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne );
variable SdrRoutine_v : typSdrRoutine_t := SdrRoutine_Null;
variable SdrRoutineSeq_v : unsigned( 7 downto 0) := X"00";
variable refreshDelayCounter_v : unsigned(23 downto 0) := x"000000";
variable SdrRefreshCounter_v : unsigned(15 downto 0) := X"0000";
variable SdrAddress_v : std_logic_vector(24 downto 0);
begin
if rising_edge(clock_i) then
ram_ack_s <= '0';
case SdrRoutine_v is
when SdrRoutine_Null =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if refreshDelayCounter_v = 0 then
SdrRoutine_v := SdrRoutine_Init;
end if;
when SdrRoutine_Init =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_pr_c;
SdrAdr_s <= (others => '1');
SdrBa_s <= "00";
SdrUdq_s <= '1';
SdrLdq_s <= '1';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"04" or SdrRoutineSeq_v = X"0C" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"14" then
SdrCmd_s <= SdrCmd_ms_c;
SdrAdr_s <= "000" & "1" & "00" & "010" & "0" & "000"; -- Single, Standard, CAS Latency=2, WT=0(seq), BL=1
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"17" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_Idle =>
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
if ram_req_s = '1' and ram_ack_s = '0' then
SdrAddress_v := ram_addr_s;
if ram_we_s = '1' then
SdrRoutine_v := SdrRoutine_WriteOne;
else
SdrRoutine_v := SdrRoutine_ReadOne;
end if;
elsif SdrRefreshCounter_v < 4096 and refresh_i = '1' then
SdrRoutine_v := SdrRoutine_RefreshAll;
SdrRefreshCounter_v := SdrRefreshCounter_v + 1;
end if;
when SdrRoutine_RefreshAll =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_re_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_ReadOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(24 downto 23);
SdrAdr_s <= SdrAddress_v(22 downto 10); -- Row (13 bits)
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_rd_c;
SdrAdr_s(12 downto 9) <= "0010"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(8 downto 0) <= SdrAddress_v(9 downto 1); -- Col (9 bits)
SdrUdq_s <= '0';
SdrLdq_s <= '0';
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
if SdrAddress_v(0) = '0' then
ram_dout_s <= mem_data_io(7 downto 0);
else
ram_dout_s <= mem_data_io(15 downto 8);
end if;
ram_ack_s <= '1';
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"06" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
when SdrRoutine_WriteOne =>
if SdrRoutineSeq_v = X"00" then
SdrCmd_s <= SdrCmd_ac_c;
SdrBa_s <= SdrAddress_v(24 downto 23);
SdrAdr_s <= SdrAddress_v(22 downto 10);
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"02" then
SdrCmd_s <= SdrCmd_wr_c;
SdrAdr_s(12 downto 9) <= "0010"; -- A10 = '1' => Auto Pre-charge
SdrAdr_s(8 downto 0) <= SdrAddress_v(9 downto 1);
SdrUdq_s <= not SdrAddress_v(0);
SdrLdq_s <= SdrAddress_v(0);
SdrDat_s <= ram_din_s & ram_din_s;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"03" then
ram_ack_s <= '1';
SdrCmd_s <= SdrCmd_xx_c;
SdrDat_s <= (others => 'Z');
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
elsif SdrRoutineSeq_v = X"05" then
SdrRoutineSeq_v := X"00";
SdrRoutine_v := SdrRoutine_Idle;
else
SdrCmd_s <= SdrCmd_xx_c;
SdrRoutineSeq_v := SdrRoutineSeq_v + 1;
end if;
end case;
refreshDelayCounter_v := refreshDelayCounter_v + 1;
if refreshDelayCounter_v >= ( freq_g * 1000 * 64 ) then
refreshDelayCounter_v := x"000000";
SdrRefreshCounter_v := x"0000";
end if;
end if;
end process;
mem_cke_o <= '1';
mem_cs_n_o <= SdrCmd_s(3);
mem_ras_n_o <= SdrCmd_s(2);
mem_cas_n_o <= SdrCmd_s(1);
mem_we_n_o <= SdrCmd_s(0);
mem_udq_o <= SdrUdq_s;
mem_ldq_o <= SdrLdq_s;
mem_ba_o <= SdrBa_s;
mem_addr_o <= SdrAdr_s;
mem_data_io <= SdrDat_s;
end architecture; | gpl-3.0 |
fbelavenuto/msx1fpga | src/cpu/t80_reg.vhd | 2 | 3810 | --
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
| gpl-3.0 |
hoglet67/AtomBusMon | src/AVR8/Memory/XDM_Generic.vhd | 3 | 991 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XDM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/i2s_intf.vhd | 2 | 6915 | --
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2s_intf is
generic (
mclk_rate : positive := 12000000;
sample_rate : positive := 8000;
preamble : positive := 1; -- I2S
word_length : positive := 16
);
port (
-- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)
clock_i : in std_logic;
reset_i : in std_logic;
-- Parallel IO
pcm_inl_o : out std_logic_vector(word_length - 1 downto 0);
pcm_inr_o : out std_logic_vector(word_length - 1 downto 0);
pcm_outl_i : in std_logic_vector(word_length - 1 downto 0);
pcm_outr_i : in std_logic_vector(word_length - 1 downto 0);
-- Codec interface (right justified mode)
-- MCLK is generated at half of the CLK input
i2s_mclk_o : out std_logic;
-- LRCLK is equal to the sample rate and is synchronous to
-- MCLK. It must be related to MCLK by the oversampling ratio
-- given in the codec datasheet.
i2s_lrclk_o : out std_logic;
-- Data is shifted out on the falling edge of BCLK, sampled
-- on the rising edge. The bit rate is determined such that
-- it is fast enough to fit preamble + word_length bits into
-- each LRCLK half cycle. The last cycle of each word may be
-- stretched to fit to LRCLK. This is OK at least for the
-- WM8731 codec.
-- The first falling edge of each timeslot is always synchronised
-- with the LRCLK edge.
i2s_bclk_o : out std_logic;
-- Output bitstream
i2s_d_o : out std_logic;
-- Input bitstream
i2s_d_i : in std_logic
);
end entity;
architecture rtl of i2s_intf is
constant ratio_mclk_fs : positive := (mclk_rate / sample_rate);
constant lrdivider_top : positive := ratio_mclk_fs - 1;
constant bdivider_top : positive := (ratio_mclk_fs / 4 / (preamble + word_length) * 2) - 1;
constant nbits : positive := preamble + word_length;
subtype lrdivider_t is integer range 0 to lrdivider_top;
subtype bdivider_t is integer range 0 to bdivider_top;
subtype bitcount_t is integer range 0 to nbits;
signal lrdivider : lrdivider_t;
signal bdivider : bdivider_t;
signal bitcount : bitcount_t;
signal mclk_r : std_logic;
signal lrclk_r : std_logic;
signal bclk_r : std_logic;
-- Shift register is long enough for the number of data bits
-- plus the preamble, plus an extra bit on the right to register
-- the incoming data
signal shiftreg : std_logic_vector(nbits downto 0);
begin
i2s_mclk_o <= mclk_r;
i2s_lrclk_o <= lrclk_r;
i2s_bclk_o <= bclk_r;
i2s_d_o <= shiftreg(nbits); -- data goes out MSb first
process(reset_i, clock_i)
begin
if reset_i = '1' then
pcm_inl_o <= (others => '0');
pcm_inr_o <= (others => '0');
-- Preload down-counters for clock generation
lrdivider <= lrdivider_top;
bdivider <= bdivider_top;
bitcount <= nbits;
mclk_r <= '0';
lrclk_r <= '0';
bclk_r <= '0';
shiftreg <= (others => '0');
elsif rising_edge(clock_i) then
-- Generate MCLK at half input clock rate
mclk_r <= not mclk_r;
-- Generate LRCLK at rate specified by codec configuration
if lrdivider = 0 then
-- LRCLK divider has reached 0 - start again from the top
lrdivider <= lrdivider_top;
-- Generate LRCLK edge and sync the BCLK counter
lrclk_r <= not lrclk_r;
bclk_r <= '0';
bitcount <= nbits; -- 1 extra required for setup
bdivider <= bdivider_top;
-- Load shift register with output data padding preamble
-- with 0s. Load output buses with input word from the
-- previous timeslot.
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
if lrclk_r = '0' then
-- Previous channel input is LEFT. This is available in the
-- shift register at the end of a cycle, right justified
pcm_inl_o <= shiftreg(word_length - 1 downto 0);
-- Next channel to output is RIGHT. Load this into the
-- shift register at the start of a cycle, left justified
shiftreg(word_length downto 1) <= pcm_outr_i;
else
-- Previous channel input is RIGHT
pcm_inr_o <= shiftreg(word_length - 1 downto 0);
-- Next channel is LEFT
shiftreg(word_length downto 1) <= pcm_outl_i;
end if;
else
-- Decrement the LRCLK counter
lrdivider <= lrdivider - 1;
-- Generate BCLK at a suitable rate to fit the required number
-- of bits into each timeslot. Data is changed on the falling edge,
-- sampled on the rising edge
if bdivider = 0 then
-- If all bits have been output for this phase then
-- stop and wait to sync back up with LRCLK
if bitcount > 0 then
-- Reset
bdivider <= bdivider_top;
-- Toggle BCLK
bclk_r <= not bclk_r;
if bclk_r = '0' then
-- Rising edge - shift in current bit and decrement bit counter
bitcount <= bitcount - 1;
shiftreg(0) <= i2s_d_i;
else
-- Falling edge - shift out next bit
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
end if;
end if;
else
-- Decrement the BCLK counter
bdivider <= bdivider - 1;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/syn-multicore/multicore_top.vhd | 1 | 19906 | -------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.msx_pack.all;
entity multicore_top is
generic (
hdmi_output_g : boolean := false
);
port (
-- Clocks
clock_50_i : in std_logic;
-- Buttons
btn_n_i : in std_logic_vector( 4 downto 1);
btn_oe_n_i : in std_logic;
btn_clr_n_i : in std_logic;
-- SRAM (AS7C34096)
sram_addr_o : out std_logic_vector(18 downto 0) := (others => '0');
sram_data_io : inout std_logic_vector( 7 downto 0) := (others => 'Z');
sram_we_n_o : out std_logic := '1';
sram_ce_n_o : out std_logic_vector( 1 downto 0) := (others => '1');
sram_oe_n_o : out std_logic := '1';
-- PS2
ps2_clk_io : inout std_logic := 'Z';
ps2_data_io : inout std_logic := 'Z';
ps2_mouse_clk_io : inout std_logic := 'Z';
ps2_mouse_data_io : inout std_logic := 'Z';
-- SD Card
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '0';
sd_mosi_o : out std_logic := '0';
sd_miso_i : in std_logic;
-- Joystick
joy1_up_i : in std_logic;
joy1_down_i : in std_logic;
joy1_left_i : in std_logic;
joy1_right_i : in std_logic;
joy1_p6_io : inout std_logic := 'Z';
joy1_p7_o : out std_logic := '1';
joy1_p9_io : inout std_logic := 'Z';
joy2_up_i : in std_logic;
joy2_down_i : in std_logic;
joy2_left_i : in std_logic;
joy2_right_i : in std_logic;
joy2_p6_io : inout std_logic;
joy2_p7_o : out std_logic := '1';
joy2_p9_io : inout std_logic;
-- Audio
dac_l_o : out std_logic := '0';
dac_r_o : out std_logic := '0';
ear_i : in std_logic;
mic_o : out std_logic := '0';
-- VGA
vga_r_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_g_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_b_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_hsync_n_o : out std_logic := '1';
vga_vsync_n_o : out std_logic := '1';
-- Debug
leds_n_o : out std_logic_vector( 7 downto 0) := (others => '0')
);
end entity;
architecture behavior of multicore_top is
-- Buttons
signal btn_por_n_s : std_logic;
signal btn_reset_n_s : std_logic;
signal btn_scan_s : std_logic;
-- Resets
signal pll_locked_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_por_s : std_logic;
signal soft_rst_cnt_s : unsigned(7 downto 0) := X"FF";
-- Clocks
signal clock_mem_s : std_logic;
signal clock_master_s : std_logic;
signal clock_vdp_s : std_logic;
signal clock_cpu_s : std_logic;
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic;
signal turbo_on_s : std_logic;
signal clock_vga_s : std_logic;
signal clock_dvi_s : std_logic;
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_do_s : std_logic_vector( 7 downto 0);
signal vram_di_s : std_logic_vector( 7 downto 0);
signal vram_ce_s : std_logic;
signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned( 7 downto 0);
signal beep_s : std_logic;
signal audio_l_s : unsigned(15 downto 0);
signal audio_r_s : unsigned(15 downto 0);
signal audio_l_amp_s : unsigned(15 downto 0);
signal audio_r_amp_s : unsigned(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_col_s : std_logic_vector( 3 downto 0);
-- signal rgb_hsync_n_s : std_logic;
-- signal rgb_vsync_n_s : std_logic;
signal cnt_hor_s : std_logic_vector( 8 downto 0);
signal cnt_ver_s : std_logic_vector( 7 downto 0);
signal vga_hsync_n_s : std_logic;
signal vga_vsync_n_s : std_logic;
signal vga_blank_s : std_logic;
signal vga_col_s : std_logic_vector( 3 downto 0);
signal vga_r_s : std_logic_vector( 3 downto 0);
signal vga_g_s : std_logic_vector( 3 downto 0);
signal vga_b_s : std_logic_vector( 3 downto 0);
signal scanlines_en_s : std_logic;
signal odd_line_s : std_logic;
signal sound_hdmi_l_s : std_logic_vector(15 downto 0);
signal sound_hdmi_r_s : std_logic_vector(15 downto 0);
signal tdms_r_s : std_logic_vector( 9 downto 0);
signal tdms_g_s : std_logic_vector( 9 downto 0);
signal tdms_b_s : std_logic_vector( 9 downto 0);
signal tdms_p_s : std_logic_vector( 3 downto 0);
signal tdms_n_s : std_logic_vector( 3 downto 0);
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- Joystick
signal joy1_out_s : std_logic;
signal joy2_out_s : std_logic;
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
begin
-- PLL1
pll: entity work.pll1
port map (
inclk0 => clock_50_i,
c0 => clock_master_s, -- 21.477
c1 => clock_mem_s, -- 42.954
locked => pll_locked_s
);
-- PLL2
pll2: entity work.pll2
port map (
inclk0 => clock_50_i,
c0 => clock_vga_s, -- 25.200
c1 => clock_dvi_s -- 126.000
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s,
por_i => not pll_locked_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 5,
hw_txt_g => "Multicore Board",
hw_version_g => actual_version,
video_opt_g => 3, -- No dblscan and external palette (Color in rgb_r_o)
ramsize_g => 512,
hw_hashwds_g => '0'
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => "00",
opt_vga_on_i => '0',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,--rom_addr_s,
rom_data_i => ram_data_from_s,
rom_ce_o => open,--rom_ce_s,
rom_oe_o => open,--rom_oe_s,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => '1',
bus_nmi_n_i => '1',
bus_int_n_i => '1',
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_do_s,
vram_data_o => vram_di_s,
vram_ce_o => vram_ce_s,
vram_oe_o => vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => mic_o,
k7_audio_i => ear_i,
-- Joystick
joy1_up_i => joy1_up_i,
joy1_down_i => joy1_down_i,
joy1_left_i => joy1_left_i,
joy1_right_i => joy1_right_i,
joy1_btn1_i => joy1_p6_io,
joy1_btn1_o => joy1_p6_io,
joy1_btn2_i => joy1_p9_io,
joy1_btn2_o => joy1_p9_io,
joy1_out_o => joy1_out_s,
joy2_up_i => joy2_up_i,
joy2_down_i => joy2_down_i,
joy2_left_i => joy2_left_i,
joy2_right_i => joy2_right_i,
joy2_btn1_i => joy2_p6_io,
joy2_btn1_o => joy2_p6_io,
joy2_btn2_i => joy2_p9_io,
joy2_btn2_o => joy2_p9_io,
joy2_out_o => joy2_out_s,
-- Video
cnt_hor_o => cnt_hor_s,
cnt_ver_o => cnt_ver_s,
rgb_r_o => rgb_col_s,
rgb_g_o => open,
rgb_b_o => open,
hsync_n_o => open,--rgb_hsync_n_s,
vsync_n_o => open,--rgb_vsync_n_s,
ntsc_pal_o => open,
vga_on_k_i => '0',
scanline_on_k_i=> '0',
vga_en_o => open,
-- SPI/SD
flspi_cs_n_o => open,
spi_cs_n_o => sd_cs_n_o,
spi_sclk_o => sd_sclk_o,
spi_mosi_o => sd_mosi_o,
spi_miso_i => sd_miso_i,
sd_pres_n_i => '0',
sd_wp_i => '0',
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
joy1_p7_o <= not joy1_out_s; -- for Sega Genesis joypad
joy2_p7_o <= not joy2_out_s; -- for Sega Genesis joypad
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_data_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- RAM and VRAM
sram0: entity work.dpSRAM_5128
port map (
clk_i => clock_mem_s,
-- Port 0
porta0_addr_i => "11101" & vram_addr_s,
porta0_ce_i => vram_ce_s,
porta0_oe_i => vram_oe_s,
porta0_we_i => vram_we_s,
porta0_data_i => vram_di_s,
porta0_data_o => vram_do_s,
-- Port 1
porta1_addr_i => ram_addr_s(18 downto 0),
porta1_ce_i => ram_ce_s,
porta1_oe_i => ram_oe_s,
porta1_we_i => ram_we_s,
porta1_data_i => ram_data_to_s,
porta1_data_o => ram_data_from_s,
-- SRAM in board
sram_addr_o => sram_addr_o,
sram_data_io => sram_data_io,
sram_ce_n_o => sram_ce_n_o(0),
sram_oe_n_o => sram_oe_n_o,
sram_we_n_o => sram_we_n_o
);
-- Audio
mixer: entity work.mixeru
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
beep_i => beep_s,
ear_i => ear_i,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => (others => '0'),
jt51_right_i => (others => '0'),
opll_mo_i => (others => '0'),
opll_ro_i => (others => '0'),
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
audio_l_amp_s <= audio_l_s(15) & audio_l_s(13 downto 0) & "0";
audio_r_amp_s <= audio_r_s(15) & audio_r_s(13 downto 0) & "0";
-- Left Channel
audiol : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_l_amp_s,
dac_o => dac_l_o
);
-- Right Channel
audior : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_r_amp_s,
dac_o => dac_r_o
);
-- Glue logic
-- Resets
btn_por_n_s <= btn_n_i(2) or btn_n_i(4);
btn_reset_n_s <= btn_n_i(3) or btn_n_i(4);
por_s <= '1' when pll_locked_s = '0' or soft_por_s = '1' or btn_por_n_s = '0' else '0';
reset_s <= '1' when soft_rst_cnt_s = X"01" or btn_reset_n_s = '0' else '0';
process(reset_s, clock_master_s)
begin
if reset_s = '1' then
soft_rst_cnt_s <= X"00";
elsif rising_edge(clock_master_s) then
if (soft_reset_k_s = '1' or soft_reset_s_s = '1' or por_s = '1') and soft_rst_cnt_s = X"00" then
soft_rst_cnt_s <= X"FF";
elsif soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
---------------------------------
-- scanlines
btnscl: entity work.debounce
generic map (
counter_size_g => 16
)
port map (
clk_i => clock_master_s,
button_i => btn_n_i(1) or btn_n_i(2),
result_o => btn_scan_s
);
process (por_s, btn_scan_s)
begin
if por_s = '1' then
scanlines_en_s <= '0';
elsif falling_edge(btn_scan_s) then
scanlines_en_s <= not scanlines_en_s;
end if;
end process;
-- VGA framebuffer
vga: entity work.vga
port map (
I_CLK => clock_master_s,
I_CLK_VGA => clock_vga_s,
I_COLOR => rgb_col_s,
I_HCNT => cnt_hor_s,
I_VCNT => cnt_ver_s,
O_HSYNC => vga_hsync_n_s,
O_VSYNC => vga_vsync_n_s,
O_COLOR => vga_col_s,
O_HCNT => open,
O_VCNT => open,
O_H => open,
O_BLANK => vga_blank_s
);
-- Scanlines
process(vga_hsync_n_s,vga_vsync_n_s)
begin
if vga_vsync_n_s = '0' then
odd_line_s <= '0';
elsif rising_edge(vga_hsync_n_s) then
odd_line_s <= not odd_line_s;
end if;
end process;
-- Index => RGB
process (clock_vga_s)
variable vga_col_v : integer range 0 to 15;
variable vga_rgb_v : std_logic_vector(15 downto 0);
variable vga_r_v : std_logic_vector( 3 downto 0);
variable vga_g_v : std_logic_vector( 3 downto 0);
variable vga_b_v : std_logic_vector( 3 downto 0);
type ram_t is array (natural range 0 to 15) of std_logic_vector(15 downto 0);
constant rgb_c : ram_t := (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
begin
if rising_edge(clock_vga_s) then
vga_col_v := to_integer(unsigned(vga_col_s));
vga_rgb_v := rgb_c(vga_col_v);
if scanlines_en_s = '1' then
--
if vga_rgb_v(15 downto 12) > 1 and odd_line_s = '1' then
vga_r_s <= vga_rgb_v(15 downto 12) - 2;
else
vga_r_s <= vga_rgb_v(15 downto 12);
end if;
--
if vga_rgb_v(11 downto 8) > 1 and odd_line_s = '1' then
vga_b_s <= vga_rgb_v(11 downto 8) - 2;
else
vga_b_s <= vga_rgb_v(11 downto 8);
end if;
--
if vga_rgb_v(3 downto 0) > 1 and odd_line_s = '1' then
vga_g_s <= vga_rgb_v(3 downto 0) - 2;
else
vga_g_s <= vga_rgb_v(3 downto 0);
end if;
else
vga_r_s <= vga_rgb_v(15 downto 12);
vga_b_s <= vga_rgb_v(11 downto 8);
vga_g_s <= vga_rgb_v( 3 downto 0);
end if;
end if;
end process;
uh: if hdmi_output_g generate
sound_hdmi_l_s <= '0' & std_logic_vector(audio_l_amp_s(15 downto 1));
sound_hdmi_r_s <= '0' & std_logic_vector(audio_r_amp_s(15 downto 1));
-- HDMI
hdmi: entity work.hdmi
generic map (
FREQ => 25200000, -- pixel clock frequency
FS => 48000, -- audio sample rate - should be 32000, 41000 or 48000 = 48KHz
CTS => 25200, -- CTS = Freq(pixclk) * N / (128 * Fs)
N => 6144 -- N = 128 * Fs /1000, 128 * Fs /1500 <= N <= 128 * Fs /300 (Check HDMI spec 7.2 for details)
)
port map (
I_CLK_PIXEL => clock_vga_s,
I_R => vga_r_s & vga_r_s,
I_G => vga_g_s & vga_g_s,
I_B => vga_b_s & vga_b_s,
I_BLANK => vga_blank_s,
I_HSYNC => vga_hsync_n_s,
I_VSYNC => vga_vsync_n_s,
-- PCM audio
I_AUDIO_ENABLE => '1',
I_AUDIO_PCM_L => sound_hdmi_l_s,
I_AUDIO_PCM_R => sound_hdmi_r_s,
-- TMDS parallel pixel synchronous outputs (serialize LSB first)
O_RED => tdms_r_s,
O_GREEN => tdms_g_s,
O_BLUE => tdms_b_s
);
hdmio: entity work.hdmi_out_altera
port map (
clock_pixel_i => clock_vga_s,
clock_tdms_i => clock_dvi_s,
red_i => tdms_r_s,
green_i => tdms_g_s,
blue_i => tdms_b_s,
tmds_out_p => tdms_p_s,
tmds_out_n => tdms_n_s
);
vga_hsync_n_o <= tdms_p_s(2); -- 2+ 10
vga_vsync_n_o <= tdms_n_s(2); -- 2- 11
vga_b_o(2) <= tdms_p_s(1); -- 1+ 144
vga_b_o(1) <= tdms_n_s(1); -- 1- 143
vga_r_o(0) <= tdms_p_s(0); -- 0+ 133
vga_g_o(2) <= tdms_n_s(0); -- 0- 132
vga_r_o(1) <= tdms_p_s(3); -- CLK+ 113
vga_r_o(2) <= tdms_n_s(3); -- CLK- 112
end generate;
nuh: if not hdmi_output_g generate
vga_r_o <= vga_r_s(3 downto 1);
vga_g_o <= vga_g_s(3 downto 1);
vga_b_o <= vga_b_s(3 downto 1);
vga_hsync_n_o <= vga_hsync_n_s;
vga_vsync_n_o <= vga_vsync_n_s;
end generate;
-- DEBUG
leds_n_o(0) <= not turbo_on_s;
-- leds_n_o(1) <= not caps_en_s;
-- leds_n_o(2) <= not soft_reset_k_s;
-- leds_n_o(3) <= not soft_por_s;
end architecture; | gpl-3.0 |
fbelavenuto/msx1fpga | src/video/vdp18/vdp18_palette.vhd | 2 | 3427 | -------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_palette.vhd,v 1.10 2016/11/09 10:47:01 fbelavenuto Exp $
--
-- Palette
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vdp18_palette is
port (
reset_i : in boolean;
clock_i : in std_logic;
we_i : in std_logic;
addr_wr_i : in std_logic_vector(0 to 3);
data_i : in std_logic_vector(0 to 15);
addr_rd_i : in std_logic_vector(0 to 3);
data_o : out std_logic_vector(0 to 15)
);
end entity;
architecture Memory of vdp18_palette is
type ram_t is array (natural range 15 downto 0) of std_logic_vector(15 downto 0);
signal ram_q : ram_t;
signal read_addr_q : unsigned(3 downto 0);
begin
process (reset_i, clock_i)
begin
if reset_i then
ram_q <= (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
elsif rising_edge(clock_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_wr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_rd_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end architecture; | gpl-3.0 |
freecores/usb_fpga_1_2 | examples/usb-fpga-1.11/1.11b/ucecho/fpga/ucecho.vhd | 42 | 580 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/arriagx_hssi_components.vhd | 1 | 66224 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAGX_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- arriagx_hssi_refclk_divider
--
COMPONENT arriagx_hssi_refclk_divider
GENERIC (
enable_divider : STRING := "true";
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
refclk_coupling_termination : STRING := "dc_coupling_external_termination"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
inclk : IN STD_LOGIC;
dprioin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
--
-- arriagx_hssi_cmu_clock_divider
--
COMPONENT arriagx_hssi_cmu_clock_divider
GENERIC (
inclk_select : integer := 0;
use_vco_bypass : string := "false";
use_digital_refclk_post_divider : string := "false";
use_coreclk_out_post_divider : string := "false";
divide_by : integer := 4;
enable_refclk_out : string := "true";
enable_pclk_x8_out : string := "false";
select_neighbor_pclk : string := "false";
coreclk_out_gated_by_quad_reset: string := "false";
select_refclk_dig : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
tipd_clk : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pclkin : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(29 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_refclkdig : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanshift : VitalDelayType01 := DefPropDelay01;
tipd_scanmode : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_coreclkout : VitalDelayType01 := DefPropDelay01;
tpd_clk_pclkx8out : VitalDelayType01 := DefPropDelay01;
tpd_pclkin_coreclkout : VitalDelayType01 := DefPropDelay01;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_digitalrefclkout_phase_shift : INTEGER := 0;
sim_pclkx8out_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
pclkin : IN STD_LOGIC := '0';
dprioin : IN STD_LOGIC_VECTOR(29 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN STD_LOGIC := '1';
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS => '0');
scanshift : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
vcobypassin : IN STD_LOGIC := '0';
analogrefclkout : OUT STD_LOGIC;
analogfastrefclkout : OUT STD_LOGIC;
digitalrefclkout : OUT STD_LOGIC;
pclkx8out : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0));
END COMPONENT;
--
-- arriagx_hssi_calibration_block
--
COMPONENT arriagx_hssi_calibration_block
GENERIC (
use_continuous_calibration_mode: string := "false";
rx_calibration_write_test_value: integer := 0;
tx_calibration_write_test_value: integer := 0;
enable_rx_calibration_test_write: string := "false";
enable_tx_calibration_test_write: string := "false";
send_rx_calibration_status : string := "true");
PORT (
clk : IN std_logic := '0';
powerdn : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;
--
-- arriagx_hssi_cmu_pll
--
COMPONENT arriagx_hssi_cmu_pll
GENERIC (
inclk0_period : INTEGER := 0; -- time period in ps
inclk1_period : INTEGER := 0;
inclk2_period : INTEGER := 0;
inclk3_period : INTEGER := 0;
inclk4_period : INTEGER := 0;
inclk5_period : INTEGER := 0;
inclk6_period : INTEGER := 0;
inclk7_period : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
multiply_by : INTEGER := 1;
divide_by : INTEGER := 1;
low_speed_test_sel : INTEGER := 0;
pll_type : STRING := "normal"; -- normal,fast,auto
charge_pump_current_test_enable : INTEGER := 0;
vco_range : STRING := "low";
loop_filter_resistor_control : INTEGER := 0;
loop_filter_ripple_capacitor_control : INTEGER := 0;
use_default_charge_pump_current_selection : STRING := "false";
use_default_charge_pump_supply_vccm_vod_control : STRING := "false";
pll_number : INTEGER := 0; -- PLL 0-2
charge_pump_current_control : INTEGER := 0;
up_down_control_percent : INTEGER := 0;
charge_pump_tristate_enable : STRING := "false";
enable_pll_cascade : STRING := "false"; -- 6.1
dprio_config_mode : INTEGER := 0; -- 6.1
protocol_hint : STRING := "basic"; -- 6.1
remapped_to_new_loop_filter_charge_pump_settings : STRING := "false";
tipd_clk : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_pllreset : VitalDelayType01 := DefPropDelay01;
tipd_pllpowerdn : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0
);
PORT (
clk : IN std_logic_vector(7 DOWNTO 0);
dprioin : IN std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN std_logic := '1';
pllreset : IN std_logic := '0';
pllpowerdn : IN std_logic := '0';
clkout : OUT std_logic;
locked : OUT std_logic;
dprioout : OUT std_logic_vector(39 DOWNTO 0);
fbclkout : OUT std_logic;
vcobypassout : OUT std_logic);
END COMPONENT;
--
-- arriagx_hssi_central_management_unit
--
COMPONENT arriagx_hssi_central_management_unit
GENERIC (
in_xaui_mode : string := "false";
portaddr : integer := 1; -- 1-based
devaddr : integer := 1; -- 1-based
bonded_quad_mode : string := "none";
use_deskew_fifo : string := "false";
num_con_errors_for_align_loss : integer := 2;
num_con_good_data_for_align_approach: integer := 3;
num_con_align_chars_for_align : integer := 4;
offset_all_errors_align : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
rx_dprio_width : INTEGER := 800; -- 6.1
tx_dprio_width : INTEGER := 400; -- 6.1
lpm_type : string := "arriagx_hssi_central_management_unit";
rx0_cru_clock0_physical_mapping: string := "refclk0";
rx0_cru_clock1_physical_mapping: string := "refclk1";
rx0_cru_clock2_physical_mapping: string := "iq0";
rx0_cru_clock3_physical_mapping: string := "iq1";
rx0_cru_clock4_physical_mapping: string := "iq2";
rx0_cru_clock5_physical_mapping: string := "iq3";
rx0_cru_clock6_physical_mapping: string := "iq4";
rx0_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx0_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx1_cru_clock0_physical_mapping: string := "refclk0";
rx1_cru_clock1_physical_mapping: string := "refclk1";
rx1_cru_clock2_physical_mapping: string := "iq0";
rx1_cru_clock3_physical_mapping: string := "iq1";
rx1_cru_clock4_physical_mapping: string := "iq2";
rx1_cru_clock5_physical_mapping: string := "iq3";
rx1_cru_clock6_physical_mapping: string := "iq4";
rx1_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx1_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx2_cru_clock0_physical_mapping: string := "refclk0";
rx2_cru_clock1_physical_mapping: string := "refclk1";
rx2_cru_clock2_physical_mapping: string := "iq0";
rx2_cru_clock3_physical_mapping: string := "iq1";
rx2_cru_clock4_physical_mapping: string := "iq2";
rx2_cru_clock5_physical_mapping: string := "iq3";
rx2_cru_clock6_physical_mapping: string := "iq4";
rx2_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx2_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx3_cru_clock0_physical_mapping: string := "refclk0";
rx3_cru_clock1_physical_mapping: string := "refclk1";
rx3_cru_clock2_physical_mapping: string := "iq0";
rx3_cru_clock3_physical_mapping: string := "iq1";
rx3_cru_clock4_physical_mapping: string := "iq2";
rx3_cru_clock5_physical_mapping: string := "iq3";
rx3_cru_clock6_physical_mapping: string := "iq4";
rx3_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx3_cru_clock8_physical_mapping: string := "cmu_div_clk";
tx0_pll_fast_clk0_physical_mapping: string := "pll0";
tx0_pll_fast_clk1_physical_mapping: string := "pll1";
tx1_pll_fast_clk0_physical_mapping: string := "pll0";
tx1_pll_fast_clk1_physical_mapping: string := "pll1";
tx2_pll_fast_clk0_physical_mapping: string := "pll0";
tx2_pll_fast_clk1_physical_mapping: string := "pll1";
tx3_pll_fast_clk0_physical_mapping: string := "pll0";
tx3_pll_fast_clk1_physical_mapping: string := "pll1";
pll0_inclk0_logical_to_physical_mapping: string := "iq0";
pll0_inclk1_logical_to_physical_mapping: string := "iq1";
pll0_inclk2_logical_to_physical_mapping: string := "iq2";
pll0_inclk3_logical_to_physical_mapping: string := "iq3";
pll0_inclk4_logical_to_physical_mapping: string := "iq4";
pll0_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll0_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll0_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll1_inclk0_logical_to_physical_mapping: string := "iq0";
pll1_inclk1_logical_to_physical_mapping: string := "iq1";
pll1_inclk2_logical_to_physical_mapping: string := "iq2";
pll1_inclk3_logical_to_physical_mapping: string := "iq3";
pll1_inclk4_logical_to_physical_mapping: string := "iq4";
pll1_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll1_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll1_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll2_inclk0_logical_to_physical_mapping: string := "iq0";
pll2_inclk1_logical_to_physical_mapping: string := "iq1";
pll2_inclk2_logical_to_physical_mapping: string := "iq2";
pll2_inclk3_logical_to_physical_mapping: string := "iq3";
pll2_inclk4_logical_to_physical_mapping: string := "iq4";
pll2_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll2_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll2_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
cmu_divider_inclk0_physical_mapping: string := "pll0";
cmu_divider_inclk1_physical_mapping: string := "pll1";
cmu_divider_inclk2_physical_mapping: string := "pll2";
rx0_logical_to_physical_mapping: integer := 0;
rx1_logical_to_physical_mapping: integer := 1;
rx2_logical_to_physical_mapping: integer := 2;
rx3_logical_to_physical_mapping: integer := 3;
tx0_logical_to_physical_mapping: integer := 0;
tx1_logical_to_physical_mapping: integer := 1;
tx2_logical_to_physical_mapping: integer := 2;
tx3_logical_to_physical_mapping: integer := 3;
pll0_logical_to_physical_mapping: integer := 0;
pll1_logical_to_physical_mapping: integer := 1;
pll2_logical_to_physical_mapping: integer := 2;
refclk_divider0_logical_to_physical_mapping: integer := 0;
refclk_divider1_logical_to_physical_mapping: integer := 1;
sim_dump_dprio_internal_reg_at_time: integer := 0;
sim_dump_filename: string := "sim_dprio_dump.txt";
analog_test_bus_enable: string := "false";
bypass_bandgap: string := "true";
central_test_bus_select: integer := 5;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_dpclk: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_dprioin: VitalDelayType01 := DefpropDelay01;
tipd_dprioload: VitalDelayType01 := DefpropDelay01;
tipd_fixedclk: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadenable: VitalDelayType01 := DefpropDelay01;
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_rxanalogreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk: VitalDelayType01 := DefpropDelay01;
tipd_rxdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxpowerdown: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_txclk: VitalDelayType01 := DefpropDelay01;
tipd_txdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
adet : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
cmudividerdprioin : IN std_logic_vector(29 DOWNTO 0) := (OTHERS => '0');
cmuplldprioin : IN std_logic_vector(119 DOWNTO 0) := (OTHERS => '0');
dpclk : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic := '0';
dprioload : IN std_logic := '0';
fixedclk : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
quadenable : IN std_logic := '1';
quadreset : IN std_logic := '0';
rdalign : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rdenablesync : IN std_logic := '1';
recovclk : IN std_logic := '0';
refclkdividerdprioin : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxclk : IN std_logic := '0';
rxctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdprioin : IN std_logic_vector(rx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpowerdown : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
syncstatus : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txclk : IN std_logic := '0';
txctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdprioin : IN std_logic_vector(tx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
alignstatus : OUT std_logic;
clkdivpowerdn : OUT std_logic;
cmudividerdprioout : OUT std_logic_vector(29 DOWNTO 0);
cmuplldprioout : OUT std_logic_vector(119 DOWNTO 0);
dpriodisableout : OUT std_logic;
dpriooe : OUT std_logic;
dprioout : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
pllresetout : OUT std_logic_vector(2 DOWNTO 0);
pllpowerdn : OUT std_logic_vector(2 DOWNTO 0);
quadresetout : OUT std_logic;
refclkdividerdprioout : OUT std_logic_vector(1 DOWNTO 0);
rxadcepowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxadceresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcruresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcrupowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdprioout : OUT std_logic_vector(rx_dprio_width - 1 DOWNTO 0);
rxibpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
txdetectrxpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdividerpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txobpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdprioout : OUT std_logic_vector(tx_dprio_width - 1 DOWNTO 0);
digitaltestout : OUT std_logic_vector(9 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_hssi_receiver
--
COMPONENT arriagx_hssi_receiver
GENERIC (
adaptive_equalization_mode : string := "none"; -- <continuous/stopped/none>;
align_loss_sync_error_num : integer := 4; -- <integer 0-7>;// wordalign
align_ordered_set_based : string := "false"; -- <true/false>;
align_pattern : string := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : integer := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only: string := "false"; -- <true/false>;
allow_align_polarity_inversion : string := "false"; -- <true/false>;
allow_pipe_polarity_inversion : string := "false"; -- <true/false>;
allow_serial_loopback : string := "false"; -- <true/false>;
bandwidth_mode : integer := 0; -- <integer 0-3>;
bit_slip_enable : string := "false"; -- <true/false>;
byte_order_pad_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_ordering_mode : string := "none"; -- <none/pattern-based/syncstatus-based>;
channel_number : integer := 0; -- <integer 0-3>;
channel_bonding : string := "none"; -- <none, x4, x8>;
channel_width : integer := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : string := "recvd_clk"; -- <recvd_clk, master_clk, local_refclk, digital_refclk>;
clk2_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk, core_clk>;
cru_clock_select : integer := 0; -- <CRUCLK<n> where n is 0 through 7 >
cru_divide_by : integer := 1; -- <1,2,4>;
cru_multiply_by : integer := 10; -- <1,2,4,5,8,10,16,20,25>;
cru_pre_divide_by : integer := 1; -- <1,2,4,8>;
cruclk0_period : integer := 10000; -- in ps
cruclk1_period : integer := 10000; -- in ps
cruclk2_period : integer := 10000; -- in ps
cruclk3_period : integer := 10000; -- in ps
cruclk4_period : integer := 10000; -- in ps
cruclk5_period : integer := 10000; -- in ps
cruclk6_period : integer := 10000; -- in ps
cruclk7_period : integer := 10000; -- in ps
datapath_protocol : string := "basic"; -- <basic/pipe/xaui>;
dec_8b_10b_compatibility_mode : string := "true"; -- <true/false>;
dec_8b_10b_mode : string := "none"; -- <normal/cascaded/none>;
deskew_pattern : string := "1100111100"; -- K28.3
disable_auto_idle_insertion : string := "false"; -- <true/false>;
disable_ph_low_latency_mode : string := "false"; -- <true/false>;
disable_running_disp_in_word_align: string := "false"; -- <true/false>;
disallow_kchar_after_pattern_ordered_set: string := "false"; -- <true/false>;
dprio_mode : string := "none"; -- <none/pma_electricals/full>;
enable_bit_reversal : string := "false"; -- <true/false>;
enable_byte_order_control_sig : string := "false"; -- <true/false>;
enable_dc_coupling : string := "false"; -- <true/false>;
enable_deep_align : string := "false"; -- <true/false>;
enable_deep_align_byte_swap : string := "false"; -- <true/false>;
enable_lock_to_data_sig : string := "false"; -- <true/false>;
enable_lock_to_refclk_sig : string := "true"; -- <true/false>;
enable_self_test_mode : string := "false"; -- <true/false>;
enable_true_complement_match_in_word_align: string := "true"; -- <true/false>;
eq_adapt_seq_control : integer := 0; -- <integer 0-3>;
eq_max_gradient_control : integer := 0; -- <integer 0-7>;
equalizer_ctrl_a : integer := 0; -- <integer 0-7>;
equalizer_ctrl_b : integer := 0; -- < integer 0-7>;
equalizer_ctrl_c : integer := 0; -- < integer 0-7>;
equalizer_ctrl_d : integer := 0; -- < integer 0-7>;
equalizer_ctrl_v : integer := 0; -- < integer 0-7>;
equalizer_dc_gain : integer := 0; -- <integer 0-3>;
force_freq_det_high : string := "false"; -- <true/false>;
force_freq_det_low : string := "false"; -- <true/false>;
force_signal_detect : string := "false"; -- <true/false>;
force_signal_detect_dig : string := "false"; -- <true/false>;
ignore_lock_detect : string := "false"; -- <true/false>;
infiniband_invalid_code : integer := 0; -- <integer 0-3>;
insert_pad_on_underflow : string := "false";
num_align_code_groups_in_ordered_set: integer := 1; -- <integer 0-3>;
num_align_cons_good_data : integer := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : integer := 4; -- <Integer 1-256>;
phystatus_reset_toggle : string := "false"; -- new in 6.0 - default false
ppmselect : integer := 20; -- <integer 0-63>;
prbs_all_one_detect : string := "false"; -- <true/false>;
rate_match_almost_empty_threshold: integer := 11; -- <integer 0-15>;
rate_match_almost_full_threshold: integer := 13; -- <integer 0-15>;
rate_match_back_to_back : string := "false"; -- <true/false>;
rate_match_fifo_mode : string := "none"; -- <normal/cascaded/generic/cascaded_generic/none>;
rate_match_ordered_set_based : string := "false";
rate_match_pattern_size : integer := 10; -- <integer 10 or 20>;
rate_match_pattern1 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_skip_set_based : string := "false"; -- <true/false>;
rd_clk_mux_select : string := "int_clk"; -- <int_clk, core_clk>;
recovered_clk_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk>;
reset_clock_output_during_digital_reset: string := "false"; -- <true/false>;
run_length : integer := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : string := "false"; -- <true/false>;
rx_detect_bypass : string := "false";
self_test_mode : string := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
send_direct_reverse_serial_loopback: string := "false"; -- <true/false>;
signal_detect_threshold : integer := 0; -- <integer 0-7 (actual values determined after PE char)>;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
use_align_state_machine : string := "false"; -- <true/false>;
use_deserializer_double_data_mode: string := "false"; -- <true/false>;
use_deskew_fifo : string := "false"; -- <true/false>;
use_double_data_mode : string := "false"; -- <true/false>;
use_parallel_loopback : string := "false"; -- <true/false>;
use_rate_match_pattern1_only : string := "false"; -- <true/false>;
use_rising_edge_triggered_pattern_align: string := "false"; -- <true/false>;
common_mode : string := "0.9V"; -- new in 5.1 SP1
loop_filter_resistor_control : integer := 0; -- new in 6.0;
loop_filter_ripple_capacitor_control : integer := 0; -- new in 6.0;
pd_mode_charge_pump_current_control : integer := 0; -- new in 6.0;
signal_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1
single_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1 - used in code
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
vco_range : string := "high"; -- new in 6.0
sim_offset_cycle_count : integer := 10; -- new in 7.1 for adce
protocol_hint : string := "basic"; -- new in 6.0
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 200; -- 6.1
allow_vco_bypass : string := "false"; -- <true/false>
charge_pump_current_control : integer := 0; -- <integer 0-3>;
up_dn_mismatch_control : integer := 0; -- <integer 0-3>;
charge_pump_test_enable : string := "false"; -- <true/false>;
charge_pump_current_test_control_pos: string := "false"; -- <true/false>
charge_pump_tristate_enable : string := "false"; -- <true/false>;
low_speed_test_select : integer := 0; -- <integer 0-15>;
cru_clk_sel_during_vco_bypass : string := "refclk1"; -- <refclk1/refclk2/ext1/ext2>
test_bus_sel : integer := 0 ; -- <integer 0-7>;
enable_phfifo_bypass : string := "false";
sim_rxpll_clkout_phase_shift : integer := 0;
sim_rxpll_clkout_latency : integer := 0;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_a1a2size: VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn: VitalDelayType01 := DefpropDelay01;
tipd_adcereset: VitalDelayType01 := DefpropDelay01;
tipd_alignstatus: VitalDelayType01 := DefpropDelay01;
tipd_alignstatussync: VitalDelayType01 := DefpropDelay01;
tipd_analogreset: VitalDelayType01 := DefpropDelay01;
tipd_bitslip: VitalDelayType01 := DefpropDelay01;
tipd_coreclk: VitalDelayType01 := DefpropDelay01;
tipd_cruclk: VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
tipd_crupowerdn: VitalDelayType01 := DefpropDelay01;
tipd_crureset: VitalDelayType01 := DefpropDelay01;
tipd_datain: VitalDelayType01 := DefpropDelay01;
tipd_digitalreset: VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin: VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew: VitalDelayType01 := DefpropDelay01;
tipd_enabyteord: VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign: VitalDelayType01 := DefpropDelay01;
tipd_fifordin: VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd: VitalDelayType01 := DefpropDelay01;
tipd_ibpowerdn: VitalDelayType01 := DefpropDelay01;
tipd_invpol: VitalDelayType01 := DefpropDelay01;
tipd_localrefclk: VitalDelayType01 := DefpropDelay01;
tipd_locktodata: VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk: VitalDelayType01 := DefpropDelay01;
tipd_masterclk: VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk: VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_phfifordenable: VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_phfifowrdisable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable: VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity: VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_pipepowerstate: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_refclk: VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa: VitalDelayType01 := DefpropDelay01;
tipd_revbyteorderwa: VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena: VitalDelayType01 := DefpropDelay01;
tipd_rmfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_rmfifowrena: VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid: VitalDelayType01 := DefpropDelay01;
tipd_rxfound: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialfdbk: VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken: VitalDelayType01 := DefpropDelay01;
tipd_termvoltage: VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tipd_testsel: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin: VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain: VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
a1a2size : IN std_logic := '0';
adcepowerdn : IN std_logic := '0';
adcereset : IN std_logic := '0';
alignstatus : IN std_logic := '0';
alignstatussync : IN std_logic := '0';
analogreset : IN std_logic := '0';
bitslip : IN std_logic := '0';
coreclk : IN std_logic := '0';
cruclk : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
crupowerdn : IN std_logic := '0';
crureset : IN std_logic := '0';
datain : IN std_logic := '0';
digitalreset : IN std_logic := '0';
disablefifordin : IN std_logic := '0';
disablefifowrin : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enabledeskew : IN std_logic := '0';
enabyteord : IN std_logic := '0';
enapatternalign : IN std_logic := '0';
fifordin : IN std_logic := '0';
fiforesetrd : IN std_logic := '0';
ibpowerdn : IN std_logic := '0';
invpol : IN std_logic := '0';
localrefclk : IN std_logic := '0';
locktodata : IN std_logic := '0';
locktorefclk : IN std_logic := '0';
masterclk : IN std_logic := '0';
parallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
phfifordenable : IN std_logic := '1';
phfiforeset : IN std_logic := '0';
phfifowrdisable : IN std_logic := '0';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrclk : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrclk : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipe8b10binvpolarity : IN std_logic := '0'; -- new in rev1.2
pipepowerdown : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); -- width from 1 -> 2 in rev1.2
pipepowerstate : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -- width change from 3 to 4 in rev1.3
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revbitorderwa : IN std_logic := '0';
revbyteorderwa : IN std_logic := '0';
rmfifordena : IN std_logic := '1';
rmfiforeset : IN std_logic := '0';
rmfifowrena : IN std_logic := '1';
rxdetectvalid : IN std_logic := '0';
rxfound : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
serialfdbk : IN std_logic := '0';
seriallpbken : IN std_logic := '0';
termvoltage : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
testsel : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
xgmctrlin : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
a1a2sizeout : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
a1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
a2detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
adetectdeskew : OUT std_logic;
alignstatussyncout : OUT std_logic;
analogtestbus : OUT std_logic_vector(7 DOWNTO 0);
bistdone : OUT std_logic;
bisterr : OUT std_logic;
byteorderalignstatus : OUT std_logic;
clkout : OUT std_logic;
cmudivclkout : OUT std_logic;
ctrldetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dataoutfull : OUT std_logic_vector(63 DOWNTO 0);
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
disperr : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
errdetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
fifordout : OUT std_logic;
freqlock : OUT std_logic;
k1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
k2detect : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
phaselockloss : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifooverflow : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifowrclkout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipebufferstat : OUT std_logic_vector(3 DOWNTO 0);
pipedatavalid : OUT std_logic;
pipeelecidle : OUT std_logic;
pipephydonestatus : OUT std_logic;
pipestatus : OUT std_logic_vector(2 DOWNTO 0);
pipestatetransdoneout : OUT std_logic;
rdalign : OUT std_logic;
recovclkout : OUT std_logic;
revparallelfdbkdata : OUT std_logic_vector(19 DOWNTO 0);
revserialfdbkout : OUT std_logic;
rlv : OUT std_logic;
rmfifoalmostempty : OUT std_logic;
rmfifoalmostfull : OUT std_logic;
rmfifodatadeleted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifodatainserted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifoempty : OUT std_logic;
rmfifofull : OUT std_logic;
runningdisp : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
signaldetect : OUT std_logic;
syncstatus : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
syncstatusdeskew : OUT std_logic;
xgmctrldet : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
xgmdatavalid : OUT std_logic;
xgmrunningdisp : OUT std_logic);
END COMPONENT;
--
-- arriagx_hssi_transmitter
--
COMPONENT arriagx_hssi_transmitter
GENERIC (
allow_polarity_inversion : string := "false";
channel_bonding : string := "none"; -- none, x8, x4
channel_number : integer := 0;
channel_width : integer := 8;
disable_ph_low_latency_mode : string := "false";
disparity_mode : string := "none"; -- legacy, new, none
divider_refclk_select_pll_fast_clk0: string := "true";
dprio_mode : string := "none";
elec_idle_delay : integer := 5; -- new in 6.0
enable_bit_reversal : string := "false";
enable_idle_selection : string := "false";
enable_symbol_swap : string := "false";
enable_reverse_parallel_loopback: string := "false";
enable_reverse_serial_loopback : string := "false";
enable_self_test_mode : string := "false";
enc_8b_10b_compatibility_mode : string := "true";
enc_8b_10b_mode : string := "none"; -- cascade, normal, none
force_echar : string := "false";
force_kchar : string := "false";
low_speed_test_select : integer := 0;
prbs_all_one_detect : string := "false";
protocol_hint : string := "basic"; -- new in 6.0
refclk_divide_by : integer := 1;
refclk_select : string := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset: string := "false";
rxdetect_ctrl : integer := 0;
self_test_mode : string := "incremental";
serializer_clk_select : string := "local"; -- analogx4refclk, anlogx8refclk
transmit_protocol : string := "basic"; -- xaui-pipe-gige-basic?
use_double_data_mode : string := "false";
use_serializer_double_data_mode: string := "false";
wr_clk_mux_select : string := "CORE_CLK"; -- INT_CLK -- int_clk
vod_selection : integer := 0;
enable_slew_rate : string := "false";
preemp_tap_1 : integer := 0;
preemp_tap_2 : integer := 0;
preemp_pretap : integer := 0;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
preemp_tap_2_inv : string := "false"; -- New in rev 2.1
preemp_pretap_inv : string := "false"; -- New in rev 2.1
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
common_mode : string := "0.6V"; -- new in 5.1 SP1
analog_power : string := "1.5V"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 100; -- 6.1
allow_vco_bypass : string := "false";
enable_phfifo_bypass : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_coreclk : VitalDelayType01 := DefPropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull : VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefPropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefPropDelay01;
tipd_analogx8fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefPropDelay01;
tipd_analogx8refclk : VitalDelayType01 := DefPropDelay01;
tipd_pma_width : VitalDelayType01 := DefPropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefPropDelay01;
tipd_pma_doublewidth : VitalDelayType01 := DefPropDelay01;
tipd_revparallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdclk : VitalDelayType01 := DefPropDelay01;
tipd_obpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_termvoltage : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forceelecidle : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefPropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dispval : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_analogx4fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_refclk : VitalDelayType01 := DefPropDelay01;
tipd_analogreset : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdenable : VitalDelayType01 := DefPropDelay01;
tipd_invpol : VitalDelayType01 := DefPropDelay01;
tipd_enrevparallellpbk : VitalDelayType01 := DefPropDelay01;
tipd_digitalreset : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8bytesel : VitalDelayType01 := DefPropDelay01;
tipd_dividerpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_analogx4refclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefPropDelay01;
tipd_revserialfdbk : VitalDelayType01 := DefPropDelay01;
tipd_clkin0 : VitalDelayType01 := DefPropDelay01;
tipd_clkin1 : VitalDelayType01 := DefPropDelay01;
tipd_reset : VitalDelayType01 := DefPropDelay01;
tipd_detectrxloop : VitalDelayType01 := DefPropDelay01;
tipd_pllfastclk : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdclk : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefPropDelay01;
tipd_detectrxpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_phfiforddisable : VitalDelayType01 := DefPropDelay01;
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
analogreset : IN std_logic := '0';
analogx4fastrefclk : IN std_logic := '0';
analogx4refclk : IN std_logic := '0';
analogx8fastrefclk : IN std_logic := '0';
analogx8refclk : IN std_logic := '0';
coreclk : IN std_logic := '0';
ctrlenable : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
datainfull : IN std_logic_vector(43 DOWNTO 0) := (OTHERS => '0');
detectrxloop : IN std_logic := '0';
detectrxpowerdn : IN std_logic := '0';
digitalreset : IN std_logic := '0';
dispval : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
dividerpowerdn : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enrevparallellpbk : IN std_logic := '0';
forcedispcompliance : IN std_logic := '0';
forcedisp : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN std_logic := '0';
invpol : IN std_logic := '0';
obpowerdn : IN std_logic := '0';
phfiforddisable : IN std_logic := '0';
phfiforeset : IN std_logic := '0';
phfifowrenable : IN std_logic := '1';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdclk : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdclk : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipestatetransdone : IN std_logic := '0';
pllfastclk : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revserialfdbk : IN std_logic := '0';
revparallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
termvoltage : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
vcobypassin : IN std_logic := '0'; -- PE-POF only
xgmctrl : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
clkout : OUT std_logic;
dataout : OUT std_logic;
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
parallelfdbkout : OUT std_logic_vector(19 DOWNTO 0);
phfifooverflow : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifordclkout : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipepowerdownout : OUT std_logic_vector(1 DOWNTO 0);
pipepowerstateout : OUT std_logic_vector(3 DOWNTO 0);
rdenablesync : OUT std_logic;
refclkout : OUT std_logic;
rxdetectvalidout : OUT std_logic;
rxfoundout : OUT std_logic_vector(1 DOWNTO 0);
serialfdbkout : OUT std_logic;
xgmctrlenable : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
end arriagx_hssi_components;
package body ARRIAGX_HSSI_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end ARRIAGX_HSSI_COMPONENTS;
| gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_alt_mem_phy_seq.vhd | 1 | 647873 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr3_int_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr3_int_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr3_int_phy_alt_mem_phy_record_pkg;
--
package body ddr3_int_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr3_int_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr3_int_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
package ddr3_int_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
package body ddr3_int_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr3_int_phy_alt_mem_phy_iram_ram;
--
entity ddr3_int_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr3_int_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr3_int_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr3_int_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr3_int_phy_alt_mem_phy_admin;
--
use work.ddr3_int_phy_alt_mem_phy_mmi;
--
use work.ddr3_int_phy_alt_mem_phy_iram;
--
use work.ddr3_int_phy_alt_mem_phy_dgrb;
--
use work.ddr3_int_phy_alt_mem_phy_dgwb;
--
use work.ddr3_int_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr3_int_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr3_int_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr3_int_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr3_int_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr3_int_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr3_int_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr3_int_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design_wrapper.vhd | 1 | 3914 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Wed Aug 26 21:30:37 2015
--Host : localhost.localdomain running 64-bit CentOS release 6.7 (Final)
--Command : generate_target base_zynq_design_wrapper.bd
--Design : base_zynq_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end base_zynq_design_wrapper;
architecture STRUCTURE of base_zynq_design_wrapper is
component base_zynq_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component base_zynq_design;
begin
base_zynq_design_i: component base_zynq_design
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
btns_5bits_tri_i(4 downto 0) => btns_5bits_tri_i(4 downto 0),
leds_8bits_tri_o(7 downto 0) => leds_8bits_tri_o(7 downto 0)
);
end STRUCTURE;
| gpl-3.0 |
freecores/usb_fpga_1_2 | examples/usb-fpga-1.15/1.15a/memtest/fpga/memtest.vhd | 5 | 24307 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
PC0 : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- mcb3_dram_odt : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
--attribute optimize : string;
--attribute optimize of counters:entity is "off";
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 3,
-- CLKFX_MULTIPLY => 33,
CLKFX_MULTIPLY => 21,
CLKFXDV_DIVIDE => 8,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
-- mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n=> mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- DCM0_CLK_VALID <= ( DCM0_LOCKED and ( not status_internal(2) ) );
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,19);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(26 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PC0 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,19);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(26 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
DreamIP/GPStudio | support/io/vga_out/hdl/PLL108.vhd | 1 | 17486 | -- megafunction wizard: %Altera PLL v15.1%
-- GENERATION: XML
-- PLL108.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PLL108 is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic -- outclk0.clk
);
end entity PLL108;
architecture rtl of PLL108 is
component PLL108_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component PLL108_0002;
begin
pll108_inst : component PLL108_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => open -- (terminated)
);
end architecture rtl; -- of PLL108
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2017 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="15.1" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="5CEBA2F17A7" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="false" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="108.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : PLL108.vho
-- RELATED_FILES: PLL108.vhd, PLL108_0002.v
| gpl-3.0 |
hoglet67/ElectronFpga | src/xilinx/DCM/dcm3.vhd | 1 | 2015 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm3 is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end dcm3;
architecture BEHAVIORAL of dcm3 is
signal CLK0_BUF : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 32.00 = 16 * 20 / 10
CLKFX_MULTIPLY => 20,
CLKFX_DIVIDE => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 62.50,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0_BUF,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/interface_management/rgmii2gmii_fifo.vhd | 1 | 3157 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: rgmi2gmii_fifo.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rgmii2gmii_fifo IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC
);
END rgmii2gmii_fifo;
ARCHITECTURE SYN OF rgmii2gmii_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
rdempty <= sub_wire1;
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 4,
lpm_widthu => 5,
lpm_widthu_r => 4,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0,
rdempty => sub_wire1
);
END SYN;
| gpl-3.0 |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/untokenize_flow.vhd | 1 | 2613 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.caph_flow_pkg.all;
entity untokenize_flow is
generic(
IMAGE_WIDTH:integer := 320;
IMAGE_HEIGHT:integer := 240;
TOKEN_SIZE: integer := 10;
SIZE:integer:=8
);
port (
clk_caph: in std_logic;
clk_proc: in std_logic;
rst_n_i : in std_logic;
fifo_empty: in std_logic;
data_i : in std_logic_vector(TOKEN_SIZE-1 downto 0);
imwidth_i : in std_LOGIC_VECTOR(31 downto 0);
imheight_i : in std_LOGIC_VECTOR(31 downto 0);
fifo_unpile: out std_logic;
frame_valid_o :out std_logic;
data_valid_o :out std_logic;
data_o : out std_logic_vector (SIZE-1 downto 0)
);
end entity untokenize_flow;
architecture rtl of untokenize_flow is
signal frame_valid_s : std_logic;
signal data_valid_s : std_logic;
signal data_s : std_logic_vector (SIZE-1 downto 0);
signal frame_valid_sr : std_logic;
signal data_valid_sr : std_logic;
signal data_sr : std_logic_vector (SIZE-1 downto 0);
signal linecpt : integer range 0 to MAX_IMAGE_HEIGHT := 0;
begin
process(clk_caph,rst_n_i)
variable datacpt : integer range 0 to MAX_IMAGE_WIDTH := 0;
begin
if (rst_n_i = '0') then
frame_valid_s<='0';
data_valid_s<='0';
data_s <= (others=>'0');
datacpt := 0;
linecpt <= 0;
elsif rising_edge(clk_caph) then
data_valid_s <= '0';
if (data_i(TOKEN_SIZE-1 downto TOKEN_SIZE-2) = CaphHeader(Data)) then
data_s <= data_i(7 downto 0);
data_valid_s <= '1';
frame_valid_s <= '1';
datacpt := datacpt + 1;
if(datacpt = to_integer(unsigned(imwidth_i))) then
datacpt := 0;
linecpt <= linecpt+1;
end if;
end if;
if(linecpt= to_integer(unsigned(imheight_i))) then
frame_valid_s <= '0';
data_valid_s <= '0';
datacpt := 0;
linecpt <= 0;
end if;
end if;
end process;
fifo_unpile <= not(fifo_empty);
data_valid_o <= data_valid_s;
frame_valid_o <= frame_valid_s;
data_o <= data_s;
--SyncCLKPROC: process(clk_caph,rst_n_i)
--begin
-- if (rst_n_i = '0') then
-- data_sr <= (others=>'0');
-- data_valid_sr <= '0';
-- frame_valid_sr <= '0';
-- data_o <= (others=>'0');
-- data_valid_o <= '0';
-- frame_valid_o <= '0';
-- elsif rising_edge(clk_caph) then
--
-- data_sr <= data_s;
-- data_o <= data_sr;
--
-- data_valid_sr <= data_valid_s;
-- data_valid_o <= data_valid_sr;
--
-- frame_valid_sr <= frame_valid_s;
-- frame_valid_o <= frame_valid_sr;
--
-- end if;
--end process;
end architecture; | gpl-3.0 |
DreamIP/GPStudio | support/process/fast/hdl/fast_slave.vhd | 1 | 895 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fast_slave is
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic
);
end fast_slave;
architecture rtl of fast_slave is
constant ENABLE_REG_ADDR : natural := 0;
signal enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2)) => enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
end rtl;
| gpl-3.0 |
DreamIP/GPStudio | support/process/harris/hdl/sup_block.vhd | 1 | 539 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package.all;
entity sup_block is
generic (
COMP_WIDTH : integer;
);
port (
oper_a : in std_logic_vector((COMP_WIDTH -1) downto 0);;
oper_b : in std_logic_vector((COMP_WIDTH -1) downto 0);;
result : out std_logic_vector((COMP_WIDTH -1) downto 0);
);
end sup_block;
architecture rtl of sup_block is
begin
end architecture
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd | 4 | 4327 | --**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;
| gpl-3.0 |
DreamIP/GPStudio | support/process/sconv/hdl/pipline_gen.vhd | 1 | 1477 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library ieee;
use ieee.std_logic_1164.all;
entity pipline_gen is
generic (
PIPLINE_LENGHT : integer;
WORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
e : in std_logic;
in_data : in std_logic_vector (WORD_SIZE-1 downto 0);
i0,i1,i2 : out std_logic_vector (WORD_SIZE-1 downto 0);
out_data : out std_logic_vector (WORD_SIZE-1 downto 0)
);
end pipline_gen;
architecture bhv of pipline_gen is
type cell_t is array (0 to (PIPLINE_LENGHT-1)) of std_logic_vector ( (WORD_SIZE-1) downto 0);
signal cell : cell_t;
begin
process(clk_proc)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
elsif (rising_edge(clk_proc)) then
if (e='1') then
cell(0) <= in_data;
for i in 1 to (PIPLINE_LENGHT-1) loop
cell(i) <= cell(i-1);
end loop;
out_data<= cell(PIPLINE_LENGHT - 1);
i0 <= cell(0);
i1 <= cell(1);
i2 <= cell(2);
end if;
end if;
end process;
end bhv;
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/Core/io_reg_file.vhd | 4 | 4134 | --************************************************************************************************
-- Internal I/O registers (implemented inside the core) decoder/multiplexer
-- for AVR core
-- Version 1.3 (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 22.04.2004
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity io_reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
adr : in std_logic_vector(15 downto 0);
iowe : in std_logic;
dbusout : in std_logic_vector(7 downto 0);
sreg_fl_in : in std_logic_vector(7 downto 0);
sreg_out : out std_logic_vector(7 downto 0);
sreg_fl_wr_en : in std_logic_vector (7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : out std_logic_vector(7 downto 0);
sph_out : out std_logic_vector(7 downto 0);
sp_ndown_up : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : out std_logic_vector(7 downto 0));
end io_reg_file;
architecture rtl of io_reg_file is
signal sreg : std_logic_vector(7 downto 0);
signal sph : std_logic_vector(7 downto 0);
signal spl : std_logic_vector(7 downto 0);
signal rampz : std_logic_vector(7 downto 0);
signal sp_int : std_logic_vector(15 downto 0);
signal sp_intp : std_logic_vector(15 downto 0);
signal sp_intm : std_logic_vector(15 downto 0);
signal sp_res : std_logic_vector(15 downto 0);
begin
sreg_write:process(cp2,ireset)
begin
if ireset='0' then
sreg <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in sreg'range loop
if (sreg_fl_wr_en(i)='1' or (adr=SREG_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
sreg(i) <= dbusout(i); -- FROM THE INTERNAL DATA BUS
else
sreg(i) <= sreg_fl_in(i); -- FROM ALU FLAGS
end if;
end if;
end loop;
end if;
end if;
end process;
sreg_out <= sreg;
sp_intp<=(sph&spl)+1;
sp_intm<=(sph&spl)-1;
sp_res<= sp_intm when sp_ndown_up='0' else sp_intp;
spl_write:process(cp2,ireset)
begin
if ireset='0' then
spl <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (sp_en='1' or (adr=SPL_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
spl <= dbusout; -- FROM THE INTERNAL DATA BUS
else
spl <= sp_res(7 downto 0); -- FROM SPL BUS
end if;
end if;
end if;
end process;
spl_out <= spl;
sph_write:process(cp2,ireset)
begin
if ireset='0' then
sph <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (sp_en='1' or (adr=SPH_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
sph <= dbusout; -- FROM THE INTERNAL DATA BUS
else
sph <= sp_res(15 downto 8); -- FROM SPH BUS
end if;
end if;
end if;
end process;
sph_out <= sph;
rampz_write:process(cp2,ireset)
begin
if ireset='0' then
rampz <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (adr=RAMPZ_Address and iowe='1') then -- CLOCK ENABLE
rampz <= dbusout; -- FROM THE INTERNAL DATA BUS
end if;
end if;
end process;
rampz_out <= rampz;
end rtl;
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/CommonPacks/spi_mod_comp_pack.vhd | 8 | 1536 | --**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_mod_comp_pack is
component spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end component;
end spi_mod_comp_pack;
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd | 4 | 1099 | --**********************************************************************************************
--
-- Version 0.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_slv_sel_comp_pack is
component spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end component;
end spi_slv_sel_comp_pack;
| gpl-3.0 |
DreamIP/GPStudio | support/process/dilate/hdl/dilate_slave.vhd | 1 | 9714 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
di00_reg_m00 : out std_logic_vector(7 downto 0);
di01_reg_m01 : out std_logic_vector(7 downto 0);
di02_reg_m02 : out std_logic_vector(7 downto 0);
di10_reg_m10 : out std_logic_vector(7 downto 0);
di11_reg_m11 : out std_logic_vector(7 downto 0);
di12_reg_m12 : out std_logic_vector(7 downto 0);
di20_reg_m20 : out std_logic_vector(7 downto 0);
di21_reg_m21 : out std_logic_vector(7 downto 0);
di22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dilate_slave;
architecture rtl of dilate_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant DI00_REG_REG_ADDR : natural := 3;
constant DI01_REG_REG_ADDR : natural := 4;
constant DI02_REG_REG_ADDR : natural := 5;
constant DI10_REG_REG_ADDR : natural := 6;
constant DI11_REG_REG_ADDR : natural := 7;
constant DI12_REG_REG_ADDR : natural := 8;
constant DI20_REG_REG_ADDR : natural := 9;
constant DI21_REG_REG_ADDR : natural := 10;
constant DI22_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_value_reg : std_logic_vector (15 downto 0);
signal di00_reg_m00_reg : std_logic_vector (7 downto 0);
signal di01_reg_m01_reg : std_logic_vector (7 downto 0);
signal di02_reg_m02_reg : std_logic_vector (7 downto 0);
signal di10_reg_m10_reg : std_logic_vector (7 downto 0);
signal di11_reg_m11_reg : std_logic_vector (7 downto 0);
signal di12_reg_m12_reg : std_logic_vector (7 downto 0);
signal di20_reg_m20_reg : std_logic_vector (7 downto 0);
signal di21_reg_m21_reg : std_logic_vector (7 downto 0);
signal di22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_value_reg <= "0000000000000000";
di00_reg_m00_reg <= "00000000";
di01_reg_m01_reg <= "00000000";
di02_reg_m02_reg <= "00000000";
di10_reg_m10_reg <= "00000000";
di11_reg_m11_reg <= "00000000";
di12_reg_m12_reg <= "00000000";
di20_reg_m20_reg <= "00000000";
di21_reg_m21_reg <= "00000000";
di22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_value_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
di00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
di01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
di02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
di10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
di11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
di12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
di20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
di21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
di22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_value_reg(15) & widthimg_reg_value_reg(14) & widthimg_reg_value_reg(13) & widthimg_reg_value_reg(12) & widthimg_reg_value_reg(11) & widthimg_reg_value_reg(10) & widthimg_reg_value_reg(9) & widthimg_reg_value_reg(8) & widthimg_reg_value_reg(7) & widthimg_reg_value_reg(6) & widthimg_reg_value_reg(5) & widthimg_reg_value_reg(4) & widthimg_reg_value_reg(3) & widthimg_reg_value_reg(2) & widthimg_reg_value_reg(1) & widthimg_reg_value_reg(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di00_reg_m00_reg(7) & di00_reg_m00_reg(6) & di00_reg_m00_reg(5) & di00_reg_m00_reg(4) & di00_reg_m00_reg(3) & di00_reg_m00_reg(2) & di00_reg_m00_reg(1) & di00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di01_reg_m01_reg(7) & di01_reg_m01_reg(6) & di01_reg_m01_reg(5) & di01_reg_m01_reg(4) & di01_reg_m01_reg(3) & di01_reg_m01_reg(2) & di01_reg_m01_reg(1) & di01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di02_reg_m02_reg(7) & di02_reg_m02_reg(6) & di02_reg_m02_reg(5) & di02_reg_m02_reg(4) & di02_reg_m02_reg(3) & di02_reg_m02_reg(2) & di02_reg_m02_reg(1) & di02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di10_reg_m10_reg(7) & di10_reg_m10_reg(6) & di10_reg_m10_reg(5) & di10_reg_m10_reg(4) & di10_reg_m10_reg(3) & di10_reg_m10_reg(2) & di10_reg_m10_reg(1) & di10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di11_reg_m11_reg(7) & di11_reg_m11_reg(6) & di11_reg_m11_reg(5) & di11_reg_m11_reg(4) & di11_reg_m11_reg(3) & di11_reg_m11_reg(2) & di11_reg_m11_reg(1) & di11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di12_reg_m12_reg(7) & di12_reg_m12_reg(6) & di12_reg_m12_reg(5) & di12_reg_m12_reg(4) & di12_reg_m12_reg(3) & di12_reg_m12_reg(2) & di12_reg_m12_reg(1) & di12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di20_reg_m20_reg(7) & di20_reg_m20_reg(6) & di20_reg_m20_reg(5) & di20_reg_m20_reg(4) & di20_reg_m20_reg(3) & di20_reg_m20_reg(2) & di20_reg_m20_reg(1) & di20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di21_reg_m21_reg(7) & di21_reg_m21_reg(6) & di21_reg_m21_reg(5) & di21_reg_m21_reg(4) & di21_reg_m21_reg(3) & di21_reg_m21_reg(2) & di21_reg_m21_reg(1) & di21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di22_reg_m22_reg(7) & di22_reg_m22_reg(6) & di22_reg_m22_reg(5) & di22_reg_m22_reg(4) & di22_reg_m22_reg(3) & di22_reg_m22_reg(2) & di22_reg_m22_reg(1) & di22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_value <= widthimg_reg_value_reg;
di00_reg_m00 <= di00_reg_m00_reg;
di01_reg_m01 <= di01_reg_m01_reg;
di02_reg_m02 <= di02_reg_m02_reg;
di10_reg_m10 <= di10_reg_m10_reg;
di11_reg_m11 <= di11_reg_m11_reg;
di12_reg_m12 <= di12_reg_m12_reg;
di20_reg_m20 <= di20_reg_m20_reg;
di21_reg_m21 <= di21_reg_m21_reg;
di22_reg_m22 <= di22_reg_m22_reg;
end rtl;
| gpl-3.0 |
hoglet67/ElectronFpga | AtomBusMon/src/Z80CpuMonLX9.vhd | 2 | 5719 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonLX9.vhd
-- /___/ /\ Timestamp : 14/10/2018
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMonLX9
--Device: XC6SLX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Mode jumper, tie low to generate NOPs when paused
mode : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic
);
end Z80CpuMonLX9;
architecture behavioral of Z80CpuMonLX9 is
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal tristate_n : std_logic;
signal tristate_ad_n: std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
-- Tristateable output drivers
MREQ_n <= 'Z' when tristate_n = '0' else MREQ_n_int;
IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
wrapper : entity work.Z80CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map(
clock => clock,
-- Z80 Signals
RESET_n => RESET_n,
CLK_n => CLK_n,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n,
Addr => Addr_int,
Data => Data,
-- Buffer Control Signals
tristate_n => tristate_n,
tristate_ad_n => tristate_ad_n,
DIRD => open,
-- Mode jumper, tie low to generate NOPs when paused
mode => mode,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2,
test3 => test3,
test4 => test4
);
end behavioral;
| gpl-3.0 |
DreamIP/GPStudio | support/process/sconv/hdl/pipliner_3x3.vhd | 1 | 4189 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pipliner_3x3 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_fv : out std_logic;
out_dv : out std_logic;
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0)
);
end pipliner_3x3;
architecture structural of pipliner_3x3 is
signal line0_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p00_s, p01_s, p02_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p10_s, p11_s, p12_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p20_s, p21_s, p22_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal all_valid,fvs,dvs : std_logic;
signal enable_reg : std_logic;
signal reset_st,reset_s : std_logic;
component pipline_gen
generic (
PIPLINE_LENGHT : integer;
WORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
e : in std_logic;
in_data : in std_logic_vector (WORD_SIZE-1 downto 0);
i0,i1,i2 : out std_logic_vector (WORD_SIZE-1 downto 0);
out_data : out std_logic_vector (WORD_SIZE-1 downto 0)
);
end component;
begin
enable_proc : process(enable_i,in_fv)
begin
if (enable_i = '0') then
reset_st <= '0';
elsif(rising_edge(in_fv)) then
reset_st <= '1';
end if;
end process;
all_valid <= in_dv and in_fv;
reset_s <= reset_st and reset_n;
data_pipline0 : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => in_data,
i0 => p22,
i1 => p21,
i2 => p20,
out_data => line0_pix_out
);
data_pipline1 : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => line0_pix_out,
i0 => p12,
i1 => p11,
i2 => p10,
out_data => line1_pix_out
);
data_pipline2 : pipline_gen
generic map (
PIPLINE_LENGHT => 3,
WORD_SIZE => PIX_WIDTH
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data => line1_pix_out,
i0 => p02,
i1 => p01,
i2 => p00
);
fv_pipline : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX + 4 ,
WORD_SIZE => 1
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data(0) => in_fv,
out_data(0) => fvs
);
dv_pipline : pipline_gen
generic map (
PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX +4 ,
WORD_SIZE => 1
)
port map (
clk_proc => clk_proc,
reset_n => reset_s,
e => all_valid,
in_data(0) => in_dv,
out_data(0) => dvs
);
out_dv <= dvs and in_dv;
out_fv <= fvs and in_fv;
end structural;
| gpl-3.0 |
hoglet67/ElectronFpga | src/altera/WatchEvents.vhd | 1 | 5498 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY WatchEvents IS
PORT
(
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE SYN OF watchevents IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
dout <= sub_wire2(71 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone II",
lpm_numwords => 256,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 72,
lpm_widthu => 8,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clk,
data => din,
rdreq => rd_en,
sclr => srst,
wrreq => wr_en,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "72"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "72"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
dskntIndustry/Hardware | platform_specific/mimas/hdl/MimasTop.vhd | 1 | 1115 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.all;
entity MimasTop is
port
(
clock : in std_logic;
status_led : out std_logic;
top_clock_output : out std_logic
);
end entity; --MimasTop
architecture arch of MimasTop is
constant G_CLOCK_FREQUENCY : integer := 512;
constant G_BASE_FREQUENCY : integer := 12E6;
constant G_CLOCK_DIVIDER : integer := 10;
signal enable : std_logic := '1';
signal clock_output : std_logic := '0';
signal clock_output_n : std_logic := '0';
begin
status_led <= '1';
clock_generator : entity hdl_library_ClockGenerator.ClockGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_CLOCK_DIVIDER => G_CLOCK_DIVIDER
)
port map
(
clock => clock,
enable => enable,
-- module clock output
clock_output => clock_output,
clock_output_n => clock_output_n
);
top_clock_output <= clock_output;
end architecture; -- arch
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_dc_as.vhd | 6 | 10777 | `protect begin_protected
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| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/tope_rof512_uart.vhd | 1 | 8195 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tope_rof512_uart is --Entidad
Port ( tx_female : out std_logic; --Entidad
LED : out std_logic_vector(7 downto 0);
rx_female : in std_logic; --Entidad
RSTn : in std_logic; --Entidad
clk : in std_logic); --Entidad
end tope_rof512_uart; --Entidad
architecture Comportamiento of tope_rof512_uart is
component uart_tx_plus --comp uart_tx_plus
Port ( data_in : in std_logic_vector(7 downto 0);--comp uart_tx_plus
write_buffer : in std_logic; --comp uart_tx_plus
reset_buffer : in std_logic; --comp uart_tx_plus
en_16_x_baud : in std_logic; --comp uart_tx_plus
serial_out : out std_logic; --comp uart_tx_plus
buffer_data_present : out std_logic; --comp uart_tx_plus
buffer_full : out std_logic; --comp uart_tx_plus
buffer_half_full : out std_logic; --comp uart_tx_plus
clk : in std_logic); --comp uart_tx_plus
end component;
component uart_rx --comp uart_rx
Port ( serial_in : in std_logic; --comp uart_rx
data_out : out std_logic_vector(7 downto 0); --comp uart_rx
read_buffer : in std_logic; --comp uart_rx
reset_buffer : in std_logic; --comp uart_rx
en_16_x_baud : in std_logic; --comp uart_rx
buffer_data_present : out std_logic; --comp uart_rx
buffer_full : out std_logic; --comp uart_rx
buffer_half_full : out std_logic; --comp uart_rx
clk : in std_logic); --comp uart_rx
end component; --comp uart_rx
signal cambio : std_logic :='0';
signal Dfilt : std_logic_vector(7 downto 0);
signal interrupt : std_logic :='0'; --señales
signal interrupt_ack : std_logic; --señales
--señales
--señales
signal baud_count : integer range 0 to 26 :=0; --señales
signal en_16_x_baud : std_logic; --señales
signal write_to_uart : std_logic; --señales
signal tx_data_present : std_logic; --señales
signal tx_full : std_logic; --señales
signal tx_half_full : std_logic; --señales
signal read_from_uart : std_logic :='0'; --señales
signal rx_data : std_logic_vector(7 downto 0); --señales
signal rx_data_present : std_logic; --señales
signal rx_full : std_logic; --señales
signal rx_half_full : std_logic; --señales
--señales
signal previous_rx_half_full : std_logic; --señales
signal rx_half_full_event : std_logic; --señales
begin --------------------------------------------- Comienzo de procesos arquitectura y portmaps
interrupt_control: process(clk) --Control de transmisión
begin --Control de transmisión
if clk'event and clk='1' then --Control de transmisión
--Control de transmisión
-- detect change in state of the 'rx_half_full' flag. --Control de transmisión
previous_rx_half_full <= rx_half_full; --Control de transmisión
rx_half_full_event <= previous_rx_half_full xor rx_half_full;--Control de transmisión
--Control de transmisión
-- processor interrupt waits for an acknowledgement --Control de transmisión
if interrupt_ack='1' then --Control de transmisión
interrupt <= '0'; --Control de transmisión
elsif rx_half_full_event='1' then --Control de transmisión
interrupt <= '1'; --Control de transmisión
else --Control de transmisión
interrupt <= interrupt; --Control de transmisión
end if; --Control de transmisión
--Control de transmisión
end if; --Control de transmisión
end process interrupt_control; --Control de transmisión
transmit: uart_tx_plus
port map ( data_in => rx_data,
write_buffer => rx_data_present,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_out => tx_female,
buffer_data_present => tx_data_present,--Pruebo: desconectado
buffer_full => tx_full, --Pruebo: desconectado
buffer_half_full => tx_half_full, --Pruebo: desconectado
clk => clk );
receive: uart_rx
port map ( serial_in => rx_female,
data_out => rx_data,
read_buffer => read_from_uart, -- Atención:fijar read_from_uart (indica lectura en el macro)
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,--Pruebo: desconectado
buffer_full => rx_full, --Pruebo: desconectado
buffer_half_full => rx_half_full, --Pruebo: desconectado
clk => clk );
LED(7) <= cambio;
LED(6) <= rx_data(6);
LED(5) <= rx_data(5);
LED(4) <= rx_data(4);
LED(3) <= rx_data(3);
LED(2) <= rx_data(2);
LED(1) <= rx_data(1);
LED(0) <= rx_data(0);
toggle: process(rx_data_present)
begin
if rx_data_present'event and rx_data_present='1' then
if cambio='0' then
cambio <= '1';
else
cambio <= '0';
end if;
else
end if;
end process toggle;
baud_timer: process(clk) --Generación de en_16_x_baud
begin --Generación de en_16_x_baud
if clk'event and clk='1' then --Generación de en_16_x_baud
if baud_count=26 then --Generación de en_16_x_baud
baud_count <= 0; --Generación de en_16_x_baud
en_16_x_baud <= '1'; --Generación de en_16_x_baud
else --Generación de en_16_x_baud
baud_count <= baud_count + 1; --Generación de en_16_x_baud
en_16_x_baud <= '0'; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end process baud_timer; --Generación de en_16_x_baud
inicio: process(rx_female)
begin
if rx_female'event and rx_female='0' then
read_from_uart <= '1';
else
end if;
end process inicio;
end Comportamiento;
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/updn_cntr.vhd | 6 | 10193 | `protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 6 | 90319 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65120)
`protect data_block
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| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_v4_0/hdl/vhdl/axi_lite_if.vhd | 7 | 11619 | -------------------------------------------------------------------------------
-- axi_lite_if.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_if.vhd
--
-- Description: Derived AXI-Lite interface module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_lite_if is
generic (
-- AXI4-Lite slave generics
-- C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 4; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_lite_if;
library unisim;
use unisim.vcomponents.all;
architecture IMP of axi_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 8 | 19921 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/async_fifo.vhd | 6 | 33323 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22928)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_v4_0/hdl/vhdl/axi_lite.vhd | 7 | 95564 | -------------------------------------------------------------------------------
-- axi_lite.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite.vhd
--
-- Description: This file is the top level module for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Update BRAM address mapping to lite_ecc_reg module. Corrected
-- signal size for XST detected unused bits in vector.
-- Plus minor code cleanup.
--
-- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add Hsiao ECC algorithm logic (similar to full_axi module HDL).
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move REG_RDATA register process out from C_ECC_TYPE generate block
-- to C_ECC generate block.
-- ^^^^^^
-- JLJ 3/22/2011 v1.03a
-- ~~~~~~
-- Add LUT level with reset signal to combinatorial outputs, AWREADY
-- and WREADY. This will ensure that the output remains LOW during reset,
-- regardless of AWVALID or WVALID input signals.
-- ^^^^^^
-- JLJ 3/28/2011 v1.03a
-- ~~~~~~
-- Remove combinatorial output paths on AWREADY and WREADY.
-- Combine AWREADY and WREADY registers.
-- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY
-- (but only for non ECC configurations).
-- Create 3-bit counter for BVALID response, seperate from AW/W channels.
--
-- Delay assertion of WREADY in ECC configurations to minimize register
-- resource utilization.
-- No pre-assertion of ARREADY in ECC configurations (due to write latency
-- with ECC enabled).
--
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Update Sl_CE and Sl_UE flag assertions to a single clock cycle.
-- Clean up comments.
-- ^^^^^^
-- JLJ 4/19/2011 v1.03a
-- ~~~~~~
-- Update BVALID assertion when ECC is enabled to match the implementation
-- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Modify FaultInjectClr signal assertion. With BVALID counter, delay
-- when fault inject register gets cleared.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 7/7/2011 v1.03a
-- ~~~~~~
-- Fix DV regression failure with reset.
-- Hold off BRAM enable output with active reset signal.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.lite_ecc_reg;
use work.parity;
use work.checkbit_handler;
use work.correct_one_bit;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_lite is
generic (
C_S_AXI_PROTOCOL : string := "AXI4LITE";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : integer := 1;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- Unused AW AXI-Lite Signals
-- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- AXI_AWLEN : in std_logic_vector(7 downto 0);
-- AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- AXI_AWBURST : in std_logic_vector(1 downto 0);
-- AXI_AWLOCK : in std_logic; -- Currently unused
-- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
-- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
-- *** AXI Write Data Channel Signals (W) ***
AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- Unused W AXI-Lite Signals
-- AXI_WLAST : in std_logic;
-- *** AXI Write Data Response Channel Signals (B) ***
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- Unused B AXI-Lite Signals
-- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- *** AXI Read Data Channel Signals (R) ***
AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- *** AXI-Lite ECC Register Interface Signals ***
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** BRAM Port A Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
-- Note: Remove BRAM_RdData_A port (unused in dual port mode)
-- Platgen will keep port open on BRAM block
-- *** BRAM Port B Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC
);
end entity axi_lite;
-------------------------------------------------------------------------------
architecture implementation of axi_lite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future implementation.
-- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8;
-- Internal data width based on C_S_AXI_DATA_WIDTH.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type LITE_SM_TYPE is ( IDLE,
SNG_WR_DATA,
RD_DATA,
RMW_RD_DATA,
RMW_MOD_DATA,
RMW_WR_DATA
);
signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE;
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_reg : std_logic := '0';
signal axi_arready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
signal axi_wready_cmb : std_logic := '0';
signal axi_wready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_set_r : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
signal axi_rlast_set_r : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0');
signal bram_en_a_cmb : std_logic := '0';
signal bram_en_b_cmb : std_logic := '0';
signal bram_en_a_int : std_logic := '0';
signal bram_en_b_int : std_logic := '0';
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC
-------------------------------------------------------------------------------
-- Internal ECC Signals
-------------------------------------------------------------------------------
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal UE_Q : std_logic := '0';
signal Enable_ECC : std_logic := '0';
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate
GEN_NO_REGS: if (C_ECC = 0) generate
begin
AXI_CTRL_AWREADY <= '0';
AXI_CTRL_WREADY <= '0';
AXI_CTRL_BRESP <= (others => '0');
AXI_CTRL_BVALID <= '0';
AXI_CTRL_ARREADY <= '0';
AXI_CTRL_RDATA <= (others => '0');
AXI_CTRL_RRESP <= (others => '0');
AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
BRAM_Addr_En <= '0';
-----------------------------------------------------------------------
-- Generate: GEN_DIS_ECC
-- Purpose: Disable ECC in read path when ECC is disabled in core.
-----------------------------------------------------------------------
GEN_DIS_ECC: if C_ECC = 0 generate
Enable_ECC <= '0';
end generate GEN_DIS_ECC;
-- For future implementation.
--
-- -----------------------------------------------------------------------
-- -- Generate: GEN_EN_ECC
-- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available.
-- -- ECC on/off control register is not accessible (so ECC is always
-- -- enabled in this configuraiton).
-- -----------------------------------------------------------------------
-- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate
-- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC
-- -- ECC registers are available. Therefore, ECC
-- -- is always enabled.
-- end generate GEN_EN_ECC;
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_CTRL_AWVALID => AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC
);
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0';
Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
end generate GEN_REGS;
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
-- AXI_AWREADY <= axi_awready_cmb;
-- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a
AXI_AWREADY <= axi_wready_int; -- v1.03a
-- AXI Write Data Channel Output Signals
-- AXI_WREADY <= axi_wready_cmb;
-- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a
AXI_WREADY <= axi_wready_int; -- v1.03a
-- AXI Write Response Channel Output Signals
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
-- AXI Read Address Channel Output Signals
-- AXI_ARREADY <= axi_arready_cmb; -- v1.03a
AXI_ARREADY <= axi_arready_int; -- v1.03a
-- AXI Read Data Channel Output Signals
-- AXI_RRESP <= axi_rresp_int;
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
-- AXI_RDATA <= axi_rdata_int;
-- Move assignment of RDATA to generate statements based on C_ECC.
AXI_RVALID <= axi_rvalid_int;
AXI_RLAST <= axi_rlast_int;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
-- Notes:
-- No address pipelining for AXI-Lite.
-- PDR feedback.
-- Remove address register stage to BRAM.
-- Rely on registers in AXI Interconnect.
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Generate all valid bits in the address(es) to BRAM.
-- If dual port, generate Port B address signal.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_SNG_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
-- Read takes priority over AWADDR
-- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i);
-- ISE should optimize away this mux when connected to the AXI Interconnect
-- as the AXI Interconnect duplicates the write or read address on both channels.
-- v1.03a
-- ARVALID may get asserted while handling ECC read-modify-write.
-- With the delay in assertion of AWREADY/WREADY, must add some logic to the
-- control on this mux select.
bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and
(lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or
(lite_sm_cs = RD_DATA))
else AXI_AWADDR (i);
end generate GEN_ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_DUAL_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_addr_a_int (i) <= AXI_AWADDR (i);
bram_addr_b_int (i) <= AXI_ARADDR (i);
end generate GEN_ADDR_DUAL_PORT;
end generate GEN_ADDR;
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY
-- Purpose: Only pre-assert ARREADY for non ECC designs.
-- With ECC, a write requires a read-modify-write and
-- will miss the address associated with the ARVALID
-- (due to the # of clock cycles).
---------------------------------------------------------------------------
GEN_ARREADY: if (C_ECC = 0) generate
begin
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- ARREADY is asserted until we detect the ARVALID.
-- Check for back-to-back ARREADY assertions (add axi_arready_int).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(AXI_ARVALID = '1' and axi_arready_int = '1') then
axi_arready_int <= '0';
-- Then ARREADY is asserted again when the read operation completes.
elsif (axi_aresetn_re = '1') or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_arready_int <= '1';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_ECC
-- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted
-- as in the non ECC configuration.
---------------------------------------------------------------------------
GEN_ARREADY_ECC: if (C_ECC = 1) generate
begin
axi_arready_int <= axi_arready_reg;
end generate GEN_ARREADY_ECC;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
-- No AXI_WLAST
---------------------------------------------------------------------------
-- Generate: GEN_WRDATA
-- Purpose: Generate BRAM port A write data. For AXI-Lite, pass
-- through from AXI bus. If ECC is enabled, merge with fault
-- inject vector.
-- Write data bits are in lower order bit lanes.
-- (31:0) or (63:0)
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-- Remove write data path register to BRAM
---------------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
bram_wrdata_a_int (i) <= AXI_WDATA (i);
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_W_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector).
-- (N:0)
---------------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- No BID support (wrap around in Interconnect)
-- In AXI-Lite, no WLAST assertion
-- Drive constant value out on BRESP
-- axi_bresp_int <= RESP_OKAY;
axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY;
---------------------------------------------------------------------------
-- Implement BVALID with counter regardless of IP configuration.
--
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bvalid_cnt = "001" and bvalid_cnt_dec = '1') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt /= "000") then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** AXI Read Data Channel Interface ***
---------------------------------------------------------------------------
-- For reductions on AXI-Lite, drive constant value on RESP
axi_rresp_int <= RESP_OKAY;
---------------------------------------------------------------------------
-- Generate: GEN_R
-- Purpose: Generate AXI R channel outputs when ECC is disabled.
-- No register delay on AXI_RVALID and AXI_RLAST.
---------------------------------------------------------------------------
GEN_R: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R;
---------------------------------------------------------------------------
-- Generate: GEN_R_ECC
-- Purpose: Generate AXI R channel outputs when ECC is enabled.
-- Must use registered delayed control signals for RLAST
-- and RVALID to align with register inclusion for corrected
-- read data in ECC logic.
---------------------------------------------------------------------------
GEN_R_ECC: if C_ECC = 1 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set_r = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set_r = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R_ECC;
---------------------------------------------------------------------------
--
-- Generate AXI bus read data. No register. Pass through
-- read data from BRAM. Determine source on single port
-- vs. dual port configuration.
--
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: RDATA_NO_ECC
-- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled.
-----------------------------------------------------------------------
RDATA_NO_ECC: if (C_ECC = 0) generate
begin
AXI_RDATA <= axi_rdata_int;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_SNG_PORT
-- Purpose: Source of read data: Port A in single port configuration.
-----------------------------------------------------------------------
GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_SNG_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_DUAL_PORT
-- Purpose: Source of read data: Port B in dual port configuration.
-----------------------------------------------------------------------
GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_DUAL_PORT;
end generate RDATA_NO_ECC;
-----------------------------------------------------------------------
-- Generate: RDATA_W_ECC
-- Purpose: Connect AXI_RDATA from ECC module when ECC enabled.
-----------------------------------------------------------------------
RDATA_W_ECC: if (C_ECC = 1) generate
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
begin
-- Logic common to either type of ECC encoding/decoding
-- Renove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0);
-- Remove GEN_RDATA that was doing bit reversal.
-- Read back data is registered prior to any single bit error correction.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rdata_int <= (others => '0');
else
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1);
end if;
end if;
end process REG_RDATA;
---------------------------------------------------------------------------
-- Generate: RDATA_W_HAMMING
-- Purpose: Add generate statement for Hamming Code ECC algorithm
-- specific logic.
---------------------------------------------------------------------------
RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate
begin
-- Move correct_one_bit logic to output side of AXI_RDATA output register.
-- Improves timing by balancing logic on both sides of pipeline stage.
-- Utilizing registers in AXI interconnect makes this feasible.
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table (i))
port map (
DIn => axi_rdata_int (31-i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i));
end generate GEN_CORR_32;
end generate RDATA_W_HAMMING;
-- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC)
end generate RDATA_W_ECC;
---------------------------------------------------------------------------
-- Main AXI-Lite State Machine
--
-- Description: Central processing unit for AXI-Lite write and read address
-- channel interface handling and handshaking.
-- Handles all arbitration between write and read channels
-- to utilize single port to BRAM
--
-- Outputs: axi_wready_int Registered
-- axi_arready_reg Registered (used in ECC configurations)
-- bvalid_cnt_inc Combinatorial
-- axi_rvalid_set Combinatorial
-- axi_rlast_set Combinatorial
-- bram_en_a_cmb Combinatorial
-- bram_en_b_cmb Combinatorial
-- bram_we_a_int Combinatorial
--
--
-- LITE_SM_CMB_PROCESS: Combinational process to determine next state.
-- LITE_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
LITE_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_WVALID,
AXI_WSTRB,
AXI_ARVALID,
AXI_RREADY,
bvalid_cnt,
axi_rvalid_int,
lite_sm_cs )
begin
-- assign default values for state machine outputs
lite_sm_ns <= lite_sm_cs;
axi_wready_cmb <= '0';
axi_arready_cmb <= '0';
bvalid_cnt_inc <= '0';
axi_rvalid_set <= '0';
axi_rlast_set <= '0';
bram_en_a_cmb <= '0';
bram_en_b_cmb <= '0';
bram_we_a_int <= (others => '0');
case lite_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- AXI Interconnect will only issue AWVALID OR ARVALID
-- at a time. In the case when the core is attached
-- to another AXI master IP, arbitrate between read
-- and write operation. Read operation will always win.
if (AXI_ARVALID = '1') then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and
(bvalid_cnt /= "111") then
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Always perform a read-modify-write sequence with ECC is enabled.
if (C_ECC = 1) then
lite_sm_ns <= RMW_RD_DATA;
-- Disable Port A write enables
bram_we_a_int <= (others => '0');
else
-- Non ECC operation or an ECC full 32-bit word write
-- Assert acknowledge of data & address on AXI.
-- Wait to assert AWREADY and WREADY in ECC designs.
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
bvalid_cnt_inc <= '1';
lite_sm_ns <= SNG_WR_DATA;
bram_we_a_int <= AXI_WSTRB;
end if;
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- With early assertion of ARREADY, the SM
-- must be able to accept a read address at any clock cycle.
-- Check here for active ARVALID and directly handle read
-- and do not proceed back to IDLE (no empty clock cycle in which
-- read address may be missed).
if (AXI_ARVALID = '1') and (C_ECC = 0) then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
-- Pre-assertion of ARREADY is only for non ECC configurations.
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
else
lite_sm_ns <= IDLE;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Data is presented to AXI bus
-- Wait for acknowledgment to process any next transfers
-- RVALID may not be asserted as we transition into this state.
if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then
lite_sm_ns <= IDLE;
end if;
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
lite_sm_ns <= RMW_MOD_DATA;
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
lite_sm_ns <= RMW_WR_DATA;
-- Hold off on assertion of WREADY and AWREADY until
-- here, so no pipeline registers necessary.
-- Assert acknowledge of data & address on AXI
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
-- Able to assert this signal early, then BVALID counter
-- will get incremented in the next clock cycle when WREADY
-- is asserted.
bvalid_cnt_inc <= '1';
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Enable all WEs to BRAM
bram_we_a_int <= (others => '1');
-- Complete write operation
lite_sm_ns <= IDLE;
--coverage off
------------------------------ Default ----------------------------
when others =>
lite_sm_ns <= IDLE;
--coverage on
end case;
end process LITE_SM_CMB_PROCESS;
---------------------------------------------------------------------------
LITE_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
lite_sm_cs <= IDLE;
axi_wready_int <= '0';
axi_arready_reg <= '0';
axi_rvalid_set_r <= '0';
axi_rlast_set_r <= '0';
else
lite_sm_cs <= lite_sm_ns;
axi_wready_int <= axi_wready_cmb;
axi_arready_reg <= axi_arready_cmb;
axi_rvalid_set_r <= axi_rvalid_set;
axi_rlast_set_r <= axi_rlast_set;
end if;
end if;
end process LITE_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0');
signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0);
signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0');
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Read on Port A
-- or any operation on Port B (it will be read only).
BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or
(bram_en_b_int = '1')
else '0';
-- BRAM_WE generated from SM
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
REG_RMW_SIGS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset values
if (S_AXI_AResetn = C_RESET_ACTIVE) then
RdModifyWr_Check <= '0';
RdModifyWr_Modify <= '0';
RdModifyWr_Write <= '0';
else
RdModifyWr_Check <= RdModifyWr_Read;
RdModifyWr_Modify <= RdModifyWr_Check;
RdModifyWr_Write <= RdModifyWr_Modify;
end if;
end if;
end process REG_RMW_SIGS;
-- v1.03a
-- Delay assertion of WREADY to minimize registers in core.
-- Use SM transition to RMW "read" to assert this signal.
RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
STORE_WRITE_DBUS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WDATA_Q <= (others => '0');
AXI_WSTRB_Q <= (others => '0');
-- v1.03a
-- With the delay assertion of WREADY, use WVALID
-- to register in WDATA and WSTRB signals.
elsif (AXI_WVALID = '1') then
AXI_WDATA_Q <= AXI_WDATA;
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process STORE_WRITE_DBUS;
wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_S_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0';
bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH)
<= WrECC xor FaultInjectECC;
------------------------------------------------------------------------
-- No need to use RdModifyWr_Write in the data path.
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
---------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
-- Bit swapping done at port level on checkbit_handler (31:0) & (6:0)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)]
CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic to use registered syndrome value.
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_S_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
end process HSIAO_ECC;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
-- Replicate BRAM read back data register for Hamming ECC
ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0);
end if;
end process REG_SYNDROME;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read.
-- Either during RMW of write operation or during BRAM read.
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' or
((Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- Register CE and UE flags to register block.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A
-- Purpose: Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HSIAO;
end generate GEN_DIN_A;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B
-- Purpose: Generate BRAM read data vector assignment in a dual port
-- configuration to be either from Port B, or from Port A in a
-- read-modify-write sequence.
-- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HSIAO;
end generate GEN_DIN_B;
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
-- With AXI-LITE no narrow operations are allowed.
-- AXI_WSTRB is ignored and all byte lanes are written.
bram_en_a_int <= bram_en_a_cmb;
-- BRAM_En_A <= bram_en_a_int;
-- DV regression failure with reset
-- 7/7/11
BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_DUAL_PORT
-- Purpose: Only generate Port B BRAM enable signal when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_en_b_int <= bram_en_b_cmb;
BRAM_En_B <= bram_en_b_int;
end generate GEN_BRAM_EN_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_En_B <= '0';
end generate GEN_BRAM_EN_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate
begin
BRAM_WE_A (i) <= bram_we_a_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A_i (i) <= '0';
BRAM_Addr_B_i (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A_i (i) <= bram_addr_a_int (i);
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_DUAL_PORT
-- Purpose: Only generate Port B BRAM address when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Addr_B_i (i) <= bram_addr_b_int (i);
end generate GEN_BRAM_ADDR_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Addr_B_i (i) <= '0';
end generate GEN_BRAM_ADDR_SNG_PORT;
end generate GEN_U_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data for Port A.
---------------------------------------------------------------------------
-- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL)
GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate
begin
BRAM_WrData_A (i) <= bram_wrdata_a_int (i);
end generate GEN_BRAM_WRDATA;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
end architecture implementation;
| gpl-3.0 |
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/builtin_prim.vhd | 6 | 111867 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 81072)
`protect data_block
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`protect end_protected
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/ramfifo/clk_x_pntrs.vhd | 6 | 35009 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24176)
`protect data_block
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`protect end_protected
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/2bytes_tb_0.vhd | 1 | 3746 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.2i
-- \ \ Application : ISE
-- / / Filename : 2bytes.vhw
-- /___/ /\ Timestamp : Fri Jul 11 07:10:20 2008
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: loopback2bytes_tb_0
--Device: Xilinx
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY loopback2bytes_tb_0 IS
END loopback2bytes_tb_0;
ARCHITECTURE testbench_arch OF loopback2bytes_tb_0 IS
COMPONENT tope_rof512_uart
PORT (
tx_female : Out std_logic;
LED : Out std_logic_vector (7 DownTo 0);
rx_female : In std_logic;
RSTn : In std_logic;
clk : In std_logic
);
END COMPONENT;
SIGNAL tx_female : std_logic := '0';
SIGNAL LED : std_logic_vector (7 DownTo 0) := "00000000";
SIGNAL rx_female : std_logic := '0';
SIGNAL RSTn : std_logic := '0';
SIGNAL clk : std_logic := '0';
constant PERIOD : time := 20 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 ns;
BEGIN
UUT : tope_rof512_uart
PORT MAP (
tx_female => tx_female,
LED => LED,
rx_female => rx_female,
RSTn => RSTn,
clk => clk
);
PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS
BEGIN
-- ------------- Current Time: 100ns
WAIT FOR 100 ns;
rx_female <= '1';
-- -------------------------------------
-- ------------- Current Time: 10010ns
WAIT FOR 9910 ns;
rx_female <= '0';
-- -------------------------------------
-- ------------- Current Time: 18690ns
WAIT FOR 8680 ns;
rx_female <= '1';
-- -------------------------------------
-- ------------- Current Time: 62090ns
WAIT FOR 43400 ns;
rx_female <= '0';
-- -------------------------------------
-- ------------- Current Time: 88130ns
WAIT FOR 26040 ns;
rx_female <= '1';
-- -------------------------------------
-- ------------- Current Time: 96810ns
WAIT FOR 8680 ns;
rx_female <= '0';
-- -------------------------------------
-- ------------- Current Time: 105490ns
WAIT FOR 8680 ns;
rx_female <= '1';
-- -------------------------------------
-- ------------- Current Time: 122850ns
WAIT FOR 17360 ns;
rx_female <= '0';
-- -------------------------------------
-- ------------- Current Time: 174930ns
WAIT FOR 52080 ns;
rx_female <= '1';
-- -------------------------------------
WAIT FOR 25090 ns;
END PROCESS;
END testbench_arch;
| gpl-3.0 |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Adicionales/Programador_StrataFlash_modificado/parallel_flash_memory_uart_programmer.vhd | 1 | 17996 | -- KCPSM3 reference design
-- PicoBlaze performing programming of Intel StrataFlash NOR Flash Memory.
--
-- Design provided and tested on the Spartan-3E Starter Kit (Revision C).
--
-- Ken Chapman - Xilinx Ltd - 28th March 2006.
--
-- The JTAG loader utility is also available for rapid program development.
--
-- The design is set up for a 50MHz system clock and UART communications of 115200 baud
-- 8-bit, no parity, 1 stop-bit. IMPORTANT note: Soft flow control XON/XOFF is used.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2006. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity parallel_flash_memory_uart_programmer is
Port ( tx_female : out std_logic;
rx_female : in std_logic;
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
strataflash_byte : out std_logic;
strataflash_sts : in std_logic; --Pullup on input
strataflash_a : out std_logic_vector(23 downto 0);
strataflash_d : inout std_logic_vector(7 downto 0);
platformflash_oe : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
spi_rom_cs : out std_logic;
spi_adc_conv : out std_logic;
spi_dac_cs : out std_logic;
clk : in std_logic);
end parallel_flash_memory_uart_programmer;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of parallel_flash_memory_uart_programmer is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component progctrl
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic; --JTAG Loader version
clk : in std_logic);
end component;
--
-- declaration of UART transmitter with integral 16 byte FIFO buffer
-- Note this is a modified version of the standard 'uart_tx' in which
-- the 'data_present' signal has also been brought out to better support
-- the XON/XOFF flow control.
--
component uart_tx_plus
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
-- declaration of UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal kcpsm3_reset : std_logic;
--
-- Signals for connection of peripherals
--
signal status_port : std_logic_vector(7 downto 0);
--
--
-- Signals for UART connections
--
signal baud_count : integer range 0 to 26 :=0;
signal en_16_x_baud : std_logic;
signal write_to_uart : std_logic;
signal tx_data_present : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal read_from_uart : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
--
--
-- Signals used to generate interrupt
--
signal previous_rx_half_full : std_logic;
signal rx_half_full_event : std_logic;
--
--
-- Signals to connect to StrataFLASH memory
--
signal strataflash_read : std_logic;
signal write_data : std_logic_vector(7 downto 0);
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- Disable unused components
----------------------------------------------------------------------------------------------------------------------------------
--
-- Although the LCD display only uses pins shared with the StrataFLASH upper data bits [15:8] the
-- following signals ensure that no possible conflict can occur when experimenting with the
-- StrataFLASH memory beyond the design currently presented.
--
lcd_rw <= '0'; --Always writing to display prevents display driving out.
lcd_e <= '0'; --No enable pulses to the display ensures that display contents do not change.
--
--
-- The LSB of the data bus to and from the StrataFLASH device (D0) is connected to many components.
-- This occurs because the board provides multiple ways to configure the Spartan-3E device and
-- consequently all these use the configuration DIN pin. Since one of these configuration options
-- is SPI memory, the board also implements an SPI bus to which further devices are connected.
-- The following signals ensure that additional connections to 'D0' can not cause any conflict with
-- access to the StrataFLASH device.
--
platformflash_oe <= '0'; --Disable (reset) Platform FLASH device used in master serial configuration.
spi_rom_cs <= '1'; --Disable SPI FLASH device used in SPI configuration.
spi_adc_conv <= '0'; --Prevent SPI based A/D converter from generating sample data.
spi_dac_cs <= '1'; --Disable SPI based D/A converter interface.
--
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- Set 8-bit mode of operation for StrataFLASH memory
----------------------------------------------------------------------------------------------------------------------------------
--
-- The StrataFLASH memory can be used in 8-bit or 16-bit modes. Since PicoBlaze is an 8-bit
-- processor and the configuration from parallel flash is conducted using an 8-bit interface,
-- this design forces the 8-bit data mode.
--
-- As a result, the 128Mbit memory is organised as 16,777,216 bytes accessed using a 24-bit address.
--
strataflash_byte <= '0';
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- Bidirectional data interface for StrataFLASH memory
----------------------------------------------------------------------------------------------------------------------------------
--
-- To read the StrataFLASH memory the output enable (OE) signal must be driven Low on the memory and
-- the pins on the Spartan-3E must become inputs (i.e. the output buffers must be high impedance).
--
--
strataflash_oe <= not(strataflash_read); --active Low output enable
--
strataflash_d <= write_data when (strataflash_read='0') else "ZZZZZZZZ";
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 and the program memory
----------------------------------------------------------------------------------------------------------------------------------
--
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => kcpsm3_reset,
clk => clk);
program_rom: progctrl
port map( address => address,
instruction => instruction,
proc_reset => kcpsm3_reset,
clk => clk);
--
----------------------------------------------------------------------------------------------------------------------------------
-- Interrupt
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- Interrupt is used to detect when the UART receiver FIFO reaches half full and this is
-- then used to send XON and XOFF flow control characters back to the PC.
--
-- If 'rx_half_full' goes High, an interrupt is generated and the subsequent ISR will transmit
-- an XOFF character to stop the flow of new characters from the PC and allow the FIFO to start to empty.
--
-- If 'rx_half_full' goes Low, an interrupt is generated and the subsequent ISR will transmit
-- an XON character which will allow the PC to send new characters and allow the FIFO to start to fill.
--
interrupt_control: process(clk)
begin
if clk'event and clk='1' then
-- detect change in state of the 'rx_half_full' flag.
previous_rx_half_full <= rx_half_full;
rx_half_full_event <= previous_rx_half_full xor rx_half_full;
-- processor interrupt waits for an acknowledgement
if interrupt_ack='1' then
interrupt <= '0';
elsif rx_half_full_event='1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end process interrupt_control;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- UART FIFO status signals to form a bus
-- Also the status signal (STS) from the StrataFlash memory
status_port <= strataflash_sts & '0' & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full & tx_data_present;
--
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(1 downto 0) is
-- read status signals at address 00 hex
when "00" => in_port <= status_port;
-- read UART receive data at address 01 hex
when "01" => in_port <= rx_data;
-- read StrataFLASH memory data at address 02 hex
when "10" => in_port <= strataflash_d;
-- Don't care used for all other addresses to ensure minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Form read strobe for UART receiver FIFO buffer at address 01 hex.
-- The fact that the read strobe will occur after the actual data is read by
-- the KCPSM3 is acceptable because it is really means 'I have read you'!
if (read_strobe='1' and port_id(1 downto 0)="01") then
read_from_uart <= '1';
else
read_from_uart <= '0';
end if;
end if;
end process input_ports;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 output ports
----------------------------------------------------------------------------------------------------------------------------------
--
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- The 24-bit address to the StrataFLASH memory requires 3 ports.
-- Address [23:16] at port 80 hex
if port_id(7)='1' then
strataflash_a(23 downto 16) <= out_port;
end if;
-- Address [15:8] at port 40 hex
if port_id(6)='1' then
strataflash_a(15 downto 8) <= out_port;
end if;
-- Address [7:0] at port 20 hex
if port_id(5)='1' then
strataflash_a(7 downto 0) <= out_port;
end if;
-- Data to be written to StrataFlash at port 10 hex
if port_id(4)='1' then
write_data <= out_port;
end if;
-- StrataFlash control signals at port 08 hex
if port_id(3)='1' then
strataflash_read <= out_port(0); --Active High and used to control data bus direction and OE
strataflash_ce <= out_port(1); --Active Low StrataFLASH device enable
strataflash_we <= out_port(2); --Active Low StrataFLASH write enable
end if;
end if;
end if;
end process output_ports;
--
-- write to UART transmitter FIFO buffer at address 04 hex.
-- This is a combinatorial decode because the FIFO is the 'port register'.
--
write_to_uart <= '1' when (write_strobe='1' and port_id(2)='1') else '0';
--
----------------------------------------------------------------------------------------------------------------------------------
-- UART
----------------------------------------------------------------------------------------------------------------------------------
--
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
-- Each contains an embedded 16-byte FIFO buffer.
--
transmit: uart_tx_plus
port map ( data_in => out_port,
write_buffer => write_to_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_out => tx_female,
buffer_data_present => tx_data_present,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
clk => clk );
receive: uart_rx
port map ( serial_in => rx_female,
data_out => rx_data,
read_buffer => read_from_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk );
--
-- Set baud rate to 115200 for the UART communications
-- Requires en_16_x_baud to be 1843200Hz which is a single cycle pulse every 27 cycles at 50MHz
--
baud_timer: process(clk)
begin
if clk'event and clk='1' then
if baud_count=26 then
baud_count <= 0;
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_timer;
--
----------------------------------------------------------------------------------------------------------------------------------
end Behavioral;
------------------------------------------------------------------------------------------------------------------------------------
--
-- END OF FILE parallel_flash_memory_uart_programmer.vhd
--
------------------------------------------------------------------------------------------------------------------------------------
| gpl-3.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_generator_v12_0/hdl/common/rd_pe_as.vhd | 6 | 25238 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
dskntIndustry/Hardware | hdl_library/I2S/I2STB.vhd | 12226531 | 0 | gpl-3.0 |
|
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_generator_v12_0/hdl/builtin/bin_cntr.vhd | 6 | 8597 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/graphicsaccelerator/VGA_Top.fixed.vhd | 1 | 6658 | library IEEE;
use ieee.std_logic_1164.all;
entity VGA_TOP is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
CLK : in std_logic;
HS : out std_logic;
VS : out std_logic;
BUTTON : in std_logic;
RESET : in std_logic;
LED : out std_logic;
ENABLES : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(6 downto 0);
INCOLOR : in std_logic_vector(2 downto 0);
MOVEUP : in std_logic;
MOVEDOWN : in std_logic;
MOVELEFT : in std_logic;
MOVERIGHT : in std_logic;
MOVEP1 : in std_logic;
MOVEP2 : in std_logic
);
end entity VGA_TOP;
architecture BEHAVIORAL of VGA_TOP is
component DEBOUNCER is
port (
CLK : in std_logic;
BUTTON : in std_logic;
DOUT : out std_logic
);
end component;
component BRESENHAMER is
port (
X1 : in std_logic_vector(9 downto 0);
Y1 : in std_logic_vector(8 downto 0);
X2 : in std_logic_vector(9 downto 0);
Y2 : in std_logic_vector(8 downto 0);
CLK : in std_logic;
STARTDRAW : in std_logic;
WRITEENABLE : out std_logic;
SS : out std_logic_vector(3 downto 0);
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
RESET : in std_logic
);
end component;
component SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in std_logic;
DATAIN : in std_logic_vector(2 downto 0);
ADDRESSX : out std_logic_vector(9 downto 0);
ADDRESSY : out std_logic_vector(8 downto 0)
);
end component;
component FRAMEBUFFER is
port (
INX : in std_logic_vector(9 downto 0);
INY : in std_logic_vector(8 downto 0);
OUTX : in std_logic_vector(9 downto 0);
OUTY : in std_logic_vector(8 downto 0);
OUTCOLOR : out std_logic_vector(2 downto 0);
INCOLOR : in std_logic_vector(2 downto 0);
BUFFERWRITE : in std_logic;
CLK : in std_logic
);
end component;
component SEVENSEGMENT is
port (
CLK : in std_logic;
DATA : in std_logic_vector(15 downto 0);
ENABLES : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(6 downto 0)
);
end component;
component POINTER is
generic (
INITX : std_logic_vector(9 downto 0);
INITY : std_logic_vector(8 downto 0)
);
port (
MOVEUP : in std_logic;
MOVEDOWN : in std_logic;
MOVELEFT : in std_logic;
MOVERIGHT : in std_logic;
MOVE : in std_logic;
CLK : in std_logic;
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
SYNCX : in std_logic_vector(9 downto 0);
SYNCY : in std_logic_vector(8 downto 0);
HERE : out std_logic
);
end component;
component FREQDIV is
port (
CLK : in std_logic;
CLK2 : out std_logic
);
end component;
signal adx, gpu_x : std_logic_vector(9 downto 0);
signal ady, gpu_y : std_logic_vector(8 downto 0);
signal data : std_logic_vector(2 downto 0);
signal gim : std_logic_vector(22 downto 0);
signal gpu_color_to_buffer : std_logic_vector(2 downto 0);
signal bufferwrite : std_logic;
signal dout : std_logic;
signal ss : std_logic_vector(3 downto 0);
signal clk2 : std_logic;
signal p1region, p2region : std_logic;
signal rt : std_logic;
signal gt : std_logic;
signal bt : std_logic;
signal x1, x2 : std_logic_vector(9 downto 0);
signal y1, y2 : std_logic_vector(8 downto 0);
begin
INS_FRAMEBUFFER : FRAMEBUFFER
port map (
INX => gpu_x,
INY => gpu_y,
OUTX => adx,
OUTY => ady,
OUTCOLOR => data,
INCOLOR => INCOLOR,
BUFFERWRITE => bufferwrite,
CLK => CLK
);
INS_SYNCHRONIZER : SYNCHRONIZER
port map (
R => rt,
G => gt,
B => bt,
HS => HS,
VS => VS,
CLK => CLK,
DATAIN => data,
ADDRESSX => adx,
ADDRESSY => ady
);
INST_DEBOUNCER : DEBOUNCER
port map (
CLK => CLK,
BUTTON => BUTTON,
DOUT => dout
);
INST_BRESENHAMER : BRESENHAMER
port map (
WRITEENABLE => bufferwrite,
X => gpu_x,
Y => gpu_y,
X1 => x1,
Y1 => y1,
X2 => x2,
Y2 => y2,
CLK => CLK,
SS => ss,
RESET => RESET,
STARTDRAW => dout
);
LED <= bufferwrite;
R <= rt when (p1region='0' and p2region='0') else
not rt;
G <= gt when (p1region='0' and p2region='0') else
not gt;
B <= bt when (p1region='0' and p2region='0') else
not bt;
INST_SEVENSEGMENT : SEVENSEGMENT
port map (
CLK => CLK,
ENABLES => ENABLES,
SEGMENTS => SEGMENTS,
DATA(3 downto 0) => ss,
DATA(15 downto 4) => "000000000000"
);
INST_POINTER1 : POINTER
generic map (
INITX => "0000000100",
INITY => "011110000"
)
port map (
MOVEUP => MOVEUP,
MOVEDOWN => MOVEDOWN,
MOVELEFT => MOVELEFT,
MOVERIGHT => MOVERIGHT,
MOVE => MOVEP1,
CLK => clk2,
HERE => p1region,
X => x1,
Y => y1,
SYNCX => adx,
SYNCY => ady
);
INST_FREQDIV : FREQDIV
port map (
CLK => CLK,
CLK2 => clk2
);
INST_POINTER2 : POINTER
generic map (
INITX => "1001111000",
INITY => "011110000"
)
port map (
MOVEUP => MOVEUP,
MOVEDOWN => MOVEDOWN,
MOVELEFT => MOVELEFT,
MOVERIGHT => MOVERIGHT,
MOVE => MOVEP2,
CLK => clk2,
HERE => p2region,
X => x2,
Y => y2,
SYNCX => adx,
SYNCY => ady
);
end architecture BEHAVIORAL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_011_test_input.fixed.vhd | 1 | 953 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Check loop statements
if a = '1' then
else
LOOP_LABEL : loop
end loop;
end if;
if a = '1' then
else
loop
end loop;
end if;
if a = '1' then
else
while a = 0
loop
end loop;
end if;
if a = '1' then
else
for i in 0 to 13
loop
end loop;
end if;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/type_definition/rule_500_test_input.vhd | 1 | 186 |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (IDLE, WRITE, READ, DONE);
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_yes_align_paren_no_align_when_yes_wrap_at_when_yes.vhd | 1 | 1835 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_502_test_input.vhd | 1 | 232 |
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
FUNCTION FUNC1 RETURN INTEGER IS BEGIN END FUNCTION FUNC1;
procedure proc1 Is begin end procedure proc1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_010_test_input.fixed.vhd | 1 | 279 |
architecture RTL of FIFO is
begin
a <= b & c;
-- violations
a <= b & c;
a <= b & c;
a <= b & c;
-- Multiple violations
a <= b & c & d & e;
-- Extra spaces
a <= b & c & d & e;
-- This is okay
a <= b
& c
& d;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/context/rule_021_test_input.fixed_add.vhd | 1 | 224 |
--This should pass
context c1 is
end context c1;
context c1 is
end context;
--This should fail
context c1 is
end context;
context c1 is
end context
;
-- Split declaration across lines
context
c1
is
end
context
;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_013_test_input.vhd | 1 | 157 |
architecture RTL of FIFO is
begin
process is
begin
end process;
-- Violations below
process IS
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_006_test_input.vhd | 1 | 204 |
architecture RTL of ENT is begin end architecture RTL;
architecture RTL of ENT
is
begin
end;
architecture RTL of ENT
-- Some domment
is
begin
end;
architecture RTL of ENT--some comment
is
begin
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_005_test_input.fixed.vhd | 1 | 191 |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin
a <= b;
end block;
-- Violations below
BLOCK_LABEL : block is begin
a <= b; end block;
end architecture RTL;
| gpl-3.0 |
Jorge9314/ElectronicaDigital | Impresora2D/TB_Divisor_Frecuencia.vhd | 1 | 975 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Divisor_Frecuencia IS
END TB_Divisor_Frecuencia;
ARCHITECTURE behavior OF TB_Divisor_Frecuencia IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divisor_Frecuencia
PORT(
clk : IN std_logic;
Salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal Salida : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divisor_Frecuencia PORT MAP (
clk => clk,
Salida => Salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_015_test_input.vhd | 1 | 487 |
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is -- Comment
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is-- Comment
signal a : std_logic;
begin end architecture RTL;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/rx-core/fei4_rx_channel.vhd | 1 | 6295 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # FE-I4 Style Rx Channel; Sync, Align & Decode
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library decode_8b10b;
entity fei4_rx_channel is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end fei4_rx_channel;
architecture behavioral of fei4_rx_channel is
component cdr_serdes
port (
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
slip : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component;
component data_alignment
port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(1 downto 0);
din_valid : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(9 downto 0);
dout_valid : out std_logic;
dout_sync : out std_logic
);
end component;
component decode_8b10b_wrapper
port(
CLK : IN std_logic;
DIN : IN std_logic_vector(9 downto 0);
CE : IN std_logic;
SINIT : IN std_logic;
DOUT : OUT std_logic_vector(7 downto 0);
KOUT : OUT std_logic;
CODE_ERR : OUT std_logic;
DISP_ERR : OUT std_logic;
ND : OUT std_logic
);
end component;
constant c_SOF : std_logic_vector(7 downto 0) := x"fc";
constant c_EOF : std_logic_vector(7 downto 0) := x"bc";
constant c_IDLE : std_logic_vector(7 downto 0) := x"3c";
signal data_raw_value : std_logic_vector(1 downto 0);
signal data_raw_valid : std_logic_vector(1 downto 0);
signal data_raw_lock : std_logic;
signal data_enc_value : std_logic_vector(9 downto 0);
signal data_enc_valid : std_logic;
signal data_enc_sync : std_logic;
signal data_enc_value_rev : std_logic_vector(9 downto 0);
signal data_enc_valid_rev : std_logic;
signal data_enc_valid_rev_d : std_logic;
signal data_dec_value : std_logic_vector(7 downto 0);
signal data_dec_valid : std_logic;
signal data_dec_kchar : std_logic;
signal data_dec_decerr : std_logic;
signal data_dec_disperr : std_logic;
signal data_fram_cnt : unsigned(1 downto 0);
signal data_frame_flag : std_logic;
signal data_frame_value : std_logic_vector(25 downto 0);
signal data_frame_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
begin
-- Status Output
rx_stat_o <= status;
status(0) <= data_raw_lock;
status(1) <= data_enc_sync;
status(2) <= data_dec_decerr;
status(3) <= data_dec_disperr;
status(5 downto 4) <= data_raw_value;
status(7 downto 6) <= data_raw_valid;
rx_data_raw_o <= data_dec_value;
-- Frame collector
rx_data_o <= data_frame_value;
rx_valid_o <= data_frame_valid and data_raw_lock and data_enc_sync and enable_i;
framing_proc : process(clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fram_cnt <= (others => '0');
data_frame_flag <= '0';
data_frame_value <= (others => '0');
data_frame_valid <= '0';
elsif rising_edge(clk_160_i) then
-- Count bytes
if (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt = 2) then
data_fram_cnt <= (others => '0');
data_frame_valid <= '1';
elsif (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt < 2) then
data_fram_cnt <= data_fram_cnt + 1;
data_frame_valid <= '0';
elsif (data_frame_flag = '0') then
data_fram_cnt <= (others => '0');
data_frame_valid <= '0';
else
data_frame_valid <= '0';
end if;
-- Mark Start and End of Frame
if (data_dec_valid = '1' and data_dec_kchar = '1' and data_dec_value = c_SOF and data_enc_sync = '1') then
data_frame_flag <= '1';
data_frame_value(25 downto 24) <= "01"; -- tag code
data_frame_value(23 downto 0) <= trig_tag_i(23 downto 0);
data_frame_valid <= '1';
elsif (data_dec_valid = '1' and data_dec_kchar = '1' and (data_dec_value = c_EOF or data_dec_value = c_IDLE)) then
data_frame_flag <= '0';
end if;
-- Build Frame
if (data_frame_flag = '1' and data_dec_valid = '1' and data_dec_kchar = '0' ) then
data_frame_value(25 downto 24) <= "00"; -- no special code
data_frame_value(23 downto 16) <= data_frame_value(15 downto 8);
data_frame_value(15 downto 8) <= data_frame_value(7 downto 0);
data_frame_value(7 downto 0) <= data_dec_value;
end if;
end if;
end process framing_proc;
-- Reverse bit order to make it standard
reverse_proc : process (clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_enc_value_rev <= (others => '0');
data_enc_valid_rev <= '0';
data_enc_valid_rev_d <= '0';
data_dec_valid <= '0';
elsif rising_edge(clk_160_i) then
for I in 0 to 9 loop
data_enc_value_rev(I) <= data_enc_value(9-I);
end loop;
data_enc_valid_rev <= data_enc_valid;
data_enc_valid_rev_d <= data_enc_valid_rev;
data_dec_valid <= data_enc_valid_rev_d;
end if;
end process reverse_proc;
cmp_cdr_serdes : cdr_serdes port map (
clk160 => clk_160_i,
clk640 => clk_640_i,
reset => not rst_n_i,
din => rx_data_i,
slip => '0',
data_value => data_raw_value,
data_valid => data_raw_valid,
data_lock => data_raw_lock
);
cmp_data_align : data_alignment port map (
clk => clk_160_i,
reset => not rst_n_i,
din => data_raw_value,
din_valid => data_raw_valid,
dout => data_enc_value,
dout_valid => data_enc_valid,
dout_sync => data_enc_sync
);
cmp_decoder: decode_8b10b_wrapper PORT MAP(
CLK => clk_160_i,
DIN => data_enc_value_rev,
CE => data_enc_valid_rev,
SINIT => '0',
DOUT => data_dec_value,
KOUT => data_dec_kchar,
CODE_ERR => data_dec_decErr,
DISP_ERR => data_dec_dispErr,
ND => open
);
end behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/record_type_definition/rule_100_test_input.vhd | 1 | 310 |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/report_statement/rule_100_test_input.vhd | 1 | 137 |
architecture rtl of fifo is
begin
process begin
report "hello";
report "hello";
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_608_test_input.vhd | 1 | 409 |
entity FIFO is
port (
WR_EN_I : in std_logic;
DATA_O : out std_logic_vector(31 downto 0);
RD_EN_B : buffer std_logic;
DATA_O : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN : buffer std_logic;
DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/logical_operator/rule_500_test_input.vhd | 1 | 151 |
architecture rtl of fifo is
begin
x <= a and b or c nand d nor e xor f xnor g;
x <= a AND b OR c NAND d NOR e XOR f XNOR g;
end architecture;
| gpl-3.0 |
rjarzmik/mips_processor | Caches/SinglePort_Cache.vhd | 1 | 5146 | -------------------------------------------------------------------------------
-- Title : Single port cache
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : SinglePort_Cache.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-19
-- Last update: 2016-11-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Cache with one access port and one port to the memory/L+1 cache
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-19 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity SinglePort_Cache is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
i_porta_req : in std_logic;
i_porta_we : in std_logic;
i_porta_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_porta_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_valid : out std_logic;
o_memory_req : out std_logic;
o_memory_we : out std_logic;
o_memory_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_memory_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_valid : in std_logic
);
end entity SinglePort_Cache;
-------------------------------------------------------------------------------
architecture passthrough of SinglePort_Cache is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
-- access handling
signal cache_initialized : boolean := false;
signal cache_loaded : boolean;
signal cache_hit : boolean;
signal cache_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := (others => '1');
signal cache_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
-- cache_valid means: for previously latched address, cache_data is valid.
-- cache_valid also means: for last time i_porta_req was raised, for the
-- i_porta_addr that was input, the data on cache_data is valid.
signal cache_valid : boolean;
-- dearm_memory_req : ensure o_memory_req is held only 1 cycle for each request
signal dearm_memory_req : boolean := false;
signal memory_ongoing : boolean := false;
begin -- architecture str
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
process(rst, clk) is
begin
if rst = '0' then
if rising_edge(clk) then
if i_porta_req = '1' then
if not cache_initialized or cache_addr /= i_porta_addr then
cache_addr <= i_porta_addr;
cache_valid <= false;
cache_data <= (others => 'X');
o_memory_addr <= i_porta_addr;
o_memory_req <= '1';
dearm_memory_req <= true;
memory_ongoing <= true;
o_memory_we <= i_porta_we;
o_memory_write_data <= i_porta_write_data;
end if;
-- If cache_valid and cache_valid = i_porta_addr, output is still
-- valid and nothing is to be done.
elsif dearm_memory_req then
o_memory_req <= '0';
dearm_memory_req <= false;
if i_memory_valid = '0' then
cache_valid <= false; -- dearm cache_valid one cycle after
-- cache_addr changed
end if;
end if;
if i_memory_valid = '1' then
memory_ongoing <= false;
cache_data <= i_memory_read_data;
cache_initialized <= true;
if not (i_porta_req = '1' and (cache_addr /= i_porta_addr)) then
cache_valid <= true;
end if;
-- In parallel, o_porta_valid will become '1'
end if;
end if;
else
o_memory_req <= '0';
cache_valid <= false;
end if;
end process;
o_porta_valid <= '1' when cache_valid else '0';
o_porta_read_data <= cache_data when cache_valid else (others => 'X');
end architecture passthrough;
---------------------------------------------------------------------------------
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/integer_type_definition/classification_test_input.vhd | 1 | 175 |
architecture RTL of FIFO is
type Voltage_Level is range 0 to 5;
type Int_64K is range -65536 to 65535;
type WORD is range 31 downto 0;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_100_test_input.fixed.vhd | 1 | 383 |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := (12, 13, 15);
begin
process
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := (12, 13, 15);
constant c_word : integer := (12, 13, 15);
begin end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_019_test_input.fixed_lower.vhd | 3 | 221 |
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ent is
begin
end rtl;
architecture RTL of Ent is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_002_test_input.fixed.vhd | 1 | 226 |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_010_test_input.vhd | 1 | 405 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
i_wr_en : in std_logic;
i_data : out std_logic_vector(31 downto 0);
i_rd_en : in std_logic;
o_data : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_no_align_paren_yes_align_when_no_wrap_at_when_yes.vhd | 1 | 2159 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_019_test_input.vhd | 1 | 241 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
| gpl-3.0 |
Yarr/Yarr-fw | syn/kintex7/rd53_ohio_16x1_640Mbps/board_pkg.vhd | 1 | 953 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.hw_type_pkg.all;
package board_pkg is
constant c_FW_IDENT : std_logic_vector(31 downto 0) := c_HW_IDENT & x"030232";
constant c_TX_ENCODING : string := "OSERDES";
constant c_TX_CHANNELS : integer := 4;
constant c_RX_CHANNELS : integer := 16;
constant c_FE_TYPE : string := "RD53";
constant c_RX_NUM_LANES : integer := 1;
constant c_RX_SPEED : string := "0640";
constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"AAAAAAAA";
constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"817e817e";
constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(16,8);
constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(500,16);
constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(4,4);
end board_pkg;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_501_test_input.fixed_lower.vhd | 1 | 169 |
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
BLOCK_LABEL : block IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_006_test_input.fixed.vhd | 1 | 1180 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
-- Failing variations
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
-- Testing generate breaks
a <= b;
gen : if '1' = '1' generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
gen : for i in 0 to 7 generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
aSlightlyLooongerName <= c;
LABEL0 : case a & b & c generate
when "000" =>
anExtraLoooooooooooooooooooongName <= c;
anExtraLoooooooooooongName <= c;
when "001" =>
anExtraLoooooooooooooooongName <= c;
anExtraLooooooooooooooooooooooooongName <= c;
end generate LABEL0;
aSlighltyLongerName <= d;
b <= c;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case_generate_alternative/rule_501_test_input.fixed_lower.vhd | 1 | 207 |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
when others =>
end generate;
GEN_LABEL : case expression generate
when others =>
end generate;
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/library/rule_007_test_input.fixed.vhd | 1 | 196 |
use stdio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_412_test_input.fixed.vhd | 1 | 3364 |
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant a : in integer; signal b : in std_logic; variable c : in std_logic);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic); -- variable ccc
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
);
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic); -- variable ccc
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic);
end package FIFO_PKG;
package body FIFO_PKG is
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
end package body FIFO_PKG;
architecture RTL of ENT is
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
begin
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES ( -- parameters
constant a : in integer;
signal b : in std_logic;
variable ccc : in std_logic
-- line starting with comment
) is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer; -- constant a
signal b : in std_logic; -- signal b
variable ccc : in std_logic -- variable ccc
) is
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/read_data_path.vhd | 20 | 24605 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/rtl/traffic_gen/read_data_path.vhd | 20 | 24605 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_017_test_input.fixed_record_constraint_open_paren__remove_new_line.vhd | 1 | 578 | architecture rtl of fifo is
constant sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)
(6
downto 0)
,
elementF(7 downto 0)
),
element6(4 downto
0),
element7(7 downto 0));
constant sig9 : t_data_struct(data(7 downto 0));
constant sig9 : t_data_struct(
data(7 downto 0)
);
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_503_test_input.fixed_upper.vhd | 1 | 109 |
package body fifo_pkg IS
end package body fifo_pkg;
package body fifo_pkg IS
end package body fifo_pkg;
| gpl-3.0 |
lelongdunet/dspunit | rtl/bit_manipulation.vhdl | 2 | 12347 | -- bit_manipulation.vhdl - miscellaneous bit manipulation functions
-- Copyright (C) 2001, 2002 Michael Riepe <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id: bit_manipulation.vhdl,v 1.10 2002/07/05 21:36:57 michael Exp $
-- url : http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/common/bit_manipulation.vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package Bit_Manipulation is
-- reverse bits in a vector
function bit_reverse (A : in signed) return signed;
function bit_reverse (A : in unsigned) return unsigned;
function bit_reverse (A : in std_logic_vector) return std_logic_vector;
-- extract 1 bit of N, starting at offset O
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector;
-- duplicate all bits in a vector
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- duplicate vector
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- AND cascade
function cascade_and (A : in std_logic_vector) return std_logic_vector;
-- OR cascade
function cascade_or (A : in std_logic_vector) return std_logic_vector;
-- n:1 AND
function reduce_and (A : in std_logic_vector) return std_logic;
-- n:1 XOR
function reduce_xor (A : in std_logic_vector) return std_logic;
-- n:1 OR
function reduce_or (A : in std_logic_vector) return std_logic;
-- left shift w/ carry-in
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- left shift w/o carry-in
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic left shift
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right shift w/ carry-in
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- right shift w/o carry-in
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic right shift
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- left rotate
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right rotate
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned;
-- function bitbit_and(A : in signed; B : in signed) return signed;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector;
end Bit_Manipulation;
package body Bit_Manipulation is
function bit_reverse (A : in signed) return signed is
begin
return signed(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in unsigned) return unsigned is
begin
return unsigned(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, yy : std_logic_vector(L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in aa'range loop
yy(i) := aa(L - 1 - i);
end loop;
return yy;
end bit_reverse;
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector is
constant L : natural := A'length;
constant L2 : natural := (L - O + N - 1) / N;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L2-1 downto 0);
begin
--pragma synthesis_off
assert L > O;
--pragma synthesis_on
for i in L2-1 downto 0 loop
yy(i) := aa(N*i+O);
end loop;
return yy;
end bit_extract;
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i/N);
end loop;
return yy;
end bit_duplicate;
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i rem L);
end loop;
return yy;
end vector_duplicate;
function cascade_and (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) and aa(k1) and aa(k2) and aa(k3);
when 2 =>
bb(j) := aa(j) and aa(k1) and aa(k2);
when 1 =>
bb(j) := aa(j) and aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_and;
function cascade_or (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) or aa(k1) or aa(k2) or aa(k3);
when 2 =>
bb(j) := aa(j) or aa(k1) or aa(k2);
when 1 =>
bb(j) := aa(j) or aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_or;
function reduce_and (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) and aa(4*i+1) and aa(4*i+2) and aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) and aa(4*k+1) and aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) and aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_and;
function reduce_xor (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 31 loop -- should be enough
exit when len = 1;
k := len / 2;
for i in 0 to k-1 loop
aa(i) := aa(2*i+0) xor aa(2*i+1);
end loop;
case len mod 2 is
when 1 => aa(k) := aa(2*k+0);
when others => null;
end case;
len := (len + 1) / 2;
end loop;
return aa(0);
end reduce_xor;
function reduce_or (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) or aa(4*i+1) or aa(4*i+2) or aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) or aa(4*k+1) or aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) or aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_or;
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-1 downto N) := aa(L-N-1 downto 0);
end if;
return yy;
end lshift;
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, '0');
end lshift;
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, A(A'right));
end lshifta;
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-N-1 downto 0) := aa(L-1 downto N);
end if;
return yy;
end rshift;
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, '0');
end rshift;
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, A(A'left));
end rshifta;
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + L - N) rem L);
end loop;
return yy;
end lrotate;
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + N) rem L);
end loop;
return yy;
end rrotate;
-- function bitbit_and(A : in signed; B : in signed) return signed is
-- begin
-- return signed(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned is
-- begin
-- return unsigned(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and bb(i);
end loop;
return yy;
end bitbit_and;
function bitbit_or(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) or bb(i);
end loop;
return yy;
end bitbit_or;
end Bit_Manipulation;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please
| gpl-3.0 |
Pinwino/sa | debugger_gw/fmc-delay/top/spec_top_std.vhd | 1 | 31850 | -------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCI-Express FMC Carrier) top level
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : spec_top_std.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the SPEC 1.1 (and later releases) cards with
-- one Fine Delay FMC.
-- Supports:
-- - SDB enumeration (SDB descriptor at 0x00000)
-- - White Rabbit and Etherbone
-- - Interrupts (via WR VIC)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.genram_pkg.all;
use work.debugger_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top_std is
generic
(
g_simulation : integer := 0
);
port
(
-------------------------------------------------------------------------
-- Standard SPEC ports (Gennum bridge, LEDS, Etc. Do not modify
-------------------------------------------------------------------------
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-------------------------------------------------------------------------
-- PLL VCXO DAC Drive
-------------------------------------------------------------------------
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
--dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic;
fmc_scl_b : inout std_logic := '1';
fmc_sda_b : inout std_logic := '1';
carrier_onewire_b : inout std_logic := '1';
fmc_prsnt_m2c_l_i : in std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- detect pin
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
-------------------------------------------------------------------------
-- Fine Delay Pins
-------------------------------------------------------------------------
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
fd_clk_ref_p_i : in std_logic;
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic;
fd_tdc_cal_pulse_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
fd_led_trig_o : out std_logic;
fd_tdc_start_dis_o : out std_logic;
fd_tdc_stop_dis_o : out std_logic;
fd_spi_cs_dac_n_o : out std_logic;
fd_spi_cs_pll_n_o : out std_logic;
fd_spi_cs_gpio_n_o : out std_logic;
fd_spi_sclk_o : out std_logic;
fd_spi_mosi_o : out std_logic;
fd_spi_miso_i : in std_logic;
fd_delay_len_o : out std_logic_vector(3 downto 0);
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd_dmtd_clk_o : out std_logic;
fd_dmtd_fb_in_i : in std_logic;
fd_dmtd_fb_out_i : in std_logic;
fd_pll_status_i : in std_logic;
fd_ext_rst_n_o : out std_logic;
fd_onewire_b : inout std_logic;
-----------------------------------------
-- UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end spec_top_std;
architecture rtl of spec_top_std is
signal wrpc_uart_rxd_i: std_logic;
signal wrpc_uart_txd_o: std_logic;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
component fd_ddr_pll
port (
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
function f_resize_slv (x : std_logic_vector; len : integer) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
if(len > x'length) then
tmp(x'length-1 downto 0) := x;
tmp(len-1 downto x'length) := (others => '0');
elsif(len < x'length) then
tmp := x(len-1 downto 0);
else
tmp := x;
end if;
return tmp;
end f_resize_slv;
function f_int2bool (x : integer) return boolean is
begin
if(x = 0) then
return false;
else
return true;
end if;
end f_int2bool;
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 3;
constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_MASTER_DEBUGGER : integer := 2;
constant c_SLAVE_FD : integer := 0;
constant c_SLAVE_WRCORE : integer := 1;
constant c_SLAVE_VIC : integer := 2;
constant c_SLAVE_DEBG : integer := 3;
constant c_DESC_SYNTHESIS : integer := 4;
constant c_DESC_REPO_URL : integer := 5;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS+1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
c_SLAVE_FD => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"),
c_SLAVE_DEBG => f_sdb_embed_device(c_xwb_dbg_slave_sdb, x"00040000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url));
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00080000");
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal local_reset_n : std_logic;
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal dcm_clk_ref_0, dcm_clk_ref_180 : std_logic;
signal fd_tdc_start : std_logic;
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic;
signal ddr_pll_reset : std_logic;
signal ddr_pll_locked, fd_pll_status : std_logic;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal fd_scl_out, fd_scl_in, fd_sda_out, fd_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal fd_owr_en, fd_owr_in : std_logic;
signal fd_irq : std_logic;
signal gn_wb_adr : std_logic_vector(31 downto 0);
signal pps : std_logic;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal vic_irqs : std_logic_vector(31 downto 0);
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
begin
U_Reset_Generator : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => l_rst_n,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
U_Buf_CLK_PLL : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_Buf_CLK_GTP : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-------------------------------------------------------------------------------
-- Gennum core
-------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
dma_clk_i => clk_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_dat_i => (others => '0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0'
);
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-------------------------------------------------------------------------------
-- Top level interconnect and interrupt controller
-------------------------------------------------------------------------------
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_VIC : xwb_vic
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => fd_irq,
irq_master_o => GPIO(0));
-------------------------------------------------------------------------------
-- White Rabbit Core + PHY
-------------------------------------------------------------------------------
-- Tristates for FMC EEPROM
fmc_scl_b <= '0' when (wrc_scl_out = '0' or fd_scl_out = '0') else 'Z';
fmc_sda_b <= '0' when (wrc_sda_out = '0' or fd_sda_out = '0') else 'Z';
wrc_scl_in <= fmc_scl_b;
wrc_sda_in <= fmc_sda_b;
fd_scl_in <= fmc_scl_b;
fd_sda_in <= fmc_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
U_WR_CORE : xwr_core
generic map (
g_simulation => g_simulation,
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_dpram_initf => "wrc-ethb.ram",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false,
g_aux_sdb => c_etherbone_sdb)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => dcm_clk_ref_0,
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
led_act_o => open,
led_link_o => LED_GREEN,
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => wrpc_uart_rxd_i,
uart_txd_o => wrpc_uart_txd_o,
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
wrf_src_o => etherbone_snk_in,
wrf_src_i => etherbone_snk_out,
wrf_snk_o => etherbone_src_in,
wrf_snk_i => etherbone_src_out,
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
btn1_i => '0',
btn2_i => '0',
rst_aux_n_o => etherbone_rst_n,
pps_p_o => pps
);
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', --phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
U_Etherbone : eb_slave_core
generic map (
g_sdb_address => f_resize_slv(c_sdb_address, 64))
port map (
clk_i => clk_sys,
nRst_i => etherbone_rst_n,
src_o => etherbone_src_out,
src_i => etherbone_src_in,
snk_o => etherbone_snk_out,
snk_i => etherbone_snk_in,
cfg_slave_o => etherbone_cfg_out,
cfg_slave_i => etherbone_cfg_in,
master_o => cnx_slave_in(c_MASTER_ETHERBONE),
master_i => cnx_slave_out(c_MASTER_ETHERBONE));
--cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- dac_clr_n_o <= '1';
sfp_tx_disable_o <= '0';
-------------------------------------------------------------------------------
-- FINE DELAY INSTANTIATION
-------------------------------------------------------------------------------
cmp_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd_tdc_start, -- Buffer output
I => fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_DDR_PLL : fd_ddr_pll
port map (
RST => ddr_pll_reset,
LOCKED => ddr_pll_locked,
CLK_IN1_P => fd_clk_ref_p_i,
CLK_IN1_N => fd_clk_ref_n_i,
CLK_OUT1 => dcm_clk_ref_0,
CLK_OUT2 => dcm_clk_ref_180);
ddr_pll_reset <= not fd_pll_status_i;
fd_pll_status <= fd_pll_status_i and ddr_pll_locked;
U_FineDelay_Core : fine_delay_core
generic map (
g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => dcm_clk_ref_0,
clk_ref_180_i => dcm_clk_ref_180,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
rst_n_i => local_reset_n,
dcm_reset_o => open,
dcm_locked_i => ddr_pll_locked,
trig_a_i => fd_trig_a_i,
tdc_cal_pulse_o => fd_tdc_cal_pulse_o,
tdc_start_i => fd_tdc_start,
dmtd_fb_in_i => fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd_dmtd_fb_out_i,
dmtd_samp_o => fd_dmtd_clk_o,
led_trig_o => fd_led_trig_o,
ext_rst_n_o => fd_ext_rst_n_o,
pll_status_i => fd_pll_status,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr,
owr_en_o => fd_owr_en,
owr_i => fd_owr_in,
i2c_scl_oen_o => fd_scl_out,
i2c_scl_i => fd_scl_in,
i2c_sda_oen_o => fd_sda_out,
i2c_sda_i => fd_sda_in,
fmc_present_n_i => fmc_prsnt_m2c_l_i,
wb_adr_i => cnx_master_out(c_SLAVE_FD).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD).stall,
wb_irq_o => fd_irq);
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
fd_onewire_b <= '0' when fd_owr_en = '1' else 'Z';
fd_owr_in <= fd_onewire_b;
U_Debugger : wb_debugger
generic map(
-- g_dbg_init_file => "dbg_code.ram"
g_dbg_init_file => "FD_node"
-- g_dbg_dpram_size => 114740/4
)
port map(
clk_sys => clk_sys,
reset_n => local_reset_n,
master_i => cnx_slave_out(c_MASTER_DEBUGGER),
master_o => cnx_slave_in(c_MASTER_DEBUGGER),
slave_i => cnx_master_out(c_SLAVE_DEBG),
slave_o => cnx_master_in(c_SLAVE_DEBG),
wrpc_uart_rxd_i => wrpc_uart_rxd_i,
wrpc_uart_txd_o => wrpc_uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
dbg_indicator => LED_RED,
dbg_control_select => button2_i
);
end rtl;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/Ascon_block_whole.vhd | 1 | 2389 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- ExtInputs
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Busy : out std_logic;
DataOut : out std_logic_vector(127 downto 0));
end entity Ascon_StateUpdate;
architecture structural of Ascon_StateUpdate is
-- Control signals
signal RoundNr : std_logic_vector(1 downto 0);
signal sel1,sel2,sel3,sel4 : std_logic_vector(1 downto 0);
signal sel0 : std_logic_vector(2 downto 0);
signal selout : std_logic;
signal Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : std_logic;
signal ActivateGen : std_logic;
signal GenSize : std_logic_vector(3 downto 0);
begin
control: entity work.Ascon_StateUpdate_control port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, Start, Mode, Size, Busy);
datapath: entity work.Ascon_StateUpdate_datapath port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, IV, Key, DataIn, DataOut);
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/PreProcessor.vhd | 9 | 20414 | -------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/API_plus_CipherCore/PreProcessor.vhd | 9 | 20414 | -------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Fullround.vhd | 1 | 4893 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Fullrounds is
port(
Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : in std_logic_vector(63 downto 0);
RoundNr : in std_logic;
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4 : out std_logic_vector(63 downto 0));
end entity Fullrounds;
architecture structural of Fullrounds is
signal RoundNr_0, RoundNr_1, RoundNr_2, RoundNr_3, RoundNr_4, RoundNr_5 : std_logic_vector(3 downto 0);
signal SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4 : std_logic_vector(63 downto 0);
signal SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4 : std_logic_vector(63 downto 0);
signal SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4 : std_logic_vector(63 downto 0);
signal SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4 : std_logic_vector(63 downto 0);
signal SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4 : std_logic_vector(63 downto 0);
signal SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4 : std_logic_vector(63 downto 0);
signal DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4 : std_logic_vector(63 downto 0);
signal DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4 : std_logic_vector(63 downto 0);
signal DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4 : std_logic_vector(63 downto 0);
signal DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4 : std_logic_vector(63 downto 0);
signal DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4 : std_logic_vector(63 downto 0);
begin
-- declare and connect all sub entities
sbox1: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr_0,
SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4);
difflayer1: entity work.FullDiffusionLayer port map(SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4,
DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4);
sbox2: entity work.Sbox port map(DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4,RoundNr_1,
SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4);
difflayer2: entity work.FullDiffusionLayer port map(SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4,
DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4);
sbox3: entity work.Sbox port map(DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4,RoundNr_2,
SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4);
difflayer3: entity work.FullDiffusionLayer port map(SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4,
DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4);
sbox4: entity work.Sbox port map(DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4,RoundNr_3,
SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4);
difflayer4: entity work.FullDiffusionLayer port map(SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4,
DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4);
sbox5: entity work.Sbox port map(DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4,RoundNr_4,
SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4);
difflayer5: entity work.FullDiffusionLayer port map(SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4,
DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4);
sbox6: entity work.Sbox port map(DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4,RoundNr_5,
SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4);
difflayer6: entity work.FullDiffusionLayer port map(SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4,
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4);
roundnrgen: process(RoundNr) is
begin
if RoundNr = '0' then
RoundNr_0 <= "0000";
RoundNr_1 <= "0001";
RoundNr_2 <= "0010";
RoundNr_3 <= "0011";
RoundNr_4 <= "0100";
RoundNr_5 <= "0101";
else
RoundNr_0 <= "0110";
RoundNr_1 <= "0111";
RoundNr_2 <= "1000";
RoundNr_3 <= "1001";
RoundNr_4 <= "1010";
RoundNr_5 <= "1011";
end if;
end process;
end architecture structural;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/AEAD_TB.vhd | 9 | 22508 | -------------------------------------------------------------------------------
--! @file AEAD_TB.vhd
--! @brief Testbench for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.0b1
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity AEAD_TB IS
generic (
--! Test parameters
G_STOP_AT_FAULT : boolean := True;
G_TEST_MODE : integer := 0;
G_TEST_ISTALL : integer := 10;
G_TEST_OSTALL : integer := 10;
G_LOG2_FIFODEPTH : integer := 8;
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_PERIOD : time := 10 ns;
G_FNAME_PDI : string := "pdi.txt";
G_FNAME_SDI : string := "sdi.txt";
G_FNAME_DO : string := "do.txt";
G_FNAME_LOG : string := "log.txt";
G_FNAME_RESULT : string := "result.txt"
);
end AEAD_TB;
architecture behavior of AEAD_TB is
--! =================== --
--! SIGNALS DECLARATION --
--! =================== --
--! simulation signals (used by ATHENa script, ignore if not used)
signal simulation_fails : std_logic := '0'; --! '0' signifies a pass at the end of simulation, '1' is fail
signal stop_clock : boolean := False; --! '1' signifies a completed simulation, '0' otherwise
--! error check signal
signal global_stop : std_logic := '1';
--! globals
signal clk : std_logic := '0';
signal io_clk : std_logic := '0';
signal rst : std_logic := '0';
--! do
signal do_ext : std_logic_vector(G_PWIDTH-1 downto 0);
signal do : std_logic_vector(G_PWIDTH-1 downto 0);
signal do_empty : std_logic;
signal do_full : std_logic;
signal do_read : std_logic := '0';
signal do_valid : std_logic;
signal do_full_selected : std_logic;
signal do_write_selected : std_logic;
signal do_ready : std_logic;
--! pdi
signal pdi_ext : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
signal pdi : std_logic_vector(G_PWIDTH-1 downto 0);
signal pdi_empty : std_logic;
signal pdi_full : std_logic;
signal pdi_ready : std_logic;
signal pdi_write : std_logic := '0';
signal pdi_read_selected : std_logic;
signal pdi_empty_selected : std_logic;
signal pdi_valid : std_logic;
signal pdi_delayed : std_logic_vector(G_PWIDTH-1 downto 0);
--! sdi
signal sdi_ext : std_logic_vector(G_SWIDTH-1 downto 0) := (others=>'0');
signal sdi : std_logic_vector(G_SWIDTH-1 downto 0);
signal sdi_empty : std_logic;
signal sdi_full : std_logic;
signal sdi_ready : std_logic;
signal sdi_write : std_logic := '0';
signal sdi_read_selected : std_logic;
signal sdi_empty_selected : std_logic;
signal sdi_valid : std_logic;
signal sdi_delayed : std_logic_vector(G_SWIDTH-1 downto 0);
--! Verification signals
signal stall_pdi_empty : std_logic := '0';
signal stall_sdi_empty : std_logic := '0';
signal stall_do_full : std_logic := '0';
------------- clock constant ------------------
constant clk_period : time := G_PERIOD;
constant io_clk_period : time := clk_period;
----------- end of clock constant -------------
------------- string constant ------------------
--! constant
constant cons_ins : string(1 to 6) := "INS = ";
constant cons_hdr : string(1 to 6) := "HDR = ";
constant cons_dat : string(1 to 6) := "DAT = ";
--! Shared constant
constant cons_eof : string(1 to 6) := "###EOF";
----------- end of string constant -------------
------------- debug constant ------------------
constant debug_input : boolean := False;
constant debug_output : boolean := False;
----------- end of clock constant -------------
-- ================= --
-- FILES DECLARATION --
-- ================= --
--------------- input / output files -------------------
file pdi_file : text open read_mode is G_FNAME_PDI;
file sdi_file : text open read_mode is G_FNAME_SDI;
file do_file : text open read_mode is G_FNAME_DO;
file log_file : text open write_mode is G_FNAME_LOG;
file result_file : text open write_mode is G_FNAME_RESULT;
------------- end of input files --------------------
begin
genClk: process
begin
if (not stop_clock and global_stop = '1') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process genClk;
genIOclk: process
begin
if ((not stop_clock) and (global_stop = '1')) then
io_clk <= '1';
wait for io_clk_period/2;
io_clk <= '0';
wait for io_clk_period/2;
else
wait;
end if;
end process genIOclk;
--! ============ --
--! PORT MAPPING --
--! ============ --
genPDIfifo: entity work.fifo(structure)
generic map (
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => pdi_write,
read => pdi_read_selected,
din => pdi_ext,
dout => pdi,
full => pdi_full,
empty => pdi_empty);
pdi_read_selected <= '0' when stall_pdi_empty = '1' else pdi_ready;
pdi_empty_selected <= '1' when stall_pdi_empty = '1' else pdi_empty; --! '1' when emptied
pdi_valid <= not pdi_empty_selected;
pdi_delayed <= pdi after 1/4*clk_period; --! Delay to simulate real HW
genSDIfifo: entity work.fifo(structure)
generic map (
G_W => G_SWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => sdi_write,
read => sdi_read_selected,
din => sdi_ext,
dout => sdi,
full => sdi_full,
empty => sdi_empty);
sdi_read_selected <= '0' when stall_sdi_empty = '1' else sdi_ready;
sdi_empty_selected <= '1' when stall_sdi_empty = '1' else sdi_empty; -- '1' when emptied
sdi_valid <= not sdi_empty_selected;
sdi_delayed <= sdi after 1/4*clk_period; --! Delay to simulate real HW
genDOfifo: entity work.fifo(structure)
generic map (
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => do_write_selected,
read => do_read,
din => do,
dout => do_ext,
full => do_full,
empty => do_empty
);
do_write_selected <= '0' when stall_do_full = '1' else do_valid;
do_full_selected <= '1' when stall_do_full = '1' else do_full; -- '1' when fulled
do_ready <= not do_full_selected;
uut: entity work.AEAD(structure)
generic map (
G_PWIDTH => G_PWIDTH,
G_SWIDTH => G_SWIDTH
)
port map (
rst => rst,
clk => clk,
pdi => pdi_delayed,
pdi_ready => pdi_ready,
pdi_valid => pdi_valid,
sdi => sdi_delayed,
sdi_ready => sdi_ready,
sdi_valid => sdi_valid,
do => do,
do_valid => do_valid,
do_ready => do_ready
);
--! =================== --
--! END OF PORT MAPPING --
--! =================== --
--! ===========================================================================
--! ==================== DATA POPULATION FOR PUBLIC DATA ======================
tb_read_pdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
--! read header
while ( not endfile (pdi_file)) and ( loop_enable = '1' ) loop
if endfile (pdi_file) then
loop_enable := '0';
end if;
readline(pdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( pdi_file ) loop
--! if the fifo is full, wait ...
pdi_write <= '1';
if ( pdi_full = '1' ) then
pdi_write <= '0';
wait until pdi_full <= '0';
wait for io_clk_period/2; --! write in the rising edge
pdi_write <= '1';
end if;
hread( line_data, word_block, read_result );
while (((read_result = False) or (valid_line = False)) and (not endfile( pdi_file ))) loop
readline(pdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr or temp_read = cons_dat)
then
valid_line := True;
pdi_write <= '1';
else
valid_line := False;
pdi_write <= '0';
end if;
hread( line_data, word_block, read_result ); --! read data
end loop;
pdi_ext <= word_block;
wait for io_clk_period;
end loop;
pdi_write <= '0';
wait;
end process;
--! ======================================================================
--! ==================== DATA POPULATION FOR SECRET DATA =================
tb_read_sdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_SWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
--! read header
while (not endfile (sdi_file)) and (loop_enable = '1') loop
if endfile (sdi_file) then
loop_enable := '0';
end if;
readline(sdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( sdi_file ) loop
--! if the fifo is full, wait ...
sdi_write <= '1';
if ( sdi_full = '1' ) then
sdi_write <= '0';
wait until sdi_full <= '0';
wait for io_clk_period/2; --! write in the rising edge
sdi_write <= '1';
end if;
hread(line_data, word_block, read_result);
while (((read_result = False) or (valid_line = False)) and (not endfile( sdi_file ))) loop
readline(sdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr or temp_read = cons_dat)
then
valid_line := True;
sdi_write <= '1';
else
valid_line := False;
sdi_write <= '0';
end if;
hread( line_data, word_block, read_result ); --! read data
end loop;
sdi_ext <= word_block;
wait for io_clk_period;
end loop;
sdi_write <= '0';
wait;
end process;
--! ===========================================================
--! ===========================================================
--! =================== DATA VERIFICATION =====================
tb_verifydata : process
variable line_no : integer := 0;
variable line_data : line;
variable logMsg : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable read_result2 : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
variable word_count : integer := 1;
variable message_count : integer := 0;
variable word_pass : integer := 1;
variable instr : boolean := False;
variable next_instr : boolean := False;
variable force_exit : boolean := False;
variable msgid : integer;
variable keyid : integer ;
variable isEncrypt : boolean := False;
variable opcode : std_logic_vector(3 downto 0);
begin
wait for 6*clk_period;
while (not endfile (do_file) and valid_line and (not force_exit)) loop
--! Keep reading new line until a valid line is found
hread( line_data, word_block, read_result );
while ((read_result = False or valid_line = False or next_instr = True)
and (not endfile(do_file)))
loop
readline(do_file, line_data);
line_no := line_no + 1;
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_ins
or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
word_count := 1;
if (temp_read = cons_ins) then
instr := True;
next_instr := False;
end if;
else
valid_line := False;
end if;
if (temp_read = cons_eof) then
force_exit := True;
end if;
hread(line_data, word_block, read_result); --! read data
if (instr = True) then
instr := False;
msgid := to_integer(unsigned(word_block(G_PWIDTH- 0-1 downto G_PWIDTH- 8)));
keyid := to_integer(unsigned(word_block(G_PWIDTH-16-1 downto G_PWIDTH-24)));
opcode := word_block(G_PWIDTH-12-1 downto G_PWIDTH-16);
isEncrypt := False;
if ((opcode = OP_AE_DEC or opcode = OP_DEC)
or (opcode = OP_AE_PASS or opcode = OP_AE_FAIL))
then
write(logMsg, string'("[Log] == Verifying msg ID #") & integer'image(msgid)
& string'(" with key ID #") & integer'image(keyid));
if (opcode = OP_AE_DEC or opcode = OP_DEC) then
isEncrypt := True;
write(logMsg, string'(" for ENC"));
else
write(logMsg, string'(" for DEC"));
end if;
writeline(log_file,logMsg);
end if;
report "---------Started verifying message number "
& integer'image(msgid) & " at " & time'image(now) severity error;
end if;
end loop;
--! if the core is slow in outputting the digested message, wait ...
if ( valid_line ) then
do_read <= '1';
if ( do_empty = '1') then
do_read <= '0';
wait until do_empty = '0';
wait for io_clk_period/2;
do_read <= '1';
end if;
wait for io_clk_period; -- wait a cycle for data to come out
word_pass := 1;
for i in G_PWIDTH-1 downto 0 loop
if do_ext(i) /= word_block(i) and word_block(i) /= 'X' then
word_pass := 0;
end if;
end loop;
if word_pass = 0 then
simulation_fails <= '1';
write(logMsg, string'("[Log] Msg ID #") & integer'image(msgid)
& string'(" fails at line #") & integer'image(line_no)
& string'(" word #") & integer'image(word_count));
writeline(log_file,logMsg);
write(logMsg, string'("[Log] Expected: ") & to_hstring(word_block)
& string'(" Received: ") & to_hstring(do_ext));
writeline(log_file,logMsg);
--! Stop the simulation right away when an error is detected
report "---------Data line #" & integer'image(line_no)
& " Word #" & integer'image(word_count)
& " at " & time'image(now) & " FAILS T_T --------" severity error;
report "Expected: " & to_hstring(word_block)
& " Actual: " & to_hstring(do_ext) severity error;
write(result_file, "fail");
if (G_STOP_AT_FAULT = True) then
force_exit := True;
else
if isEncrypt = False then
next_instr := True;
report "---------Skip to a next instruction"
& " at " & time'image(now) severity error;
write(logMsg, string'("[Log] ...skips to next message ID"));
writeline(log_file, logMsg);
end if;
end if;
end if;
word_count := word_count + 1;
end if;
end loop;
do_read <= '0';
wait for io_clk_period;
if (simulation_fails = '1') then
report "FAIL (1): SIMULATION FINISHED || Input/Output files :: T_T"
& G_FNAME_PDI & "/" & G_FNAME_SDI & "/" & G_FNAME_DO severity error;
write(result_file, "1");
else
report "PASS (0): SIMULATION FINISHED || Input/Output files :: ^0^"
& G_FNAME_PDI & "/" & G_FNAME_SDI & "/" & G_FNAME_DO severity error;
write(result_file, "0");
end if;
write(logMsg, string'("[Log] Done"));
writeline(log_file,logMsg);
stop_clock <= True;
wait;
end process;
--! ===========================================================
--! ===========================================================
--! =================== Test MODE =====================
genInputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
wait until rising_edge( pdi_ready );
wait for io_clk_period;
stall_pdi_empty <= '1';
stall_sdi_empty <= '1';
wait for io_clk_period*G_TEST_ISTALL;
stall_pdi_empty <= '0';
stall_sdi_empty <= '0';
else
wait;
end if;
end process;
genOutputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
wait until rising_edge( do_valid );
wait for io_clk_period;
stall_do_full <= '1';
wait for io_clk_period*G_TEST_OSTALL;
stall_do_full <= '0';
else
wait;
end if;
end process;
end;
| gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/aux_fifo.vhd | 9 | 6213 | -------------------------------------------------------------------------------
--! @file aux_fifo.vhd
--! @brief Auxiliary FIFO. A custom FIFO used for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aux_fifo is
generic (
G_W : integer := 32;
G_LOG2DEPTH : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
fifo_din : in std_logic_vector(G_W-1 downto 0);
fifo_dout : out std_logic_vector(G_W-1 downto 0);
fifo_ctrl_in : in std_logic_vector(3 downto 0);
fifo_ctrl_out : out std_logic_vector(2 downto 0)
);
end entity aux_fifo;
architecture structure of aux_fifo is
signal readpointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal save_writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal bytecounter : std_logic_vector(G_LOG2DEPTH downto 0);
signal last_bytecounter : std_logic_vector(G_LOG2DEPTH downto 0); --! Byte counter of unread data
signal last_bytecounter_in : std_logic_vector(G_LOG2DEPTH downto 0); --! Byte counter of unread data
signal fifo_save_state : std_logic;
signal fifo_restore_state : std_logic;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
signal fifo_unread_avail : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
type t_mem is array (0 to 2**G_LOG2DEPTH-1) of std_logic_vector(G_W-1 downto 0);
signal memory : t_mem;
begin
fifo_ctrl_out <= fifo_full & fifo_empty & fifo_unread_avail;
fifo_save_state <= fifo_ctrl_in (0);
fifo_restore_state <= fifo_ctrl_in (1);
fifo_write <= fifo_ctrl_in (2);
fifo_read <= fifo_ctrl_in (3);
uDPRAM:
process(clk)
begin
if (rising_edge(clk)) then
if (fifo_write = '1') then
memory(to_integer(unsigned(writepointer))) <= fifo_din;
end if;
if (fifo_read = '1') then
fifo_dout <= memory(to_integer(unsigned(readpointer)));
end if;
end if;
end process;
p_fifo_ptr:
process(clk)
begin
if rising_edge( clk ) then
if rst = '1' then
readpointer <= (others => '0');
writepointer <= (others => '0');
bytecounter <= (others => '0'); --differences (write pointer - read pointer)
save_writepointer <= (others => '0');
else
if (fifo_save_state = '1') then
save_writepointer <= std_logic_vector(unsigned(readpointer) + unsigned(bytecounter(G_LOG2DEPTH-1 downto 0)));
last_bytecounter <= bytecounter;
end if;
if (fifo_write = '1' and fifo_read = '1') then
writepointer <= std_logic_vector(unsigned(writepointer) + 1);
readpointer <= std_logic_vector(unsigned(readpointer) + 1);
if (unsigned(last_bytecounter) /= 0) then
last_bytecounter <= std_logic_vector(unsigned(last_bytecounter_in) - 1);
end if;
elsif (fifo_write = '1' and fifo_read = '0') then
writepointer <= std_logic_vector(unsigned(writepointer) + 1);
bytecounter <= std_logic_vector(unsigned(bytecounter) + 1);
elsif (fifo_write = '0' and fifo_read = '1') then
readpointer <= std_logic_vector(unsigned(readpointer) + 1);
if (fifo_restore_state = '1') then
writepointer <= save_writepointer;
bytecounter <= '0' & std_logic_vector(unsigned(save_writepointer) - (unsigned(readpointer) - 1));
else
bytecounter <= std_logic_vector(unsigned(bytecounter) - 1);
end if;
if (unsigned(last_bytecounter) /= 0) then
last_bytecounter <= std_logic_vector(unsigned(last_bytecounter_in) - 1);
end if;
elsif (fifo_restore_state = '1') then
writepointer <= save_writepointer;
bytecounter <= '0' & std_logic_vector(unsigned(save_writepointer) - unsigned(readpointer));
end if;
end if;
end if;
end process;
last_bytecounter_in <= bytecounter when fifo_save_state = '1' else last_bytecounter;
fifo_unread_avail <= '1' when unsigned(last_bytecounter) > 0 else '0';
-- fifo_empty <= '1' when (unsigned(bytecounter) = 0 or (fifo_read = '1' and unsigned(bytecounter) = 1)) else '0';
fifo_empty <= '1' when (unsigned(bytecounter) = 0) else '0';
fifo_full <= '1' when (unsigned(bytecounter) >= 2**G_LOG2DEPTH-1) else '0';
end structure; | gpl-3.0 |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/Kernel/FullDiffLayer.vhd | 1 | 1363 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
Diff1In : in std_logic_vector(63 downto 0);
Diff2In : in std_logic_vector(63 downto 0);
Diff3In : in std_logic_vector(63 downto 0);
DiffOut : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
DiffOut <= Diff1In xor Diff2In xor Diff3In;
end architecture structural;
| gpl-3.0 |
db-electronics/FMPBC | PBCFM.vhd | 1 | 8898 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2014 - 2017 René Richard
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity PBCFM is
generic(
-- 0 = no init code, fm always enabled
-- 1 = regular PBC init code, fm always enabled
-- 2 = db PBC init code, fm can be disabled by holding up during boot
mode_g : integer := 1;
-- amount of time to wait to enable sound output
senCount_g : integer := 256
);
port (
--Z80 control signals (from md obviously)
CLK_p : in std_logic;
nRST_p : in std_logic;
nWR_p : in std_logic;
nRD_p : in std_logic;
nIORQ_p : in std_logic;
nCRTOE_p : in std_logic;
nCART_p : out std_logic;
nRSTG_p : out std_logic;
nRSTS_p : out std_logic;
--non z80 signals
HSCLK_p : in std_logic;
FMEN_p : in std_logic;
--YM2413 control signals
SEN_p : out std_logic;
nYMCS_p : out std_logic;
nYMIC_p : out std_logic;
--address and databus
ADDR_p : in std_logic_vector(7 downto 0);
DATA_p : inout std_logic_vector(7 downto 0)
);
end entity;
architecture PBCFM_a of PBCFM is
--ym2413 signals
signal nkbsel_s : std_logic;
signal nfmcs_s : std_logic;
signal nbitcs_s : std_logic;
--detect bit for Z80 software
signal bitq_s : std_logic;
--internal ym2413 enable signal, disabled by db boot code if up is held on power up
signal enym_s : std_logic;
--internal signal to detect when the boot code disables the ym2413
signal disableym_s : std_logic;
--internal databus signals
signal datain_s : std_logic_vector(7 downto 0);
signal dataout_s : std_logic_vector(7 downto 0);
--signal which enables the stack code to be driven onto the databus
signal doBoot_s : std_logic;
--signal which resets the doBoot flipflop
signal rstStack_s : std_logic;
signal endStack_s : std_logic;
-- Power Base Converter stack init code
-- source http://www.smspower.org/forums/viewtopic.php?t=14084
--21 01 E1 : LD HL, $E101
--25 -- -- : DEC H
--F9 -- -- : LD SP,HL
--C7 -- -- : RST $00
--01 01 -- : LD BC, $xx01
-- Array containing boot ROM of orignal PBC
type PBCROM_t is array (0 to 7) of std_logic_vector(7 downto 0);
constant PCBBootROM : PBCROM_t :=
(x"21",x"01",x"e1",x"25",x"f9",x"c7",x"01",x"01");
-- Array containing ROM of db PBCFM init code
--;*************************************************************
--; Boot section
--;*************************************************************
-- ld sp, $e001 ; setup stack pointer to point to DFFF after reset
-- ld b, $00 ; clear b as iteration counter = 256
---: in a,(IOPortA) ; read joypad
-- bit 0,a ; check if up is pressed
-- jr nz,+ ; if 1, reset and leave FM sound enabled
-- djnz - ; must read 256 times as 0 to disable FM sound
-- nop ; nop, hardware will disable the FM chip if this opcode is read
--+: rst $00 ; reset, nWR signal will disable this small BIOS and enable the game to boot
type dbROM_t is array (0 to 15) of std_logic_vector(7 downto 0);
constant dbBootROM : dbROM_t :=
(x"31",x"01",x"e0",x"06",x"00",x"db",x"dc",x"cb",
x"4f",x"20",x"03",x"10",x"f8",x"00",x"c7",x"00");
-- type dbROM_t is array (0 to 24) of std_logic_vector(7 downto 0);
-- constant dbBootROM : dbROM_t :=
-- (x"f3",x"3e",x"f5",x"d3",x"3f",x"06",x"00",x"e3",
-- x"10",x"fd",x"31",x"01",x"e0",x"06",x"00",x"db",
-- x"dc",x"cb",x"47",x"20",x"03",x"10",x"f8",x"00",
-- x"c7");
--*************************************************************
--LOGIC BEGINS HERE
--*************************************************************
begin
--output to databus
--dataout_s driven by process in PBC Stack Init section
DATA_p <= dataout_s when doBoot_s = '1' and nRD_p = '0' and nCRTOE_p = '0' else --PBC bios code
"ZZZZZ" & "00" & bitq_s when (nbitcs_s = '0' and nRD_p = '0') else --FM detect bit
(others=>'Z');
--read in databus
datain_s <= DATA_p;
--reset signal from reset generator into HRST of Genesis
nRSTG_p <= nRST_p;
nRSTS_p <= nRST_p;
--*************** YM2413 SECTION ***************
--YM2413 signals
nYMIC_p <= nRST_p;
nYMCS_p <= nfmcs_s when nRST_p = '1' else '1';
--generate kbsel internally as it does not exist on MD
nkbsel_s <= '0' when nIORQ_p = '0' and
ADDR_p(7 downto 6)="11"
else '1';
--FM chip at address F0 and F1
nfmcs_s <= '0' when ADDR_p(2 downto 1)="00" and
nkbsel_s = '0' and
nWR_p = '0' and
enym_s = '1'
else '1';
--FM detect bit at address F2
--read bit cs generation
nbitcs_s <= '0' when ADDR_p(2 downto 1)="01" and
nkbsel_s = '0' and
enym_s = '1'
else '1';
-- Instantiate DFF for detect bit
fmcheckFF : DFF
port map (
d => datain_s(0),
clk => nbitcs_s or nWR_p, -- bnand for clarity
clrn => nRST_p,
prn => '1',
q => bitq_s
);
-- internal ym2413 enable signal, on by default, off when boot code disables it
-- by reading the NOP at address 0x0D of the db boot code
-- this only matters for mode_g = 2
disableym_s <= '1' when doBoot_s = '1' and
nCRTOE_p = '0' and
ADDR_p = x"0d"
else '0';
-- sample the pause button (FMEN_p) during reset, hold afterwards
process( nRST_p, FMEN_p)
begin
if nRST_p = '0' then
enym_s <= FMEN_p; -- on by default
else
enym_s <= enym_s;
end if;
end process;
-- after senCount_g amount of nIORQ_p's, enable sound output, not deterministic
-- but is the longest wait time possible with the least amount of macrocells used
process( nRST_p, doBoot_s, nIORQ_p, enym_s)
variable senCount_v : integer range 0 to senCount_g;
begin
if nRST_p = '0' then
SEN_p <= '0';
senCount_v := 0;
elsif doBoot_s = '1' or enym_s = '0' then
SEN_p <= '0';
elsif (rising_edge(nIORQ_p)) then
senCount_v := senCount_v + 1;
if senCount_v = senCount_g then
SEN_p <= '1';
end if;
end if;
end process;
--*************** PBC Stack Init Section ***************
--Cart output enable, don't gate the CRTOE_p if mode_g = 0
nCART_p <= nCRTOE_p when doBoot_s = '0' or mode_g = 0 else '1';
--DFF to determine when to drive stack code onto bus
--enables the doBoot_s at reset, stops it at the first nWR during stack write mode 1
--or after encountering RST opcode in mode 2
process( nRST_p, rstStack_s, doBoot_s)
begin
if nRST_p = '0' then
doBoot_s <= '1';
elsif rstStack_s = '1' then
doBoot_s <= '0';
else
doBoot_s <= doBoot_s;
end if;
end process;
--reset the doBoot flipflop
--original PBC resets on nWR_p during RST instruction
process( nRST_p, nWR_p, nCRTOE_p, endStack_s )
begin
if nRST_p = '0' then
rstStack_s <= '0';
else
case mode_g is
when 0 =>
rstStack_s <= not(nWR_p);
when 1 =>
rstStack_s <= not(nWR_p);
when 2 =>
rstStack_s <= endStack_s;
when others =>
rstStack_s <= '0';
end case;
end if;
end process;
--endStack_s only matters in mode_g = 2
process( nRST_p, nCRTOE_p, ADDR_p)
begin
if nRST_p = '0' then
endStack_s <= '0';
elsif (rising_edge(nCRTOE_p)) then
if ADDR_p = x"0e" then --read the reset instruction in BIOS
endStack_s <= '1';
end if;
end if;
end process;
--drive stack code (depends on mode_g)
process( nRST_p, ADDR_p, nRD_p, nCRTOE_p, doBoot_s)
begin
if nRST_p = '0' then
dataout_s <= (others=>'Z');
elsif doBoot_s = '1' then
if nRD_p = '0' and nCRTOE_p = '0' then
case mode_g is
when 0 =>
dataout_s <= (others=>'Z');
when 1 =>
dataout_s <= PCBBootROM(to_integer(unsigned(ADDR_p(2 downto 0))));
when 2 =>
dataout_s <= dbBootROM(to_integer(unsigned(ADDR_p(3 downto 0))));
when others =>
dataout_s <= (others=>'Z');
end case;
else
dataout_s <= (others=>'Z');
end if;
else
dataout_s <= (others=>'Z');
end if;
end process;
end PBCFM_a;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.vhdl | 1 | 202365 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.vhdl
-- Design : bg_mid
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 4 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_bindec : entity is "bindec";
end bg_mid_bindec;
architecture STRUCTURE of bg_mid_bindec is
begin
ENOUT: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\ENOUT__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(1)
);
\ENOUT__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(1),
I2 => addra(2),
O => ena_array(2)
);
\ENOUT__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => addra(2),
O => ena_array(3)
);
\ENOUT__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(2),
I2 => addra(1),
O => ena_array(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_mid_blk_mem_gen_mux;
architecture STRUCTURE of bg_mid_blk_mem_gen_mux is
signal \douta[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0),
O => douta(0)
);
\douta[10]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[10]_INST_0_i_1_n_0\,
I1 => \douta[10]_INST_0_i_2_n_0\,
O => douta(10),
S => sel_pipe_d1(2)
);
\douta[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6),
O => \douta[10]_INST_0_i_1_n_0\
);
\douta[10]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(6),
I2 => sel_pipe_d1(1),
O => \douta[10]_INST_0_i_2_n_0\
);
\douta[11]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[11]_INST_0_i_1_n_0\,
I1 => \douta[11]_INST_0_i_2_n_0\,
O => douta(11),
S => sel_pipe_d1(2)
);
\douta[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7),
O => \douta[11]_INST_0_i_1_n_0\
);
\douta[11]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(7),
I2 => sel_pipe_d1(1),
O => \douta[11]_INST_0_i_2_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => \douta[4]_INST_0_i_2_n_0\,
O => douta(4),
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(0),
I2 => sel_pipe_d1(1),
O => \douta[4]_INST_0_i_2_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => \douta[5]_INST_0_i_2_n_0\,
O => douta(5),
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(1),
I2 => sel_pipe_d1(1),
O => \douta[5]_INST_0_i_2_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => \douta[6]_INST_0_i_2_n_0\,
O => douta(6),
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(2),
I2 => sel_pipe_d1(1),
O => \douta[6]_INST_0_i_2_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => \douta[7]_INST_0_i_2_n_0\,
O => douta(7),
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(3),
I2 => sel_pipe_d1(1),
O => \douta[7]_INST_0_i_2_n_0\
);
\douta[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_1_n_0\,
I1 => \douta[8]_INST_0_i_2_n_0\,
O => douta(8),
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4),
O => \douta[8]_INST_0_i_1_n_0\
);
\douta[8]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(4),
I2 => sel_pipe_d1(1),
O => \douta[8]_INST_0_i_2_n_0\
);
\douta[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_1_n_0\,
I1 => \douta[9]_INST_0_i_2_n_0\,
O => douta(9),
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5),
O => \douta[9]_INST_0_i_1_n_0\
);
\douta[9]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(5),
I2 => sel_pipe_d1(1),
O => \douta[9]_INST_0_i_2_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_wrapper_init is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_mid_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF43FFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF73FFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF43FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"EFFEFFE63EFFEFFEFFEFFEFFFFFFFFFFFDFFDFFDFFDFFDFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FF7FF7FF7FF7FF7FF7FF7FFFFFFFFFF",
INIT_08 => X"FEFFEFFEFFEFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_09 => X"BFFBFFBFFBFFBFFBFFFFFFFF7FF7FF7FF7FF7FF27F7FF7FFFFFFFFFFEFFEFFEF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF96FFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFBFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFDFFFFFB7FFFFFFFFFFFFFFDFFFFFFF7FFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFEFFFFFFFFFFFFFFFFF7FBFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFF",
INIT_13 => X"FFFFFFDFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFF97FFBFEFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFF97FF7FFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFF737EFFF7FFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFBFFFFDF",
INIT_17 => X"FFFFF7FFFFFFFFFFFFFFFFFFFFFDFFFFF7FFFFFFFFFFFFFFFFFFFFEA7FFFFFFF",
INIT_18 => X"FFFBFFFFFF7FFFFFFDFFFBFDBFFFFFFBFF7FFFFB7FFFFFFFFFFFFFFFFFFFFFF7",
INIT_19 => X"FFFFFEFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFEF7F",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF7FBFFFDFFFFFFF7FFFFFFFFFDFFBFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FF7FBF7FFFFF7FFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFEDBD7F",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFF7FDFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFB7FFFFFFFFFFFEEFFFFFFDFFFFBFFDFFF7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFEFF7FFFFEEFFFFFFFFFFFFBFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFBFFFD",
INIT_23 => X"FFFFFFFFBFFFFFFFFFFFFFFA7FFFFFFFFFFFFFBFFF5F8FDBFFFFFFDFFFFFBFFF",
INIT_24 => X"FFFFFFF97FDFFFFFFFFEFFFFFDFEFFFFFFFFBDFFFFFFFFBFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFBFEBFFFFFFBFEFFBF7FFDFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FEFF7FFDFBEEFFFFFFFFFFFBFFFFFFFFFFFFFFFBFFFF9FFFFFFFFFFB7FFFF7FF",
INIT_27 => X"BBFFFFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFDFA7FFFFEFFFFDFDF7FFFF6FFFE",
INIT_28 => X"FFFFFFEFFFFFFFFFFFFFFEFA6FF7DFFFFFFFFD7BBEEFFFFFFFFEFFFFFEFFFFFF",
INIT_29 => X"FFFFFFFB5FEFFFDF7FFFFFFFEFFF5BDFFFFFDFFFFFFFFFFFFFFFFFFFFFFEFFFF",
INIT_2A => X"FDFFFFFEFB7FFFFDFFFE7FFFFFFFFF7FBEFFFFFFF7FFFDFFFFFFFFFFFFFFFEFF",
INIT_2B => X"FFFFFFFFEFFFB7FFFFFBFFFD7DEFFFFFFFFFFFFFFFFFFFDFFFFBFFD97FFFFEFF",
INIT_2C => X"FFFFFFFFFEFFEFFFFFFFFFFFFFFFF7FEFFBFDFFA3FFFFFFFFF3F7FFFFEFFFF7F",
INIT_2D => X"FFFFFFFFFFFBADFFEFDFFF7B7FFFFFFDFFFFFFFFFFFFFFFFFFFD3FFFE3FFFFFF",
INIT_2E => X"FFFF7FFA7FBB767BFFBFFFFFFFEEFFEFFDBFFFFFFFFDFFFFFFFFFFFFDFFFFFFD",
INIT_2F => X"BB7FFFFFFFF74FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBDDCCFED",
INIT_30 => X"FEFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFAF77772BF63BFFFDDB7FD16AAD",
INIT_31 => X"FFFFFFFFFFFFFFFEFFBFD2AEBF72F15AFCEED7EA7DE8DFC8B5B76FFFFEFDFFDF",
INIT_32 => X"FFDFADBBFFFF5758AFBF74495DBFD6F3D98FFD6FFFFFABFBFFFFFFFFFFFFFFFF",
INIT_33 => X"DCE6FFF27B42F9AFEB69632F3FFDFFEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"7CEF6EA4DFFF5FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFEFFFFFADBF56D3CFC7B",
INIT_35 => X"7FFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFFFF7AD6FFEFFFE7FE7BF697969FA4FF1",
INIT_36 => X"FFFFFFFFFFFFFFFFFFD91DFB43FD6C69AAFD9FD35DE4F3AEA13F9B4F88BBFDFF",
INIT_37 => X"F6FDFFFEBCECB2FAEAFEBEF33DD4F49EF953DD4F6D6FFFFFFFFFFFFFFFFFDFFF",
INIT_38 => X"9963EB3A12236E9B4AFB2236684FFFFFFDFFFFFFFBFFFDFFFFFFFFFFFFFFFFFF",
INIT_39 => X"B7EAEFBD55BBFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFDAF466DB3ECDE4EF7",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CECFBBEE1B7D6DD776DD6EFB4EFBDCB5",
INIT_3B => X"FFEFFFBFFFBF7B7FBA66DD59F19AB2765FF6F70128DCD396FC648DCDA7133FFF",
INIT_3C => X"7E5D965F7FFA25A6197CAEB90EEF9E97A6AEEEF9F7A6C2FBFDFFFFFFFFFFFFFF",
INIT_3D => X"AFA95F635D77303C3BB5D773B85CD1FFF7FFFFFFFFFFEFFFFFFFEFBBDBFA7FAE",
INIT_3E => X"54D2319F77BB4F3FFFFFFFFFFFFFFDFFFFEC979E64D7479133B3C9DDDB45E1CE",
INIT_3F => X"FFFFFFFFFFFFF7FFFFEFFC63AB6D9BDBEB7FADBACEF6FBA57876544A6319F7F3",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[0]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5055500505505545404455350500450054605055750555065070030075033055",
INIT_01 => X"0550755570304057505550745555407900554044553505004500542505045434",
INIT_02 => X"4507553053055075070745564540775405550477050733505300064356657072",
INIT_03 => X"5FF9575756550555565755555305505555055553705545505740035000705504",
INIT_04 => X"605555559775597F95F57F5F77B759777D79FF977F7F5777FB77FF95F5F95757",
INIT_05 => X"0055057035500555035705555073550555507007000707455005737075050750",
INIT_06 => X"0540320545557053705005070577007900550357055550735505055555055035",
INIT_07 => X"7037555353505555050005447073475555350534505550705405055745000555",
INIT_08 => X"7977550503575550575453320234000746504505507037755430545050055437",
INIT_09 => X"53020555579F5F977957F777F797DFF57777977F9797F9B77779777F597F7F7F",
INIT_0A => X"4505305070453403753040050057405440505535775573453570003050750565",
INIT_0B => X"9053555300500007005570523503306904537530400500574054300054403703",
INIT_0C => X"5550555050755600545553444455500750455555055005370005505507577555",
INIT_0D => X"7755754777070755577005055535555305055575557505543350670575553444",
INIT_0E => X"0070030735557559D7F775F779F399955F59BDF757F7F99BF77F7F77BF579797",
INIT_0F => X"5534555355050505405053545755455050452050300705000007055705003705",
INIT_10 => X"5000500075555550544505555370507805354050535457554550005425505475",
INIT_11 => X"7755075735002550370555554575457074556055770775507500555055030075",
INIT_12 => X"5504557550457547550455534050555055540700575755672523570300505554",
INIT_13 => X"55275033500535555579595FF5797FF777795775F77F79F77F95F77F57B7D7D7",
INIT_14 => X"0500730355350030505500003005055903005557057055055704555003555070",
INIT_15 => X"5500547547055340355700005005008900505055000030050559035300070555",
INIT_16 => X"3056553075500073350530006435660554405570705070755790535004755505",
INIT_17 => X"5775755055667050567503504750507556506755505055575053053350540006",
INIT_18 => X"055005030500300005353572597537F79F57FF95B77F95F7F577FF79977F5F5F",
INIT_19 => X"5307500555305043050050570505550504035352505053523573353003007550",
INIT_1A => X"0457507503003375035500455430709807730500505705055505545550703050",
INIT_1B => X"7540737063507555070540505574500570057705704055000720500005705707",
INIT_1C => X"7405554505007055047046300075057505075065767755750575555050550555",
INIT_1D => X"53004030505005355050050335755557557755F5979577399F959775BF959597",
INIT_1E => X"7570550300000550757077005300300355000555300705370435030545320303",
INIT_1F => X"0535350353450400735000505070007903307570770053003003053507350707",
INIT_20 => X"0343044070505050555505550405507507503050057750030535073030740303",
INIT_21 => X"0555070550453003053507303074030305353503534504007350005305353503",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => \douta[3]\(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB5C95D6EF67D27EDDC4FA4FA4FB6BB6BB6B92B92B9BBDBBDBB49F49F49",
INIT_01 => X"FEDF9AFB3FDBFDBF59F59F59F7DF7DF75F35F35FB7FB7FB7F6EF6EF67D27D27D",
INIT_02 => X"7D57D57DC79C79C78E78E78EFAAFAAFACD7CD7CDFEDFEDFECFACFACFBEFAD7CD",
INIT_03 => X"6FF6FF6F76F76F769E39E39EABEABEABEABEABEA3CE3E39EABEB3C74157D57D5",
INIT_04 => X"FDBFDBFDBDDBDDBDDBDDBDDBDFFDDBFDBDDBFB7737BB7BB7BB7BB7BBFBFFBFFB",
INIT_05 => X"67D67D6756356356B76B76B42B3EB3EBACFACFAC6AC6AC6AD6ED6ED67D67D67D",
INIT_06 => X"A76A76A638778778E5CE5CE54E54E54ED4ED4ED4EF0EF0EFBB5BB5BB59F59F59",
INIT_07 => X"EF7EF7EFFEBFEBFEAFEAFEAFFAFFAFFA3B53B53BC3BC3BC32E72E72E72A72A72",
INIT_08 => X"D67D67D6FF6FF6FFFABFABFABFEBFEBF7BF7BF7BF5FF5FF57F57F57A57FD7FD7",
INIT_09 => X"9F59F59FDBFDBFDBEFBEFBEF3EB3EB3EB3EB3EB27B7FB7FB7DF7DF7D67D67D67",
INIT_0A => X"75C75C75D71D71D79D79D79A6B9EB9EB8EB8EB8E3AE3AE3AF3AF3AF33D73D73D",
INIT_0B => X"9D79D79A6BDEBDEBCEBCEBCE3EE3EE3EF3AF3AF3BD7BD7BDEBCEBCEB5CF5CF5C",
INIT_0C => X"FFF7F5FB9EB7CFE4AFD7E927BE2D4C4AEBCEBCEB5EF5EF5E75E75E75F71F71F7",
INIT_0D => X"54FBB6EFC7F761CDFF3EFFBDFFDBFF0FD8FCCD9DFAE9DFC77F5657F865DB2BDD",
INIT_0E => X"F9ED77F3FFD766BFBEAE47EF9EF69A3E9B6FFF727E7DD253FFC76DD2BFAEFDA9",
INIT_0F => X"E6DB6B78F6F3B9AFFFFDEBEA7EFD8F9A6EFDFF7DFDDF7DE48E7D67FB48A4CF4F",
INIT_10 => X"AFD743F27D6FEFE7775C69F3BFEEFABF696B7A2FA881A4DEDFB7FFEBDF7FDFF7",
INIT_11 => X"FFEEFFF0F67BE31EFD651CBFF57ED6D5F6F4CB2D7EE3F5F7DBDE3BD2EAF9CDDE",
INIT_12 => X"1C6F5DD7E8FF3D5F3F1774FDCEBF8F4D677E6B71FF55FFFFC57FCF9A73F577CD",
INIT_13 => X"F55DB2FEE35D63F791D2FEFFDFDEF7F7FFFBFFFA7ED1DF37FFF9FF84CEF5FFFD",
INIT_14 => X"AAD9B6FBFFF7B4E3EE31E7F077F7FFCF7F2EFE7F51DAF535F6F3AFEFADFB8BF0",
INIT_15 => X"5FFEBD326ABD361BDB8DCEBC06732D1D9FB3FBF7A9FF21F66EEF3BEBDDFF67FE",
INIT_16 => X"F508FC3A09E1D6FAFE667297F7FFAD3A87D9DCF7B57ADCEEFFFA7D5FFBEF664F",
INIT_17 => X"89D4E74FFBECC10AFF2FFFEDB7BCAFFD735D37FFFEE5FDB79FFB67E87CBEA9DF",
INIT_18 => X"FF9A7FEFED7F67FF5DFDE371BFBFD6D9FF2FFFF2217FF853FE530005357AFEB7",
INIT_19 => X"FBDEAEE070A4BA07DFF1DD42257FB40517E9118293DC3FE5C59883FFCE5CC1EF",
INIT_1A => X"F4A6FAB236FFD54035F5DAD73877778E8EEBD8FFFC903EECFFFAFFFDBD697FFF",
INIT_1B => X"0F9781D280FAA177319C7DDAFF97475FFFFF6DF1FF07FFFFFFBBFD1E3F4AC87D",
INIT_1C => X"AC4ABA69E4D519FF9FFFEFDBD39FFFFFFE9FF8FF37DF4C7FDFFDEFE2697FEA59",
INIT_1D => X"1FFF6FF7FDFFFFFFFFFFFFFF0ED3A05EFFDBE9A8183FE236E7FFF1E3C2E8343E",
INIT_1E => X"FEDDDEEC01836377FFDEBF500C9C166CA2DFDBE0177CF4217C2AFD96D8E2CBFA",
INIT_1F => X"976BE81A3AFE89FF67DFEEF05FC7DBFF13F7DB47041005DF1FFFBFFFDFDDFFFF",
INIT_20 => X"E59EFC760EF8E6D85C9FA0E45AC9C6FA5DFF3FFFBF7BFFF07E67AB778CDF1DE6",
INIT_21 => X"B2F1CF8889BEEC6F24FFC7FB8DAFFFE650399EA530E2E5FE19A86B620C3B2FFF",
INIT_22 => X"087F65BD777F7FF4FE9A7D84E7FF8F77332ECFDA42FED7561FFF79DF9F5BF78C",
INIT_23 => X"EDA4D1B1B39FEF3B5F3B7D3213FE9FD3E6F75FAF7F5F089AADA7BA074FF6B87F",
INIT_24 => X"FD76DFC83D5FFF3B9BDE684E7DBCF5D497609CE91DFFB81F8188759FFC7E04F7",
INIT_25 => X"FF3FABA7F7F386A57B55698F1BBD7BEF70EE97FFFF7578485E751DDDE7E4F856",
INIT_26 => X"CEA875617AA2E6DFFDFD5FFBFBDFD7F1C8EC3679A9FE9F58FFE7F56A19FEF5E6",
INIT_27 => X"2BFEFFEF5FE77E9C973ECBFC4F7F7FA7BE7BFD786F7F7AFBC95DC811FBD6AD18",
INIT_28 => X"29976BEEDFAF5FCC1FFAECFA6FF5D5B4FEE69C3B1EACE17ABF76EDE47E39FAC0",
INIT_29 => X"223F7F4A4FCB5BD77F924B454184118F89C70AFF28F7DF55C57FFF8FFFF6FF6A",
INIT_2A => X"395527AE3853FD9197AA6A939130D26A3EBCDFFFF7FFED7DB6DE7FF9F9FFAAFF",
INIT_2B => X"F68DB15D2EB6A0FF77FB93FD09EE9AFBDD4BFFF27EFF098FFDFB9FD27FD6B27F",
INIT_2C => X"EEEACBBFCAAEEE7F6FBFFFEF9D37A1E8F9BFD1E23FF0070D511755FFCAE7EA3F",
INIT_2D => X"FEFFDFBD5BE7BD7B4F431C724ED35FDC759031FFFFFBB919BF2D2EDD62A7826F",
INIT_2E => X"2CE97FD864420149AF9CB3A7FFAE74AC3D93C78FDEF15BF56EE1D145DE9BE73D",
INIT_2F => X"0037FC7EFFF74A15054399F62F98CA3F52C1413F97DE8D47577FC7FC49922394",
INIT_30 => X"B8979E4FF95F05EFCCB5DDBBCBF5EF6EFBEFB6470F680C6B3870800232DB5A25",
INIT_31 => X"5542EFFDB73DEF96B5B4E04040BF1230CA2D03024CA46C55ADA055F9DCFD259C",
INIT_32 => X"FBDB6DA28E404901046DF00208304000045484449BFF22DB6B67F577DF4FABF5",
INIT_33 => X"34D0E8125200892C2000D9082FFDB15FABAEED3DF19B114F9E27FFD7F7EF7DEF",
INIT_34 => X"448400008FD64D3AED972FAB3F67BEAFCA976BEF5D3DAEBEFAF6420622208A89",
INIT_35 => X"7E35BCFFF219BFBFB17FF2B7BFD8FA36B7D02C8EA14C0D513380003008000844",
INIT_36 => X"2DDFFBEB57EFFCFDEFDD0012206208E08A2C1C423000B198008A920B0A33BC93",
INIT_37 => X"C6CC00420A008AD2020C8E0211102018111111022109D57F03547DF71FFB06DF",
INIT_38 => X"1902A11A1010489A104901041003C5BF148B9FD5F94DA93583A9F7FDFDFBBBDE",
INIT_39 => X"2162A40440B001AA2B3E7BEFD6C7B7CF4ADEEDF8D8FABFD9B9226820073444AA",
INIT_3A => X"2795BE5DEDE74CDFEEFFDBC7E7F1FC8646482A461001010622C548920A404405",
INIT_3B => X"5FE7EFB1915A1245900009005192886E44724002204400022000044000031DD1",
INIT_3C => X"66481158000005A4281802001241960B20872419C1B0CAF52CB796DF5DF67DFF",
INIT_3D => X"420045425906202C0B1190620890011EFF5F62FFEFAD2F5F65E6E09D5D5384A0",
INIT_3E => X"40C0301400A05E0D4FFF7D77F7A5C9FA72C51216280349113296889489202001",
INIT_3F => X"F7FF0BBCFF5F82FFBDC0B4422B7A0050C0682021808601001810100023014303",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[1]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB549556EB679276DD44F24F24FB6BB6BB6A92A92A9BADBADBA49E49E49",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB6EB6EB679279279",
INIT_02 => X"5D55D55DD79D79D78F38F38FBABBABBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"7FF7FF7FF7FF7FF7CE3CE3CEAEEAEEAEEAAEAAEABCEAE3CEAEEB9C7415DD5DD5",
INIT_04 => X"FDFFDFFDFFDFFDFFDFFDFFDFFFFFDFFDFFDFFBF73FFBFFBFFBFFBFFBFFFFFFFF",
INIT_05 => X"4BD4BD4BD6BD6BD63F23F23433BB3BB3A97A97A97AD7AD7A47E47E4776776776",
INIT_06 => X"E76E76E63C77C77CE5CE5CE5CE5CE5CEDCEDCEDCEF8EF8EFF91F91F99DD9DD9D",
INIT_07 => X"DF7DF7DFFFBFFBFFAFBAFBAFBAFBAFBA3B73B73BE3BE3BE32E72E72E72E72E72",
INIT_08 => X"DC7DC7DCEFCEFCEFEEBEEBEEBEEBEEBEFBEFBEFBFDFFDFFD7DD7DD7A57DD7DD7",
INIT_09 => X"1F71F71FF3BF3BF3AF3AF3AF3AF3AF3AE3EE3EE27E77E77E75E75E75E75E75E7",
INIT_0A => X"EDDEDDED5ED5ED5ED7ED7ED27F3FF3FFBDBBDBBDABDABDABDAFDAFDA7FE7FE7F",
INIT_0B => X"9939939A2BDABDAB4AB4AB4A36E36E3673273273B57B57B5BF6BF6BFF9FF9FF9",
INIT_0C => X"FFFBFDBB0FFDCEB6FFF7FBBF3EBF6DDAC9CC9CC95ED5ED5E55A55A55B71B71B7",
INIT_0D => X"5EDD7FEFC3FFF3AFFBA7DFBDF7EBEF0FD8EED1BDEEEBEFCFEF56FFF8677BABDF",
INIT_0E => X"CDED77FBDFDB5EFFBFB767FB1FFE9A3E9BEFEE325EFFF75AAF6729D2FF26BDF9",
INIT_0F => X"EF7B6F7ABEF79DEFDFEFEB9A76FF9FDEAEFCE73DFD7F6DE5CE5DEFC4B775EFDF",
INIT_10 => X"6BD9937A7DEAE96FF7D7FFE7B7F7FBBFF9FFFA105701B5FF5FBEAEEE9FD7FFF9",
INIT_11 => X"7EE9FF1AEE2F765CCD650E000A82DF95F7E4D93D76EBF5F7F9DE92F6C9F9DDD6",
INIT_12 => X"3E6F4CC017003DFFBF5776F5CEBFCF3DB7FF7BEBFF57FF7FD57FEFB23B5577F9",
INIT_13 => X"D5EFFBBCFB656AF791F0F65EFF9BEFB3FEFB7BFA7DD28B1F29FFFFFC5FF4FBDF",
INIT_14 => X"9B7DB3FFDEDFFF76F767F77016F29BCF79FFFFFFF3DAB1B7F7DB9A0052240FFA",
INIT_15 => X"4FBEFC322EC735EAE2F7FFFFFF736D5DBFB02101170121FF0AE5BBCF7F7D624F",
INIT_16 => X"FAF7FFFFFDA5F6FAF464066808000DFA7BDA6DF6FDDA9BFBFEDA6D4FBBFFDBDF",
INIT_17 => X"89F0C4B04400013FFFFFF7FFB7B4FFFEF7593FFEF77FF6FFBEF7FEA877FFCFEF",
INIT_18 => X"FFFA9FEDEF6FFFFFBDF5427D9EF7FBFBFB2DFFFA1FFF67FCEDEDFFFFFE5A7EA5",
INIT_19 => X"FF76FCFFF7FB6FFFFFFFFFFA7BFFDFFFFCDFFF7D7E283F654D100180220C41EF",
INIT_1A => X"3F3FFFFA5FFFEEFFEF6F276AFFAB668E9AABD00084D03AFEFFFFFFFDBDFFFFFF",
INIT_1B => X"FB5AFE7D7F7FA156311C5D80020447DFFFFFFDB1F6BFFFFFFFEEF7FFCDFFFFFB",
INIT_1C => X"846A2A2804D119FFFFFEF2CB927FFFFFFFF80FFFF93BFFFDBFF7FFFA77FFF7B7",
INIT_1D => X"FFFFDDB6FFFFFFFFFFFFFFFEFFFDFFFFCFFFFFF87FFFFDC9FA9FFF1E3D28243E",
INIT_1E => X"FFFF7FFFFF7DFFDFFFFFFFF87F77FFD7FDB786DFEC09B425450B4C9659C2CAF5",
INIT_1F => X"FFFDFFFA774FFEA8D95EEEBFA3D7589E13D41B09040089FFFFFFF5CA7FA7FFFF",
INIT_20 => X"3E745C4BF9A82558CC8220A45AC996FAFFFFDFBFFFDFFFFFF7FFFFDAFFFDEFFF",
INIT_21 => X"92D9CD030022606FFFFFFE5EFFFFFFFBBFFEF7FFFFBF7ABFFFF7FEFA7BE5FF65",
INIT_22 => X"FFFFFFF3ADFFFFFFADF7EF7BB97BFDFFFFFDFB3A3FAF7957F91B83B974129084",
INIT_23 => X"73FFAF7FBBBF7FEFFFFDFFEA6EBBFB88BD9B55BB8057098A08973A164984A27A",
INIT_24 => X"FFFDCAB87E9CEC336CEC6A5FD988F554874094E15E43021F7EFFFB79DFFDFFFE",
INIT_25 => X"A9B2A3B4AE278AA52017498E395D10EF8FBB66FF55DF9FB7AFBAF3B94F446FFF",
INIT_26 => X"CAB975617A0243DABAF3FB7BAFBD7F5E7FB7FFABA1BC9DEFFF7EBFF277739546",
INIT_27 => X"292F6AD65D67EBF7F9D5F6F60F766F7BFFAF95C85BDCEAABBFCD49154094AC98",
INIT_28 => X"DF7B954E5FAF763FFEF8AEF246B6D7B4B6E4BC3306A8E17C8122ED60461940C0",
INIT_29 => X"FFDF6F4A4F6B1BD749B2EB45498401C17EC30AFD28DF8D45117FFEFF49E48ADF",
INIT_2A => X"31212A8A3053D4502B326A934138D26AAAAD2E59F75B7DF3FDBBDFA8F9FBB279",
INIT_2B => X"8889B05C2C2600D51C337D792DE59ABD67BDEE9A2E7F1F974FDA93D27DBFEE3F",
INIT_2C => X"D31FB8F6DAB7637ED27271EFD9A7A4CAFFBFD17A2AF3B1894D14156F8A8D4A2E",
INIT_2D => X"4E3C303D7FFFBDDF43431E724EDF5FDC51AB507FAF12A9184D2D2CC922A782EF",
INIT_2E => X"EDE97FD86FFBF76BAF883385002476EF7513C78DDCE151F095FEBFFB5A8BEF7D",
INIT_2F => X"FB77FC76A2854A50054191F62F980A3FBF3FFFFCEFDE851277EEC7FEFDDFBFFD",
INIT_30 => X"B0979A4B785F056FB36E35AF7CC5EF7E8B2237EFFFFFAFDF33FFFDDA5FCF7BBD",
INIT_31 => X"ABBD6BBDBDBCBE86F53CFFEEFFFFF7FBFFEBDFCA7DEEF7DFBDBF7FFC6619219E",
INIT_32 => X"A9DBED3FFDFF7FD9AFFFA44A5DBFD6F3DDFF7D6C8535229B4B43F477DF6763F5",
INIT_33 => X"7AF757E27B4AF9AFEB7BFAAF2428B05E23AE6D3D7089154F73DABFD7F6EF5DEE",
INIT_34 => X"7CEF6EB4CF064D98CD972FAABF679AAF75F349BDB934A6BE7A7EDBF76F3CF7FA",
INIT_35 => X"2B17B8FFF211B6BA4EDCBEF7BEF9DF3696F7A9EDDF7FFF6FCFBF6B6869FB47E5",
INIT_36 => X"360FED6B57A7BDD9AFDD1DFB6FFF6DE9AAFDDFB27DE5F63EA9BF9B5FEA11BC07",
INIT_37 => X"D6F9FFFEB7ECBAF8EAFEFEF23DD4D59EF947DD4DEC7AD43E63557DFE1DBB06FF",
INIT_38 => X"9B676B6A16272C0B4ABB627278DFC5BF8C8397BDF94D2D35C6BDD3BDBD5B935E",
INIT_39 => X"16AEE3B9D5F3C1AA0B3E7BEF56C787CFD75EADF9D9FEBFFDBF642593EBFE5E7F",
INIT_3A => X"3715DE5DC1A54CDFEEBB5FCFEFF1FD97C9DF9BED1B7D6DD576DD2EFA6E3B9DB5",
INIT_3B => X"DBE7E8BFFFFF7B7E7B66D459FDDAFF7A5FB6F7120A9AD397DE64A9ADA75A7DD1",
INIT_3C => X"7A5D975F7FFA3D76397CAEB81CAF0D9E86AFCAF0F7B60E755CB53ABF5DF64D75",
INIT_3D => X"EFAB5E224571503070E45715B8CDD9FE7B176F6F6929235F67F7EF6FCFE9FFAE",
INIT_3E => X"5416C1CBF73B1D37CFEF3DDFE7A349DA7AEDD5DA6DD6CF9511A7CBCDFB67DFCF",
INIT_3F => X"F7FF6FF6BF4F827F3BEFFA61BBDFBBCBEB1FADBB4EF2FFF5727ED4C86C1CB7F6",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[2]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"021002232042042040440440444444444404404484084084FFFFFFFFFFFFFFFF",
INIT_02 => X"B7BB7BB7BB7BB7BBFBFFBFFB6FF6FF6F01101101021021020220220222221101",
INIT_03 => X"C5CC5CC55E15E15EFFEFFEFFFDBFDBFDBDDBDDBDDBDDFEFFFDBFFFD4BFB7FB7F",
INIT_04 => X"73173173857857856A56A56AC6AD31738578E627B0AF0AF0AD4AD4AD58D58D58",
INIT_05 => X"FDAFDAFD2DD2DD2DD0DD0DD49F4DF4DF5FB5FB5FA5BA5BA5BA1BA1BA9BE9BE9B",
INIT_06 => X"4DB4DB47A6DA6DA6DA2DA2DABFEBFEBF69B69B69B4DB4DB486E86E86FA6FA6FA",
INIT_07 => X"36D36D3651651651F75F75F74D34D34D6DA6DA6D36D36D36D16D16D1FF5FF5FF",
INIT_08 => X"3AA3AA3AB1EB1EB1D7DD7DD74D34D34DB69B69B68B28B28BBAFBAFBB69A69A69",
INIT_09 => X"A8EA8EA87AC7AC7A55E55E5575575575D51D51D10F58F58FCABCABCAAEAAEAAE",
INIT_0A => X"96B96B96A92A92A9BA9BA9B909E09E0972D72D725525525537537537C13C13C1",
INIT_0B => X"67E67E61767F67F6FD6FD6FDEFDEFDEFCCFCCFCCFECFECFED4DD4DD44F04F04F",
INIT_0C => X"21759F6DF0D65D5928DA0D41CF51F22F3F33F33FB3FB3FB3EB7EB7EB7EF7EF7E",
INIT_0D => X"F326D2B8BC240D704E58E86A8D5F11F937D52F4BD71D54BC74BD654B2E957FED",
INIT_0E => X"73BEAB9532B4EFA5E56AFFACA8E575E375DCBBF979FEC8B77E9EFE7BECFBF3A6",
INIT_0F => X"34A5FDAFD54AFBB964D4B5612FFCF1B17BEBFFD66BCADF9AB3A315FFFFCE1125",
INIT_10 => X"BF3E7EB11A1FBFB75DBFFFFBDA2934794EDAEDFFFFFF5ED0A6FBD5D3657D4A16",
INIT_11 => X"CB7FFFFF35FAABE3B3BAF3FFFFFF602A4ADF7796DBD66FAE973B6F9D3FAE6A2F",
INIT_12 => X"F595FF7FFFFFD3C5FDBB996B3554BCCB6E25DC5662FFFFE97AA350D955BFDBCE",
INIT_13 => X"2A3966D7BFDFF5AEFECF2DF5D4FFFFDCA5DD9D6146FFFCF77E9FFFFFEA8F8DAD",
INIT_14 => X"FF975EC4B5FFFFFBAAB91BBB7FFFFFF5DFFFFFFFFDBDDE6E48BFFFFFFFFFF22F",
INIT_15 => X"F8DFFFF97FFFFFFF1FFFFFFFFFDEBFFBC56FFFFFFFFFFED0FFFF6578CAD7FFFF",
INIT_16 => X"DFFFFFFFFFDF4DA53B9FFFFFFFFFFF05FFF5DE9FB36FFFFFFFFFFAF84FFFFFFC",
INIT_17 => X"FFEFFFFFFFFFFECAFFEC99215EDFFFFFFFFFD625AFFFFFF2652FFFFB7FFFFFFF",
INIT_18 => X"FFFF6E7AB9FFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF3FFFFFFFFFFDABDF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFEDDBF3FFFFFFFFFFFF1A",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFDBFFFF7FBFFFFFFFEDC1FFFE44CACBFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF9FFF3E7FFFFFFFA30FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFE",
INIT_1C => X"FFFFFDFFFFFFF74AFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_1D => X"FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFEF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FCA",
INIT_1F => X"FFFFFFF97FFFFFFFFFFFFBFFFFFFEFEFEEFFEEFFFFFFFF2AFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFF7FB7FFFFFFFFF7F85FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"7FFE77FFFFFFFFBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFD7BFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFC7FFF7FFFFF5",
INIT_24 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFDFFFFDFF7B7EFFFFFFEAFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFF7FFFFFFFFF79E7FEFFB0FFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFF",
INIT_26 => X"BFFFAEDFDFFFFF35FFFFFFFFFFFFFFFFFFFFFFFFFEDBFFFFFFFFFFF97FFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFDEFFFFFFFFFFFFB7FFFFFFFFFFFFFEFFFFFFBF7",
INIT_28 => X"FFFFFFFFFAFAFFFFFFFFFFF97FFFFB7FFFFFFFFFFFFFFFFFFFFF7F9FBFEFFF3F",
INIT_29 => X"FFFFFDF97FFFFFEFFFFFFDFFFFFFFFFFFFFDF5AAFFFAFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFDFFDFFFF7FFFFFFFFF6DFFCFBF95FFFFFFFEFFFFFFFFFFFFFFFF8744DFFF",
INIT_2B => X"FFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9ABFFFFFFFFFFF97FFFFFF6",
INIT_2C => X"FFFFFFFFFFFBFFFFFFFFFFFFB758FFFFFFFF7FF97FFFFFFFFFFFFED6FFFFFFFF",
INIT_2D => X"FFFFFFC280000000FDFDF7893120A027AEFFFFD2FFFFFFFFFFFBFB3EDF7E7F9A",
INIT_2E => X"121680231000001050F7CEFFFFFFFFFFFAFEFDF36FDFFFAFFFFFFFFFFFFCFED7",
INIT_2F => X"0008039BFFFFFFEFFFFE6E7DD16FFFD0FFFFFFFFFFF3FEFFFFFFF80000004000",
INIT_30 => X"FF7DF7B6BFF7FBFAFFFFFFF7FFFF39F5FFFFC800000000000000000100000000",
INIT_31 => X"FFFFFEDAFFFB7FFD7FFF00100000000000000021000000000000002FFFFFFFFB",
INIT_32 => X"7FF40000000000000000000100000000000000037FFFFFFEFFFD9BC9AEFDDC7A",
INIT_33 => X"8000000100000000000000001FFFFFEFFCFBD6EAAFF6FFBAFFFFF67CBF5BAB57",
INIT_34 => X"0000000013FFFFE7BB69DAD5DABFEDF0FFFCFF6B47FFFFDBEFC0000000010000",
INIT_35 => X"F7FED72E2DFE5F4FFFEFE5BEEF16ABFFFD800400008000000000000300000010",
INIT_36 => X"FFF11BDFF8FF56E7720000000000000000000001000000000000000001FFF3FE",
INIT_37 => X"20000000000100000000000100000000000000000007FBD5FEFEE32FE655FDD5",
INIT_38 => X"00000001400002200000000002007FFAFBFD7CD25FF6FFCAFF773F7373EEEEE1",
INIT_39 => X"8000080000083E55F7E38431A9397BFA39A7FA8EAE9171100000000000000000",
INIT_3A => X"FCEFB3EABF7EFF20D77DA030100E026000000000000000000000000100800000",
INIT_3B => X"34DC10000000000000000000000000000000000100000000000000000000027F",
INIT_3C => X"00002000000000000000000300000000000000000000000BEB6FD5D0BB5DFFCA",
INIT_3D => X"0000000100000000000000000000000385E99299B6DEFEAA9D68000000000040",
INIT_3E => X"00000000000000007A34D266997EBEB5AF100000000000000000000000000000",
INIT_3F => X"0891922970B17FC5D40000000000000000000000000000000000000300000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[3]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"09880909880909008888000B09880909880909008888000B0988090988090900",
INIT_01 => X"880988008809000B88880988880988008809000B88880988880988008809000B",
INIT_02 => X"8809880B88090988090988098809880B88090988090988098809880B88090988",
INIT_03 => X"8809888809888809000988008809888809888809000988008809888809888809",
INIT_04 => X"09880909008888000B09880909880909008888000B0988090988090900888800",
INIT_05 => X"09008888000B098809098809090088000B88880988880988008809000B880000",
INIT_06 => X"0B88090988090988098809880B8809880988880988008809000B888809888809",
INIT_07 => X"8809888809000988008809888809888809000988008809888809888809000988",
INIT_08 => X"09008888000B09880909880909008888000B09880909880909008888000B0988",
INIT_09 => X"000B88880988880988008809000B88880988880988008809000B888809888809",
INIT_0A => X"8855777755887777077777778855777755887777077777778855777755887777",
INIT_0B => X"5588557707887777555577075588557707887777555577075588557707887777",
INIT_0C => X"0788777755887707778855770788777755887707778855770788777755887707",
INIT_0D => X"5588550777555577778877775588550777555577778877775588550777555577",
INIT_0E => X"0055887777077777778855777755887777077777778855777755887777077777",
INIT_0F => X"777707777777885577775588777707777755557707558855770788777700FFFF",
INIT_10 => X"7755887707778855770788777755885577075588557707887777555577075588",
INIT_11 => X"0777555577778877775588550777555577778877775588550777555577778877",
INIT_12 => X"7777077777778855777755887777077777778855777755887777077777778855",
INIT_13 => X"7777555577075588557707887777555577075588557707887777555577075588",
INIT_14 => X"770B8877000988098809000D770B8877000988098809000D770B887700098809",
INIT_15 => X"000909098877000D090B8888000909098877000D090B8888000909098877000D",
INIT_16 => X"8877090D09778888770909888877090D09778888770909888877090D09778888",
INIT_17 => X"09770B88770009880977090009770B88770009880977090009770B8877000988",
INIT_18 => X"FF000988098809000D770B8877000988098809000D770B887700098809880900",
INIT_19 => X"88098809000D770B88770009880988000D090B88880009090988770010FF7070",
INIT_1A => X"0D09778888770909888877090D09770B8888000909098877000D090B88880009",
INIT_1B => X"88770009880977090009770B88770009880977090009770B8877000988097709",
INIT_1C => X"88098809000D770B8877000988098809000D770B8877000988098809000D770B",
INIT_1D => X"000D090B8888000909098877000D090B8888000909098877000D090B88880009",
INIT_1E => X"5588440009008855077707005588440009008855077707005588440009008855",
INIT_1F => X"0900775507000700888844070900775507000700888844070900775507000700",
INIT_20 => X"0700770088554407000077880700770088554407000077880700770088554407",
INIT_21 => X"8855880700097788550077078855880700097788550077078855880700097788",
INIT_22 => X"FF00008855077707005588440009008855077707005588440009008855077707",
INIT_23 => X"8855077707005588440009008855070700888844070900775507000700FFFFFF",
INIT_24 => X"0088554407000077880700770088558844070900775507000700888844070900",
INIT_25 => X"0700097788550077078855880700097788550077078855880700097788550077",
INIT_26 => X"8855077707005588440009008855077707005588440009008855077707005588",
INIT_27 => X"0700888844070900775507000700888844070900775507000700888844070900",
INIT_28 => X"097777000B7707BB09880005097777000B7707BB09880005097777000B7707BB",
INIT_29 => X"0B7709BB09770005777777090B7709BB09770005777777090B7709BB09770005",
INIT_2A => X"0977880577097709007709070977880577097709007709070977880577097709",
INIT_2B => X"77097709000B0907BB77880077097709000B0907BB77880077097709000B0907",
INIT_2C => X"FF007707BB09880005097777000B7707BB09880005097777000B7707BB098800",
INIT_2D => X"BB09770005777777090B7709BB09770005777777090B7709BB09770000FF7070",
INIT_2E => X"0577097709007709070977880577097709007709070977880577097709007709",
INIT_2F => X"09000B0907BB77880077097709000B0907BB77880077097709000B0907BB7788",
INIT_30 => X"07BB09880005097777000B7707BB09880005097777000B7707BB098800050977",
INIT_31 => X"0005777777090B7709BB09770005777777090B7709BB09770005777777090B77",
INIT_32 => X"887700097700077777090B99887700097700077777090B998877000977000777",
INIT_33 => X"7700997777770B99887700997700997777770B99887700997700997777770B99",
INIT_34 => X"7777099988880099090099077777099988880099090099077777099988880099",
INIT_35 => X"88887799097799077777090B88887799097799077777090B8888779909779907",
INIT_36 => X"FF0000077777090B99887700097700077777090B99887700097700077777090B",
INIT_37 => X"7777770B99887700997700997777770B99887700997700997777770B00FFFFFF",
INIT_38 => X"9988880099090099077777099988880099090099077777099988880099090099",
INIT_39 => X"99097799077777090B88887799097799077777090B8888779909779907777709",
INIT_3A => X"077777090B99887700097700077777090B99887700097700077777090B998877",
INIT_3B => X"0B99887700997700997777770B99887700997700997777770B99887700997700",
INIT_3C => X"770B77778809770977778800770B77778809770977778800770B777788097709",
INIT_3D => X"8809880977008800070B77778809880977008800070B77778809880977008800",
INIT_3E => X"7700770007777777770988777700770007777777770988777700770007777777",
INIT_3F => X"07770B77778888770900778807770B77778888770900778807770B7777888877",
INIT_40 => X"008809770977778800770B77778809770977778800770B777788097709777788",
INIT_41 => X"0977008800070B77778809880977008800070B7777880988097700880000FFFF",
INIT_42 => X"0007777777770988777700770007777777770988777700770007777777770988",
INIT_43 => X"77778888770900778807770B77778888770900778807770B7777888877090077",
INIT_44 => X"770977778800770B77778809770977778800770B77778809770977778800770B",
INIT_45 => X"8800070B77778809880977008800070B77778809880977008800070B77778809",
INIT_46 => X"0077000B777777880D880B0B0077000B777777880D880B0B0077000B77777788",
INIT_47 => X"777709880D770B0B99770077777709880D770B0B99770077777709880D770B0B",
INIT_48 => X"0D77880B990000770B7709770D77880B990000770B7709770D77880B99000077",
INIT_49 => X"990077770B7709778877880B990077770B7709778877880B990077770B770977",
INIT_4A => X"00777777880D880B0B0077000B777777880D880B0B0077000B777777880D880B",
INIT_4B => X"880D770B0B99770077777709880D770B0B99770077777709880D770B0B0077F8",
INIT_4C => X"0B990000770B7709770D77880B990000770B7709770D77880B990000770B7709",
INIT_4D => X"770B7709778877880B990077770B7709778877880B990077770B770977887788",
INIT_4E => X"77880D880B0B0077000B777777880D880B0B0077000B777777880D880B0B0077",
INIT_4F => X"0B0B99770077777709880D770B0B99770077777709880D770B0B997700777777",
INIT_50 => X"99777777777755885577880B99777777777755885577880B9977777777775588",
INIT_51 => X"77770B885599880B0777777777770B885599880B0777777777770B885599880B",
INIT_52 => X"5599770B0799777777770B555599770B0799777777770B555599770B07997777",
INIT_53 => X"0799777777770B55889977880799777777770B55889977880799777777770B55",
INIT_54 => X"10777755885577880B99777777777755885577880B9977777777775588557788",
INIT_55 => X"885599880B0777777777770B885599880B0777777777770B885599880B00BB99",
INIT_56 => X"0B0799777777770B555599770B0799777777770B555599770B0799777777770B",
INIT_57 => X"7777770B55889977880799777777770B55889977880799777777770B55889977",
INIT_58 => X"55885577880B99777777777755885577880B99777777777755885577880B9977",
INIT_59 => X"880B0777777777770B885599880B0777777777770B885599880B077777777777",
INIT_5A => X"880988880B88097709007777880988880B88097709007777880988880B880977",
INIT_5B => X"0B887777090977770B0988090B887777090977770B0988090B88777709097777",
INIT_5C => X"090900770B88880988887709090900770B88880988887709090900770B888809",
INIT_5D => X"0B880909880B7709770900770B880909880B7709770900770B880909880B7709",
INIT_5E => X"000B88097709007777880988880B88097709007777880988880B880977090077",
INIT_5F => X"77090977770B0988090B887777090977770B0988090B8877770909777700D7F8",
INIT_60 => X"770B88880988887709090900770B88880988887709090900770B888809888877",
INIT_61 => X"09880B7709770900770B880909880B7709770900770B880909880B7709770900",
INIT_62 => X"097709007777880988880B88097709007777880988880B880977090077778809",
INIT_63 => X"77770B0988090B887777090977770B0988090B887777090977770B0988090B88",
INIT_64 => X"0B99777788008809550977770777550009887709777709775577099900098809",
INIT_65 => X"7755885588D77777000055880977007777770755880905885509775555047788",
INIT_66 => X"0B99090B777777998877770055880B7777880B990000770B770B770D09775509",
INIT_67 => X"077788777707778877880088550B77880077778877000988770B887788997788",
INIT_68 => X"0077880B990077770B7705887709778855058809000988880088907788885588",
INIT_69 => X"5588000B7788077709770900990007095588777755007788078877770001F899",
INIT_6A => X"8800070B7777880977777709880955887788550B7700777700770909DD007777",
INIT_6B => X"77770988770909990000770B7700550977079955BB0B99007709550788770900",
INIT_6C => X"887777770B8877887788550B880988880777770B777777000999090900777788",
INIT_6D => X"77887777880B8877550977BB0B77775588000B77880777077709887788770977",
INIT_6E => X"8877999999BB777777770077558870075507775509095588070B770907770577",
INIT_6F => X"098809005507770977770B7777770B770B777700557788558877880988777777",
INIT_70 => X"88778877008877070B0988090B448809000B8800777709880055885577090977",
INIT_71 => X"770B000B008800770B77550909880007990B88098F0B997777885500990B8809",
INIT_72 => X"00000B880077770977008888888877770088057799557755097709005509880B",
INIT_73 => X"770999887709778877007709008877770077880B8877880B990B00880900D799",
INIT_74 => X"0B0B997700777755888800775588770977090988779977099909887707770009",
INIT_75 => X"0009887707887777779900550B778855098877090988008888770055880B7777",
INIT_76 => X"77070B887707880788770988550B770799000B55770088098855887777880788",
INIT_77 => X"07880B0B77550900887788098800097709778877097788880077070055097788",
INIT_78 => X"DDBBDDDDBBDDDDDDBB7707550988990507775509777777885577090577887788",
INIT_79 => X"885509097707000999770B777777098855777709550077008888BBBBBBDDBBBB",
INIT_7A => X"77888877880709000B880577887788770900770B88880588887707098F770955",
INIT_7B => X"550B880988778809008888778877996B88888FBBBB8F8888990B778877888F47",
INIT_7C => X"100700770B888805888888008888557700090977777777888855098804557709",
INIT_7D => X"77880B7777886B770000770B778895778877000977997788070B0B057700D799",
INIT_7E => X"880B078855887799778807770955000788050B00885509888855880988777700",
INIT_7F => X"77078809558877550B7777777709070009880009887777880977887700097799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"770B09777788778855880B880B887788078855770077007777077788550B0B07",
INIT_01 => X"0B7709047788887788090088777700BB000B770B7700770B880007097755000B",
INIT_02 => X"BBDDBBDDBBDDDDDDBB9999999999998877097777098809558800550077077705",
INIT_03 => X"5588775588990977778877770055880700000077880977099999BBDDBBBBBBBB",
INIT_04 => X"880977880B778877777788550B77077777078888770977557709008800077700",
INIT_05 => X"55887788098877880D7705880B887DDDDDFFFFDDFFDDDD888888880B99058888",
INIT_06 => X"007707888877097755777799000B880B88778809000B0B880B77880955880088",
INIT_07 => X"0B558809000B880877770988770B0B07550B9977090900770B778888550077F8",
INIT_08 => X"77770B0988050B7700778877889999777788995588770977777709770B008809",
INIT_09 => X"8877558877090B88777709888877889955090B770B09880B8807558899777709",
INIT_0A => X"098877000B778809888877055509887777880077098809880077887709888877",
INIT_0B => X"77007777097788558888770B098809097788097777990B88090B777777000977",
INIT_0C => X"BBBBBBBBDDBBDDBBDDBBBBBBBBBB889977880907550777550735997709770977",
INIT_0D => X"00770B0B7707990009078809097709078F99990B777777996B8FBBBBBBBBBBBB",
INIT_0E => X"7777880B55887709090B880B885588770B7788550955880B0977990707770B99",
INIT_0F => X"0B8807778877880B77888F8F88BBBBDDFFFFFFFFFFFFFFFFBBBB6B8877990D09",
INIT_10 => X"000B7788550977880B070B0099889988998877889977888888005555880B0977",
INIT_11 => X"770009779977090499778877777788887788550977770777880955880B00D799",
INIT_12 => X"7788887707778877990099889988778888888888888888886B88887788777788",
INIT_13 => X"550B885509880077557788077700777709887777880977775588770B55097777",
INIT_14 => X"777709997788770977097788778877770055990988887777990B555588770900",
INIT_15 => X"770988888888778809550988097788000977778809775509778800770B779900",
INIT_16 => X"BBBBBBDDBBDDDDDDBBBBBBBBBBBBBBBB99997788777709007788550777007700",
INIT_17 => X"99097788778805099977770977007788998899BB888899BB778899BB99BBBBBB",
INIT_18 => X"0B88055588778855887707770588090B00770477880B778888770B7788885500",
INIT_19 => X"330B880B000B0B778877778888DDDDFFFFFFFFFFFFFFFFFFFFDDDDDDDD889999",
INIT_1A => X"1000770477880B5588889988998F0D0B886B990B880B07B609990B8855888800",
INIT_1B => X"887788770700770B88880788880977880B777788000B7788448888077700BB99",
INIT_1C => X"888833007788770788BB8F8888BB8F7D8F888FBBDD8F8F88886B7788090B0777",
INIT_1D => X"00990900990909770088557709990B09777788770B8807090B880B887788770B",
INIT_1E => X"8807880D770988009988550B0B009988098800995509770B0077007709008877",
INIT_1F => X"77770B04097709775577770B880755887777007755098855880B6B0077000B99",
INIT_20 => X"BBDDBBDDBBBBDDBBBBBB88BBBBDDBBBBBB999999775588777777007777097709",
INIT_21 => X"778877770977075588770B88779988888899BBDD88BB88BBBBBBBB99BBBBBBBB",
INIT_22 => X"DD88DD888F9955880077098800097709880B7700090B99775509007799887777",
INIT_23 => X"09887700880B0B0077DD88DD888F88DDFFFFFFFFFFFFFFDDDDFFFFFFFFFFFF88",
INIT_24 => X"000B0B88998888BB88888F888F6B880B880B6B8888BB8F888F88999977887788",
INIT_25 => X"887788550B7788550955880B0955998877777777097788880B7788000901F899",
INIT_26 => X"88770B007700770B888FBB8FDDFFFFFFFFDDFFFFDDFFDDDDBB88887D0955880B",
INIT_27 => X"0F996B7D889988770B7755887777990077057788090B00550088777777777777",
INIT_28 => X"0B885577887777770B88778877886B009988889999BB88BBBB8FBBBB888F8877",
INIT_29 => X"8FBBBB99886B8F99888888090B880B88550988777709778877880B9988557777",
INIT_2A => X"BB99BBDDBBDDDD88BBBBBBBBBBBBBB8899998899999909778888078805770755",
INIT_2B => X"8809557777887788770988779999BBBBBBBB88BBBB99BB8FBBBBBBBB99BBBB88",
INIT_2C => X"DDDDDDDDDD88880D8F8877880999007709558899888809000977998800070988",
INIT_2D => X"777755BBBB9988BB8FDDDDDDBB88DDFFFFFFDDDDFFFFFFDDFFDDFFFFFFFFDDDD",
INIT_2E => X"00BB88998F77888F88DDBBBBBB88DD88999908888F88BBDDDDDDDDBB8899880B",
INIT_2F => X"0900090B00770477880B44888888889988DD8F888F8899BB8F990F888F00D799",
INIT_30 => X"770B7777888F8F888F8FFFDD8FFFFFFFDDFFBBDDDDBBFFDDDD888F7788880744",
INIT_31 => X"88888888880888BB88880B88009900990988880B007709770988090B00770777",
INIT_32 => X"885588885507098855880B778899888F880B99888FBBDDDDFFFFFFDD8FBB8F7D",
INIT_33 => X"BBDDDDDDDDBB8888888899887709550B0B88550B88880955007777880988880B",
INIT_34 => X"BBBBBBBBDDBBBBBBBBBBBBBBBBBBBBBBBB996B99888899885555777777097709",
INIT_35 => X"777788886B7D0B09997777999988BB9999BBBBBB997D8899BBDDDDBBDDBBBBBB",
INIT_36 => X"DDDDDDDDFFDD9988880B77999977090077885577098877998877887777997799",
INIT_37 => X"888877887DBBDDBBDDDDDDDDBBDDDDDDFFFFFFFFFFFFDDDDDDDDFFFFFFDDFFDD",
INIT_38 => X"108F888FBB8FDDDDFFDDFFFFFFFFFFDD880D6B9988DDDDFFFFFFDDBB8F888F88",
INIT_39 => X"779977777788770B777788070B7D8F8FDD8FFFDDDDFF8FBB88BB888F880099F8",
INIT_3A => X"007700770B8888DDBBFFFFDDDDFFDDFFFF8FFFFFBBFFDDBB88DD888855778877",
INIT_3B => X"7D888F888F7D888899889988880B99889999778855008877777788777788770B",
INIT_3C => X"7709770009888877000977886B888F99887D8F7D88FFFFFFFFFFFFFFFFFFDDBB",
INIT_3D => X"FFFFFFFFFFFFFFFFDDDD885500887777887777880B0777880777885577075588",
INIT_3E => X"BB88BBBBBBDDBBBBBBBBBB99BBBB9999BBBB9999999999770909550588558855",
INIT_3F => X"889999998899998888887D7799BB99998888BB998F88BBBBDDBBDDDDBBBBBBBB",
INIT_40 => X"DDDDFFFFDDFFDDBB9988BB88889977990B778877007700098809776B8F880B88",
INIT_41 => X"777788BB88FFBBDDDD8FDDBBDDDDBBFFDDDDDDDDDDDDDDDDDDDDDDDDDDFFDD8F",
INIT_42 => X"1099BBDDDDDDDDFFDDFFFFFFFFFFFFFFBB88886BBBDDDDDDDDFFDDFFDDDDBBBB",
INIT_43 => X"888F8888886B88888F9988998888BBFFFFFFFFFFFFFFFFFFFFFFFF88DD00D799",
INIT_44 => X"888FBB888F8F8FBB8FDDFFFFBBFFFF8FFFFFDD8FDDBBFFDDFF88DD88888F7D88",
INIT_45 => X"DDBBDD8F88888F8888880F886B8899880B880B99998F886B99880F887D778F88",
INIT_46 => X"88778899887755888F88886B8888888F7D8888DDDDFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFDDDD8F888F8809550B0B77888800777788000900770B77",
INIT_48 => X"BBBBDD99BBBB888F99BB99BB888899996B88998F99999988B677070988778877",
INIT_49 => X"0B889999997799886B999988BB0999090B9999999999BB8888BBBBBBBBBBBBBB",
INIT_4A => X"BBDDDDFFDDDDFFBBBBBBDDBB88BB999999098877888877886B88779999779988",
INIT_4B => X"DDDDDD8FDD88BBBB8F88BBDD8FDDDD8FDDDDDD8FDDDDDD88BBDDDDDDDDDDBBDD",
INIT_4C => X"00DD8FDDDDBBDDFFDDFFFFFFFFFFFFFFFFDDBB8FDDFFDDDDDDDDDDDDDDFFDDFF",
INIT_4D => X"888FDD888F888F8888888888DDDDDDFFFFFFDDFFFFFFDDFFDDFFDDDDDD00D799",
INIT_4E => X"DD8F8F8899DDDDDD88DD8FDDDDBBDDDDBBDD8FBBFFDD8FDDDDDDDDDDDD8F888F",
INIT_4F => X"FFFFFFFFFFDDFF8FBB887D8F6B888899887D8F7D888FBB8F8F888FDDDDDDDDDD",
INIT_50 => X"88997777887709887D88887D8FDDDDFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFDD885577007777778807778888777700770977",
INIT_52 => X"88BBBBBBBB88999988778F88998F999999998877880B77098808775577075509",
INIT_53 => X"8899997D88BB8899776B889988998888887799886B999999BBBBBBBBBBBBBBBB",
INIT_54 => X"DDDDFFFFFFDDDDDDDDBB88BBDDBB88889988770B9977886B8899999988888899",
INIT_55 => X"DDDD8FBBDD8FDD88BB8F8FBBDD88DD88BBBBDDBBBBDD88DDBB8FDDBBDDBB88BB",
INIT_56 => X"10DDBBFFDDFFFFDDFFFFFFFFFFFFFFFFFFFFDDBBDD8FDDBBDD88DDDDDDDDDDDD",
INIT_57 => X"6BBB88FFDDFFDDDDBB998FDDDDFFFFDDFFFFFF8FFFDDFFDDFFDDFFFFDD00BB99",
INIT_58 => X"DDDDBBBB888FBB88DD8FDDDD88DD88DD8F88DDDD88DDDDDDDD8FFFFFFFBB0D77",
INIT_59 => X"FFFFFFFFFFFFFFFFFFDD88BB88DD8FBB8F888888BB88DD8FDDDDDDFFFFFFFFDD",
INIT_5A => X"778800880B8888BB778FDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF8F887D88887D88889988886B888899998F88",
INIT_5C => X"BBBBBBBBBBBB88BBBB9999BB9988BBBB998899998F7788770577098877777777",
INIT_5D => X"99998888998F9988BB9999887777999999886B7777888F8888BB99BBBB99BB99",
INIT_5E => X"BBDDDDDDDDDDDDDDBB8F8F88887D887D889988999999998899886B8F8F77770B",
INIT_5F => X"DDDDDDDD88BB888FBBDD998FDDBB88BB88DDDDDDDDDDDDBBBB88DDFFDDDDBBDD",
INIT_60 => X"008FFFDDBBDDDDFFDDFFFFFFFFFFFFFFFFFFFFDDBBDDFFDDDDBBDD8FBBDDDDFF",
INIT_61 => X"88BBDDFFFFFFFFFF8F8888FFBBFFDDFFFFFFFFDDFF8FFFFFFFFFFFDDDD00D7F8",
INIT_62 => X"DDDD888FDDBBBB8FBBBBDD8F8FBB8F88DDFFDDDD8F8FDDDDDDFFFFFFFF8FBB88",
INIT_63 => X"FFFFFFFFFFFFFFDDFFDDDD8F8FBBBBBBBBBBBBBB8FDDDDDDFFFFFFFFFFFFFFFF",
INIT_64 => X"886B998899998FBBBBDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFDDDDFFFFFFFFFFFFFFFFFFFFFFFFBB888888776B6B886B8888996B888F7700",
INIT_66 => X"BBBBBB99998899998888998899BB99888F999988779999887788777700770077",
INIT_67 => X"88996B99BB8899998F887D9988998899BB8F88BB889977998FBB8899889999BB",
INIT_68 => X"BBBBDDDDDDDDBBDDBBBB888F88998F99998F88BB99888F998F99887788888899",
INIT_69 => X"FFFFFFDDDDBB88BB88BBBB8888888F888F888F8FDD7DDD88BBBBBBDDDDDD8FBB",
INIT_6A => X"00DDDDFFFFDDDDDDDDDDFFFFFFFFFFFFFFFFFFDDDDDDBBDDDDDDBBBBDDBBBBDD",
INIT_6B => X"8F88BBBBFFFFFFFFFFFFDD8FFFDDFFFFFFFFFFDDFFDDDDFFFFDDFFDDFF01F899",
INIT_6C => X"DDDDDDDD8F888FDD888FDD88DDDDBBFF8FDD8FDDDDDDDDDDDDFFDDFFFFFFFFDD",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFF8FFFFFFFFFFFFFFFFFFFFFFFFFBB",
INIT_6E => X"7788888F888FDD8FFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFDD88BB7D88886B88886B8888998888BB",
INIT_70 => X"BB8899888899997D8888BB999999889977889999889988BB888877770B550B55",
INIT_71 => X"9988BB6BBB888F7D9999BB99889988DDBB88BBBB8888996B8899998899888899",
INIT_72 => X"DDDDDDBBDD88BBBB99BBBBBB88BB997D88BB888899889999999988998F7D9988",
INIT_73 => X"8FDDFFDDDDDDBBDD88BBDD8FBB8F888888BB99BBBB7D88BB8F88BBDDDDDDDDDD",
INIT_74 => X"10DDDDDDFFFFDDDDBBDDDD88BB88DDDDDDDDDDFFDD8888DDDD8FBBDDBB88DDDD",
INIT_75 => X"FFFF8FFFFFFFFFFFFFFFDDFFFFFFFFDDFFDDFFFFFFFF8FFFDD8FDDFFDD0099F8",
INIT_76 => X"DDDDDDDDDDDDDD8FBBDDDDDDDDDDBB8FDDFFFFDDDDDD8FFFDDFFBBFFDDFF8FFF",
INIT_77 => X"FFFFFFFFFFFFFFDDFFFFDDFFFFFFDDFFBBFFDDFFFFFFFFDDFF8FFFDD8FFFDDDD",
INIT_78 => X"BB88DDFFFFFFFFFFFFBBDDBBBBFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFF8FDD888FBB886B8888886BBB88BB88BB",
INIT_7A => X"8F99999999889999999999BB999999997D9999997DBB9988D7770D7788778877",
INIT_7B => X"99999977998F887788886B889988BBBBBBBB8F778899887799BB999977BBBB8F",
INIT_7C => X"DDBBDDBBBBBB888F8F88997799888F88BB888F7788990BBB886BBB778888886B",
INIT_7D => X"DDFFBBDDDDBBBB8FBB889988888F88BB888F888F8F77888F88BB8888DDDDDDDD",
INIT_7E => X"10DDFFFFBBDD8FDDBB88BBBB8F888FDD88DDDDDDFFDDDDBB88BB8FBB8FBBBBBB",
INIT_7F => X"8FDDDD8FDDFFFFFFDDFFFFDDFFDDBBFFFFFFFFDDFFDDDDDDDDDDDDFFFF00D799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"8FDDDDDD8F88DDDD8F8FDD88888FBB88DDDDDDBBFFFFDDFFFFFFFFDDDDFFFFDD",
INIT_01 => X"DDFFFFFFBBFFFFDDDDFFFFDDDDFFFFFFFFDDFFDDFFDDFFFFDDFFBBFFDDBBFFBB",
INIT_02 => X"8FDDFFFFFFFFFFFFDD8FBB8FFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDDDDD",
INIT_03 => X"DDFFDDFFFFFFDDFFFFFFFFFFFFFFFFFFDDDDBB88888F888F8FBB888F88888888",
INIT_04 => X"99889988888F88998888999988999988770B997799888F8F8877777777097709",
INIT_05 => X"7D88996B88779999779999BBBBBB88BBBB99889999999999886B889999889999",
INIT_06 => X"DDDDDDDD88BBBBDD88BB8FBB8899998FBBBB888F9988BB77BB88998877999999",
INIT_07 => X"BBBBFFDDDD8FDDBBBBDDDD8FBB88BB8FBB88BB88888899998F88BBBBDDBBFFDD",
INIT_08 => X"00DDDDDDFFBBDDDDDDDD8FBBBBDDBB8FDDDD8FDD8F8F888FBB8888BBBB88BB8F",
INIT_09 => X"DDDDDDFFFFDDDDFFFFDD8FDDBBDDDDDDDDFFFFDDFFDDFFBBDD88FFDDDD0077F8",
INIT_0A => X"DDDD8888DDDD7DDD88BB88DDDDDD8FDDBB8888DDDDBBDDBB8FBBFFFFFFFFFFDD",
INIT_0B => X"DDBBDD88DDDDDDDDDDDDFFFFFFDDDDBBFFDDDDFFBBFF8FDDFFDDFFDDDDFFDD8F",
INIT_0C => X"88DDDDDDFFFFDD8F88DD88DD8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDBB8FDD",
INIT_0D => X"DDDDFFDDDDFFDDDDFFFFFFFFFFFFFFFFFF8FDDDDDD8888BBBB8FBB888FDD8FBB",
INIT_0E => X"BB999999BB9999BBBB998FBBBBBB8899BB888899BBBB99999977880988778877",
INIT_0F => X"77990B8899998F8F88886B887D999977778F999977886B88BB99998F0B997D77",
INIT_10 => X"BBDDDD88BB8FBBBB99BB9988BB8F88BB88BBBB8899BBBBBB88999999BB888F99",
INIT_11 => X"DDDDDD888FBBBB8FBBBBBB8888BB888877BBBBBBBB997D8888BB778F88BBBB88",
INIT_12 => X"00BBDDDDDDDD88DD88BB88BB888F88DDBB88DD88DDBBBB8899889988998F88DD",
INIT_13 => X"DDDD8FFFDDDDFF8FDDDD88DD8F88BBDDFFFFDDDD88BB888FBBBBDDFFFF00D799",
INIT_14 => X"8FBB8FDD7DBBBB88BB888F8888BB88888FDDDDDD88FFBBFFDDFFFFFFDDFFFF8F",
INIT_15 => X"8FBB88BBFF88BBDDFFDDDD8FBBDDFFDDDD8FFFBBFFFFDDFFBBDDDDDDDDBBDDDD",
INIT_16 => X"DDBB8FBBDD8FBB88DD888FFFFFFF8FFFDDFF8FFFFFFFFFFFFFFFFFFFDDFFDDDD",
INIT_17 => X"DDDDDDDDFFDDDDDDDDFFFFFFFFFFFFFFDD888FDDDDFFDDFFFFDD8F8FBBBBDD88",
INIT_18 => X"9988999977BBBB888FBBBBBB9988BB99888F88BBBB997D9999888888770B770B",
INIT_19 => X"BB990B9988BB996B8899BB7799888F88BB9977774799889999998F779988886B",
INIT_1A => X"DDBBBBBBBBBBBBBB8F888F88BB888F88998F8F8F8899997D88998FBB888F8899",
INIT_1B => X"88BB8FDDDD88BBDD88BBBB88DDBB888899889988BB88BB88888F887788BB8F88",
INIT_1C => X"00DDDDBBDDDD8FBB8FBB888F88BB88DD88DDDD888FBB8888886B996B7799BBBB",
INIT_1D => X"DDFFDDFFFFFFFFFFDDDDFFFF88DDBB8FDD888F8888887D88DDDD88BBDD00D7F8",
INIT_1E => X"888F88887D9977887799778888778888BB8888DD8F88888FDDDDFFBB8FDDFFFF",
INIT_1F => X"BB8F88DDBBBBDD888FDD88DDDDFFDDDDFFBBDDBBDDDDDDFFBBDD8888DDDDDD88",
INIT_20 => X"888FBB8F888FDD7DDD888F8888FFBBDDDDDDDDDDDD8FDDDD8FFFFFFFDDFF88BB",
INIT_21 => X"BBDDDDDDDDDDDDBBFFDDDDDD88DDDDDDDD8F888FDDBBDD88BBDDDD888FBBBB8F",
INIT_22 => X"997D998F8F88DDBBBB88BBBBBBBB888FBB99BBBBBB997799098F997788778877",
INIT_23 => X"889999BB9988778899886B9999999999778F99886B778F99778888996B999977",
INIT_24 => X"7D88BB8F88BB8F888899BBBB88BB998F8888778899889988BB88998899889999",
INIT_25 => X"BBDDDDBB88DDBBBB8F88DDBB888FBB8F9988889988997D999988997D888888DD",
INIT_26 => X"00DD8FFF888FDDBBDDBBF8888F88BBBB8F8888BB888FBB6B999988886B998F88",
INIT_27 => X"FFFFFFFFFFFFDDFFDD8FFFFFDD8FBBDD888F99BB8FBB88BB88BBDDDD8F01F899",
INIT_28 => X"BB886B99777788770B886B9999889999BB8888BB88DDDDDDDD8FDDFFDDFFFFDD",
INIT_29 => X"DDBBDDBB888F88DDDDBBFF88DDBBDDBBDDDDDDFFBBBBDD8888BBDD8F88BB9988",
INIT_2A => X"BB88BB88BB88BB88DD88BB88DD88DD8FDDBBBB888FDDDDDDDDBBDDDDBBDDDDDD",
INIT_2B => X"DDBBBBBBDDDDDDDD88BB88DD8FBB88DDBBDDDDBB998F88BB8F88888F88888F88",
INIT_2C => X"999977777799BB88BBDDBB88888F8F7799BBBB8FBB99BBBB8877880977777777",
INIT_2D => X"996B88BBBB8FBBBB99BB99888F887D8899886B998899598877998F99887777BB",
INIT_2E => X"88BB8FBBDD8F88BBBBBB886B997D8888778F99997D6B88998899888F99889988",
INIT_2F => X"8FBB88BB8FBBBB8FDDFF8F88BBBB88BB8899888FBB8F888888998877998FBBBB",
INIT_30 => X"00DDDD88BBDDDD8FBB8F8888BBBB8FDD88BBBB888F8899886B886B9999888899",
INIT_31 => X"FFFFFFFFFFFF8FFFBBFFFFDDDD8888BB88BB888F7788DD88DD8888DDBB00D799",
INIT_32 => X"889988990B990977880B478888776B99888F8F888F88BB88DD88DDBBFFDDDDDD",
INIT_33 => X"BB88DDDDFFDDDDDD88BB8FDDBB88DDDDDDDDFF88DD8F88DDDDBB8FBB888F7D88",
INIT_34 => X"88BB88BB88DD888F88BB778F888FBB88BB8FDD8FDD888F88BBFFBB8FDDDDDDBB",
INIT_35 => X"88BB888F88BBDDBB8F8F8888BBBBDD88DD88DD888FBB888FBB888F88888F8888",
INIT_36 => X"9988778888F88899BB99BB8F999988F8BB88BB9999BB887D77770988770B770B",
INIT_37 => X"8877999988BB888F8899887D8899997D8F778877998899779988779999998F88",
INIT_38 => X"BB88BBBBBB99BBBB88BB99888F88BB8F889988998877990B7D9999887799998F",
INIT_39 => X"88BBDDDD88DDDD88DD888FBB888F99886B888F998899997D8F99997799779988",
INIT_3A => X"10FFBBDD8FBB8F88DD88BB888F88BBBBDD8F8FBB8899888F886B880B8899888F",
INIT_3B => X"FFDDFFFFFFFFFFDDDDBBFFBB88DD8F888FBBBB88BB888F88DD8FBBBB880099F8",
INIT_3C => X"990B990988887788998888776B08880B998888BB88888F88BBDD8FDDDDBBFFFF",
INIT_3D => X"FFDDDD8FDDBBBB8FDDDDBB88BB8FBBDD888FDDDDBBDDFFBB888F8888BB887799",
INIT_3E => X"8F888F888F88BB88BB8F88998F888888DD8888BB88BB88DD88DDDD88BB8FDDDD",
INIT_3F => X"998F8F99888FBB88BBBB88BB888F88DDBB8F8FBB88BB8FBB8F88BBDDBB888FBB",
INIT_40 => X"99D76BBB6B88888F9999BB778F999988BB88BBBBBB99BB997707999999999999",
INIT_41 => X"8899BBBBBBBBBB8899BB886B99BB888F77888899888899886B777799990B9999",
INIT_42 => X"998F99BBBB888F8F8899888F886B9999888888999999998899888888000D6B99",
INIT_43 => X"88BB8888BB8888998888889999886B998F997D8888888F998F9988886B8F888F",
INIT_44 => X"0088BBFFBB8888BB88BB88888F887DBB888F8F8899777D8F7799888899889999",
INIT_45 => X"DDDDDD8FFFFFFFBBFF888F888899BB998FBB889988887D8F8F888F88BB0077F8",
INIT_46 => X"6B88998888778877880988998877887709887D88BB8F88BBBBBB7DDD888FDDDD",
INIT_47 => X"DDDDBBDD8FDDDD8FBBDDDD8FDDBB8888DDBBBBDDBBDDBB8FBB88BB8F888F8899",
INIT_48 => X"BB8FBBBB88BBBB888F88886B9988BB8F88BBBBBB88BB88BBDD8FBBDD88DD88DD",
INIT_49 => X"BBBB997D99BB9988998F88888F888F888F8888888F8F8FBB88DDDDDD8888888F",
INIT_4A => X"995988998899999988886B88777788778FBB99BB88886B889988990B99889988",
INIT_4B => X"BB7D77DD88DDDDBB88889999990B778899998F99779977098877887788770B77",
INIT_4C => X"9988998F7799998888999999998899998F998F0B998F9988887D8F99BBBBBB88",
INIT_4D => X"8F88BBBB88BBBB8F8F997D8899998899778877998F9977089988999999889988",
INIT_4E => X"008F8F998888888FBB887D8F8899888899BB99888F99888808888F7709888888",
INIT_4F => X"DDDD8FDDDDDD8FDDDDDDBB8F8F8888889988886B88887788998899998F00D799",
INIT_50 => X"887707777709090077887707770B7777889977776B99888FBB88888F88BBBB8F",
INIT_51 => X"88DD8888DD88BBDD88BBDD888FBB8FDDDD88BB8F88888F8888BB88BB8899996B",
INIT_52 => X"888888888F88888FBB88BB88886B88886B888F778F888F88DD888888BBBBDD8F",
INIT_53 => X"7D8F88BB88BB888F889988BB888899DDBBBBDDBB888888BBBB88BB8888BBBB77",
INIT_54 => X"0B7799BB99999988999977777D99999988779988999988998F77779977997799",
INIT_55 => X"BB99DDBBDDBB8888BB99887DBB99888F8F888899889988997799097709997788",
INIT_56 => X"99998888BB8F99998F889988999988887788BB88BB88996BBB77998899998FBB",
INIT_57 => X"99998888BB998F8899BB77BB990B998899997799770B88BB88990B99886B778F",
INIT_58 => X"1088888F888FBB8888BB77887D888F7D887788BB7777888F996B888877888877",
INIT_59 => X"BB88BBBB8F88DDFF8888BB88888F8FBB8F9999886B6B888888888F889900BB99",
INIT_5A => X"990B880B887777990B770077007788880999997D88777D888F998F77BB888F88",
INIT_5B => X"BB8FDDBBBB8FDD88DDBBDDDD88DDBB8F888F88BB888888BB8FBBBB887D990899",
INIT_5C => X"8F997D99887D8F88888F888FBB886B7D889999888899889988BB8F8F88DDBB88",
INIT_5D => X"99BBBB88DD8FBBBBBBBB8F88BB8F888FBBDDDD8FDDDDBB8FBB888F8F88BB8F8F",
INIT_5E => X"9999888F0F886B99BB9988BB99888899BB8F6B998F99999988886B886B886B88",
INIT_5F => X"88BBBBBBDDBBBB9988999999886B9988779977889999990B998899887788990B",
INIT_60 => X"886B99998899888F88BB6B997D88BB88BB886B99889988998F9988BB888888BB",
INIT_61 => X"998899BB777D99888F8F998899886B6B8F0B9988998899776B88770B77888877",
INIT_62 => X"008F8FBB88BB8FBB88888F88999977777D997D77996B6B8877999999886B0900",
INIT_63 => X"888F888888DDDD888F8F888F8F88888877888F88999999886B8888777D00D7F8",
INIT_64 => X"88550988770B09885509770B09777777889988998F7D99BB8888BB998899778F",
INIT_65 => X"DD88BBDDBBBB8FBBBB7D8888BBBB88BBBB888F88BBBBBB88888F889988888888",
INIT_66 => X"8888997D8899888F8899887D0B7788776B88888FBB6B887D998888888F8888BB",
INIT_67 => X"8888BBDDBBBB88DDBBBBBBDD88DD8FDD8FBBDDDD8899BBBB88DD8888BB8888BB",
INIT_68 => X"990B778F8FF88899779988999988887777999999999988597D77779988778877",
INIT_69 => X"BB77BBBB8888BB889999889988778F888F8F885988770B9977D7990B880B9977",
INIT_6A => X"886B88BB888F8F88BBBBBB88BB998FBB88998FBB8899998899999988889999BB",
INIT_6B => X"99770B77990B9977889977BB7D99777799776B889999990B0B88778877778877",
INIT_6C => X"0077099977777799777709770555777799770977D70777077777997777888F99",
INIT_6D => X"9988998FBB0B778899888F99999977889999998877887D998F7777779900D799",
INIT_6E => X"097755777755777777777D55556B777D770B776B77770B775577037777557777",
INIT_6F => X"BB88BBBB88888899BBBB8888888FBBBBBBBBDD8FBBBBBBBBBB99777777779977",
INIT_70 => X"BB888F8F88BB88998899990B8809777788888899778888779977778877888F88",
INIT_71 => X"DDBBBBDDBB88BBDD8F888FDDDDDDDDBBFFBBDD8FDDDDDDFFDDFFDDDDDDBBDD88",
INIT_72 => X"7788997788886B998888770B99098F88990099886B996B8888778877990B990B",
INIT_73 => X"997D8888BBDD8F77BB8F99889999887D88089999998877888899999977770B88",
INIT_74 => X"BBBBBBBBBBBBBBBBBB99888FBB88BB8F9988888899887D99887D888F8F887D77",
INIT_75 => X"7799770977D70777888F990B770B99990B9977770909887788990B9999886B88",
INIT_76 => X"1077770955775555556B555555097705470555550955556B0977050977095577",
INIT_77 => X"555577997777095577777799770909778F7777777777777777779977070099F8",
INIT_78 => X"556B555507550B770755097755556B4705996B475555777D7705596B55070B55",
INIT_79 => X"998F77889988888F77888FBB8F888FBB8F8F999999777777770777777777550B",
INIT_7A => X"88DDDDBBDD88888F8808098877778899880999990B880977990B997D990B88BB",
INIT_7B => X"DDBBDD88DDDD88DDBBBBDDDDDDDDDDFFDDFFDDDDDDDDDD88DDDD8888888FBBBB",
INIT_7C => X"999977997777778877999977889999990BBB9999889988999999778877777777",
INIT_7D => X"99999999998899889988998F99996B77779909770B9999777788888899887799",
INIT_7E => X"88BB88BBBBBB88BB88BBBBBB8F88BB888F888F8F889988999977997799BB99BB",
INIT_7F => X"05470555550955550955777799777777D707770777779999097777886B778899",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"1055037705557D5507470F336B746B770F77556B770977475509777405770977",
INIT_01 => X"090F77073309550555077707559555354755350555550955555509055500D799",
INIT_02 => X"475555596B777D4777777D556B595555740F5509776B5555557703556B55776B",
INIT_03 => X"88BBBBBB8F8F8888BBBB8899BBBB88BBBB99777799077759556B550905777777",
INIT_04 => X"BB887DDD88DDBBBB8888BBBB9908098877770809887777880988887777887799",
INIT_05 => X"88BBDDDDBBBBDDDDBBDD88BBDDFFDDBBBBBBDD88BB8899888899880B77778888",
INIT_06 => X"0B7788888899990B998899887788888899999999997799886B88889988778877",
INIT_07 => X"889988886B99998F779999889988778888999988776B889999B60999776B8877",
INIT_08 => X"BB8FDDBBBB8FDD8FBBBBBB8888BB8F8899998899990B998888998F8888777799",
INIT_09 => X"770F77556B77097777097755470555550977556B5577057777778847880D99BB",
INIT_0A => X"000755597707095577557709596B477755776B053377550555770F6B556B746B",
INIT_0B => X"777755597D556B475555770B0703556B550509554755770755055577050077F8",
INIT_0C => X"556B5955505955556B5577076B6B776B550505770F476B5547596B7759095547",
INIT_0D => X"770D888899889988BB8F888F7D88999977776B5547775547056B558F55555509",
INIT_0E => X"88998888DD88BB887D9988008877090B770B887D8888000B0809990B9988778F",
INIT_0F => X"DDBBDDBBDDBBDD88DDBBDDDDDDDDBBDDBB888899880B8877880B778800770977",
INIT_10 => X"8877997788888877998877996B8877000B7777990B99777D7788888899779977",
INIT_11 => X"99886B9988998F8899886B99996B7788887777889977990B9988777799777788",
INIT_12 => X"779999BBBBDDBB88BBBB8F88BB88BB88998F8F8F998F8899886B9988888F8877",
INIT_13 => X"55550F55556B0F05356B476B557705053395550555770F550947050955070909",
INIT_14 => X"1035070577550955330F77075950555505770F557D5555095555555500775505",
INIT_15 => X"0599950B55070555556B4755777755076B35773307557755093307073300BB99",
INIT_16 => X"77555555777D33555577595559555555090747556B55557747550F595509776B",
INIT_17 => X"770B000B08990B8888888F8877097707556B470F7777777D330F770555740755",
INIT_18 => X"887788880988880B778877098877880009770B7788770900778877097788880B",
INIT_19 => X"BBDDDD88BBBB8FDDDDDDBBDDDDBB880B880B8888770088777700098809887777",
INIT_1A => X"6B7788779999990B8899990B77990BDD99999988997799889977099988778877",
INIT_1B => X"6B9988996B997777889988998877888F00887709778899779909880788779977",
INIT_1C => X"09777799BB88BBBBBBBB88BB88BB8FBB889988889999990B998899B6888888BB",
INIT_1D => X"5505770F557D555577550547550F74556B7D056B6B0F5533470F550F77555505",
INIT_1E => X"007D3577057707558F555577470F550F7755550547779977550F7D0977075055",
INIT_1F => X"99556B7D5933470B7777056B070555475507033533055505550555330F00D7F8",
INIT_20 => X"0F557D0F55556B550D0B7D550555078F7755595535596B476B555059770F5533",
INIT_21 => X"0B888877000988990B887777556B777755777755550B77355555055509776B55",
INIT_22 => X"050B5507770B9988999988880B88090B880988990B88888F8809778800770899",
INIT_23 => X"BB88DDDDBBDDBBDD8FDDDD88990B777799880B99888F0B88770B885588770B00",
INIT_24 => X"7709778888778877997788999988888888996B77886B77998899880977777777",
INIT_25 => X"88776B998877998F779999779977D7889999779988778877889977997799770B",
INIT_26 => X"7705099977778888BBBB99BB998888998F888F998888998877990B77D7990B99",
INIT_27 => X"0F775555054777990750550F057705557D3355095555550F5555057409050977",
INIT_28 => X"00550509770999053305555555550574090509775305055555445555096B0F55",
INIT_29 => X"55053533475507477D095555359505330955550B33094755095507335501F899",
INIT_2A => X"770555555555596B5577555977075555555555550747556B0907555505555907",
INIT_2B => X"88990B000988770B8877550709555555050F770F776609056B55557777775305",
INIT_2C => X"080988778888880B777705007709995588770B77880500770999008809880009",
INIT_2D => X"BBDDBBBBDDDDDDBBDD88BB7788880B0B880B8877057777090055888809880077",
INIT_2E => X"7777887709997799999999880B09F877778F77886B88880B77097777880B880B",
INIT_2F => X"8FBB886B776B887799990B8899880D7788997788770B9999777D8F7788888877",
INIT_30 => X"0547740907096B8F998FBB88998FBB888899888877778F996B9999BB090D8877",
INIT_31 => X"550F5907740977556B0F55557755770547099977050F7D350905774777550744",
INIT_32 => X"00056B770533095555590507090577477755074409475533538F056B77055509",
INIT_33 => X"075595090709770955557705777709550574090777770555053347550F00D799",
INIT_34 => X"09556B0F474755555977075505596B050F55550F77550F476B77770F55777759",
INIT_35 => X"770B88097777007777440977476B7777779909555559775555555507550F7759",
INIT_36 => X"0988098809077777000B08990B888800770B77007708995588880B77770B0988",
INIT_37 => X"099988DDBB88DDBBBBBB090B077777887777770B08550B880B00770988098888",
INIT_38 => X"9909997777880B77776B77887709778899998F59990877998888558877887788",
INIT_39 => X"997D77999999887799889988998899559988887777770988777788770D88000B",
INIT_3A => X"74050755055577030D55554777997D6B888F99889977996B990B77887788776B",
INIT_3B => X"05555577950977070F550F530774050755050947055509770905770F55555305",
INIT_3C => X"100B050755050947055509770905770F555553050705097455000B7707555509",
INIT_3D => X"0555550F0577770F55595505770755090747350577774409055959550F00D799",
INIT_3E => X"550F055953556B475559550B0555098F070735056B0977097D47557755553309",
INIT_3F => X"07770955097777097777555577530F5555550555555555555577550555557755",
INIT_40 => X"770B0088077709880B8800778809887700090B770B0988070B88090707777709",
INIT_41 => X"887799099977886B7709000D770D998877770B88990B8888770B888807770988",
INIT_42 => X"77887788008F998899889999778899770B998899887D8F880999777709770977",
INIT_43 => X"7799996B77778F99889909990B997788779999880B887777880B058855779977",
INIT_44 => X"0955556B55778F9974550F7405557777778899999988998888998888887D8877",
INIT_45 => X"09550F3235095577555333550709557709745577090F5532094755550F535599",
INIT_46 => X"008F0F7709745577090F5532094755550F5355990755550933008F3377090755",
INIT_47 => X"05770977770974440905550F77747755553377093309057707475533770077F8",
INIT_48 => X"0555550F55336B6B55596B44597705557747094755775599035577556B054759",
INIT_49 => X"7709776B775555770D356B770F05330F7733770F330509355509033509770559",
INIT_4A => X"8877097788090955880777007755770977098888777777887777558877050977",
INIT_4B => X"057709770B5577770B77997777888805880B8809007709770077777788090955",
INIT_4C => X"0B7799779947779907779999997777887799BBBB997788888888990988778877",
INIT_4D => X"99990B5977998888999988777777888F097777777709777777D7880977777788",
INIT_4E => X"747D7755775577050747777D9909555555559909999999777799070977997799",
INIT_4F => X"550F33590F05053305337D0955747D0907557709553335590577050555330905",
INIT_50 => X"0055740907557709553335590577050555330905557D0F745500555509070F77",
INIT_51 => X"095507050F557D0977770955050709770F5305777755950F770533770500D799",
INIT_52 => X"09770777050F555509595555355509770905557705330F7755550B5959775359",
INIT_53 => X"55770D0F553303743577094777555505500D535577777705557D550905775347",
INIT_54 => X"0777770955777777777707070999097777777707777709557709995500777755",
INIT_55 => X"8888770977888809770B8800000B77880B770977770577770777090955777777",
INIT_56 => X"88770B990B0B0988770B889999880B7799889999888899997777097777777777",
INIT_57 => X"0999887799887D776B9999779988098888550B88777788090900997788770977",
INIT_58 => X"05230577095955557747775574777D530F740577777709777788998899099988",
INIT_59 => X"555533355555470977055977090523775509740F55338F355533477755057755",
INIT_5A => X"100953775509740F55338F355533477755057755092355055500090577554474",
INIT_5B => X"7707775555073555053307770B9577775507550509050595077709740900BB99",
INIT_5C => X"0577057774740F7777470977590F7709447455056B7433470F0777556B330777",
INIT_5D => X"03743577050F55740959950F7705550735550B59335507330F35075555090705",
INIT_5E => X"7705557705555507556B55777755775509555577050977050977550555445533",
INIT_5F => X"55770988770B07778888778F9988777777777799073303337709777705555507",
INIT_60 => X"997709888877998877887788090077099988BBBB888899880B8877770B770B77",
INIT_61 => X"99770B5588778F097799887799880B000B995588550B7709880B558877777777",
INIT_62 => X"777755050F5505774777476B7705550F533577776B7407093377770709B69988",
INIT_63 => X"550F3377095905770777550F0577776B05555309553333775955050733770F53",
INIT_64 => X"0077556B05555309553333775955050733770F5305770374550077056B050753",
INIT_65 => X"77336B55770F09550F55550777550B770509050F55550707590F35050501F899",
INIT_66 => X"095559555555055555555555550F5907770F334747770977337477740F770599",
INIT_67 => X"09777D550553440977770F5577550B0555098F070735056B0977097D47550533",
INIT_68 => X"55440F33076B5577594459033509336B6B55595555770555778F077735055509",
INIT_69 => X"090777990900558807880059997777557707770B0535055503743533076B5577",
INIT_6A => X"0B778899770B0B770B09779988BB99779999888FBBBB88779977997788778877",
INIT_6B => X"0B777777B60B7788990B99770B77778899777709555588550B77770B88777788",
INIT_6C => X"057755557777770D6B550F530555777435590705740F77775505557777078809",
INIT_6D => X"557459053377533355470533090577033355770755595505770353550F473355",
INIT_6E => X"000709033355770755595505770353550F473355097755097709075503330977",
INIT_6F => X"556B05775555770555093309590F745509770955557705330F53550B7700D799",
INIT_70 => X"77054755770F55770F556B0909557405555555474747740555590F095555556B",
INIT_71 => X"990903777707330577775533096B445977055577470947557755990355770955",
INIT_72 => X"0759770F6B55094759550F5509057753474477076B5959770555777D09470F77",
INIT_73 => X"9077880777998809770755F805770B6B05470944770533555574097705534409",
INIT_74 => X"8877770B09D7778877998899990B77770B77999988998F7788770B8877097709",
INIT_75 => X"55000909007788777777880B77887777090B77887777097755880B7755888877",
INIT_76 => X"7405050577050555530F7705550F550555550FB6077733050977555533770577",
INIT_77 => X"094435550705090953530F557774057747473333093507550547095333535505",
INIT_78 => X"1055777747473333093507550547095333535505770507775533550577474733",
INIT_79 => X"09555907335574550933057747500507775577070905590974550F77550099F8",
INIT_7A => X"33550F0D5505550F44553555773307775505055905470577554705740F550959",
INIT_7B => X"7707550B0555555577330305075555355509770905557705330F7755550B556B",
INIT_7C => X"05997774770F777D4777336B77596B5955097435550F35555577093355775533",
INIT_7D => X"0B097788770B55777777550955555559775577075533470F0707550977073305",
INIT_7E => X"770B0088777777779977996B77777788770999998F9988990B88777777887788",
INIT_7F => X"770777770977777700777788770777009955550977558807075588770B775509",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"55746B77550F05557D95775555550F6B550F770999500F777705553303070555",
INIT_01 => X"33095505555577550F5555090555740547074747335553055505770F47550977",
INIT_02 => X"100F590547074747335553055505770F475509770574230509550F4705473347",
INIT_03 => X"7705350F77050555070F5307470B35770509555559097774595505054700D799",
INIT_04 => X"0F5555550F74077709050F770333550905350977096B4733556B6B05770F7733",
INIT_05 => X"47550F775505330955537755550977590F7709447455056B7433470F07770547",
INIT_06 => X"55550F55555555337D0F55554759550F557D74090933590F5509440F55050F74",
INIT_07 => X"9988000955770577056B55550F055505556B0577050555055533075505555555",
INIT_08 => X"77777709008809777788778855777777880B7777888809558855880955775577",
INIT_09 => X"6B77055555355555090777555509770009338855070055887707007755090777",
INIT_0A => X"05555577777709070707770755474755559909050753770777050B955507550F",
INIT_0B => X"0977055507050709553355776B05555509555507090505550555075505337705",
INIT_0C => X"00075555095555070905055505550755053377056B5555055505070555093355",
INIT_0D => X"0935740F5533093547055533070955334409550F09557707550577447700D799",
INIT_0E => X"055533550F593347550F055505770709054709550955057747050F7709555505",
INIT_0F => X"770F33775555553355335577555555550F5907770F3347477709773374770555",
INIT_10 => X"476B550F47550F555509770D337D4755057433075547550F5507775533473377",
INIT_11 => X"07097777550509550F0355775505550935445547553333330733357477090F77",
INIT_12 => X"7707777799777788097709778899007777777709777777885509778877007700",
INIT_13 => X"553309320905555555770900558809777709557788077707007709770D888855",
INIT_14 => X"4755550F05555595777705950755473535337777770F530F059977050B956B55",
INIT_15 => X"7455070553773555070F470503475533070553097407770577093507470F0547",
INIT_16 => X"10740533070553097407770577093507470F0547035555090547740733070953",
INIT_17 => X"5509553355055533090F550F097777070555055544093533335509353300BB99",
INIT_18 => X"55774705555059050955550909553344770B7705550F55550F7D500777050555",
INIT_19 => X"0505550F5505050F55090755056B0909557405555555474747740555590F0977",
INIT_1A => X"0F550D05555544595555075509555547033505556B7709550705550555474747",
INIT_1B => X"777755597755747D77770B077777595505777709090507333355330555555533",
INIT_1C => X"558805090B770077557788778809990B88777788778807770B88557709770977",
INIT_1D => X"0F77777777030907335555590755550977770077075500777709003300090955",
INIT_1E => X"05094755320F0509537709777705770F77095507073359770955097753075505",
INIT_1F => X"0535334705050533555577555505095547770577053305470577055547555509",
INIT_20 => X"0005335547770577053305470577055547555509550905743305057755470705",
INIT_21 => X"0577550955090977075505550555057705474705555505550533070F0500D7F8",
INIT_22 => X"074755556B0F595507077707075505770705097705550577550509330F777705",
INIT_23 => X"777D55059977597D555577093335557733077755050559054705775547050777",
INIT_24 => X"55055574070709770577557755556B7733353335350777335577557705595547",
INIT_25 => X"55550B4759557755557774550755477755590F7455550533470D550B5505050F",
INIT_26 => X"07777790557777058807770077990077448809558877778855770B7777777777",
INIT_27 => X"5505327705773353550977353355055555557709550999000055770977888877",
INIT_28 => X"77530B0F055555777755077755550F5505770974550535477733550555557709",
INIT_29 => X"0955090907530935050533050977530933095555090977095323090577050555",
INIT_2A => X"0009550933095555090977095323090577050555095305330977090709335555",
INIT_2B => X"35550B550574770574770933053374093305057709097709350977557701F899",
INIT_2C => X"5947470B55337709770955777709770555775509553355090947445505550955",
INIT_2D => X"3307556B55595555070505778F0F770333550905350977096B4733556B6B0955",
INIT_2E => X"556B550F6B7755555509550F59553507330755330F550333050905470977776B",
INIT_2F => X"557747557705550F55556B6B7709550F556B77057733550F7707057705777755",
INIT_30 => X"09880577888809550B0477880955887700557777880077099977778855885588",
INIT_31 => X"7755550977055553555933095309775577555505335507335509775533078877",
INIT_32 => X"5574773305330533557755090553053333057733530555555553097707050577",
INIT_33 => X"55330907057777550505530F0555745309550977550933077705770555050F55",
INIT_34 => X"1077075309550977550933077705770555050F55057435050507770753090509",
INIT_35 => X"09779507550977057733097733330705095555050B09475505745577070099F8",
INIT_36 => X"77090F05777707057709740F555509550907300B057709770955777705770907",
INIT_37 => X"7705470F773377776B33050907055505770709054709550955057747050F0905",
INIT_38 => X"77057777550F6B55706B777D555577550F350705055505775509055509555555",
INIT_39 => X"07749959555574550F557707770F330509747777746B5377097707550F350705",
INIT_3A => X"5533777755058855007709557707330999000955090777550000095509550977",
INIT_3B => X"05330F7774090307557755777735335505090577090555033355075555555507",
INIT_3C => X"5505070977550505330977440F555307557403550F3309554735333355337733",
INIT_3D => X"07550709555509530F0977090F55057707554409070777095533090F53090933",
INIT_3E => X"1033337707554409070777095533090F530909330F0533557744330577075544",
INIT_3F => X"0955333533055533053347050F7077097703550977770507550B07097700D799",
INIT_40 => X"774455770309550977550777050977330F5533550944330F530F077409030F53",
INIT_41 => X"773347330F7074097707550955770577055555550F5555550974095505097755",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_width is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_mid_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_mid_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => \douta[0]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3 downto 0) => \douta[3]\(3 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[1]\(0) => \douta[1]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[2]\(0) => \douta[2]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[3]\(0) => \douta[3]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_mid_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_mid_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_douta : STD_LOGIC;
signal ram_ena_n_0 : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_mid_bindec
port map (
addra(2 downto 0) => addra(14 downto 12),
ena_array(4 downto 0) => ena_array(4 downto 0)
);
\has_mux_a.A\: entity work.bg_mid_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0) => ram_douta,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_7\,
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(2 downto 0) => addra(14 downto 12),
clka => clka,
douta(11 downto 0) => douta(11 downto 0)
);
ram_ena: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(14),
O => ram_ena_n_0
);
\ramloop[0].ram.r\: entity work.bg_mid_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => ram_douta,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3) => \ramloop[1].ram.r_n_0\,
\douta[3]\(2) => \ramloop[1].ram.r_n_1\,
\douta[3]\(1) => \ramloop[1].ram.r_n_2\,
\douta[3]\(0) => \ramloop[1].ram.r_n_3\,
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(1),
\douta[1]\(0) => \ramloop[2].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(2),
\douta[2]\(0) => \ramloop[3].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(3),
\douta[3]\(0) => \ramloop[4].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[5].ram.r_n_0\,
\douta[11]\(6) => \ramloop[5].ram.r_n_1\,
\douta[11]\(5) => \ramloop[5].ram.r_n_2\,
\douta[11]\(4) => \ramloop[5].ram.r_n_3\,
\douta[11]\(3) => \ramloop[5].ram.r_n_4\,
\douta[11]\(2) => \ramloop[5].ram.r_n_5\,
\douta[11]\(1) => \ramloop[5].ram.r_n_6\,
\douta[11]\(0) => \ramloop[5].ram.r_n_7\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[6].ram.r_n_0\,
\douta[11]\(6) => \ramloop[6].ram.r_n_1\,
\douta[11]\(5) => \ramloop[6].ram.r_n_2\,
\douta[11]\(4) => \ramloop[6].ram.r_n_3\,
\douta[11]\(3) => \ramloop[6].ram.r_n_4\,
\douta[11]\(2) => \ramloop[6].ram.r_n_5\,
\douta[11]\(1) => \ramloop[6].ram.r_n_6\,
\douta[11]\(0) => \ramloop[6].ram.r_n_7\,
ena_array(0) => ena_array(1),
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[7].ram.r_n_0\,
\douta[11]\(6) => \ramloop[7].ram.r_n_1\,
\douta[11]\(5) => \ramloop[7].ram.r_n_2\,
\douta[11]\(4) => \ramloop[7].ram.r_n_3\,
\douta[11]\(3) => \ramloop[7].ram.r_n_4\,
\douta[11]\(2) => \ramloop[7].ram.r_n_5\,
\douta[11]\(1) => \ramloop[7].ram.r_n_6\,
\douta[11]\(0) => \ramloop[7].ram.r_n_7\,
ena_array(0) => ena_array(2),
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[8].ram.r_n_0\,
\douta[11]\(6) => \ramloop[8].ram.r_n_1\,
\douta[11]\(5) => \ramloop[8].ram.r_n_2\,
\douta[11]\(4) => \ramloop[8].ram.r_n_3\,
\douta[11]\(3) => \ramloop[8].ram.r_n_4\,
\douta[11]\(2) => \ramloop[8].ram.r_n_5\,
\douta[11]\(1) => \ramloop[8].ram.r_n_6\,
\douta[11]\(0) => \ramloop[8].ram.r_n_7\,
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized8\
port map (
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_mid_blk_mem_gen_top;
architecture STRUCTURE of bg_mid_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_mid_blk_mem_gen_generic_cstr
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_mid_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_mid_blk_mem_gen_top
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_mid_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_mid_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_mid_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_mid_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_mid_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_mid_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_mid_blk_mem_gen_v8_3_5_synth
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_mid : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_mid : entity is "bg_mid,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_mid : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_mid;
architecture STRUCTURE of bg_mid is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_mid_blk_mem_gen_v8_3_5
port map (
addra(14 downto 0) => addra(14 downto 0),
addrb(14 downto 0) => B"000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(14 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(14 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(14 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(14 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev10.vhd | 1 | 38449 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev10 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev10 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : integer;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= 0;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(std_logic_vector(mvect(rcount))))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)))))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/win/win_stub.vhdl | 2 | 1344 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:35:24 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/win_1/win_stub.vhdl
-- Design : win
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity win is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end win;
architecture stub of win is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| gpl-3.0 |
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