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malkolmalburquenque/PipelinedProcessor | VHDL/signextender.vhd | 1 | 585 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY signextender IS
PORT (
immediate_in: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
immediate_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END signextender;
ARCHITECTURE Behavioral OF signextender IS
BEGIN
process (immediate_in)
begin
--Only Sign extend at the moment
if immediate_in(15) = '1' then
immediate_out(31 downto 16) <= "1000000000000000";
else
immediate_out(31 downto 16) <= "0000000000000000";
end if;
immediate_out(15 downto 0) <= immediate_in;
end process;
END Behavioral;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/instructionMemory.vhd | 1 | 2292 | --Adapted from Example 12-15 of Quartus Design and Synthesis handbook
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionMemory IS
GENERIC(
-- might need to change it
ram_size : INTEGER := 1024;
mem_delay : time := 1 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END instructionMemory;
ARCHITECTURE rtl OF instructionMemory IS
TYPE MEM IS ARRAY(ram_size-1 downto 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to ram_size-1;
SIGNAL write_waitreq_reg: STD_LOGIC := '1';
SIGNAL read_waitreq_reg: STD_LOGIC := '1';
BEGIN
--This is the main section of the SRAM model
mem_process: PROCESS (clock)
FILE f : text;
variable row : line;
variable rowData : std_logic_vector(31 downto 0);
variable rowCounter : integer:=0;
BEGIN
--This is a cheap trick to initialize the SRAM in simulation
IF(now < 1 ps)THEN
file_open(f,"program.txt.",READ_MODE);
while (not endfile(f)) loop
readline(f,row);
read(row,rowData);
ram_block(rowCounter) <= rowData;
rowCounter := rowCounter + 1;
end loop;
end if;
file_close(f);
--This is the actual synthesizable SRAM block
IF (clock'event AND clock = '1') THEN
IF (memwrite = '1') THEN
ram_block(address) <= writedata;
END IF;
read_address_reg <= address;
END IF;
END PROCESS;
readdata <= ram_block(read_address_reg);
--The waitrequest signal is used to vary response time in simulation
--Read and write should never happen at the same time.
waitreq_w_proc: PROCESS (memwrite)
BEGIN
IF(memwrite'event AND memwrite = '1')THEN
write_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitreq_r_proc: PROCESS (memread)
BEGIN
IF(memread'event AND memread = '1')THEN
read_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitrequest <= write_waitreq_reg and read_waitreq_reg;
END rtl;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/alu_tb.vhd | 1 | 2454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY alu_tb IS
END alu_tb;
ARCHITECTURE behav of alu_tb IS
COMPONENT alu IS
PORT(
input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
SIGNAL clock: STD_LOGIC := '0';
CONSTANT clock_period : time := 1 ns;
SIGNAL input_a : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL input_b : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sel : STD_LOGIC_VECTOR(4 downto 0);
SIGNAL out_alu : STD_LOGIC_VECTOR (31 downto 0);
BEGIN
alutest : alu
PORT MAP(
input_a => input_a,
input_b => input_b,
SEL => sel,
out_alu => out_alu
);
clock_process : PROCESS
BEGIN
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
END PROCESS;
test_process : PROCESS
BEGIN
wait for clock_period;
-- ADD
input_a <= "00000000000000000000000000000000";
input_b <= "00000000000000000000000000000001";
sel <= "00000";
wait for clock_period;
--SUBTRACT
input_a <= "00000000000000000000000000000001";
input_b <= "00000000000000000000000000000001";
sel <= "00001";
wait for clock_period;
--SLL
input_a <= "00000000000000000000000000000010";
input_b <= "00000000000000000000000100000000";
sel <= "10001";
wait for clock_period;
--MUL1
input_a <= "00000000000000000000000000000100";
input_b <= "00000000000000000000001000000000";
sel <= "00011";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--MUL2
input_a <= "10000000000000000000000000000000";
input_b <= "00000000010000000000000000000000";
sel <= "00011";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--DIV1
input_a <= "00000000000000000000000000001000";
input_b <= "00000000000000000000000000000010";
sel <= "00100";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--DIV2
input_a <= "00000000000000000000000000001000";
input_a <= "00000000000000000000000000000011";
sel <= "00100";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
WAIT;
END PROCESS;
END behav;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/controller_tb.vhd | 1 | 2699 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity controller_tb is
end controller_tb;
architecture controller_tb_arch of controller_tb is
component controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal opcodeInput,functInput : std_logic_vector(5 downto 0);
signal ALU1srcO,ALU2srcO,MemReadO,MemWriteO,RegWriteO,MemToRegO : std_logic;
signal output : std_logic_vector(4 downto 0);
begin
controllerTest : controller
port map(
clk => clk,
opcode => opcodeInput,
funct => functInput,
ALU1src => ALU1srcO,
ALU2src => ALU2srcO,
MemRead => MemReadO,
MemWrite => MemWriteO,
RegWrite => RegWriteO,
MemToReg => MemToRegO,
ALUOp => output
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
report "STARTING SIMULATION \n";
opcodeInput <= "100000";
functInput <= "000000";
wait for clk_period;
opcodeInput <= "100010";
wait for clk_period;
opcodeInput <= "001000";
wait for clk_period;
opcodeInput <= "101010";
wait for clk_period;
opcodeInput <= "001010";
wait for clk_period;
opcodeInput <= "100100";
wait for clk_period;
opcodeInput <= "100101";
wait for clk_period;
opcodeInput <= "100111";
wait for clk_period;
opcodeInput <= "100110";
wait for clk_period;
opcodeInput <= "001100";
wait for clk_period;
opcodeInput <= "001101";
wait for clk_period;
opcodeInput <= "001110";
wait for clk_period;
opcodeInput <= "001111";
wait for clk_period;
opcodeInput <= "000010";
wait for clk_period;
opcodeInput <= "100011";
wait for clk_period;
opcodeInput <= "101011";
wait for clk_period;
opcodeInput <= "000100";
wait for clk_period;
opcodeInput <= "000101";
wait for clk_period;
opcodeInput <= "000011";
wait for clk_period;
--OPCODE WITH FUNCT
opcodeInput <= "000000";
wait for clk_period;
functInput <= "011010";
wait for clk_period;
functInput <= "011000";
wait for clk_period;
functInput <= "000011";
wait for clk_period;
functInput <= "001010";
wait for clk_period;
functInput <= "001100";
wait;
end process;
end controller_tb_arch; | gpl-3.0 |
LarbiBekka34/miniproject-vhdl | Ripple_Carry_Adder/RCA_64.vhd | 1 | 2106 | -------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--64-bit Kogge-Stone adder is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------
-------------------------------------------------------
-- Project : Computer arithmetic, fast adders (3rd year mini project)
-- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi
-- Date : 10-05-2014
-- File : RCA_64.vhd
-- Design : 64-bit Ripple-Carry Adder
------------------------------------------------------
-- Description : a 64-bit Ripple-Carry Adder
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY RCA_64 IS
PORT(x : IN std_logic_vector(63 downto 0);
y : IN std_logic_vector(63 downto 0);
c_in : IN std_logic;
sum : OUT std_logic_vector(63 downto 0);
c_o : OUT std_logic;
END RCA_64;
ARCHITECTURE arch OF RCA_64 IS
SIGNAL in_c : std_logic_vector(64 downto 0);
BEGIN
inconc_c(0) <= c_in;
for_gen:
FOR i in 0 to 63 GENERATE
sum(i) <= x(i) XOR y(i) XOR inconc_c(i);
in_c(i+1) <= (x(i) AND y(i)) OR (inconc_c(i) AND x(i)) OR (inconc_c(i) AND y(i));
END GENERATE;
c_o <= in_c(64);
END arch;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/PC.vhd | 1 | 505 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pc is
port(clk : in std_logic;
reset : in std_logic;
counterOutput : out std_logic_vector(31 downto 0);
counterInput : in std_logic_vector(31 downto 0) := x"00000000"
);
end pc;
architecture pc_arch of pc is
begin
process (clk,reset)
begin
if (reset = '1') then
counterOutput <= x"00000000";
elsif (clk'event and clk = '1') then
counterOutput <= counterInput;
end if;
end process;
end pc_arch;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/Controller.vhd | 1 | 8006 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
branch: in std_logic;
oldBranch: in std_logic;
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
RType: out STD_LOGIC;
JType: out STD_LOGIC;
Shift: out STD_LOGIC;
structuralStall : out STD_LOGIC;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end controller;
architecture controller_arch of controller is
begin
process (opcode,funct)
begin
--Send empty ctrl insturctions
if (branch = '1') or (oldBranch = '1') then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "00000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
else
case opcode is
-- SLL PADED BY SIGN EXTEND TO DO OUTPUT 17
when "000000" =>
if funct = "000000" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10001";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--SUB OUTPUT 1
elsif funct = "100010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00001";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--XOR OUTPUT 10
elsif funct = "101000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01010";
RType <= '1';
Shift <= '0';
structuralStall <= '0';
--AND OUTPUT 7
elsif funct = "100100" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00111";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ADD OUTPUT 0
elsif funct = "100000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SLT OUTPUT 5
elsif funct = "101010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00101";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SRL PADED BY SIGN EXTEND OUTPUT 18
elsif funct = "000010" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10010";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--OR OUTPUT 8
elsif funct = "100101" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--NOR OUTPUT 9
elsif funct = "100111" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01001";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--JUMP REGISTER OUTPUT 25
elsif funct = "001000" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "11001";
RType <= '1';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
-- DIVIDING OUTPUT 4
elsif funct = "011010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00100";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- MULT OUTPUT 3
elsif funct = "011000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00011";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SRA OUTPUT 18
elsif funct = "000011" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10010";
RType <= '1';
JType <= '0';
structuralStall <= '0';
-- TO DO HIGH OUTPUT 14
elsif funct = "001010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01110";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--TO DO LOW OUTPUT 15
elsif funct = "001100" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01111";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
end if;
--ADDI OUTPUT 2
when "001000" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00010";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SLTI OUTPUT 6
when "001010" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00110";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ANDI OUTPUT 11
when "001100" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01011";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ORI OUTPUT 12
when "001101" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01100";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--XORI OUTPUT 13
when "001110" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01101";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--LUI OUTPUT 16
when "001111" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10000";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- LW OUTPUT 20
when "100011" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '1';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '1';
ALUOp <= "10100";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '1';
-- Store OUTPUT 21
when "101011" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '1';
RegWrite <= '0';
MemToReg <= '1';
ALUOp <= "10101";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- BEQ OUTPUT 22
when "000100" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "10110";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--BNE OUTPUT 23
when "000101" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "10111";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- JUMP OUTPUT 24
when "000010" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "11000";
RType <= '0';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
-- JUMP AND LINK OUTPUT 26
when "000011" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "11010";
RType <= '0';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
when others =>
end case;
end if;
end process;
end controller_arch;
| gpl-3.0 |
LarbiBekka34/miniproject-vhdl | Kogge_Stone_Adder/KSA_64.vhd | 1 | 4970 | -------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--64-bit Kogge-Stone adder is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------
-------------------------------------------------------
-- Project : Computer arithmetic, fast adders (3rd year mini project)
-- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi
-- Date : 10-05-2014
-- File : KSA_64.vhd
-- Design : 64-bit Kogge-Stone adder
------------------------------------------------------
-- Description : a 64-bit Kogge-Stone adder
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.KSA_pkg.all;
ENTITY KSA_64 IS
PORT(
x : IN std_logic_vector(63 downto 0);
y : IN std_logic_vector(63 downto 0);
c_in : IN std_logic;
sum : OUT std_logic_vector(63 downto 0);
c_out : OUT std_logic
);
END KSA_64;
ARCHITECTURE arch OF KSA_64 IS
--internal individual g,p signals--
SIGNAL g_in : std_logic_vector(63 downto 0);
SIGNAL p_in : std_logic_vector(63 downto 0);
--output g,p signals of each KS stage--
--stage 01
SIGNAL g_1 : std_logic_vector(63 downto 0);
SIGNAL p_1 : std_logic_vector(63 downto 0);
--stage 02
SIGNAL g_2 : std_logic_vector(63 downto 0);
SIGNAL p_2 : std_logic_vector(63 downto 0);
--stage 03
SIGNAL g_3 : std_logic_vector(63 downto 0);
SIGNAL p_3 : std_logic_vector(63 downto 0);
--stage 04
SIGNAL g_4 : std_logic_vector(63 downto 0);
SIGNAL p_4 : std_logic_vector(63 downto 0);
--stage 05
SIGNAL g_5 : std_logic_vector(63 downto 0);
SIGNAL p_5 : std_logic_vector(63 downto 0);
--stage 06
SIGNAL g_6 : std_logic_vector(63 downto 0);
SIGNAL p_6 : std_logic_vector(63 downto 0);
--internal carries--
SIGNAL c : std_logic_vector(63 downto 0);
--SIGNAL p_block : std_logic_vector(63 downto 0);
BEGIN
--generating stage00 g,p signals--
stg00:
FOR i IN 0 TO 63 GENERATE
pm: gp_gen PORT MAP (x => x(i) , y => y(i) , g => g_in(i) , p => p_in(i) );
END GENERATE;
--stage01 carry operations--
g_1(0) <= g_in(0);
p_1(0) <= p_in(0);
stg01:
FOR i IN 0 TO 62 GENERATE
pm: carry_op PORT MAP (g1 => g_in(i) , p1 => p_in(i) , g2 => g_in(i+1) , p2 => p_in(i+1) , go => g_1(i+1) , po => p_1(i+1) );
END GENERATE;
--stage02 carry operations--
buffa1:
FOR i IN 0 TO 1 GENERATE
g_2(i) <= g_1(i);
p_2(i) <= p_1(i);
END GENERATE;
stg02:
FOR i IN 0 TO 61 GENERATE
pm: carry_op PORT MAP (g1 => g_1(i) , p1 => p_1(i) , g2 => g_1(i+2) , p2 => p_1(i+2) , go => g_2(i+2) , po => p_2(i+2) );
END GENERATE;
--stage03 carry operations--
buffa2:
FOR i IN 0 TO 3 GENERATE
g_3(i) <= g_2(i);
p_3(i) <= p_2(i);
END GENERATE;
stg03:
FOR i IN 0 TO 59 GENERATE
pm: carry_op PORT MAP (g1 => g_2(i) , p1 => p_2(i) , g2 => g_2(i+4) , p2 => p_2(i+4) , go => g_3(i+4) , po => p_3(i+4) );
END GENERATE;
--stage04 carry operations--
buffa3:
FOR i IN 0 TO 7 GENERATE
g_4(i) <= g_3(i);
p_4(i) <= p_3(i);
END GENERATE;
stg04:
FOR i IN 0 TO 55 GENERATE
pm: carry_op PORT MAP (g1 => g_3(i) , p1 => p_3(i) , g2 => g_3(i+8) , p2 => p_3(i+8) , go => g_4(i+8) , po => p_4(i+8) );
END GENERATE;
--stage05 carry operations--
buffa4:
FOR i IN 0 TO 15 GENERATE
g_5(i) <= g_4(i);
p_5(i) <= p_4(i);
END GENERATE;
stg05:
FOR i IN 0 TO 47 GENERATE
pm: carry_op PORT MAP (g1 => g_4(i) , p1 => p_4(i) , g2 => g_4(i+16) , p2 => p_4(i+16) , go => g_5(i+16) , po => p_5(i+16) );
END GENERATE;
--stage06 carry operations--
buffa5:
FOR i IN 0 TO 31 GENERATE
g_6(i) <= g_5(i);
p_6(i) <= p_5(i);
END GENERATE;
stg06:
FOR i IN 0 TO 31 GENERATE
pm: carry_op PORT MAP (g1 => g_5(i) , p1 => p_5(i) , g2 => g_5(i+32) , p2 => p_5(i+32) , go => g_6(i+32) , po => p_6(i+32) );
END GENERATE;
c_gen:
FOR i IN 0 TO 63 GENERATE
c(i) <= g_6(i) OR (c_in AND p_6(i));
END GENERATE;
c_out <= c(63);
sum(0) <= c_in XOR p_in(0);
addin:
FOR i IN 1 TO 63 GENERATE
sum(i) <= c(i-1) XOR p_in(i);
END GENERATE;
END arch;
| gpl-3.0 |
malkolmalburquenque/PipelinedProcessor | VHDL/memory.vhd | 1 | 2428 | --Adapted from Example 12-15 of Quartus Design and Synthesis handbook
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY memory IS
GENERIC(
ram_size : INTEGER := 8192;
mem_delay : time := 0.5 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
writeToText : IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END memory;
ARCHITECTURE rtl OF memory IS
TYPE MEM IS ARRAY(ram_size-1 downto 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to ram_size-1;
SIGNAL write_waitreq_reg: STD_LOGIC := '1';
SIGNAL read_waitreq_reg: STD_LOGIC := '1';
BEGIN
process(writeToText)
file memoryFile : text open write_mode is "memory.txt";
variable outLine : line;
variable rowLine : integer := 0;
begin
if writeToText = '1' then
while (rowLine < 8192) loop
write(outLine, ram_block(rowLine));
writeline(memoryFile, outLine);
rowLine := rowLine + 1;
end loop;
end if;
end process;
--This is the main section of the SRAM model
mem_process: PROCESS (clock)
BEGIN
--This is a cheap trick to initialize the SRAM in simulation
IF(now < 1 ps)THEN
For i in 0 to ram_size-1 LOOP
ram_block(i) <= std_logic_vector(to_unsigned(0,32));
END LOOP;
end if;
--This is the actual synthesizable SRAM block
IF (clock'event AND clock = '1') THEN
IF (memwrite = '1') THEN
ram_block(address) <= writedata;
END IF;
END IF;
END PROCESS;
process (memread)
begin
IF (memread = '1')THEN
readdata <= ram_block(address);
END IF;
end process;
--The waitrequest signal is used to vary response time in simulation
--Read and write should never happen at the same time.
waitreq_w_proc: PROCESS (memwrite)
BEGIN
IF(memwrite'event AND memwrite = '1')THEN
write_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitreq_r_proc: PROCESS (memread)
BEGIN
IF(memread'event AND memread = '1')THEN
read_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitrequest <= write_waitreq_reg and read_waitreq_reg;
END rtl;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/sigma_delta_dac/vhdl_source/mash.vhd | 5 | 2882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/video/vhdl_source/sync_separator.vhd | 5 | 2599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_separator is
generic (
g_clock_mhz : natural := 50 );
port (
clock : in std_logic;
sync_in : in std_logic;
mute : out std_logic;
h_sync : out std_logic;
v_sync : out std_logic );
end sync_separator;
architecture low_level of sync_separator is
constant c_delay : integer := 50;
signal h_sync_i : std_logic := '0';
signal release : std_logic := '0';
signal sync_c : std_logic := '0';
signal sync_d1 : std_logic := '0';
signal sync_d2 : std_logic := '0';
signal v_sync_pre : std_logic := '0';
signal delay : integer range 0 to c_delay * g_clock_mhz := 0;
signal raw_c : std_logic;
signal raw_d1 : std_logic;
signal raw_d2 : std_logic;
signal line_count : unsigned(8 downto 0) := (others => '0');
begin
h_sync <= h_sync_i;
process(sync_in, release)
begin
if release='1' then
h_sync_i <= '0';
elsif falling_edge(sync_in) then
h_sync_i <= '1';
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
sync_c <= h_sync_i;
sync_d1 <= sync_c;
sync_d2 <= sync_d1;
-- raw_c <= sync_in;
-- raw_d1 <= raw_c;
-- raw_d2 <= raw_d1;
--
-- if raw_d1='0' and raw_d2='1' then -- falling edge
-- if delay /= 0 then
-- mute <= '1';
-- else
-- mute <= '0';
-- end if;
-- end if;
if (line_count < 4) or (line_count > 305) then
mute <= '1';
else
mute <= '0';
end if;
release <= '0';
if sync_d1='1' and sync_d2='0' then -- rising edge
delay <= c_delay * g_clock_mhz;
if v_sync_pre = '1' then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
elsif delay /= 0 then
delay <= delay - 1;
end if;
if delay = 1 then
v_sync_pre <= not sync_in; -- sample
release <= '1';
end if;
end if;
end process;
v_sync <= v_sync_pre;
end low_level;
| gpl-3.0 |
J-Rios/VHDL_Modules | 2.Secuencial/Counter.vhd | 1 | 2376 | ----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- RST ---------| RST | --
-- | Q |--------- Q[BITS-1:0] --
-- CE ---------| CE | --
-- | | --
-- | | --
-- CLK ---------| CLK TC |--------- TC --
-- | | --
-- ------------------- --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
----------------------------------------------------------------------------------
entity COUNTER is
Generic
(
BITS : INTEGER := 4
);
Port
(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end COUNTER;
----------------------------------------------------------------------------------
architecture Behavioral of COUNTER is
signal Qr : UNSIGNED (BITS-1 downto 0);
signal Qn : UNSIGNED (BITS-1 downto 0);
signal TCsignal : STD_LOGIC;
begin
process(RST, CLK, CE)
begin
if (CLK'event and CLK = '1') then -- Rising clock
if (CE = '1') then -- Clock enable active
if (RST = '1') then -- Reset active
Qr <= (others => '0'); -- Reset the count to zero
else
Qr <= Qn; -- Set the count
end if;
end if;
end if;
end process;
-- Next state logic
Qn <= Qr + 1; -- Increase the count
-- Output logic
Q <= std_logic_vector(Qr); -- Output vector
TC <= '1' when Qr = (2**BITS-1) else '0'; -- Tick-Count bit (End-count)
TCsignal <= TC;
CEO <= '1' when (TCsignal = '1' and CE = '1') else '0'; -- Clock Enable Out
end Behavioral;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/nano_cpu/vhdl_sim/nano_tb.vhd | 5 | 807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/iec_interface/vhdl_source/s3_iec.vhd | 5 | 6091 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_1400a.vhd | 4 | 9786 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/usb/vhdl_sim/tb_ulpi_host.vhd | 3 | 9976 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_logic := '0';
signal reset : std_logic;
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
begin
i_mut: entity work.ulpi_host
port map (
clock => clock,
reset => reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
do_reset => open,
power_en => open,
reset_done => '1',
speed => "10",
reset_pkt => '0',
reset_data => X"00",
reset_last => '0',
reset_valid => '0',
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_descr_ram: entity work.bram_model_32sp
generic map("descriptors", 9)
port map (
CLK => clock,
SSR => reset,
EN => descr_en,
WE => descr_we,
ADDR => descr_addr,
DI => descr_wdata,
DO => descr_rdata );
i_buf_ram: entity work.bram_model_8sp
generic map("buffer", 12)
port map (
CLK => clock,
SSR => reset,
EN => buf_en,
WE => buf_we,
ADDR => buf_addr,
DI => buf_wdata,
DO => buf_rdata );
b_tx_bfm: block
signal tx_delay : integer range 0 to 31 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
tx_ack <= '0';
user_next <= '0';
if tx_delay = 28 then -- transmit packet
user_next <= '1';
if user_last='1' and user_valid='1' then
tx_delay <= 0; -- done;
user_next <= '0';
end if;
elsif tx_delay = 0 then
if send_token='1' then
tx_delay <= 6;
tx_ack <= '1';
elsif send_handsh='1' then
tx_delay <= 4;
tx_ack <= '1';
elsif send_data='1' then
tx_ack <= '1';
if no_data='1' then
tx_delay <= 5;
else
tx_delay <= 31;
end if;
end if;
else
tx_delay <= tx_delay - 1;
end if;
end if;
end process;
tx_busy <= '0' when tx_delay = 0 else '1';
end block;
p_test: process
variable desc : h_mem_object;
variable buf : h_mem_object;
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
data_out <= pkt(i);
data_valid <= '1';
if i = pkt'left then
data_start <= '1';
else
data_start <= '0';
end if;
end loop;
wait until clock='1';
data_valid <= '0';
data_start <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
bind_mem_model("descriptors", desc);
bind_mem_model("buffer", buf);
wait until reset='0';
write_memory_32(desc, X"0000_0100", t_transaction_to_data((
transaction_type => control,
state => busy, -- activate
pipe_pointer => "00000",
transfer_length => to_unsigned(8, 11),
buffer_address => to_unsigned(100, 12) )));
write_memory_32(desc, X"0000_0104", t_transaction_to_data((
transaction_type => bulk,
state => busy, -- activate
pipe_pointer => "00001",
transfer_length => to_unsigned(60, 11),
buffer_address => to_unsigned(256, 12) )));
write_memory_32(desc, X"0000_0000", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(64, 11),
data_toggle => '0' ) ));
write_memory_32(desc, X"0000_0004", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(8, 11),
data_toggle => '0' ) ));
for i in 0 to 7 loop
write_memory_8(buf, std_logic_vector(to_unsigned(100+i,32)),
std_logic_vector(to_unsigned(33+i,8)));
end loop;
wait until tx_busy='0'; -- first sof token
wait until tx_busy='0'; -- setup token
wait until tx_busy='0'; -- setup data
wait until tx_busy='0'; -- retried setup token
wait until tx_busy='0'; -- retried setup data
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
-- control out
for i in 0 to 7 loop
wait until tx_busy='0'; -- out token
wait until tx_busy='0'; -- out data
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
end loop;
wait until tx_busy='0'; -- in token
assert tx_pid = c_pid_in
report "Expected in token! (pid = " & hstr(tx_pid) & ")"
severity error;
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_packet <= '1';
wait until clock='1';
valid_packet <= '0';
-- -- control in..
-- wait until send_token='1';
-- wait until tx_busy='0'; -- in token done
-- wait until clock='1';
-- wait until clock='1';
-- wait until clock='1';
-- packet((X"01", X"02", X"03", X"04", X"05", X"06"));
-- valid_packet <= '1';
-- wait until clock='1';
-- valid_packet <= '0';
wait;
end process;
end tb;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/busses/vhdl_source/io_bus_arbiter_pri.vhd | 4 | 2183 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity io_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_io_req_array(0 to g_ports-1);
resps : out t_io_resp_array(0 to g_ports-1);
req : out t_io_req;
resp : in t_io_resp );
end entity;
architecture rtl of io_bus_arbiter_pri is
signal req_i : t_io_req;
signal select_i : integer range 0 to g_ports-1;
signal select_c : integer range 0 to g_ports-1;
type t_state is (idle, busy);
signal state : t_state;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_io_req_init;
select_i <= 0;
for i in reqs'range loop
if reqs(i).read='1' or reqs(i).write='1' then
req_i <= reqs(i);
select_i <= i;
exit;
end if;
end loop;
end process;
p_access: process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
req <= req_i;
if req_i.read='1' then
select_c <= select_i;
state <= busy;
elsif req_i.write='1' then
select_c <= select_i;
state <= busy;
end if;
when busy =>
req <= reqs(select_c);
if resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
-- send the reply to everyone, but mask the acks to non-active clients
process(resp, select_c)
begin
for i in resps'range loop
resps(i) <= resp;
if i /= select_c then
resps(i).ack <= '0';
end if;
end loop;
end process;
end architecture;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/memory/vhdl_source/spram.vhd | 5 | 1660 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
address : in unsigned(g_depth_bits-1 downto 0);
rdata : out std_logic_vector(g_width_bits-1 downto 0);
wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
en : in std_logic := '1';
we : in std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of spram : entity is "yes";
end entity;
architecture xilinx of spram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_port: process(clock)
begin
if rising_edge(clock) then
if en = '1' then
if g_read_first then
rdata <= ram(to_integer(address));
end if;
if we = '1' then
ram(to_integer(address)) := wdata;
end if;
if not g_read_first then
rdata <= ram(to_integer(address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/memory/vhdl_source/dpram_rdw.vhd | 5 | 4658 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/1541/vhdl_sim/testcase_format.vhd | 5 | 931 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_mem_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":testcase_format:harness:iec_bfm:", iec);
bind_mem_model (":testcase_format:harness:sram", ram);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(iec, X"28"); -- Drive 8, Listen (I will talk)
iec_send_atn(iec, X"6F"); -- Open channel 15
iec_send_message(iec, "N:HALLO,66");
iec_send_atn(iec, X"3F"); -- Unlisten
wait;
end process;
harness: entity work.harness_1541;
end tb;
| gpl-3.0 |
J-Rios/VHDL_Modules | 1.Combinational/MUX_BCD.vhd | 1 | 1991 | ----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- A[BITS-1:0] ---------| A | --
-- B[BITS-1:0] ---------| B | --
-- C[BITS-1:0] ---------| C Z |--------- Z[BITS-1:0] --
-- D[BITS-1:0] ---------| D | --
-- | | --
-- S[1:0] ---------| S | --
-- | | --
-- ------------------- --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity MUX_BCD is
generic
(
BITS : INTEGER := 4
);
Port
(
A : in STD_LOGIC_VECTOR (BITS-1 downto 0);
B : in STD_LOGIC_VECTOR (BITS-1 downto 0);
C : in STD_LOGIC_VECTOR (BITS-1 downto 0);
D : in STD_LOGIC_VECTOR (BITS-1 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Z : out STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end MUX_BCD;
----------------------------------------------------------------------------------
architecture Behavioral of MUX_BCD is
begin
-- One option
Z <= A when S = "00" else
B when S = "01" else
C when S = "10" else
D when S = "11";
-- Other option
-- with S select Z <=
-- A when "00",
-- B when "01",
-- C when "10",
-- D when "11",
-- D when others; -- Dummy (Needed for simulation)
end Behavioral;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/1541/vhdl_sim/testcase_init.vhd | 5 | 950 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_init is
end testcase_init;
architecture tb of testcase_init is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_mem_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":testcase_init:harness:iec_bfm:", iec);
bind_mem_model (":testcase_init:harness:sram", ram);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(iec, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(iec, X"6F"); -- Open channel 15
iec_turnaround(iec); -- start to listen
iec_get_message(iec, msg);
iec_print_message(msg);
wait;
end process;
harness: entity work.harness_1541;
end tb;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v5_sdr_tb.vhd | 5 | 4403 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_sdr_tb is
end ext_mem_ctrl_v5_sdr_tb;
architecture tb of ext_mem_ctrl_v5_sdr_tb is
signal clock : std_logic := '1';
signal clock_shifted : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_req;
signal resp : t_mem_burst_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal MEM_A : std_logic_vector(14 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 15 ns; -- 270 degrees
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => MEM_A,
MEM_D => MEM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_burst_req_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '0'; -- write
-- req.read_writen <= '1'; -- read
req.request <= '1';
req.data_pop <= '1';
while true loop
wait until clock='1';
if resp.ready='1' then
req.address <= req.address + 4;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Q(0)='Z' then
MEM_D <= Q after 3.6 ns;
else
MEM_D <= Q after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/spi/vhdl_source/spi_peripheral.vhd | 5 | 3591 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_peripheral is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral;
architecture gideon of spi_peripheral is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" =>
do_send <= '1';
wdata <= bus_wdata;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= bus_wdata;
rate(8) <= bus_wdata(7);
end if;
when "10" =>
force_ss <= bus_wdata(0);
level_ss <= bus_wdata(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
if reset='1' then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
force_ss <= '0';
level_ss <= '1';
wdata <= (others => '0');
end if;
end if;
end process;
with bus_addr select bus_rdata <=
rdata when "00",
rate(7 downto 0) when "01",
busy & "00000" & level_ss & force_ss when "10",
crc_out when "11",
X"FF" when others;
end gideon;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/usb/vhdl_sim/tb_ulpi_bus.vhd | 3 | 3037 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/sid6581/vhdl_source/wave_map.vhd | 6 | 7491 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wave_map is
generic (
g_num_voices : integer := 8; -- 8 or 16, clock should then be 8 or 16 MHz, too!
g_sample_bits : integer := 8 );
port (
clock : in std_logic;
reset : in std_logic;
osc_val : in unsigned(23 downto 0);
carry_20 : in std_logic;
msb_other: in std_logic := '0';
ring_mod : in std_logic := '0';
test : in std_logic := '0';
voice_i : in unsigned(3 downto 0);
comb_mode: in std_logic;
enable_i : in std_logic;
wave_sel : in std_logic_vector(3 downto 0);
sq_width : in unsigned(11 downto 0);
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
wave_out : out unsigned(g_sample_bits-1 downto 0) );
end wave_map;
architecture Gideon of wave_map is
type noise_array_t is array (natural range <>) of unsigned(22 downto 0);
signal noise_reg : noise_array_t(0 to g_num_voices-1) := (others => (0 => '1', others => '0'));
type voice_array_t is array (natural range <>) of unsigned(g_sample_bits-1 downto 0);
signal voice_reg : voice_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type t_byte_array is array(natural range <>) of unsigned(7 downto 0);
constant c_wave_TP : t_byte_array(0 to 255) := (
16#FF# => X"FF", 16#F7# => X"F7", 16#EF# => X"EF", 16#E7# => X"E0",
16#FE# => X"FE", 16#F6# => X"F0", 16#EE# => X"E0", 16#E6# => X"00",
16#FD# => X"FD", 16#F5# => X"FD", 16#ED# => X"E0", 16#E5# => X"00",
16#FC# => X"F8", 16#F4# => X"80", 16#EC# => X"00", 16#E4# => X"00",
16#FB# => X"FB", 16#F3# => X"F0", 16#EB# => X"E0", 16#E3# => X"00",
16#FA# => X"F8", 16#F2# => X"08", 16#EA# => X"00", 16#E2# => X"00",
16#F9# => X"F0", 16#F1# => X"00", 16#E9# => X"00", 16#E1# => X"00",
16#F8# => X"80", 16#F0# => X"00", 16#E8# => X"00", 16#E0# => X"00",
16#DF# => X"DF", 16#DE# => X"D0", 16#DD# => X"C0", 16#DB# => X"C0",
16#D7# => X"C0", 16#CF# => X"C0", 16#BF# => X"BF", 16#BE# => X"B0",
16#BD# => X"A0", 16#B9# => X"80", 16#B7# => X"80", 16#AF# => X"80",
16#7F# => X"7F", 16#7E# => X"70", 16#7D# => X"70", 16#7B# => X"60",
16#77# => X"40", others => X"00" );
constant c_wave_TS : t_byte_array(0 to 255) := (
16#7F# => X"1E", 16#FE# => X"18", 16#FF# => X"3E", others => X"00" );
begin
process(clock)
variable noise_tmp : unsigned(22 downto 0);
variable voice_tmp : unsigned(g_sample_bits-1 downto 0);
variable triangle : unsigned(g_sample_bits-1 downto 0);
variable square : unsigned(g_sample_bits-1 downto 0);
variable sawtooth : unsigned(g_sample_bits-1 downto 0);
variable out_tmp : unsigned(g_sample_bits-1 downto 0);
variable new_bit : std_logic;
begin
if rising_edge(clock) then
-- take top of list
voice_tmp := voice_reg(0);
noise_tmp := noise_reg(0);
if reset='1' or test='1' then
noise_tmp := (others => '1'); -- seed not equal to zero
elsif carry_20='1' then
new_bit := noise_tmp(22) xor noise_tmp(21) xor noise_tmp(20) xor noise_tmp(15);
noise_tmp := noise_tmp(21 downto 0) & new_bit;
end if;
if osc_val(23)='1' then
triangle := not osc_val(22 downto 23-g_sample_bits);
else
triangle := osc_val(22 downto 23-g_sample_bits);
end if;
if ring_mod='1' and msb_other='0' then
triangle := not triangle;
end if;
sawtooth := osc_val(23 downto 24-g_sample_bits);
if osc_val(23 downto 12) < sq_width then
square := (others => '0');
else
square := (others => '1');
end if;
out_tmp := (others => '0');
case wave_sel is
when X"0" =>
out_tmp := voice_tmp;
when X"1" =>
out_tmp := triangle;
when X"2" =>
out_tmp := sawtooth;
when X"3" =>
if comb_mode='0' then
out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
c_wave_TS(to_integer(osc_val(23 downto 23-g_sample_bits)));
else -- 8580
out_tmp := triangle and sawtooth;
end if;
when X"4" =>
out_tmp := square;
when X"5" => -- combined triangle and square
if comb_mode='0' then
if square(0)='1' then
out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
c_wave_TP(to_integer(triangle(g_sample_bits-1 downto g_sample_bits-8)));
end if;
else -- 8580
out_tmp := triangle and square;
end if;
when X"6" => -- combined saw and pulse
if comb_mode='1' then
out_tmp := sawtooth and square;
end if;
when X"7" => -- combined triangle, saw and pulse
if comb_mode='1' then
out_tmp := triangle and sawtooth and square;
end if;
when X"8" =>
out_tmp(g_sample_bits-1) := noise_tmp(22); -- unsure.. 21?
out_tmp(g_sample_bits-2) := noise_tmp(20);
out_tmp(g_sample_bits-3) := noise_tmp(16);
out_tmp(g_sample_bits-4) := noise_tmp(13);
out_tmp(g_sample_bits-5) := noise_tmp(11);
out_tmp(g_sample_bits-6) := noise_tmp(7);
out_tmp(g_sample_bits-7) := noise_tmp(4);
out_tmp(g_sample_bits-8) := noise_tmp(2);
-- when X"9"|X"A"|X"B"|X"C"|X"D"|X"E"|X"F" =>
-- out_tmp := noise_tmp(20 downto 21-g_sample_bits);
-- noise_tmp := (others => '0');
when others =>
null;
end case;
if enable_i='1' then
noise_reg(g_num_voices-1) <= noise_tmp;
noise_reg(0 to g_num_voices-2) <= noise_reg(1 to g_num_voices-1);
voice_reg(g_num_voices-1) <= out_tmp;
voice_reg(0 to g_num_voices-2) <= voice_reg(1 to g_num_voices-1);
end if;
--out_tmp(out_tmp'high) := not out_tmp(out_tmp'high);
wave_out <= unsigned(out_tmp);
voice_o <= voice_i;
enable_o <= enable_i;
end if;
end process;
end Gideon;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/usb/vhdl_source/ulpi_bus.vhd | 3 | 7397 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_32_tb.vhd | 5 | 7761 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd | 3 | 2517 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_cpu_pkg is
-- Instruction bit 14..12: alu operation
-- Instruction bit 11: when 1, accu is updated
-- Instruction bit 15: when 0, flags are updated
-- Instruction Set (bit 10...0) are address when needed
-- ALU
constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
constant c_in : std_logic_vector(15 downto 11) := X"6" & '1'; -- ext
-- no update flags
constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- Specials
constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
constant c_branch : std_logic_vector(15 downto 14) := "11";
-- Branches (bit 10..0) are address
constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
-- ALU operations
constant c_alu_load : std_logic_vector(2 downto 0) := "000";
constant c_alu_or : std_logic_vector(2 downto 0) := "001";
constant c_alu_and : std_logic_vector(2 downto 0) := "010";
constant c_alu_xor : std_logic_vector(2 downto 0) := "011";
constant c_alu_add : std_logic_vector(2 downto 0) := "100";
constant c_alu_sub : std_logic_vector(2 downto 0) := "101";
end;
| gpl-3.0 |
J-Rios/VHDL_Modules | 3.Peripherals/UART/UART_Rx.vhd | 1 | 2375 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity UART_RX is
Generic
(
DBIT : integer := 8; -- # Data BITS
SB_TICK : integer := 16 -- # Stop BITS Tick (1 -> 16, 1.5 -> 24, 2 -> 32)
);
Port
(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RX : in STD_LOGIC;
S_TICK : in STD_LOGIC;
RX_DONE_TICK : out STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (7 downto 0)
);
end UART_RX;
-------------------------------------------------------------------------
architecture Behavioral of UART_RX is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
begin
-- FSMD state & data registers
process(CLK,RESET)
begin
if RESET='1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
elsif (CLK'event and CLK='1') then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end process;
-- Next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,S_TICK,RX)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
RX_DONE_TICK <='0';
case state_reg is
when idle =>
if RX='0' then
state_next <= start;
s_next <= (others=>'0');
end if;
when start =>
if (S_TICK = '1') then
if s_reg=7 then
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (S_TICK = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= RX & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (S_TICK = '1') then
RX_DONE_TICK <='1';
if s_reg=(SB_TICK-1) then
state_next <= idle;
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
DOUT <= b_reg;
end Behavioral;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/sid6581/vhdl_source/sid_io_regs_pkg.vhd | 5 | 2668 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_io_regs_pkg is
constant c_sid_voices : unsigned(3 downto 0) := X"0";
constant c_sid_filter_div : unsigned(3 downto 0) := X"1";
constant c_sid_base_left : unsigned(3 downto 0) := X"2";
constant c_sid_base_right : unsigned(3 downto 0) := X"3";
constant c_sid_snoop_left : unsigned(3 downto 0) := X"4";
constant c_sid_snoop_right : unsigned(3 downto 0) := X"5";
constant c_sid_enable_left : unsigned(3 downto 0) := X"6";
constant c_sid_enable_right : unsigned(3 downto 0) := X"7";
constant c_sid_extend_left : unsigned(3 downto 0) := X"8";
constant c_sid_extend_right : unsigned(3 downto 0) := X"9";
constant c_sid_wavesel_left : unsigned(3 downto 0) := X"A";
constant c_sid_wavesel_right : unsigned(3 downto 0) := X"B";
type t_sid_control is record
base_left : unsigned(11 downto 4);
snoop_left : std_logic;
enable_left : std_logic;
extend_left : std_logic;
comb_wave_left : std_logic;
base_right : unsigned(11 downto 4);
snoop_right : std_logic;
enable_right : std_logic;
extend_right : std_logic;
comb_wave_right : std_logic;
end record;
constant c_sid_control_init : t_sid_control := (
base_left => X"40",
snoop_left => '1',
enable_left => '1',
extend_left => '0',
comb_wave_left => '0',
base_right => X"40",
snoop_right => '1',
enable_right => '1',
extend_right => '0',
comb_wave_right => '0' );
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 7...1 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 4...1 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 4...3 are significant)
-- .. etc
end package;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/busses/vhdl_source/io_dummy.vhd | 5 | 468 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/zpu/vhdl_source/zpu_compare.vhd | 5 | 2270 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- oper input can have the following values, producing the following results
-- 000 => false
-- 001 => a = b
-- 010 => false
-- 011 => a = b
-- 100 => a < b
-- 101 => a <= b
-- 110 => a < b (unsigned)
-- 111 => a <= b (unsigned)
entity zpu_compare is
port (
a : in unsigned(31 downto 0);
b : in unsigned(31 downto 0);
oper : in std_logic_vector(2 downto 0);
y : out boolean );
end zpu_compare;
architecture gideon of zpu_compare is
signal result : boolean;
signal equal : boolean;
signal ext_a : signed(32 downto 0);
signal ext_b : signed(32 downto 0);
begin
equal <= (a = b);
ext_a(32) <= not oper(1) and a(31); -- if oper(1) is 1, then we'll do an unsigned compare = signed compare with '0' in front.
ext_b(32) <= not oper(1) and b(31); -- if oper(1) is 0, when we'll do a signed compare = extended signed with sign bit.
ext_a(31 downto 0) <= signed(a);
ext_b(31 downto 0) <= signed(b);
result <= (ext_a < ext_b);
process(oper, result, equal)
variable r : boolean;
begin
r := false;
if oper(0)='1' then
r := r or equal;
end if;
if oper(2)='1' then
r := r or result;
end if;
y <= r;
end process;
end gideon;
-- constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); -- 100100
-- constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); -- 100101
-- constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); -- 100110
-- constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); -- 100111
-- Note, the mapping is such, that for the opcodes above, the lower three bits of the opcode can be fed directly
-- into the compare unit.
-- constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); -- 101110
-- constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); -- 101111
-- For these operations, the decoder must do extra work.
-- TODO: make a smarter mapping to support EQ and NEQ without external decoding.
| gpl-3.0 |
etingi01/MIPS_with_multiplier-VHDL- | myNAND2.vhd | 1 | 1023 | ----------------------------------------------------------------------------------
-- Company: University of Cyprus, Department of Computer Science
-- Engineer: Dr. Petros Panayi
--
-- Create Date: 16:59:07 03/23/2007
-- Design Name:
-- Module Name: myNAND2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myNAND2 is
Port ( I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O : out STD_LOGIC);
end myNAND2;
architecture Behavioral of myNAND2 is
begin
O <= I1 NAND I2;-- after 1 ns;
end Behavioral;
| gpl-3.0 |
kuruoujou/ECE-337-USB-Data-Sniffer | source/sd_control.vhd | 1 | 10459 | -- $Id: $
-- File name: sd_control.vhd
-- Created: 2/20/2012
-- Author: Spencer Julian
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: SD CArd Control
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
entity sd_control is
port (
clk : in std_logic;
rst : in std_logic;
sd_clock : in std_logic;
fifo_empty : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk_mode : out std_logic;
tsr_load : out std_logic;
sd_enable : out std_logic;
clk_enable : out std_logic;
data_read : out std_logic
);
end entity sd_control;
architecture sd_arch of sd_control is
type sdState is (qs, start,syncClock,idle,spi,blank,chksum,ackWait,cmd1,cycWait,cmd25,beginWriteWait,writeStart,writeByte,endWrite);
signal sd, nextSd: sdState;
signal count1, nextCount1 : std_logic_vector(6 downto 0);
signal count2, nextCount2 : std_logic_vector(4 downto 0);
signal count3, nextCount3 : std_logic_vector(2 downto 0);
signal sdc, sd_clock1, sd_clock2 : std_logic;
begin
GREGI: process(rst, clk)
begin
if(rst = '0') then --reset
sd <= qs;
count1 <= "0000000";
count2 <= "00000";
count3 <= "000";
sd_clock1 <= '0';
sd_clock2 <= '0';
sdc <= '0';
elsif(rising_edge(clk)) then
sd <= nextSd; --next state
count1 <= nextCount1;
count2 <= nextCount2;
count3 <= nextCount3;
if (sd_clock2 = '0' and sd_clock1 = '1') then --sd clock edge detector
sdc <= '1';
else
sdc <= '0';
end if;
sd_clock2 <= sd_clock1;
sd_clock1 <= sd_clock;
end if;
end process GREGI;
NXT: process(sd,nextSd,sdc,data_in,fifo_empty,count1,count2,count3)
begin
-- defaults
nextSd <= sd;
nextCount1 <= (others => '0');
nextCount2 <= (others => '0');
nextCount3 <= (others => '0');
case sd is --outputs: data_out, clk_mode, tsr_load, sd_enable, clk_enable
when qs => --start state - should fix weird startup error with nextcount
if (sdc = '1') then nextSd <= syncClock;
else nextSd <= qs;
end if;
when start => --turn cs off (pull high), loop with syncClock 80 times
nextCount1 <= count1;
if (sdc = '1') then nextSd <= syncClock;
else nextSd <= start;
end if;
when syncClock => --loop with above 79 times (80th comes from idle state)
if (count1 = 77) then nextSd <= idle;
else nextCount1 <= count1 + 1;
nextSd <= start;
end if;
when idle => --reset nextcount, load cmd0 into tsr
if (sdc='1') then nextSd <= spi;
else nextSd <= idle;
end if;
when spi => --output command to sd card
if (sdc='1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= spi;
elsif(sdc='1' and count1 = 7) then nextSd <= blank;
else nextSd <= spi;
nextCount1 <= count1;
end if;
when blank => --output 4 blank bytes
if (sdc='1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= blank;
nextCount2 <= count2;
elsif(sdc='1' and count1 = 7 and count2 < 2) then nextSd <= blank;
nextCount2 <= count2 + 1;
elsif(sdc='1' and count1 = 7 and count2 = 2) then
nextSd <= chksum;
else nextSd <= blank;
nextCount2 <= count2;
nextCount1 <= count1;
end if;
when chksum => --output the checksum
if (sdc='1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= chksum;
elsif(sdc='1' and count1 = 7) then nextSd <= ackWait;
else nextSd <= chksum;
nextCount1 <= count1;
end if;
when ackWait => --wait for ack
nextCount3 <= count3;
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextCount2 <= count2;
nextSd <= ackWait;
elsif (sdc = '1' and count1 = 7 and count2 < 1) then nextCount2 <= count2 + 1;
nextSd <= ackWait;
elsif (sdc = '1' and count1 = 7 and count2 = 1 and count3 < 5) then
nextSd <= cmd1;
elsif (sdc = '1' and count1 = 7 and count2 = 1 and count3 = 5) then
nextSd <= cycWait;
else nextSd <= ackWait;
nextCount1 <= count1;
nextCount2 <= count2;
end if;
when cmd1 => --send command 1 (are you ready? signal)
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= cmd1;
nextCount3 <= count3;
elsif (sdc = '1' and count1 = 7 and count3 < 5) then nextCount3 <= count3 + 1;
nextSd <= ackWait;
else nextSd <= cmd1;
nextCount1 <= count1;
nextCount3 <= count3;
end if;
when cycWait => --wait for period (16 clocks)
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= cycWait;
nextCount2 <= count2;
elsif (sdc = '1' and count1 = 7) then
nextSd <= cmd25;
else nextSd <= cycWait;
nextCount1 <= count1;
end if;
when cmd25 => --send command 25 (begin write signal)
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= cmd25;
elsif (sdc = '1' and count1 = 7) then
nextSd <= beginWriteWait;
else nextSd <= cmd25;
nextCount1 <= count1;
end if;
when beginWriteWait => --wait for period (16 clocks)
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= beginWriteWait;
nextCount2 <= count2;
elsif (sdc = '1' and count1 = 7 and count2 < 1) then nextCount2 <= count2 + 1;
nextSd <= beginWriteWait;
elsif (sdc = '1' and count1 = 7 and count2 = 1) then
nextSd <= writeStart;
else nextSd <= beginWriteWait;
nextCount1 <= count1;
nextCount2 <= count2;
end if;
when writeStart => -- write start of packet
if (count1 = 7 and fifo_empty = '1') then
nextCount1 <= "0000111"; --want to continue back to this if/elsif condition
end if;
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= writeStart;
elsif (sdc = '1' and count1 = 7 and fifo_empty = '0') then
nextSd <= writeByte;
else nextSd <= writeStart;
nextCount1 <= count1;
end if;
when writeByte => --Write each byte out, pause if no byte to write
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= writeByte;
elsif (sdc = '1' and count1 = 7) then
nextSd <= endWrite;
else nextSd <= writeByte;
nextCount1 <= count1;
end if;
when endWrite => --write end of each byte, prepare for next byte
if (sdc = '1' and count1 < 7) then nextCount1 <= count1 + 1;
nextSd <= endWrite;
elsif (sdc = '1' and count1 = 7) then
nextSd <= beginWriteWait;
else nextSd <= endWrite;
nextCount1 <= count1;
end if;
when others => nextSd <= qs;
end case;
end process NXT;
THINGS: process(sd,nextSd,count1,count2,count3,data_in,fifo_empty)
begin
-- defaults
data_out <= "11111111";
clk_mode <= '1';
tsr_load <= '0';
sd_enable <= '0';
clk_enable <= '1';
data_read <= '0';
case sd is --outputs: data_out, clk_mode, tsr_load, sd_enable, clk_enable
when qs => --start state - should fix weird startup error with nextcount
clk_mode <= '0';
sd_enable <= '1';
when start => --turn cs off (pull high), loop with syncClock 80 times
clk_mode <= '0'; --0 for 400 kHz, 1 for 25 MHz-ish
sd_enable <= '1'; -- active low
when syncClock => --loop with above 79 times (80th comes from idle state)
clk_mode <= '0';
sd_enable <= '1';
when idle => --reset nextcount, load cmd0 into tsr
clk_mode <= '0';
data_out <= x"40";
tsr_load <= '1';
when spi => --output command to sd card
clk_mode <= '0';
if (count1 = 7) then --last bit outputed, load next thing
tsr_load <= '1';
end if;
when blank => --output 4 blank bytes
clk_mode <= '0';
if (count2 = 2 and count1 = 7) then --load checksum instead of blank
data_out <= x"95";
elsif (count2 < 2 and count1 = 7) then --load blank instead of checksum
data_out <= x"00";
end if;
if (count1 = 7) then --last bit outputed, load next thing
tsr_load <= '1';
end if;
when chksum => --output the checksum
clk_mode <= '0';
if (count1 = 7) then --last bit outputed, load next thing
tsr_load <= '1';
end if;
when ackWait => --wait for ack
clk_mode <= '0';
if (count1 = 7 and (count2 < 1 or count3 = 5)) then --last bit outputted, load next thing
tsr_load <= '1';
elsif (count1 = 7 and count2 = 1 and count3 < 5) then
tsr_load <= '1';
data_out <= x"41";
end if;
when cmd1 => --send command 1 (are you ready? signal)
clk_mode <='0';
if (count1 = 7 and count3 <= 4) then --last bit outputted, load next thing
tsr_load <= '1';
end if;
when cycWait => --wait for period (16 clocks)
if (count1 = 7) then --last bit outputted, load next thing
tsr_load <= '1';
data_out <= x"59"; -- prepare command 25
end if;
when cmd25 => --send command 25 (begin write signal)
if (count1 = 7) then --last bit outputted, load next thing
tsr_load <= '1';
end if;
when beginWriteWait => --wait for period (16 clocks)
if (count1 = 7 and count2 < 1) then --last bit outputted, load next thing
tsr_load <= '1';
elsif (count1 = 7 and count2 = 1) then
tsr_load <= '1';
data_out <= x"FC";
end if;
when writeStart => -- write start of packet
if (count1 = 7 and fifo_empty = '0') then --last bit outputted, load next thing
tsr_load <= '1';
data_out <= data_in;
data_read <= '1';
elsif (count1 = 7 and fifo_empty = '1') then
clk_enable <= '0'; --pause the clock while waiting for data in fifo
end if;
when writeByte =>
if (count1 = 7) then --last bit outputted, load next thing
tsr_load <= '1';
data_out <= x"3F";
end if;
when endWrite =>
if (count1 = 7) then --last bit outputted, load next thing
tsr_load <= '1';
data_out <= x"FF";
end if;
end case;
end process THINGS;
end sd_arch;
| gpl-3.0 |
etingi01/MIPS_with_multiplier-VHDL- | my32BitRegistersFile.vhd | 1 | 10085 | ----------------------------------------------------------------------------------
-- Company: University of Cyprus, Department of Computer Science
-- Engineer: Dr. Petros Panayi
--
-- Create Date: 16:40:29 03/25/2007
-- Design Name:
-- Module Name: my32BitRegistersFile - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity my32BitRegistersFile is
Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0);
ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0);
WriteRegister : in STD_LOGIC_VECTOR (4 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
ReadData1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData2 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData3 : out STD_LOGIC_VECTOR (31 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end my32BitRegistersFile;
architecture Behavioral of my32BitRegistersFile is
-- The Internal Registers are Decleared as Signals
signal REG00: STD_LOGIC_VECTOR(31 downto 0);
signal REG01: STD_LOGIC_VECTOR(31 downto 0);
signal REG02: STD_LOGIC_VECTOR(31 downto 0);
signal REG03: STD_LOGIC_VECTOR(31 downto 0);
signal REG04: STD_LOGIC_VECTOR(31 downto 0);
signal REG05: STD_LOGIC_VECTOR(31 downto 0);
signal REG06: STD_LOGIC_VECTOR(31 downto 0);
signal REG07: STD_LOGIC_VECTOR(31 downto 0);
signal REG08: STD_LOGIC_VECTOR(31 downto 0);
signal REG09: STD_LOGIC_VECTOR(31 downto 0);
signal REG10: STD_LOGIC_VECTOR(31 downto 0);
signal REG11: STD_LOGIC_VECTOR(31 downto 0);
signal REG12: STD_LOGIC_VECTOR(31 downto 0);
signal REG13: STD_LOGIC_VECTOR(31 downto 0);
signal REG14: STD_LOGIC_VECTOR(31 downto 0);
signal REG15: STD_LOGIC_VECTOR(31 downto 0);
signal REG16: STD_LOGIC_VECTOR(31 downto 0);
signal REG17: STD_LOGIC_VECTOR(31 downto 0);
signal REG18: STD_LOGIC_VECTOR(31 downto 0);
signal REG19: STD_LOGIC_VECTOR(31 downto 0);
signal REG20: STD_LOGIC_VECTOR(31 downto 0);
signal REG21: STD_LOGIC_VECTOR(31 downto 0);
signal REG22: STD_LOGIC_VECTOR(31 downto 0);
signal REG23: STD_LOGIC_VECTOR(31 downto 0);
signal REG24: STD_LOGIC_VECTOR(31 downto 0);
signal REG25: STD_LOGIC_VECTOR(31 downto 0);
signal REG26: STD_LOGIC_VECTOR(31 downto 0);
signal REG27: STD_LOGIC_VECTOR(31 downto 0);
signal REG28: STD_LOGIC_VECTOR(31 downto 0);
signal REG29: STD_LOGIC_VECTOR(31 downto 0);
signal REG30: STD_LOGIC_VECTOR(31 downto 0);
signal REG31: STD_LOGIC_VECTOR(31 downto 0);
begin
core_reg:PROCESS(clk, Reset)
begin
-- When the Reset is set to High all the values are set to Zero
if RESET = '1' then
case RESET is
when '1' =>
REG00 <= X"00000000";
REG01 <= X"00000000";
REG02 <= X"00000000";
REG03 <= X"00000000";
REG04 <= X"00000000";
REG05 <= X"00000000";
REG06 <= X"00000000";
REG07 <= X"00000000";
REG08 <= X"00000000";
REG09 <= X"00000022";
REG10 <= X"00000024";
REG11 <= X"00000800";
REG12 <= X"00000900";
REG13 <= X"00000000";
REG14 <= X"00001000";
REG15 <= X"00000000";
REG16 <= X"0000A100";
REG17 <= X"00000000";
REG18 <= X"00000000";
REG19 <= X"00008900";
REG20 <= X"00000000";
REG21 <= X"00000000";
REG22 <= X"00000000";
REG23 <= X"00000000";
REG24 <= X"00000000";
REG25 <= X"00000000";
REG26 <= X"00000000";
REG27 <= X"00000000";
REG28 <= X"00000000";
REG29 <= X"00000000";
REG30 <= X"00000000";
REG31 <= X"00000000";
when others => NULL;
end case;
elsif RegWrite = '1' and FALLING_EDGE(clk) then
case WriteRegister is
when "00000" => REG00 <= WriteData;
when "00001" => REG01 <= WriteData;
when "00010" => REG02 <= WriteData;
when "00011" => REG03 <= WriteData;
when "00100" => REG04 <= WriteData;
when "00101" => REG05 <= WriteData;
when "00110" => REG06 <= WriteData;
when "00111" => REG07 <= WriteData;
when "01000" => REG08 <= WriteData;
when "01001" => REG09 <= WriteData;
when "01010" => REG10 <= WriteData;
when "01011" => REG11 <= WriteData;
when "01100" => REG12 <= WriteData;
when "01101" => REG13 <= WriteData;
when "01110" => REG14 <= WriteData;
when "01111" => REG15 <= WriteData;
when "10000" => REG16 <= WriteData;
when "10001" => REG17 <= WriteData;
when "10010" => REG18 <= WriteData;
when "10011" => REG19 <= WriteData;
when "10100" => REG20 <= WriteData;
when "10101" => REG21 <= WriteData;
when "10110" => REG22 <= WriteData;
when "10111" => REG23 <= WriteData;
when "11000" => REG24 <= WriteData;
when "11001" => REG25 <= WriteData;
when "11010" => REG26 <= WriteData;
when "11011" => REG27 <= WriteData;
when "11100" => REG28 <= WriteData;
when "11101" => REG29 <= WriteData;
when "11110" => REG30 <= WriteData;
when "11111" => REG31 <= WriteData;
when others => NULL;
end case;
end if;
end process;
-----------------------------------------
-- Reading Data From the Registers File
-- We allow two inputs and two outputs
-----------------------------------------
-- REG_SS_SEL
ReadData1 <= REG00 when ReadRegister1 = "00000" else
REG01 when ReadRegister1 = "00001" else
REG02 when ReadRegister1 = "00010" else
REG03 when ReadRegister1 = "00011" else
REG04 when ReadRegister1 = "00100" else
REG05 when ReadRegister1 = "00101" else
REG06 when ReadRegister1 = "00110" else
REG07 when ReadRegister1 = "00111" else
REG08 when ReadRegister1 = "01000" else
REG09 when ReadRegister1 = "01001" else
REG10 when ReadRegister1 = "01010" else
REG11 when ReadRegister1 = "01111" else
REG12 when ReadRegister1 = "01100" else
REG13 when ReadRegister1 = "01101" else
REG14 when ReadRegister1 = "01110" else
REG15 when ReadRegister1 = "01111" else
REG16 when ReadRegister1 = "10000" else
REG17 when ReadRegister1 = "10001" else
REG18 when ReadRegister1 = "10010" else
REG19 when ReadRegister1 = "10011" else
REG20 when ReadRegister1 = "10100" else
REG21 when ReadRegister1 = "10101" else
REG22 when ReadRegister1 = "10110" else
REG23 when ReadRegister1 = "10111" else
REG24 when ReadRegister1 = "11000" else
REG25 when ReadRegister1 = "11001" else
REG26 when ReadRegister1 = "11010" else
REG27 when ReadRegister1 = "11011" else
REG28 when ReadRegister1 = "11100" else
REG29 when ReadRegister1 = "11101" else
REG30 when ReadRegister1 = "11110" else
REG31 when ReadRegister1 = "11111" else REG00;
ReadData2 <= REG00 when ReadRegister2 = "00000" else
REG01 when ReadRegister2 = "00001" else
REG02 when ReadRegister2 = "00010" else
REG03 when ReadRegister2 = "00011" else
REG04 when ReadRegister2 = "00100" else
REG05 when ReadRegister2 = "00101" else
REG06 when ReadRegister2 = "00110" else
REG07 when ReadRegister2 = "00111" else
REG08 when ReadRegister2 = "01000" else
REG09 when ReadRegister2 = "01001" else
REG10 when ReadRegister2 = "01010" else
REG11 when ReadRegister2 = "01011" else
REG12 when ReadRegister2 = "01100" else
REG13 when ReadRegister2 = "01101" else
REG14 when ReadRegister2 = "01110" else
REG15 when ReadRegister2 = "01111" else
REG16 when ReadRegister2 = "10000" else
REG17 when ReadRegister2 = "10001" else
REG18 when ReadRegister2 = "10010" else
REG19 when ReadRegister2 = "10011" else
REG20 when ReadRegister2 = "10100" else
REG21 when ReadRegister2 = "10101" else
REG22 when ReadRegister2 = "10110" else
REG23 when ReadRegister2 = "10111" else
REG24 when ReadRegister2 = "11000" else
REG25 when ReadRegister2 = "11001" else
REG26 when ReadRegister2 = "11010" else
REG27 when ReadRegister2 = "11011" else
REG28 when ReadRegister2 = "11100" else
REG29 when ReadRegister2 = "11101" else
REG30 when ReadRegister2 = "11110" else
REG31 when ReadRegister2 = "11111" else REG00;
ReadData3 <= REG00 when WriteRegister = "00000" else
REG01 when WriteRegister = "00001" else
REG02 when WriteRegister = "00010" else
REG03 when WriteRegister = "00011" else
REG04 when WriteRegister = "00100" else
REG05 when WriteRegister = "00101" else
REG06 when WriteRegister = "00110" else
REG07 when WriteRegister = "00111" else
REG08 when WriteRegister = "01000" else
REG09 when WriteRegister = "01001" else
REG10 when WriteRegister = "01010" else
REG11 when WriteRegister = "01011" else
REG12 when WriteRegister = "01100" else
REG13 when WriteRegister = "01101" else
REG14 when WriteRegister = "01110" else
REG15 when WriteRegister = "01111" else
REG16 when WriteRegister = "10000" else
REG17 when WriteRegister = "10001" else
REG18 when WriteRegister = "10010" else
REG19 when WriteRegister = "10011" else
REG20 when WriteRegister = "10100" else
REG21 when WriteRegister = "10101" else
REG22 when WriteRegister = "10110" else
REG23 when WriteRegister = "10111" else
REG24 when WriteRegister = "11000" else
REG25 when WriteRegister = "11001" else
REG26 when WriteRegister = "11010" else
REG27 when WriteRegister = "11011" else
REG28 when WriteRegister = "11100" else
REG29 when WriteRegister = "11101" else
REG30 when WriteRegister = "11110" else
REG31 when WriteRegister = "11111" else REG00;
end Behavioral;
| gpl-3.0 |
pshdl/org.pshdl | src/pshdl_pkg.vhd | 1 | 21987 | -- PSHDL is a library and (trans-)compiler for PSHDL input. It generates
-- output suitable for implementation or simulation of it.
--
-- Copyright (C) 2013 Karsten Becker (feedback (at) pshdl (dot) org)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- This License does not grant permission to use the trade names, trademarks,
-- service marks, or product names of the Licensor, except as required for
-- reasonable and customary use in describing the origin of the Work.
--
--Contributors:
-- Karsten Becker - initial API and implementation
--Updated for version 0.1.80 on 2014-05-19
--Added log2ceil and log2floor
--Updated for version 0.1.75 on 2014-04-23
--Added ternary overload for boolean
--Added not overload for integer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ShiftOps is
function srlUint(arg: unsigned; s:natural) return unsigned;
function srlInt(arg: signed; s:natural) return signed;
function srlNatural(arg: natural; s:natural) return natural;
function srlInteger(arg: integer; s:natural) return integer;
function srlBit(arg: std_logic; s:natural) return std_logic;
function srlBitvector(arg: std_logic_vector; s:natural) return std_logic_vector;
function sraUint(arg: unsigned; s:natural) return unsigned;
function sraInt(arg: signed; s:natural) return signed;
function sraNatural(arg: natural; s:natural) return natural;
function sraInteger(arg: integer; s:natural) return integer;
function sraBit(arg: std_logic; s:natural) return std_logic;
function sraBitvector(arg: std_logic_vector; s:natural) return std_logic_vector;
function sllUint(arg: unsigned; s:natural) return unsigned;
function sllInt(arg: signed; s:natural) return signed;
function sllNatural(arg: natural; s:natural) return natural;
function sllInteger(arg: integer; s:natural) return integer;
function sllBit(arg: std_logic; s:natural) return std_logic;
function sllBitvector(arg: std_logic_vector; s:natural) return std_logic_vector;
end;
package body ShiftOps is
function sraBitvector(arg: std_logic_vector; s:natural) return std_logic_vector is
begin
return std_logic_vector(sraUint(unsigned(arg),s));
end sraBitvector;
function srlBitvector(arg: std_logic_vector; s:natural) return std_logic_vector is
begin
return std_logic_vector(srlUint(unsigned(arg),s));
end srlBitvector;
function sllBitvector(arg: std_logic_vector; s:natural) return std_logic_vector is
begin
return std_logic_vector(sllUint(unsigned(arg),s));
end sllBitvector;
function sraBit(arg: std_logic; s:natural) return std_logic is
begin
--The MSB is the bit itself, so it is returned
return arg;
end sraBit;
function srlBit(arg: std_logic; s:natural) return std_logic is
begin
if (s=0) then
return arg;
end if;
return '0';
end srlBit;
function sllBit(arg: std_logic; s:natural) return std_logic is
begin
if (s=0) then
return arg;
end if;
return '0';
end sllBit;
function srlUint(arg: unsigned; s:natural) return unsigned is
begin
return SHIFT_RIGHT(arg,s);
end srlUint;
function sraUint(arg: unsigned; s:natural) return unsigned is
begin
return SHIFT_RIGHT(arg,s);
end sraUint;
function sllUint(arg: unsigned; s:natural) return unsigned is
begin
return SHIFT_LEFT(arg,s);
end sllUint;
function srlInt(arg: signed; s:natural) return signed is
begin
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), s));
end srlInt;
function sraInt(arg: signed; s:natural) return signed is
begin
return SHIFT_RIGHT(arg,s);
end sraInt;
function sllInt(arg: signed; s:natural) return signed is
begin
return SHIFT_LEFT(arg,s);
end sllInt;
function srlInteger(arg: integer; s:natural) return integer is
begin
return to_integer(SHIFT_RIGHT(to_UNSIGNED(ARG,32), s));
end srlInteger;
function sraInteger(arg: integer; s:natural) return integer is
begin
return to_integer(SHIFT_RIGHT(to_SIGNED(arg,32),s));
end sraInteger;
function sllInteger(arg: integer; s:natural) return integer is
begin
return to_integer(SHIFT_LEFT(to_SIGNED(arg,32),s));
end sllInteger;
function srlNatural(arg: natural; s:natural) return natural is
begin
return to_integer(SHIFT_RIGHT(to_UNSIGNED(ARG,32), s));
end srlNatural;
function sraNatural(arg: natural; s:natural) return natural is
begin
return to_integer(SHIFT_RIGHT(to_UNSIGNED(arg,32),s));
end sraNatural;
function sllNatural(arg: natural; s:natural) return natural is
begin
return to_integer(SHIFT_LEFT(to_UNSIGNED(arg,32),s));
end sllNatural;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Casts is
function max (LEFT, RIGHT: INTEGER) return INTEGER ;
function min (LEFT, RIGHT: INTEGER) return INTEGER ;
function boolToBit(ARG: boolean) return std_logic;
function boolToBitvector(ARG: boolean) return std_logic_vector;
function boolToInt(ARG: boolean) return signed;
function boolToUint(ARG: boolean) return unsigned;
function boolToInteger(ARG: boolean) return integer;
function boolToNatural(ARG: boolean) return natural;
function intToUint (ARG : signed) return unsigned;
function intToBit (ARG : signed) return std_logic;
function intToBitvector (ARG : signed) return std_logic_vector;
function intToInteger (ARG : signed) return integer;
function intToNatural (ARG : signed) return natural;
function uintToInt (ARG : unsigned) return signed;
function uintToBit (ARG : unsigned) return std_logic;
function uintToBitvector (ARG : unsigned) return std_logic_vector;
function uintToInteger (ARG : unsigned) return integer;
function uintToNatural (ARG : unsigned) return natural;
function bitToInt (ARG : std_logic) return signed;
function bitToUint (ARG : std_logic) return unsigned;
function bitToBitvector (ARG : std_logic) return std_logic_vector;
function bitToInteger (ARG : std_logic) return integer;
function bitToNatural (ARG : std_logic) return natural;
function bitvectorToInt (ARG : std_logic_vector) return signed;
function bitvectorToUint (ARG : std_logic_vector) return unsigned;
function bitvectorToBit (ARG : std_logic_vector) return std_logic;
function bitvectorToInteger (ARG : std_logic_vector) return integer;
function bitvectorToNatural (ARG : std_logic_vector) return natural;
function integerToInt (ARG : integer) return signed;
function integerToUint (ARG : integer) return unsigned;
function integerToBit (ARG : integer) return std_logic;
function integerToBitvector (ARG : integer) return std_logic_vector;
function integerToNatural (ARG : integer) return natural;
function naturalToInt (ARG : natural) return signed;
function naturalToUint (ARG : natural) return unsigned;
function naturalToBit (ARG : natural) return std_logic;
function naturalToBitvector (ARG : natural) return std_logic_vector;
function naturalToInteger (ARG : natural) return integer;
function resizeSLV(S:std_logic_vector; NEWSIZE:natural) return std_logic_vector;
function resizeBit(S:std_logic; NEWSIZE:natural) return std_logic_vector;
function resizeInt(S:signed; NEWSIZE:natural) return signed;
function resizeUint(S:unsigned; NEWSIZE:natural) return unsigned;
function resizeInteger(S:integer; NEWSIZE:natural) return signed;
function resizeNatural(S:natural; NEWSIZE:natural) return unsigned;
end;
package body Casts is
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function boolToBit(ARG: boolean) return std_logic is
begin
if (ARG) then
return '1';
end if;
return '0';
end;
function boolToBitvector(ARG: boolean) return std_logic_vector is
begin
if (ARG) then
return "01";
end if;
return "00";
end;
function boolToInt(ARG: boolean) return signed is
begin
if (ARG) then
return "01";
end if;
return "00";
end;
function boolToUint(ARG: boolean) return unsigned is
begin
if (ARG) then
return "01";
end if;
return "00";
end;
function boolToInteger(ARG: boolean) return integer is
begin
if (ARG) then
return 1;
end if;
return 0;
end;
function boolToNatural(ARG: boolean) return natural is
begin
if (ARG) then
return 1;
end if;
return 0;
end;
function intToUint (ARG : signed) return unsigned is
begin
return unsigned(ARG);
end;
function intToBit (ARG : signed) return std_logic is
begin
if (ARG/=0) then
return '1';
else
return '0';
end if;
end;
function intToBitvector (ARG : signed) return std_logic_vector is
begin
return std_logic_vector(ARG);
end;
function intToInteger (ARG : signed) return integer is
begin
return to_integer(ARG);
end;
function uintToInt (ARG : unsigned) return signed is
begin
return signed(ARG);
end;
function uintToBit (ARG : unsigned) return std_logic is
begin
if (ARG/=0) then
return '1';
else
return '0';
end if;
end;
function uintToBitvector (ARG : unsigned) return std_logic_vector is
begin
return std_logic_vector(ARG);
end;
function uintToInteger (ARG : unsigned) return integer is
begin
return to_integer(signed(ARG));
end;
function bitToInt (ARG : std_logic) return signed is
begin
if (ARG/='0') then
return to_signed(1,2);
else
return to_signed(0,2);
end if;
end;
function bitToUint (ARG : std_logic) return unsigned is
begin
if (ARG/='0') then
return to_unsigned(1,2);
else
return to_unsigned(0,2);
end if;
end;
function bitToBitvector (ARG : std_logic) return std_logic_vector is
variable res: std_logic_vector(0 downto 0);
begin
res(0):=ARG;
return res;
end;
function bitToInteger (ARG : std_logic) return integer is
begin
if (ARG/='0') then
return 1;
else
return 0;
end if;
end;
function bitvectorToInt (ARG : std_logic_vector) return signed is
begin
return signed(ARG);
end;
function bitvectorToUint (ARG : std_logic_vector) return unsigned is
begin
return unsigned(ARG);
end;
function bitvectorToBit (ARG : std_logic_vector) return std_logic is
begin
if (ARG/=(ARG'range=>'0')) then
return '1';
else
return '0';
end if;
end;
function bitvectorToInteger (ARG : std_logic_vector) return integer is
begin
return to_integer(signed(ARG));
end;
function bitvectorToInt (ARG : signed) return signed is
begin
return ARG;
end;
function bitvectorToUint (ARG : signed) return unsigned is
begin
return unsigned(ARG);
end;
function bitvectorToBit (ARG : signed) return std_logic is
begin
if (ARG/=(ARG'range=>'0')) then
return '1';
else
return '0';
end if;
end;
function bitvectorToInteger (ARG : signed) return integer is
begin
return to_integer(signed(ARG));
end;
function bitvectorToInt (ARG : unsigned) return signed is
begin
return signed(ARG);
end;
function bitvectorToUint (ARG : unsigned) return unsigned is
begin
return ARG;
end;
function bitvectorToBit (ARG : unsigned) return std_logic is
begin
if (ARG/=(ARG'range=>'0')) then
return '1';
else
return '0';
end if;
end;
function bitvectorToInteger (ARG : unsigned) return integer is
begin
return to_integer(signed(ARG));
end;
function integerToInt (ARG : integer) return signed is
begin
return to_signed(ARG,32);
end;
function integerToUint (ARG : integer) return unsigned is
begin
return to_unsigned(ARG,32);
end;
function integerToBit (ARG : integer) return std_logic is
begin
if (ARG/=0) then
return '1';
else
return '0';
end if;
end;
function integerToBitvector (ARG : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(ARG,32));
end;
function intToNatural (ARG : signed) return natural is
begin
return to_integer(unsigned(ARG));
end;
function uintToNatural (ARG : unsigned) return natural is
begin
return to_integer('0'&ARG);
end;
function bitToNatural (ARG : std_logic) return natural is
begin
if (ARG/='0') then
return 1;
else
return 0;
end if;
end;
function bitvectorToNatural (ARG : std_logic_vector) return natural is
begin
return to_integer(unsigned(ARG));
end;
function bitvectorToNatural (ARG : unsigned) return natural is
begin
return to_integer(ARG);
end;
function bitvectorToNatural (ARG : signed) return natural is
begin
return to_integer(unsigned(ARG));
end;
function integerToNatural (ARG : integer) return natural is
begin
return ARG;
end;
function naturalToInt (ARG : natural) return signed is
begin
return to_signed(ARG,32);
end;
function naturalToUint (ARG : natural) return unsigned is
begin
return to_unsigned(ARG,32);
end;
function naturalToBit (ARG : natural) return std_logic is
begin
if (ARG/=0) then
return '1';
else
return '0';
end if;
end;
function naturalToBitvector (ARG : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(ARG,32));
end;
function naturalToInteger (ARG : natural) return integer is
begin
return ARG;
end;
function resizeSLV(S:std_logic_vector; NEWSIZE:natural) return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(S),NEWSIZE));
end;
function resizeBit(S:std_logic; NEWSIZE:natural) return std_logic_vector is
begin
return std_logic_vector(resize(bitToUint(S),NEWSIZE));
end;
function resizeNatural(S:natural; NEWSIZE:natural) return unsigned is
begin
return resize(integerToUint(S),NEWSIZE);
end;
function resizeInteger(S:integer; NEWSIZE:natural) return signed is
begin
return resize(integerToInt(S),NEWSIZE);
end;
function resizeUint(S:unsigned; NEWSIZE:natural) return unsigned is
begin
if (S'length=NEWSIZE) then
return S;
elsif (S'LENGTH>NEWSIZE) then
return S(NEWSIZE-1 downto 0);
else
return ((NEWSIZE-S'LENGTH)-1 downto 0 =>'0') & S;
end if;
end;
function resizeInt(S:signed; NEWSIZE:natural) return signed is
begin
if (S'length=NEWSIZE) then
return S;
elsif (S'LENGTH>NEWSIZE) then
return S(NEWSIZE-1 downto 0);
else
return ((NEWSIZE-S'LENGTH)-1 downto 0 =>S(S'LEFT)) & S;
end if;
end;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Casts.all;
use work.ShiftOps.all;
package Types is
function ternaryOp(condition: boolean; thenValue: integer; elseValue:integer) return integer;
function ternaryOp(condition: boolean; thenValue: boolean; elseValue:boolean) return boolean;
function ternaryOp(condition: boolean; thenValue: unsigned; elseValue:unsigned) return unsigned;
function ternaryOp(condition: boolean; thenValue: signed; elseValue:signed) return signed;
function ternaryOp(condition: boolean; thenValue: std_logic_vector; elseValue:std_logic_vector) return std_logic_vector;
function ternaryOp(condition: boolean; thenValue: std_logic; elseValue:std_logic) return std_logic;
function "not" (L: INTEGER) return INTEGER;
function log2ceil (L: POSITIVE) return NATURAL;
function log2floor (L: POSITIVE) return NATURAL;
function "or" (L: INTEGER; R: INTEGER) return INTEGER;
function "xor" (L: INTEGER; R: INTEGER) return INTEGER;
function "and" (L: INTEGER; R: INTEGER) return INTEGER;
function widthOf(a: std_logic_vector) return INTEGER;
function widthOf(a: unsigned) return INTEGER;
function widthOf(a: signed) return INTEGER;
function msbOf(a: std_logic_vector) return INTEGER;
function msbOf(a: unsigned) return INTEGER;
function msbOf(a: signed) return INTEGER;
end;
package body Types is
function ternaryOp(condition: boolean; thenValue: boolean; elseValue:boolean) return boolean is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function ternaryOp(condition: boolean; thenValue: integer; elseValue:integer) return integer is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function ternaryOp(condition: boolean; thenValue: unsigned; elseValue:unsigned) return unsigned is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function ternaryOp(condition: boolean; thenValue: signed; elseValue:signed) return signed is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function ternaryOp(condition: boolean; thenValue: std_logic_vector; elseValue:std_logic_vector) return std_logic_vector is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function ternaryOp(condition: boolean; thenValue: std_logic; elseValue:std_logic) return std_logic is
begin
if (condition) then
return thenValue;
else
return elseValue;
end if;
end ternaryOp;
function "not" (L: INTEGER) return INTEGER is
begin
return intToInteger(not resizeInteger(L,32));
end "not";
function log2ceil (L: POSITIVE) return NATURAL is
variable bitCount : natural;
variable i: unsigned(31 downto 0);
begin
i := to_UNSIGNED(L-1, 32);
bitCount:=0;
while (i > 0) loop
bitCount := bitCount + 1;
i:=SHIFT_RIGHT(i,1);
end loop;
return bitCount;
end log2ceil;
function log2floor (L: POSITIVE) return NATURAL is
variable bitCount : natural;
variable i: unsigned(31 downto 0);
begin
i := to_UNSIGNED(L,32);
bitCount:=0;
while (i > 1) loop
bitCount := bitCount + 1;
i:=SHIFT_RIGHT(i,1);
end loop;
return bitCount;
end log2floor;
function "or" (L: INTEGER; R: INTEGER) return INTEGER is
begin
return intToInteger(resizeInteger(L,32) or resizeInteger(R,32));
end "or";
function "xor" (L: INTEGER; R: INTEGER) return INTEGER is
begin
return intToInteger(resizeInteger(L,32) xor resizeInteger(R,32));
end "xor";
function "and" (L: INTEGER; R: INTEGER) return INTEGER is
begin
return intToInteger(resizeInteger(L,32) and resizeInteger(R,32));
end "and";
function widthOf(a: std_logic_vector) return INTEGER is
begin
return a'LENGTH;
end widthOf;
function widthOf(a: unsigned) return INTEGER is
begin
return a'LENGTH;
end widthOf;
function widthOf(a: signed) return INTEGER is
begin
return a'LENGTH;
end widthOf;
function msbOf(a: std_logic_vector) return INTEGER is
begin
return a'HIGH;
end msbOf;
function msbOf(a: unsigned) return INTEGER is
begin
return a'HIGH;
end msbOf;
function msbOf(a: signed) return INTEGER is
begin
return a'HIGH;
end msbOf;
end;
| gpl-3.0 |
kuruoujou/ECE-337-USB-Data-Sniffer | source/tb_SpiXmitSR.vhd | 1 | 2315 | -- $Id: $
-- File name: tb_XmitSR.vhd
-- Created: 3/2/2012
-- Author: David Kauer
-- Lab Section: 2
-- Version: 1.0 Initial Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_SpiXmitSR is
generic
(
srWidth : integer := 8;
CLK_PERIOD : Time := 10 ns
);
end tb_SpiXmitSR;
architecture TEST of tb_SpiXmitSR is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component SpiXmitSR
PORT(
clk : in std_logic;
resetN : in std_logic;
tsrEnable : in std_logic;
shiftCtrl : in std_logic;
tsrLoad : in std_logic;
tsrData : in std_logic_vector(srWidth-1 downto 0);
mosi : out std_logic
);
end component;
signal clk : std_logic;
signal resetN : std_logic;
signal tsrEnable : std_logic;
signal shiftCtrl : std_logic;
signal tsrLoad : std_logic;
signal tsrData : std_logic_vector(srWidth-1 downto 0);
signal mosi : std_logic;
begin
process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD/2;
end process;
DUT: SpiXmitSR port map(
clk => clk,
resetN => resetN,
tsrEnable => tsrEnable,
shiftCtrl => shiftCtrl,
tsrLoad => tsrLoad,
tsrData => tsrData,
mosi => mosi
);
process
begin
-- run for 400 ns
tsrEnable <= '0';
shiftCtrl <= '0';
tsrLoad <= '0';
tsrData <= "00000000";
-- Reset System
resetN <= '0';
wait for 10 ns;
resetN <= '1';
-- Load data into SR
tsrLoad <= '1';
tsrData <= "10101010";
wait for 10 ns;
tsrLoad <= '0';
-- Shift data out
shiftCtrl <= '1';
for i in 0 to 7 loop
tsrEnable <= '1';
wait for 10 ns;
tsrEnable <= '0';
wait for 40 ns;
end loop;
shiftCtrl <= '0';
wait for 10 ns;
-- Load data into SR
tsrLoad <= '1';
tsrData <= "11001100";
wait for 10 ns;
tsrLoad <= '0';
wait;
end process;
end TEST;
| gpl-3.0 |
etingi01/MIPS_with_multiplier-VHDL- | Tester_tb.vhd | 1 | 1887 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:48:40 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/Tester_tb.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Tester
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tester_tb IS
END Tester_tb;
ARCHITECTURE behavior OF Tester_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Tester
PORT(
A : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Outputs
signal A : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Tester PORT MAP (
A => A
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
kuruoujou/ECE-337-USB-Data-Sniffer | source/shift_greg.vhd | 1 | 1135 | Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Simple 8-bit shift register. Same as the one in Lab 5 except no STOP bit necessary.
ENTITY shift_greg is
port(clk, rst, shift_en, data_in: IN STD_LOGIC;
data_out: out STD_LOGIC_VECTOR(7 downto 0);
data_ready: out STD_LOGIC
);
end ENTITY;
architecture shift of shift_greg is
signal pre_val, nxt_val: STD_LOGIC_VECTOR(7 downto 0);
signal cnt, nxt_cnt: STD_LOGIC_VECTOR(2 downto 0);
signal nxt_data_ready, cur_data_ready: STD_LOGIC;
begin
se1: process(clk, rst)
begin
if rst = '0' then
pre_val <= x"00";
cur_data_ready <= '0';
cnt <= "000";
elsif (clk'event and clk = '1') then
pre_val <= nxt_val;
cnt <= nxt_cnt;
cur_data_ready <= nxt_data_ready;
end if;
end process;
nxt_data_ready <= '1' when (cnt = "000" AND rst = '1') else '0';
nxt_val <= data_in & pre_val(7 downto 1) when shift_en = '1'
else pre_val;
nxt_cnt <= cnt + 1 when shift_en = '1' else cnt;
data_out <= pre_val;
data_ready <= cur_data_ready;
end architecture;
| gpl-3.0 |
kuruoujou/ECE-337-USB-Data-Sniffer | source/FifoRead.vhd | 1 | 1286 | -- $Id: $
-- File name: SpiSlaveFifoRead
-- Created: 3/17/2012
-- Author: David Kauer
-- Lab Section:
-- Version: 1.0 Initial Design Entry
-- Description: SPI Slave Fifo Read Counter
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FifoRead is
generic
(
gregLength : integer := 16;
addrSize : integer := 4 -- 2^addrSize = gregLength
);
port (
clk : in std_logic;
resetN : in std_logic;
rEnable : in std_logic;
fifoEmpty : in std_logic;
rSel : out std_logic_vector(addrSize-1 downto 0)
);
end FifoRead;
architecture FifoRead_arch of FifoRead is
signal count,nextCount : std_logic_vector(addrSize-1 downto 0);
begin
process(clk,resetN)
begin
if resetN = '0' then
count <= (others => '0');
elsif rising_edge(clk) then
count <= nextCount;
end if;
end process;
nextCount <= count when fifoEmpty = '1' -- cannot read if fifo empty
else (others => '0') when ((conv_integer(count)) = gregLength-1) and rEnable = '1' -- reset
else count+1 when rEnable = '1' -- increment
else count;
rSel <= count;
end FifoRead_arch;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/syn/vhdl/contact_discovery_AXILiteS_s_axi.vhd | 3 | 16468 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
matched_finished :in STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x14 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x18 : Data signal of matched_finished
-- bit 31~0 - matched_finished[31:0] (Read)
-- 0x1c : reserved
-- 0x20 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x24 : reserved
-- 0x28 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#10#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#14#;
constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#18#;
constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#1c#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#20#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#24#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#28#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_MATCHED_FINISHED_DATA_0 =>
rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_finished <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_matched_finished <= UNSIGNED(matched_finished); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/syn/vhdl/contact_discoverybkb.vhd | 3 | 3125 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverybkb_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 13;
mem_size : integer := 8192
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverybkb_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverybkb is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 8192;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverybkb is
component contact_discoverybkb_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverybkb_ram_U : component contact_discoverybkb_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi/solution1/impl/vhdl/compare.vhd | 3 | 117905 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity compare is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
db_index : IN STD_LOGIC_VECTOR (30 downto 0);
contacts_index : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_address0 : OUT STD_LOGIC_VECTOR (12 downto 0);
contacts_ce0 : OUT STD_LOGIC;
contacts_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_address1 : OUT STD_LOGIC_VECTOR (12 downto 0);
contacts_ce1 : OUT STD_LOGIC;
contacts_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
database_address0 : OUT STD_LOGIC_VECTOR (14 downto 0);
database_ce0 : OUT STD_LOGIC;
database_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
database_address1 : OUT STD_LOGIC_VECTOR (14 downto 0);
database_ce1 : OUT STD_LOGIC;
database_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of compare is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (32 downto 0) := "000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (32 downto 0) := "000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (32 downto 0) := "000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (32 downto 0) := "000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (32 downto 0) := "000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (32 downto 0) := "000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (32 downto 0) := "000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (32 downto 0) := "000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (32 downto 0) := "000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (32 downto 0) := "001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (32 downto 0) := "010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (32 downto 0) := "100000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
constant ap_const_lv13_2 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000010";
constant ap_const_lv13_3 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000011";
constant ap_const_lv13_4 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000100";
constant ap_const_lv13_5 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000101";
constant ap_const_lv13_6 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000110";
constant ap_const_lv13_7 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000111";
constant ap_const_lv13_8 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001000";
constant ap_const_lv13_9 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001001";
constant ap_const_lv13_A : STD_LOGIC_VECTOR (12 downto 0) := "0000000001010";
constant ap_const_lv13_B : STD_LOGIC_VECTOR (12 downto 0) := "0000000001011";
constant ap_const_lv13_C : STD_LOGIC_VECTOR (12 downto 0) := "0000000001100";
constant ap_const_lv13_D : STD_LOGIC_VECTOR (12 downto 0) := "0000000001101";
constant ap_const_lv13_E : STD_LOGIC_VECTOR (12 downto 0) := "0000000001110";
constant ap_const_lv13_F : STD_LOGIC_VECTOR (12 downto 0) := "0000000001111";
constant ap_const_lv13_10 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010000";
constant ap_const_lv13_11 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010001";
constant ap_const_lv13_12 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010010";
constant ap_const_lv13_13 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010011";
constant ap_const_lv13_14 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010100";
constant ap_const_lv13_15 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010101";
constant ap_const_lv13_16 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010110";
constant ap_const_lv13_17 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010111";
constant ap_const_lv13_18 : STD_LOGIC_VECTOR (12 downto 0) := "0000000011000";
constant ap_const_lv13_19 : STD_LOGIC_VECTOR (12 downto 0) := "0000000011001";
constant ap_const_lv13_1A : STD_LOGIC_VECTOR (12 downto 0) := "0000000011010";
constant ap_const_lv13_1B : STD_LOGIC_VECTOR (12 downto 0) := "0000000011011";
constant ap_const_lv13_1C : STD_LOGIC_VECTOR (12 downto 0) := "0000000011100";
constant ap_const_lv13_1D : STD_LOGIC_VECTOR (12 downto 0) := "0000000011101";
constant ap_const_lv13_1E : STD_LOGIC_VECTOR (12 downto 0) := "0000000011110";
constant ap_const_lv13_1F : STD_LOGIC_VECTOR (12 downto 0) := "0000000011111";
constant ap_const_lv13_20 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100000";
constant ap_const_lv13_21 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100001";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv13_22 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100010";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv13_23 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100011";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv13_24 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100100";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv13_25 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100101";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv13_26 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100110";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv13_27 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100111";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv13_28 : STD_LOGIC_VECTOR (12 downto 0) := "0000000101000";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv13_29 : STD_LOGIC_VECTOR (12 downto 0) := "0000000101001";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv13_2A : STD_LOGIC_VECTOR (12 downto 0) := "0000000101010";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv13_2B : STD_LOGIC_VECTOR (12 downto 0) := "0000000101011";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv13_2C : STD_LOGIC_VECTOR (12 downto 0) := "0000000101100";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv13_2D : STD_LOGIC_VECTOR (12 downto 0) := "0000000101101";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv13_2E : STD_LOGIC_VECTOR (12 downto 0) := "0000000101110";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv13_2F : STD_LOGIC_VECTOR (12 downto 0) := "0000000101111";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv13_30 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110000";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv13_31 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110001";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv13_32 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110010";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv13_33 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110011";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv13_34 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110100";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv13_35 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110101";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv13_36 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110110";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv13_37 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110111";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv13_38 : STD_LOGIC_VECTOR (12 downto 0) := "0000000111000";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv13_39 : STD_LOGIC_VECTOR (12 downto 0) := "0000000111001";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv13_3A : STD_LOGIC_VECTOR (12 downto 0) := "0000000111010";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv13_3B : STD_LOGIC_VECTOR (12 downto 0) := "0000000111011";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv13_3C : STD_LOGIC_VECTOR (12 downto 0) := "0000000111100";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv13_3D : STD_LOGIC_VECTOR (12 downto 0) := "0000000111101";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv13_3E : STD_LOGIC_VECTOR (12 downto 0) := "0000000111110";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv13_3F : STD_LOGIC_VECTOR (12 downto 0) := "0000000111111";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal tmp_fu_1352_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_reg_2975 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_s_fu_1364_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_reg_3041 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_reg_3127 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal grp_fu_1342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_1_reg_3132 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp4_fu_1494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_3177 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_4_reg_3182 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal tmp_15_5_reg_3187 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp3_fu_1596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_3232 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_8_reg_3237 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_15_9_reg_3242 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal tmp11_fu_1691_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_3287 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_11_reg_3292 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal tmp_15_12_reg_3297 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp2_fu_1798_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_3342 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_15_reg_3347 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal tmp_15_16_reg_3352 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal tmp19_fu_1893_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_3397 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_19_reg_3402 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_15_20_reg_3407 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal tmp18_fu_1995_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_reg_3452 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_23_reg_3457 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal tmp_15_24_reg_3462 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal tmp26_fu_2090_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_reg_3507 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_27_reg_3512 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal tmp_15_28_reg_3517 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal tmp17_fu_2197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_reg_3562 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_31_reg_3567 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal tmp_15_32_reg_3572 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state19 : signal is "none";
signal tmp35_fu_2292_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_reg_3617 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_35_reg_3622 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
signal tmp_15_36_reg_3627 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none";
signal tmp34_fu_2394_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_reg_3672 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_39_reg_3677 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
signal tmp_15_40_reg_3682 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
signal tmp42_fu_2489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_reg_3727 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_43_reg_3732 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
signal tmp_15_44_reg_3737 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal tmp33_fu_2596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_reg_3782 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_47_reg_3787 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal tmp_15_48_reg_3792 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal tmp50_fu_2691_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_reg_3837 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_51_reg_3842 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal tmp_15_52_reg_3847 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state29 : signal is "none";
signal tmp49_fu_2793_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_reg_3892 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_55_reg_3897 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none";
signal tmp_15_56_reg_3902 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
signal tmp57_fu_2888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_reg_3947 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_59_reg_3952 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
signal tmp_15_60_reg_3957 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_1372_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_1377_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_1_fu_1388_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_1_fu_1399_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_2_fu_1409_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_2_fu_1419_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_3_fu_1429_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_3_fu_1439_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_4_fu_1449_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_4_fu_1459_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_5_fu_1469_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_5_fu_1479_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_6_fu_1505_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_6_fu_1515_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_7_fu_1525_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_7_fu_1535_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_8_fu_1545_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_8_fu_1555_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_9_fu_1565_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_9_fu_1575_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_s_fu_1606_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_s_fu_1616_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_10_fu_1626_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_10_fu_1636_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_11_fu_1646_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_11_fu_1656_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_12_fu_1666_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_12_fu_1676_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_13_fu_1702_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_13_fu_1712_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_14_fu_1722_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_14_fu_1732_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_15_fu_1742_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_15_fu_1752_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_16_fu_1762_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_16_fu_1772_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_17_fu_1808_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_17_fu_1818_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_18_fu_1828_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_18_fu_1838_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_19_fu_1848_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_19_fu_1858_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_20_fu_1868_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_20_fu_1878_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_21_fu_1904_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_21_fu_1914_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_22_fu_1924_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_22_fu_1934_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_23_fu_1944_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_23_fu_1954_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_24_fu_1964_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_24_fu_1974_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_25_fu_2005_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_25_fu_2015_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_26_fu_2025_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_26_fu_2035_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_27_fu_2045_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_27_fu_2055_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_28_fu_2065_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_28_fu_2075_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_29_fu_2101_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_29_fu_2111_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_30_fu_2121_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_30_fu_2131_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_31_fu_2141_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_31_fu_2151_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_32_fu_2161_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_32_fu_2171_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_33_fu_2207_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_33_fu_2217_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_34_fu_2227_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_34_fu_2237_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_35_fu_2247_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_35_fu_2257_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_36_fu_2267_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_36_fu_2277_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_37_fu_2303_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_37_fu_2313_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_38_fu_2323_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_38_fu_2333_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_39_fu_2343_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_39_fu_2353_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_40_fu_2363_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_40_fu_2373_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_41_fu_2404_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_41_fu_2414_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_42_fu_2424_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_42_fu_2434_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_43_fu_2444_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_43_fu_2454_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_44_fu_2464_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_44_fu_2474_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_45_fu_2500_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_45_fu_2510_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_46_fu_2520_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_46_fu_2530_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_47_fu_2540_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_47_fu_2550_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_48_fu_2560_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_48_fu_2570_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_49_fu_2606_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_49_fu_2616_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_50_fu_2626_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_50_fu_2636_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_51_fu_2646_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_51_fu_2656_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_52_fu_2666_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_52_fu_2676_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_53_fu_2702_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_53_fu_2712_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_54_fu_2722_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_54_fu_2732_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_55_fu_2742_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_55_fu_2752_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_56_fu_2762_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_56_fu_2772_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_57_fu_2803_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_57_fu_2813_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_58_fu_2823_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_58_fu_2833_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_59_fu_2843_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_59_fu_2853_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_60_fu_2863_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_60_fu_2873_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_61_fu_2899_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_61_fu_2909_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_62_fu_2919_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_62_fu_2929_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal tmp_127_fu_1348_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_128_fu_1360_p1 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_11_s_fu_1382_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_s_fu_1393_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_1_fu_1404_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_1_fu_1414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_2_fu_1424_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_2_fu_1434_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_3_fu_1444_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_3_fu_1454_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_4_fu_1464_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_4_fu_1474_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_fu_1488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_1484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_5_fu_1500_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_5_fu_1510_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_6_fu_1520_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_6_fu_1530_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_7_fu_1540_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_7_fu_1550_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_8_fu_1560_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_8_fu_1570_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp9_fu_1584_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_1580_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp7_fu_1590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_9_fu_1601_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_9_fu_1611_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_10_fu_1621_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_10_fu_1631_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_11_fu_1641_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_11_fu_1651_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_12_fu_1661_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_12_fu_1671_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_1685_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_1681_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_13_fu_1697_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_13_fu_1707_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_14_fu_1717_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_14_fu_1727_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_15_fu_1737_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_15_fu_1747_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_16_fu_1757_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_16_fu_1767_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_1781_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_1777_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_1787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_1793_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_17_fu_1803_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_17_fu_1813_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_18_fu_1823_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_18_fu_1833_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_19_fu_1843_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_19_fu_1853_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_20_fu_1863_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_20_fu_1873_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp21_fu_1887_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_1883_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_21_fu_1899_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_21_fu_1909_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_22_fu_1919_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_22_fu_1929_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_23_fu_1939_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_23_fu_1949_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_24_fu_1959_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_24_fu_1969_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp24_fu_1983_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_1979_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_1989_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_25_fu_2000_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_25_fu_2010_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_26_fu_2020_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_26_fu_2030_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_27_fu_2040_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_27_fu_2050_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_28_fu_2060_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_28_fu_2070_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp28_fu_2084_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp27_fu_2080_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_29_fu_2096_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_29_fu_2106_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_30_fu_2116_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_30_fu_2126_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_31_fu_2136_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_31_fu_2146_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_32_fu_2156_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_32_fu_2166_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp31_fu_2180_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp30_fu_2176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp29_fu_2186_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_2192_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_33_fu_2202_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_33_fu_2212_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_34_fu_2222_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_34_fu_2232_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_35_fu_2242_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_35_fu_2252_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_36_fu_2262_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_36_fu_2272_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp37_fu_2286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp36_fu_2282_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_37_fu_2298_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_37_fu_2308_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_38_fu_2318_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_38_fu_2328_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_39_fu_2338_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_39_fu_2348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_40_fu_2358_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_40_fu_2368_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp40_fu_2382_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp39_fu_2378_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp38_fu_2388_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_41_fu_2399_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_41_fu_2409_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_42_fu_2419_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_42_fu_2429_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_43_fu_2439_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_43_fu_2449_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_44_fu_2459_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_44_fu_2469_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp44_fu_2483_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp43_fu_2479_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_45_fu_2495_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_45_fu_2505_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_46_fu_2515_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_46_fu_2525_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_47_fu_2535_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_47_fu_2545_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_48_fu_2555_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_48_fu_2565_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp47_fu_2579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp46_fu_2575_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp45_fu_2585_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp41_fu_2591_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_49_fu_2601_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_49_fu_2611_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_50_fu_2621_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_50_fu_2631_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_51_fu_2641_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_51_fu_2651_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_52_fu_2661_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_52_fu_2671_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp52_fu_2685_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp51_fu_2681_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_53_fu_2697_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_53_fu_2707_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_54_fu_2717_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_54_fu_2727_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_55_fu_2737_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_55_fu_2747_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_56_fu_2757_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_56_fu_2767_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp55_fu_2781_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp54_fu_2777_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp53_fu_2787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_57_fu_2798_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_57_fu_2808_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_58_fu_2818_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_58_fu_2828_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_59_fu_2838_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_59_fu_2848_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_60_fu_2858_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_60_fu_2868_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp59_fu_2882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp58_fu_2878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_61_fu_2894_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_61_fu_2904_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_62_fu_2914_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_13_62_fu_2924_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp62_fu_2942_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp61_fu_2938_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp60_fu_2948_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp56_fu_2954_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp48_fu_2959_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp32_fu_2964_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp1_fu_2934_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_1_s_fu_2969_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_NS_fsm : STD_LOGIC_VECTOR (32 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
ap_return_preg <= found_1_s_fu_2969_p2;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
tmp11_reg_3287 <= tmp11_fu_1691_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state17)) then
tmp17_reg_3562 <= tmp17_fu_2197_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
tmp18_reg_3452 <= tmp18_fu_1995_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
tmp19_reg_3397 <= tmp19_fu_1893_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
tmp26_reg_3507 <= tmp26_fu_2090_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
tmp2_reg_3342 <= tmp2_fu_1798_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state25)) then
tmp33_reg_3782 <= tmp33_fu_2596_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state21)) then
tmp34_reg_3672 <= tmp34_fu_2394_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state19)) then
tmp35_reg_3617 <= tmp35_fu_2292_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
tmp3_reg_3232 <= tmp3_fu_1596_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state23)) then
tmp42_reg_3727 <= tmp42_fu_2489_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state29)) then
tmp49_reg_3892 <= tmp49_fu_2793_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
tmp4_reg_3177 <= tmp4_fu_1494_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state27)) then
tmp50_reg_3837 <= tmp50_fu_2691_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state31)) then
tmp57_reg_3947 <= tmp57_fu_2888_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_15_11_reg_3292 <= grp_fu_1336_p2;
tmp_15_12_reg_3297 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
tmp_15_15_reg_3347 <= grp_fu_1336_p2;
tmp_15_16_reg_3352 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
tmp_15_19_reg_3402 <= grp_fu_1336_p2;
tmp_15_20_reg_3407 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
tmp_15_1_reg_3132 <= grp_fu_1342_p2;
tmp_15_reg_3127 <= grp_fu_1336_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
tmp_15_23_reg_3457 <= grp_fu_1336_p2;
tmp_15_24_reg_3462 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
tmp_15_27_reg_3512 <= grp_fu_1336_p2;
tmp_15_28_reg_3517 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state18)) then
tmp_15_31_reg_3567 <= grp_fu_1336_p2;
tmp_15_32_reg_3572 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state20)) then
tmp_15_35_reg_3622 <= grp_fu_1336_p2;
tmp_15_36_reg_3627 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state22)) then
tmp_15_39_reg_3677 <= grp_fu_1336_p2;
tmp_15_40_reg_3682 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state24)) then
tmp_15_43_reg_3732 <= grp_fu_1336_p2;
tmp_15_44_reg_3737 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
tmp_15_47_reg_3787 <= grp_fu_1336_p2;
tmp_15_48_reg_3792 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_15_4_reg_3182 <= grp_fu_1336_p2;
tmp_15_5_reg_3187 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state28)) then
tmp_15_51_reg_3842 <= grp_fu_1336_p2;
tmp_15_52_reg_3847 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state30)) then
tmp_15_55_reg_3897 <= grp_fu_1336_p2;
tmp_15_56_reg_3902 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
tmp_15_59_reg_3952 <= grp_fu_1336_p2;
tmp_15_60_reg_3957 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp_15_8_reg_3237 <= grp_fu_1336_p2;
tmp_15_9_reg_3242 <= grp_fu_1342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_reg_2975(12 downto 6) <= tmp_fu_1352_p3(12 downto 6);
tmp_s_reg_3041(31 downto 6) <= tmp_s_fu_1364_p3(31 downto 6);
end if;
end if;
end process;
tmp_reg_2975(5 downto 0) <= "000000";
tmp_s_reg_3041(5 downto 0) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state14 <= ap_CS_fsm(13);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state19 <= ap_CS_fsm(18);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state20 <= ap_CS_fsm(19);
ap_CS_fsm_state21 <= ap_CS_fsm(20);
ap_CS_fsm_state22 <= ap_CS_fsm(21);
ap_CS_fsm_state23 <= ap_CS_fsm(22);
ap_CS_fsm_state24 <= ap_CS_fsm(23);
ap_CS_fsm_state25 <= ap_CS_fsm(24);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state28 <= ap_CS_fsm(27);
ap_CS_fsm_state29 <= ap_CS_fsm(28);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state30 <= ap_CS_fsm(29);
ap_CS_fsm_state31 <= ap_CS_fsm(30);
ap_CS_fsm_state32 <= ap_CS_fsm(31);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state33)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state33))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state33)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(ap_CS_fsm_state33, found_1_s_fu_2969_p2, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
ap_return <= found_1_s_fu_2969_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
contacts_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, tmp_12_fu_1372_p1, tmp_12_2_fu_1409_p1, tmp_12_4_fu_1449_p1, tmp_12_6_fu_1505_p1, tmp_12_8_fu_1545_p1, tmp_12_s_fu_1606_p1, tmp_12_11_fu_1646_p1, tmp_12_13_fu_1702_p1, tmp_12_15_fu_1742_p1, tmp_12_17_fu_1808_p1, tmp_12_19_fu_1848_p1, tmp_12_21_fu_1904_p1, tmp_12_23_fu_1944_p1, tmp_12_25_fu_2005_p1, tmp_12_27_fu_2045_p1, tmp_12_29_fu_2101_p1, tmp_12_31_fu_2141_p1, tmp_12_33_fu_2207_p1, tmp_12_35_fu_2247_p1, tmp_12_37_fu_2303_p1, tmp_12_39_fu_2343_p1, tmp_12_41_fu_2404_p1, tmp_12_43_fu_2444_p1, tmp_12_45_fu_2500_p1, tmp_12_47_fu_2540_p1, tmp_12_49_fu_2606_p1, tmp_12_51_fu_2646_p1, tmp_12_53_fu_2702_p1, tmp_12_55_fu_2742_p1, tmp_12_57_fu_2803_p1, tmp_12_59_fu_2843_p1, tmp_12_61_fu_2899_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
contacts_address0 <= tmp_12_61_fu_2899_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
contacts_address0 <= tmp_12_59_fu_2843_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
contacts_address0 <= tmp_12_57_fu_2803_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
contacts_address0 <= tmp_12_55_fu_2742_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
contacts_address0 <= tmp_12_53_fu_2702_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
contacts_address0 <= tmp_12_51_fu_2646_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
contacts_address0 <= tmp_12_49_fu_2606_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
contacts_address0 <= tmp_12_47_fu_2540_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
contacts_address0 <= tmp_12_45_fu_2500_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
contacts_address0 <= tmp_12_43_fu_2444_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
contacts_address0 <= tmp_12_41_fu_2404_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
contacts_address0 <= tmp_12_39_fu_2343_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
contacts_address0 <= tmp_12_37_fu_2303_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
contacts_address0 <= tmp_12_35_fu_2247_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
contacts_address0 <= tmp_12_33_fu_2207_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
contacts_address0 <= tmp_12_31_fu_2141_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
contacts_address0 <= tmp_12_29_fu_2101_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
contacts_address0 <= tmp_12_27_fu_2045_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
contacts_address0 <= tmp_12_25_fu_2005_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address0 <= tmp_12_23_fu_1944_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
contacts_address0 <= tmp_12_21_fu_1904_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
contacts_address0 <= tmp_12_19_fu_1848_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
contacts_address0 <= tmp_12_17_fu_1808_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
contacts_address0 <= tmp_12_15_fu_1742_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address0 <= tmp_12_13_fu_1702_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
contacts_address0 <= tmp_12_11_fu_1646_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
contacts_address0 <= tmp_12_s_fu_1606_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
contacts_address0 <= tmp_12_8_fu_1545_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= tmp_12_6_fu_1505_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
contacts_address0 <= tmp_12_4_fu_1449_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
contacts_address0 <= tmp_12_2_fu_1409_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
contacts_address0 <= tmp_12_fu_1372_p1(13 - 1 downto 0);
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, tmp_12_1_fu_1388_p1, tmp_12_3_fu_1429_p1, tmp_12_5_fu_1469_p1, tmp_12_7_fu_1525_p1, tmp_12_9_fu_1565_p1, tmp_12_10_fu_1626_p1, tmp_12_12_fu_1666_p1, tmp_12_14_fu_1722_p1, tmp_12_16_fu_1762_p1, tmp_12_18_fu_1828_p1, tmp_12_20_fu_1868_p1, tmp_12_22_fu_1924_p1, tmp_12_24_fu_1964_p1, tmp_12_26_fu_2025_p1, tmp_12_28_fu_2065_p1, tmp_12_30_fu_2121_p1, tmp_12_32_fu_2161_p1, tmp_12_34_fu_2227_p1, tmp_12_36_fu_2267_p1, tmp_12_38_fu_2323_p1, tmp_12_40_fu_2363_p1, tmp_12_42_fu_2424_p1, tmp_12_44_fu_2464_p1, tmp_12_46_fu_2520_p1, tmp_12_48_fu_2560_p1, tmp_12_50_fu_2626_p1, tmp_12_52_fu_2666_p1, tmp_12_54_fu_2722_p1, tmp_12_56_fu_2762_p1, tmp_12_58_fu_2823_p1, tmp_12_60_fu_2863_p1, tmp_12_62_fu_2919_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
contacts_address1 <= tmp_12_62_fu_2919_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
contacts_address1 <= tmp_12_60_fu_2863_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
contacts_address1 <= tmp_12_58_fu_2823_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
contacts_address1 <= tmp_12_56_fu_2762_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
contacts_address1 <= tmp_12_54_fu_2722_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
contacts_address1 <= tmp_12_52_fu_2666_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
contacts_address1 <= tmp_12_50_fu_2626_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
contacts_address1 <= tmp_12_48_fu_2560_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
contacts_address1 <= tmp_12_46_fu_2520_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
contacts_address1 <= tmp_12_44_fu_2464_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
contacts_address1 <= tmp_12_42_fu_2424_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
contacts_address1 <= tmp_12_40_fu_2363_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
contacts_address1 <= tmp_12_38_fu_2323_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
contacts_address1 <= tmp_12_36_fu_2267_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
contacts_address1 <= tmp_12_34_fu_2227_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
contacts_address1 <= tmp_12_32_fu_2161_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
contacts_address1 <= tmp_12_30_fu_2121_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
contacts_address1 <= tmp_12_28_fu_2065_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
contacts_address1 <= tmp_12_26_fu_2025_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address1 <= tmp_12_24_fu_1964_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
contacts_address1 <= tmp_12_22_fu_1924_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
contacts_address1 <= tmp_12_20_fu_1868_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
contacts_address1 <= tmp_12_18_fu_1828_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
contacts_address1 <= tmp_12_16_fu_1762_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address1 <= tmp_12_14_fu_1722_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
contacts_address1 <= tmp_12_12_fu_1666_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
contacts_address1 <= tmp_12_10_fu_1626_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
contacts_address1 <= tmp_12_9_fu_1565_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address1 <= tmp_12_7_fu_1525_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
contacts_address1 <= tmp_12_5_fu_1469_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
contacts_address1 <= tmp_12_3_fu_1429_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
contacts_address1 <= tmp_12_1_fu_1388_p1(13 - 1 downto 0);
else
contacts_address1 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32))) then
contacts_ce0 <= ap_const_logic_1;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32))) then
contacts_ce1 <= ap_const_logic_1;
else
contacts_ce1 <= ap_const_logic_0;
end if;
end process;
database_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, tmp_14_fu_1377_p1, tmp_14_2_fu_1419_p1, tmp_14_4_fu_1459_p1, tmp_14_6_fu_1515_p1, tmp_14_8_fu_1555_p1, tmp_14_s_fu_1616_p1, tmp_14_11_fu_1656_p1, tmp_14_13_fu_1712_p1, tmp_14_15_fu_1752_p1, tmp_14_17_fu_1818_p1, tmp_14_19_fu_1858_p1, tmp_14_21_fu_1914_p1, tmp_14_23_fu_1954_p1, tmp_14_25_fu_2015_p1, tmp_14_27_fu_2055_p1, tmp_14_29_fu_2111_p1, tmp_14_31_fu_2151_p1, tmp_14_33_fu_2217_p1, tmp_14_35_fu_2257_p1, tmp_14_37_fu_2313_p1, tmp_14_39_fu_2353_p1, tmp_14_41_fu_2414_p1, tmp_14_43_fu_2454_p1, tmp_14_45_fu_2510_p1, tmp_14_47_fu_2550_p1, tmp_14_49_fu_2616_p1, tmp_14_51_fu_2656_p1, tmp_14_53_fu_2712_p1, tmp_14_55_fu_2752_p1, tmp_14_57_fu_2813_p1, tmp_14_59_fu_2853_p1, tmp_14_61_fu_2909_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
database_address0 <= tmp_14_61_fu_2909_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
database_address0 <= tmp_14_59_fu_2853_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
database_address0 <= tmp_14_57_fu_2813_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
database_address0 <= tmp_14_55_fu_2752_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
database_address0 <= tmp_14_53_fu_2712_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
database_address0 <= tmp_14_51_fu_2656_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
database_address0 <= tmp_14_49_fu_2616_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
database_address0 <= tmp_14_47_fu_2550_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
database_address0 <= tmp_14_45_fu_2510_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
database_address0 <= tmp_14_43_fu_2454_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
database_address0 <= tmp_14_41_fu_2414_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
database_address0 <= tmp_14_39_fu_2353_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
database_address0 <= tmp_14_37_fu_2313_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
database_address0 <= tmp_14_35_fu_2257_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
database_address0 <= tmp_14_33_fu_2217_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
database_address0 <= tmp_14_31_fu_2151_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
database_address0 <= tmp_14_29_fu_2111_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
database_address0 <= tmp_14_27_fu_2055_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
database_address0 <= tmp_14_25_fu_2015_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
database_address0 <= tmp_14_23_fu_1954_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
database_address0 <= tmp_14_21_fu_1914_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
database_address0 <= tmp_14_19_fu_1858_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
database_address0 <= tmp_14_17_fu_1818_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
database_address0 <= tmp_14_15_fu_1752_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
database_address0 <= tmp_14_13_fu_1712_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
database_address0 <= tmp_14_11_fu_1656_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
database_address0 <= tmp_14_s_fu_1616_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
database_address0 <= tmp_14_8_fu_1555_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
database_address0 <= tmp_14_6_fu_1515_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
database_address0 <= tmp_14_4_fu_1459_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
database_address0 <= tmp_14_2_fu_1419_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
database_address0 <= tmp_14_fu_1377_p1(15 - 1 downto 0);
else
database_address0 <= "XXXXXXXXXXXXXXX";
end if;
end process;
database_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, tmp_14_1_fu_1399_p1, tmp_14_3_fu_1439_p1, tmp_14_5_fu_1479_p1, tmp_14_7_fu_1535_p1, tmp_14_9_fu_1575_p1, tmp_14_10_fu_1636_p1, tmp_14_12_fu_1676_p1, tmp_14_14_fu_1732_p1, tmp_14_16_fu_1772_p1, tmp_14_18_fu_1838_p1, tmp_14_20_fu_1878_p1, tmp_14_22_fu_1934_p1, tmp_14_24_fu_1974_p1, tmp_14_26_fu_2035_p1, tmp_14_28_fu_2075_p1, tmp_14_30_fu_2131_p1, tmp_14_32_fu_2171_p1, tmp_14_34_fu_2237_p1, tmp_14_36_fu_2277_p1, tmp_14_38_fu_2333_p1, tmp_14_40_fu_2373_p1, tmp_14_42_fu_2434_p1, tmp_14_44_fu_2474_p1, tmp_14_46_fu_2530_p1, tmp_14_48_fu_2570_p1, tmp_14_50_fu_2636_p1, tmp_14_52_fu_2676_p1, tmp_14_54_fu_2732_p1, tmp_14_56_fu_2772_p1, tmp_14_58_fu_2833_p1, tmp_14_60_fu_2873_p1, tmp_14_62_fu_2929_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
database_address1 <= tmp_14_62_fu_2929_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
database_address1 <= tmp_14_60_fu_2873_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
database_address1 <= tmp_14_58_fu_2833_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
database_address1 <= tmp_14_56_fu_2772_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
database_address1 <= tmp_14_54_fu_2732_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
database_address1 <= tmp_14_52_fu_2676_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
database_address1 <= tmp_14_50_fu_2636_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
database_address1 <= tmp_14_48_fu_2570_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
database_address1 <= tmp_14_46_fu_2530_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
database_address1 <= tmp_14_44_fu_2474_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
database_address1 <= tmp_14_42_fu_2434_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
database_address1 <= tmp_14_40_fu_2373_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
database_address1 <= tmp_14_38_fu_2333_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
database_address1 <= tmp_14_36_fu_2277_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
database_address1 <= tmp_14_34_fu_2237_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
database_address1 <= tmp_14_32_fu_2171_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
database_address1 <= tmp_14_30_fu_2131_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
database_address1 <= tmp_14_28_fu_2075_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
database_address1 <= tmp_14_26_fu_2035_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
database_address1 <= tmp_14_24_fu_1974_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
database_address1 <= tmp_14_22_fu_1934_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
database_address1 <= tmp_14_20_fu_1878_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
database_address1 <= tmp_14_18_fu_1838_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
database_address1 <= tmp_14_16_fu_1772_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
database_address1 <= tmp_14_14_fu_1732_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
database_address1 <= tmp_14_12_fu_1676_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
database_address1 <= tmp_14_10_fu_1636_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
database_address1 <= tmp_14_9_fu_1575_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
database_address1 <= tmp_14_7_fu_1535_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
database_address1 <= tmp_14_5_fu_1479_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
database_address1 <= tmp_14_3_fu_1439_p1(15 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
database_address1 <= tmp_14_1_fu_1399_p1(15 - 1 downto 0);
else
database_address1 <= "XXXXXXXXXXXXXXX";
end if;
end process;
database_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32))) then
database_ce0 <= ap_const_logic_1;
else
database_ce0 <= ap_const_logic_0;
end if;
end process;
database_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32))) then
database_ce1 <= ap_const_logic_1;
else
database_ce1 <= ap_const_logic_0;
end if;
end process;
found_1_s_fu_2969_p2 <= (tmp32_fu_2964_p2 and tmp1_fu_2934_p2);
grp_fu_1336_p2 <= "1" when (contacts_q0 = database_q0) else "0";
grp_fu_1342_p2 <= "1" when (contacts_q1 = database_q1) else "0";
tmp10_fu_1793_p2 <= (tmp14_fu_1787_p2 and tmp11_reg_3287);
tmp11_fu_1691_p2 <= (tmp13_fu_1685_p2 and tmp12_fu_1681_p2);
tmp12_fu_1681_p2 <= (tmp_15_8_reg_3237 and tmp_15_9_reg_3242);
tmp13_fu_1685_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp14_fu_1787_p2 <= (tmp16_fu_1781_p2 and tmp15_fu_1777_p2);
tmp15_fu_1777_p2 <= (tmp_15_11_reg_3292 and tmp_15_12_reg_3297);
tmp16_fu_1781_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp17_fu_2197_p2 <= (tmp25_fu_2192_p2 and tmp18_reg_3452);
tmp18_fu_1995_p2 <= (tmp22_fu_1989_p2 and tmp19_reg_3397);
tmp19_fu_1893_p2 <= (tmp21_fu_1887_p2 and tmp20_fu_1883_p2);
tmp1_fu_2934_p2 <= (tmp17_reg_3562 and tmp2_reg_3342);
tmp20_fu_1883_p2 <= (tmp_15_15_reg_3347 and tmp_15_16_reg_3352);
tmp21_fu_1887_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp22_fu_1989_p2 <= (tmp24_fu_1983_p2 and tmp23_fu_1979_p2);
tmp23_fu_1979_p2 <= (tmp_15_19_reg_3402 and tmp_15_20_reg_3407);
tmp24_fu_1983_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp25_fu_2192_p2 <= (tmp29_fu_2186_p2 and tmp26_reg_3507);
tmp26_fu_2090_p2 <= (tmp28_fu_2084_p2 and tmp27_fu_2080_p2);
tmp27_fu_2080_p2 <= (tmp_15_23_reg_3457 and tmp_15_24_reg_3462);
tmp28_fu_2084_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp29_fu_2186_p2 <= (tmp31_fu_2180_p2 and tmp30_fu_2176_p2);
tmp2_fu_1798_p2 <= (tmp10_fu_1793_p2 and tmp3_reg_3232);
tmp30_fu_2176_p2 <= (tmp_15_27_reg_3512 and tmp_15_28_reg_3517);
tmp31_fu_2180_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp32_fu_2964_p2 <= (tmp48_fu_2959_p2 and tmp33_reg_3782);
tmp33_fu_2596_p2 <= (tmp41_fu_2591_p2 and tmp34_reg_3672);
tmp34_fu_2394_p2 <= (tmp38_fu_2388_p2 and tmp35_reg_3617);
tmp35_fu_2292_p2 <= (tmp37_fu_2286_p2 and tmp36_fu_2282_p2);
tmp36_fu_2282_p2 <= (tmp_15_31_reg_3567 and tmp_15_32_reg_3572);
tmp37_fu_2286_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp38_fu_2388_p2 <= (tmp40_fu_2382_p2 and tmp39_fu_2378_p2);
tmp39_fu_2378_p2 <= (tmp_15_35_reg_3622 and tmp_15_36_reg_3627);
tmp3_fu_1596_p2 <= (tmp7_fu_1590_p2 and tmp4_reg_3177);
tmp40_fu_2382_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp41_fu_2591_p2 <= (tmp45_fu_2585_p2 and tmp42_reg_3727);
tmp42_fu_2489_p2 <= (tmp44_fu_2483_p2 and tmp43_fu_2479_p2);
tmp43_fu_2479_p2 <= (tmp_15_39_reg_3677 and tmp_15_40_reg_3682);
tmp44_fu_2483_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp45_fu_2585_p2 <= (tmp47_fu_2579_p2 and tmp46_fu_2575_p2);
tmp46_fu_2575_p2 <= (tmp_15_43_reg_3732 and tmp_15_44_reg_3737);
tmp47_fu_2579_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp48_fu_2959_p2 <= (tmp56_fu_2954_p2 and tmp49_reg_3892);
tmp49_fu_2793_p2 <= (tmp53_fu_2787_p2 and tmp50_reg_3837);
tmp4_fu_1494_p2 <= (tmp6_fu_1488_p2 and tmp5_fu_1484_p2);
tmp50_fu_2691_p2 <= (tmp52_fu_2685_p2 and tmp51_fu_2681_p2);
tmp51_fu_2681_p2 <= (tmp_15_47_reg_3787 and tmp_15_48_reg_3792);
tmp52_fu_2685_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp53_fu_2787_p2 <= (tmp55_fu_2781_p2 and tmp54_fu_2777_p2);
tmp54_fu_2777_p2 <= (tmp_15_51_reg_3842 and tmp_15_52_reg_3847);
tmp55_fu_2781_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp56_fu_2954_p2 <= (tmp60_fu_2948_p2 and tmp57_reg_3947);
tmp57_fu_2888_p2 <= (tmp59_fu_2882_p2 and tmp58_fu_2878_p2);
tmp58_fu_2878_p2 <= (tmp_15_55_reg_3897 and tmp_15_56_reg_3902);
tmp59_fu_2882_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp5_fu_1484_p2 <= (tmp_15_reg_3127 and tmp_15_1_reg_3132);
tmp60_fu_2948_p2 <= (tmp62_fu_2942_p2 and tmp61_fu_2938_p2);
tmp61_fu_2938_p2 <= (tmp_15_59_reg_3952 and tmp_15_60_reg_3957);
tmp62_fu_2942_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp6_fu_1488_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp7_fu_1590_p2 <= (tmp9_fu_1584_p2 and tmp8_fu_1580_p2);
tmp8_fu_1580_p2 <= (tmp_15_4_reg_3182 and tmp_15_5_reg_3187);
tmp9_fu_1584_p2 <= (grp_fu_1336_p2 and grp_fu_1342_p2);
tmp_11_10_fu_1621_p2 <= (tmp_reg_2975 or ap_const_lv13_B);
tmp_11_11_fu_1641_p2 <= (tmp_reg_2975 or ap_const_lv13_C);
tmp_11_12_fu_1661_p2 <= (tmp_reg_2975 or ap_const_lv13_D);
tmp_11_13_fu_1697_p2 <= (tmp_reg_2975 or ap_const_lv13_E);
tmp_11_14_fu_1717_p2 <= (tmp_reg_2975 or ap_const_lv13_F);
tmp_11_15_fu_1737_p2 <= (tmp_reg_2975 or ap_const_lv13_10);
tmp_11_16_fu_1757_p2 <= (tmp_reg_2975 or ap_const_lv13_11);
tmp_11_17_fu_1803_p2 <= (tmp_reg_2975 or ap_const_lv13_12);
tmp_11_18_fu_1823_p2 <= (tmp_reg_2975 or ap_const_lv13_13);
tmp_11_19_fu_1843_p2 <= (tmp_reg_2975 or ap_const_lv13_14);
tmp_11_1_fu_1404_p2 <= (tmp_reg_2975 or ap_const_lv13_2);
tmp_11_20_fu_1863_p2 <= (tmp_reg_2975 or ap_const_lv13_15);
tmp_11_21_fu_1899_p2 <= (tmp_reg_2975 or ap_const_lv13_16);
tmp_11_22_fu_1919_p2 <= (tmp_reg_2975 or ap_const_lv13_17);
tmp_11_23_fu_1939_p2 <= (tmp_reg_2975 or ap_const_lv13_18);
tmp_11_24_fu_1959_p2 <= (tmp_reg_2975 or ap_const_lv13_19);
tmp_11_25_fu_2000_p2 <= (tmp_reg_2975 or ap_const_lv13_1A);
tmp_11_26_fu_2020_p2 <= (tmp_reg_2975 or ap_const_lv13_1B);
tmp_11_27_fu_2040_p2 <= (tmp_reg_2975 or ap_const_lv13_1C);
tmp_11_28_fu_2060_p2 <= (tmp_reg_2975 or ap_const_lv13_1D);
tmp_11_29_fu_2096_p2 <= (tmp_reg_2975 or ap_const_lv13_1E);
tmp_11_2_fu_1424_p2 <= (tmp_reg_2975 or ap_const_lv13_3);
tmp_11_30_fu_2116_p2 <= (tmp_reg_2975 or ap_const_lv13_1F);
tmp_11_31_fu_2136_p2 <= (tmp_reg_2975 or ap_const_lv13_20);
tmp_11_32_fu_2156_p2 <= (tmp_reg_2975 or ap_const_lv13_21);
tmp_11_33_fu_2202_p2 <= (tmp_reg_2975 or ap_const_lv13_22);
tmp_11_34_fu_2222_p2 <= (tmp_reg_2975 or ap_const_lv13_23);
tmp_11_35_fu_2242_p2 <= (tmp_reg_2975 or ap_const_lv13_24);
tmp_11_36_fu_2262_p2 <= (tmp_reg_2975 or ap_const_lv13_25);
tmp_11_37_fu_2298_p2 <= (tmp_reg_2975 or ap_const_lv13_26);
tmp_11_38_fu_2318_p2 <= (tmp_reg_2975 or ap_const_lv13_27);
tmp_11_39_fu_2338_p2 <= (tmp_reg_2975 or ap_const_lv13_28);
tmp_11_3_fu_1444_p2 <= (tmp_reg_2975 or ap_const_lv13_4);
tmp_11_40_fu_2358_p2 <= (tmp_reg_2975 or ap_const_lv13_29);
tmp_11_41_fu_2399_p2 <= (tmp_reg_2975 or ap_const_lv13_2A);
tmp_11_42_fu_2419_p2 <= (tmp_reg_2975 or ap_const_lv13_2B);
tmp_11_43_fu_2439_p2 <= (tmp_reg_2975 or ap_const_lv13_2C);
tmp_11_44_fu_2459_p2 <= (tmp_reg_2975 or ap_const_lv13_2D);
tmp_11_45_fu_2495_p2 <= (tmp_reg_2975 or ap_const_lv13_2E);
tmp_11_46_fu_2515_p2 <= (tmp_reg_2975 or ap_const_lv13_2F);
tmp_11_47_fu_2535_p2 <= (tmp_reg_2975 or ap_const_lv13_30);
tmp_11_48_fu_2555_p2 <= (tmp_reg_2975 or ap_const_lv13_31);
tmp_11_49_fu_2601_p2 <= (tmp_reg_2975 or ap_const_lv13_32);
tmp_11_4_fu_1464_p2 <= (tmp_reg_2975 or ap_const_lv13_5);
tmp_11_50_fu_2621_p2 <= (tmp_reg_2975 or ap_const_lv13_33);
tmp_11_51_fu_2641_p2 <= (tmp_reg_2975 or ap_const_lv13_34);
tmp_11_52_fu_2661_p2 <= (tmp_reg_2975 or ap_const_lv13_35);
tmp_11_53_fu_2697_p2 <= (tmp_reg_2975 or ap_const_lv13_36);
tmp_11_54_fu_2717_p2 <= (tmp_reg_2975 or ap_const_lv13_37);
tmp_11_55_fu_2737_p2 <= (tmp_reg_2975 or ap_const_lv13_38);
tmp_11_56_fu_2757_p2 <= (tmp_reg_2975 or ap_const_lv13_39);
tmp_11_57_fu_2798_p2 <= (tmp_reg_2975 or ap_const_lv13_3A);
tmp_11_58_fu_2818_p2 <= (tmp_reg_2975 or ap_const_lv13_3B);
tmp_11_59_fu_2838_p2 <= (tmp_reg_2975 or ap_const_lv13_3C);
tmp_11_5_fu_1500_p2 <= (tmp_reg_2975 or ap_const_lv13_6);
tmp_11_60_fu_2858_p2 <= (tmp_reg_2975 or ap_const_lv13_3D);
tmp_11_61_fu_2894_p2 <= (tmp_reg_2975 or ap_const_lv13_3E);
tmp_11_62_fu_2914_p2 <= (tmp_reg_2975 or ap_const_lv13_3F);
tmp_11_6_fu_1520_p2 <= (tmp_reg_2975 or ap_const_lv13_7);
tmp_11_7_fu_1540_p2 <= (tmp_reg_2975 or ap_const_lv13_8);
tmp_11_8_fu_1560_p2 <= (tmp_reg_2975 or ap_const_lv13_9);
tmp_11_9_fu_1601_p2 <= (tmp_reg_2975 or ap_const_lv13_A);
tmp_11_s_fu_1382_p2 <= (tmp_fu_1352_p3 or ap_const_lv13_1);
tmp_127_fu_1348_p1 <= contacts_index(7 - 1 downto 0);
tmp_128_fu_1360_p1 <= db_index(26 - 1 downto 0);
tmp_12_10_fu_1626_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_10_fu_1621_p2),64));
tmp_12_11_fu_1646_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_11_fu_1641_p2),64));
tmp_12_12_fu_1666_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_12_fu_1661_p2),64));
tmp_12_13_fu_1702_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_13_fu_1697_p2),64));
tmp_12_14_fu_1722_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_14_fu_1717_p2),64));
tmp_12_15_fu_1742_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_15_fu_1737_p2),64));
tmp_12_16_fu_1762_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_16_fu_1757_p2),64));
tmp_12_17_fu_1808_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_17_fu_1803_p2),64));
tmp_12_18_fu_1828_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_18_fu_1823_p2),64));
tmp_12_19_fu_1848_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_19_fu_1843_p2),64));
tmp_12_1_fu_1388_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_s_fu_1382_p2),64));
tmp_12_20_fu_1868_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_20_fu_1863_p2),64));
tmp_12_21_fu_1904_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_21_fu_1899_p2),64));
tmp_12_22_fu_1924_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_22_fu_1919_p2),64));
tmp_12_23_fu_1944_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_23_fu_1939_p2),64));
tmp_12_24_fu_1964_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_24_fu_1959_p2),64));
tmp_12_25_fu_2005_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_25_fu_2000_p2),64));
tmp_12_26_fu_2025_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_26_fu_2020_p2),64));
tmp_12_27_fu_2045_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_27_fu_2040_p2),64));
tmp_12_28_fu_2065_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_28_fu_2060_p2),64));
tmp_12_29_fu_2101_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_29_fu_2096_p2),64));
tmp_12_2_fu_1409_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_1_fu_1404_p2),64));
tmp_12_30_fu_2121_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_30_fu_2116_p2),64));
tmp_12_31_fu_2141_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_31_fu_2136_p2),64));
tmp_12_32_fu_2161_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_32_fu_2156_p2),64));
tmp_12_33_fu_2207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_33_fu_2202_p2),64));
tmp_12_34_fu_2227_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_34_fu_2222_p2),64));
tmp_12_35_fu_2247_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_35_fu_2242_p2),64));
tmp_12_36_fu_2267_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_36_fu_2262_p2),64));
tmp_12_37_fu_2303_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_37_fu_2298_p2),64));
tmp_12_38_fu_2323_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_38_fu_2318_p2),64));
tmp_12_39_fu_2343_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_39_fu_2338_p2),64));
tmp_12_3_fu_1429_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_2_fu_1424_p2),64));
tmp_12_40_fu_2363_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_40_fu_2358_p2),64));
tmp_12_41_fu_2404_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_41_fu_2399_p2),64));
tmp_12_42_fu_2424_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_42_fu_2419_p2),64));
tmp_12_43_fu_2444_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_43_fu_2439_p2),64));
tmp_12_44_fu_2464_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_44_fu_2459_p2),64));
tmp_12_45_fu_2500_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_45_fu_2495_p2),64));
tmp_12_46_fu_2520_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_46_fu_2515_p2),64));
tmp_12_47_fu_2540_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_47_fu_2535_p2),64));
tmp_12_48_fu_2560_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_48_fu_2555_p2),64));
tmp_12_49_fu_2606_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_49_fu_2601_p2),64));
tmp_12_4_fu_1449_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_3_fu_1444_p2),64));
tmp_12_50_fu_2626_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_50_fu_2621_p2),64));
tmp_12_51_fu_2646_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_51_fu_2641_p2),64));
tmp_12_52_fu_2666_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_52_fu_2661_p2),64));
tmp_12_53_fu_2702_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_53_fu_2697_p2),64));
tmp_12_54_fu_2722_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_54_fu_2717_p2),64));
tmp_12_55_fu_2742_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_55_fu_2737_p2),64));
tmp_12_56_fu_2762_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_56_fu_2757_p2),64));
tmp_12_57_fu_2803_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_57_fu_2798_p2),64));
tmp_12_58_fu_2823_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_58_fu_2818_p2),64));
tmp_12_59_fu_2843_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_59_fu_2838_p2),64));
tmp_12_5_fu_1469_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_4_fu_1464_p2),64));
tmp_12_60_fu_2863_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_60_fu_2858_p2),64));
tmp_12_61_fu_2899_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_61_fu_2894_p2),64));
tmp_12_62_fu_2919_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_62_fu_2914_p2),64));
tmp_12_6_fu_1505_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_5_fu_1500_p2),64));
tmp_12_7_fu_1525_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_6_fu_1520_p2),64));
tmp_12_8_fu_1545_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_7_fu_1540_p2),64));
tmp_12_9_fu_1565_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_8_fu_1560_p2),64));
tmp_12_fu_1372_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1352_p3),64));
tmp_12_s_fu_1606_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_9_fu_1601_p2),64));
tmp_13_10_fu_1631_p2 <= (tmp_s_reg_3041 or ap_const_lv32_B);
tmp_13_11_fu_1651_p2 <= (tmp_s_reg_3041 or ap_const_lv32_C);
tmp_13_12_fu_1671_p2 <= (tmp_s_reg_3041 or ap_const_lv32_D);
tmp_13_13_fu_1707_p2 <= (tmp_s_reg_3041 or ap_const_lv32_E);
tmp_13_14_fu_1727_p2 <= (tmp_s_reg_3041 or ap_const_lv32_F);
tmp_13_15_fu_1747_p2 <= (tmp_s_reg_3041 or ap_const_lv32_10);
tmp_13_16_fu_1767_p2 <= (tmp_s_reg_3041 or ap_const_lv32_11);
tmp_13_17_fu_1813_p2 <= (tmp_s_reg_3041 or ap_const_lv32_12);
tmp_13_18_fu_1833_p2 <= (tmp_s_reg_3041 or ap_const_lv32_13);
tmp_13_19_fu_1853_p2 <= (tmp_s_reg_3041 or ap_const_lv32_14);
tmp_13_1_fu_1414_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2);
tmp_13_20_fu_1873_p2 <= (tmp_s_reg_3041 or ap_const_lv32_15);
tmp_13_21_fu_1909_p2 <= (tmp_s_reg_3041 or ap_const_lv32_16);
tmp_13_22_fu_1929_p2 <= (tmp_s_reg_3041 or ap_const_lv32_17);
tmp_13_23_fu_1949_p2 <= (tmp_s_reg_3041 or ap_const_lv32_18);
tmp_13_24_fu_1969_p2 <= (tmp_s_reg_3041 or ap_const_lv32_19);
tmp_13_25_fu_2010_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1A);
tmp_13_26_fu_2030_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1B);
tmp_13_27_fu_2050_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1C);
tmp_13_28_fu_2070_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1D);
tmp_13_29_fu_2106_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1E);
tmp_13_2_fu_1434_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3);
tmp_13_30_fu_2126_p2 <= (tmp_s_reg_3041 or ap_const_lv32_1F);
tmp_13_31_fu_2146_p2 <= (tmp_s_reg_3041 or ap_const_lv32_20);
tmp_13_32_fu_2166_p2 <= (tmp_s_reg_3041 or ap_const_lv32_21);
tmp_13_33_fu_2212_p2 <= (tmp_s_reg_3041 or ap_const_lv32_22);
tmp_13_34_fu_2232_p2 <= (tmp_s_reg_3041 or ap_const_lv32_23);
tmp_13_35_fu_2252_p2 <= (tmp_s_reg_3041 or ap_const_lv32_24);
tmp_13_36_fu_2272_p2 <= (tmp_s_reg_3041 or ap_const_lv32_25);
tmp_13_37_fu_2308_p2 <= (tmp_s_reg_3041 or ap_const_lv32_26);
tmp_13_38_fu_2328_p2 <= (tmp_s_reg_3041 or ap_const_lv32_27);
tmp_13_39_fu_2348_p2 <= (tmp_s_reg_3041 or ap_const_lv32_28);
tmp_13_3_fu_1454_p2 <= (tmp_s_reg_3041 or ap_const_lv32_4);
tmp_13_40_fu_2368_p2 <= (tmp_s_reg_3041 or ap_const_lv32_29);
tmp_13_41_fu_2409_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2A);
tmp_13_42_fu_2429_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2B);
tmp_13_43_fu_2449_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2C);
tmp_13_44_fu_2469_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2D);
tmp_13_45_fu_2505_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2E);
tmp_13_46_fu_2525_p2 <= (tmp_s_reg_3041 or ap_const_lv32_2F);
tmp_13_47_fu_2545_p2 <= (tmp_s_reg_3041 or ap_const_lv32_30);
tmp_13_48_fu_2565_p2 <= (tmp_s_reg_3041 or ap_const_lv32_31);
tmp_13_49_fu_2611_p2 <= (tmp_s_reg_3041 or ap_const_lv32_32);
tmp_13_4_fu_1474_p2 <= (tmp_s_reg_3041 or ap_const_lv32_5);
tmp_13_50_fu_2631_p2 <= (tmp_s_reg_3041 or ap_const_lv32_33);
tmp_13_51_fu_2651_p2 <= (tmp_s_reg_3041 or ap_const_lv32_34);
tmp_13_52_fu_2671_p2 <= (tmp_s_reg_3041 or ap_const_lv32_35);
tmp_13_53_fu_2707_p2 <= (tmp_s_reg_3041 or ap_const_lv32_36);
tmp_13_54_fu_2727_p2 <= (tmp_s_reg_3041 or ap_const_lv32_37);
tmp_13_55_fu_2747_p2 <= (tmp_s_reg_3041 or ap_const_lv32_38);
tmp_13_56_fu_2767_p2 <= (tmp_s_reg_3041 or ap_const_lv32_39);
tmp_13_57_fu_2808_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3A);
tmp_13_58_fu_2828_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3B);
tmp_13_59_fu_2848_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3C);
tmp_13_5_fu_1510_p2 <= (tmp_s_reg_3041 or ap_const_lv32_6);
tmp_13_60_fu_2868_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3D);
tmp_13_61_fu_2904_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3E);
tmp_13_62_fu_2924_p2 <= (tmp_s_reg_3041 or ap_const_lv32_3F);
tmp_13_6_fu_1530_p2 <= (tmp_s_reg_3041 or ap_const_lv32_7);
tmp_13_7_fu_1550_p2 <= (tmp_s_reg_3041 or ap_const_lv32_8);
tmp_13_8_fu_1570_p2 <= (tmp_s_reg_3041 or ap_const_lv32_9);
tmp_13_9_fu_1611_p2 <= (tmp_s_reg_3041 or ap_const_lv32_A);
tmp_13_s_fu_1393_p2 <= (tmp_s_fu_1364_p3 or ap_const_lv32_1);
tmp_14_10_fu_1636_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_10_fu_1631_p2),64));
tmp_14_11_fu_1656_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_11_fu_1651_p2),64));
tmp_14_12_fu_1676_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_12_fu_1671_p2),64));
tmp_14_13_fu_1712_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_13_fu_1707_p2),64));
tmp_14_14_fu_1732_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_14_fu_1727_p2),64));
tmp_14_15_fu_1752_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_15_fu_1747_p2),64));
tmp_14_16_fu_1772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_16_fu_1767_p2),64));
tmp_14_17_fu_1818_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_17_fu_1813_p2),64));
tmp_14_18_fu_1838_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_18_fu_1833_p2),64));
tmp_14_19_fu_1858_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_19_fu_1853_p2),64));
tmp_14_1_fu_1399_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_s_fu_1393_p2),64));
tmp_14_20_fu_1878_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_20_fu_1873_p2),64));
tmp_14_21_fu_1914_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_21_fu_1909_p2),64));
tmp_14_22_fu_1934_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_22_fu_1929_p2),64));
tmp_14_23_fu_1954_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_23_fu_1949_p2),64));
tmp_14_24_fu_1974_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_24_fu_1969_p2),64));
tmp_14_25_fu_2015_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_25_fu_2010_p2),64));
tmp_14_26_fu_2035_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_26_fu_2030_p2),64));
tmp_14_27_fu_2055_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_27_fu_2050_p2),64));
tmp_14_28_fu_2075_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_28_fu_2070_p2),64));
tmp_14_29_fu_2111_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_29_fu_2106_p2),64));
tmp_14_2_fu_1419_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_1_fu_1414_p2),64));
tmp_14_30_fu_2131_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_30_fu_2126_p2),64));
tmp_14_31_fu_2151_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_31_fu_2146_p2),64));
tmp_14_32_fu_2171_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_32_fu_2166_p2),64));
tmp_14_33_fu_2217_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_33_fu_2212_p2),64));
tmp_14_34_fu_2237_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_34_fu_2232_p2),64));
tmp_14_35_fu_2257_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_35_fu_2252_p2),64));
tmp_14_36_fu_2277_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_36_fu_2272_p2),64));
tmp_14_37_fu_2313_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_37_fu_2308_p2),64));
tmp_14_38_fu_2333_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_38_fu_2328_p2),64));
tmp_14_39_fu_2353_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_39_fu_2348_p2),64));
tmp_14_3_fu_1439_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_2_fu_1434_p2),64));
tmp_14_40_fu_2373_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_40_fu_2368_p2),64));
tmp_14_41_fu_2414_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_41_fu_2409_p2),64));
tmp_14_42_fu_2434_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_42_fu_2429_p2),64));
tmp_14_43_fu_2454_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_43_fu_2449_p2),64));
tmp_14_44_fu_2474_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_44_fu_2469_p2),64));
tmp_14_45_fu_2510_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_45_fu_2505_p2),64));
tmp_14_46_fu_2530_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_46_fu_2525_p2),64));
tmp_14_47_fu_2550_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_47_fu_2545_p2),64));
tmp_14_48_fu_2570_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_48_fu_2565_p2),64));
tmp_14_49_fu_2616_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_49_fu_2611_p2),64));
tmp_14_4_fu_1459_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_3_fu_1454_p2),64));
tmp_14_50_fu_2636_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_50_fu_2631_p2),64));
tmp_14_51_fu_2656_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_51_fu_2651_p2),64));
tmp_14_52_fu_2676_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_52_fu_2671_p2),64));
tmp_14_53_fu_2712_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_53_fu_2707_p2),64));
tmp_14_54_fu_2732_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_54_fu_2727_p2),64));
tmp_14_55_fu_2752_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_55_fu_2747_p2),64));
tmp_14_56_fu_2772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_56_fu_2767_p2),64));
tmp_14_57_fu_2813_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_57_fu_2808_p2),64));
tmp_14_58_fu_2833_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_58_fu_2828_p2),64));
tmp_14_59_fu_2853_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_59_fu_2848_p2),64));
tmp_14_5_fu_1479_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_4_fu_1474_p2),64));
tmp_14_60_fu_2873_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_60_fu_2868_p2),64));
tmp_14_61_fu_2909_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_61_fu_2904_p2),64));
tmp_14_62_fu_2929_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_62_fu_2924_p2),64));
tmp_14_6_fu_1515_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_5_fu_1510_p2),64));
tmp_14_7_fu_1535_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_6_fu_1530_p2),64));
tmp_14_8_fu_1555_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_7_fu_1550_p2),64));
tmp_14_9_fu_1575_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_8_fu_1570_p2),64));
tmp_14_fu_1377_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_s_fu_1364_p3),64));
tmp_14_s_fu_1616_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_9_fu_1611_p2),64));
tmp_fu_1352_p3 <= (tmp_127_fu_1348_p1 & ap_const_lv6_0);
tmp_s_fu_1364_p3 <= (tmp_128_fu_1360_p1 & ap_const_lv6_0);
end behav;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/syn/vhdl/contact_discoverycud.vhd | 3 | 4164 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverycud_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 19;
mem_size : integer := 480000
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverycud_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverycud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 480000;
AddressWidth : INTEGER := 19);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverycud is
component contact_discoverycud_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverycud_ram_U : component contact_discoverycud_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_experimental/solution1/impl/vhdl/contact_discoverybkb.vhd | 3 | 4160 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverybkb_ram is
generic(
mem_type : string := "block";
dwidth : integer := 512;
awidth : integer := 7;
mem_size : integer := 128
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverybkb_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverybkb is
generic (
DataWidth : INTEGER := 512;
AddressRange : INTEGER := 128;
AddressWidth : INTEGER := 7);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverybkb is
component contact_discoverybkb_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverybkb_ram_U : component contact_discoverybkb_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/vhdl/contact_discovery.vhd | 3 | 74971 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity contact_discovery is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 15;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of contact_discovery is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.619000,HLS_SYN_LAT=5282525,HLS_SYN_TPT=none,HLS_SYN_MEM=249,HLS_SYN_DSP=0,HLS_SYN_FF=5431,HLS_SYN_LUT=7231}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000001000";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000100000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (16 downto 0) := "00000000001000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (16 downto 0) := "00000000010000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (16 downto 0) := "00000000100000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (16 downto 0) := "00000001000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (16 downto 0) := "00000010000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (16 downto 0) := "00000100000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (16 downto 0) := "00001000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (16 downto 0) := "00010000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (16 downto 0) := "00100000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (16 downto 0) := "01000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (16 downto 0) := "10000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_1D4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001110101001011";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000";
constant ap_const_lv13_1D4C : STD_LOGIC_VECTOR (12 downto 0) := "1110101001100";
constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal operation_ap_vld : STD_LOGIC;
signal operation_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal operation_ap_vld_preg : STD_LOGIC := '0';
signal operation_ap_vld_in_sig : STD_LOGIC;
signal contact_in_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal contact_in_ce0 : STD_LOGIC;
signal contact_in_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal database_in_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal database_in_ce0 : STD_LOGIC;
signal database_in_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal matched_out_ce0 : STD_LOGIC;
signal matched_out_we0 : STD_LOGIC;
signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal matched_finished_1_vld_reg : STD_LOGIC := '0';
signal matched_finished_1_vld_in : STD_LOGIC;
signal matched_finished_1_ack_in : STD_LOGIC;
signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal error_out_1_vld_reg : STD_LOGIC := '0';
signal error_out_1_vld_in : STD_LOGIC;
signal error_out_1_ack_in : STD_LOGIC;
signal database_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal database_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal database_size_out_1_vld_reg : STD_LOGIC := '0';
signal database_size_out_1_vld_in : STD_LOGIC;
signal database_size_out_1_ack_in : STD_LOGIC;
signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal contacts_size_out_1_vld_reg : STD_LOGIC := '0';
signal contacts_size_out_1_vld_in : STD_LOGIC;
signal contacts_size_out_1_ack_in : STD_LOGIC;
signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal database_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal contacts_ce0 : STD_LOGIC;
signal contacts_we0 : STD_LOGIC;
signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal contacts_ce1 : STD_LOGIC;
signal contacts_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal database_address0 : STD_LOGIC_VECTOR (18 downto 0);
signal database_ce0 : STD_LOGIC;
signal database_we0 : STD_LOGIC;
signal database_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal database_ce1 : STD_LOGIC;
signal database_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal results_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal results_ce0 : STD_LOGIC;
signal results_we0 : STD_LOGIC;
signal results_q0 : STD_LOGIC_VECTOR (0 downto 0);
signal operation_blk_n : STD_LOGIC;
signal i_reg_245 : STD_LOGIC_VECTOR (12 downto 0);
signal operation_read_read_fu_116_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal contacts_size_load_reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal database_size_load_reg_502 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_cast_fu_344_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_2_cast_reg_514 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_7_fu_336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_cast_fu_370_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_9_cast_reg_522 : STD_LOGIC_VECTOR (14 downto 0);
signal icmp_fu_361_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_378_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal database_index_1_fu_384_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal database_index_1_reg_531 : STD_LOGIC_VECTOR (12 downto 0);
signal exitcond_fu_390_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_536 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state5_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal i_1_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_4_fu_402_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_reg_545 : STD_LOGIC_VECTOR (63 downto 0);
signal i_3_fu_413_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_3_reg_558 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal exitcond_i5_fu_407_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sum_i9_fu_428_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal sum_i9_reg_568 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_3_fu_433_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_fu_454_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_2_reg_581 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal exitcond_i_fu_448_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sum_i_fu_469_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal sum_i_reg_591 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_s_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state5 : STD_LOGIC;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal grp_match_db_contact_fu_302_ap_start : STD_LOGIC;
signal grp_match_db_contact_fu_302_ap_done : STD_LOGIC;
signal grp_match_db_contact_fu_302_ap_idle : STD_LOGIC;
signal grp_match_db_contact_fu_302_ap_ready : STD_LOGIC;
signal grp_match_db_contact_fu_302_contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal grp_match_db_contact_fu_302_contacts_ce0 : STD_LOGIC;
signal grp_match_db_contact_fu_302_contacts_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal grp_match_db_contact_fu_302_contacts_ce1 : STD_LOGIC;
signal grp_match_db_contact_fu_302_database_address0 : STD_LOGIC_VECTOR (18 downto 0);
signal grp_match_db_contact_fu_302_database_ce0 : STD_LOGIC;
signal grp_match_db_contact_fu_302_database_address1 : STD_LOGIC_VECTOR (18 downto 0);
signal grp_match_db_contact_fu_302_database_ce1 : STD_LOGIC;
signal grp_match_db_contact_fu_302_results_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal grp_match_db_contact_fu_302_results_ce0 : STD_LOGIC;
signal grp_match_db_contact_fu_302_results_we0 : STD_LOGIC;
signal grp_match_db_contact_fu_302_results_d0 : STD_LOGIC_VECTOR (0 downto 0);
signal database_index_reg_233 : STD_LOGIC_VECTOR (12 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_i4_reg_256 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal storemerge_reg_267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal i_i_reg_279 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal storemerge1_reg_290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal ap_reg_grp_match_db_contact_fu_302_ap_start : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal tmp_i6_fu_419_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal sum_i9_cast_fu_444_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_fu_460_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal sum_i_cast_fu_485_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_128_fu_341_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_fu_352_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_127_fu_367_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_i6_cast_fu_424_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_i_cast_fu_465_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_block_state8 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (16 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component match_db_contact IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
database_index : IN STD_LOGIC_VECTOR (12 downto 0);
contacts_address0 : OUT STD_LOGIC_VECTOR (12 downto 0);
contacts_ce0 : OUT STD_LOGIC;
contacts_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_address1 : OUT STD_LOGIC_VECTOR (12 downto 0);
contacts_ce1 : OUT STD_LOGIC;
contacts_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
database_address0 : OUT STD_LOGIC_VECTOR (18 downto 0);
database_ce0 : OUT STD_LOGIC;
database_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
database_address1 : OUT STD_LOGIC_VECTOR (18 downto 0);
database_ce1 : OUT STD_LOGIC;
database_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
results_address0 : OUT STD_LOGIC_VECTOR (12 downto 0);
results_ce0 : OUT STD_LOGIC;
results_we0 : OUT STD_LOGIC;
results_d0 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component contact_discoverybkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (12 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverycud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (18 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (18 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverydEe IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (0 downto 0);
q0 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component contact_discovery_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0);
operation_ap_vld : OUT STD_LOGIC;
contact_in_address0 : IN STD_LOGIC_VECTOR (5 downto 0);
contact_in_ce0 : IN STD_LOGIC;
contact_in_q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
database_in_address0 : IN STD_LOGIC_VECTOR (5 downto 0);
database_in_ce0 : IN STD_LOGIC;
database_in_q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
matched_out_address0 : IN STD_LOGIC_VECTOR (12 downto 0);
matched_out_ce0 : IN STD_LOGIC;
matched_out_we0 : IN STD_LOGIC;
matched_out_d0 : IN STD_LOGIC_VECTOR (0 downto 0);
matched_finished : IN STD_LOGIC_VECTOR (31 downto 0);
error_out : IN STD_LOGIC_VECTOR (31 downto 0);
database_size_out : IN STD_LOGIC_VECTOR (31 downto 0);
contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
contacts_U : component contact_discoverybkb
generic map (
DataWidth => 8,
AddressRange => 8192,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => contacts_address0,
ce0 => contacts_ce0,
we0 => contacts_we0,
d0 => contact_in_q0,
q0 => contacts_q0,
address1 => grp_match_db_contact_fu_302_contacts_address1,
ce1 => contacts_ce1,
q1 => contacts_q1);
database_U : component contact_discoverycud
generic map (
DataWidth => 8,
AddressRange => 480000,
AddressWidth => 19)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => database_address0,
ce0 => database_ce0,
we0 => database_we0,
d0 => database_in_q0,
q0 => database_q0,
address1 => grp_match_db_contact_fu_302_database_address1,
ce1 => database_ce1,
q1 => database_q1);
results_U : component contact_discoverydEe
generic map (
DataWidth => 1,
AddressRange => 7500,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => results_address0,
ce0 => results_ce0,
we0 => results_we0,
d0 => grp_match_db_contact_fu_302_results_d0,
q0 => results_q0);
contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation,
operation_ap_vld => operation_ap_vld,
contact_in_address0 => contact_in_address0,
contact_in_ce0 => contact_in_ce0,
contact_in_q0 => contact_in_q0,
database_in_address0 => database_in_address0,
database_in_ce0 => database_in_ce0,
database_in_q0 => database_in_q0,
matched_out_address0 => matched_out_address0,
matched_out_ce0 => matched_out_ce0,
matched_out_we0 => matched_out_we0,
matched_out_d0 => results_q0,
matched_finished => matched_finished_1_data_reg,
error_out => error_out_1_data_reg,
database_size_out => database_size_out_1_data_reg,
contacts_size_out => contacts_size_out_1_data_reg);
grp_match_db_contact_fu_302 : component match_db_contact
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_match_db_contact_fu_302_ap_start,
ap_done => grp_match_db_contact_fu_302_ap_done,
ap_idle => grp_match_db_contact_fu_302_ap_idle,
ap_ready => grp_match_db_contact_fu_302_ap_ready,
database_index => database_index_reg_233,
contacts_address0 => grp_match_db_contact_fu_302_contacts_address0,
contacts_ce0 => grp_match_db_contact_fu_302_contacts_ce0,
contacts_q0 => contacts_q0,
contacts_address1 => grp_match_db_contact_fu_302_contacts_address1,
contacts_ce1 => grp_match_db_contact_fu_302_contacts_ce1,
contacts_q1 => contacts_q1,
database_address0 => grp_match_db_contact_fu_302_database_address0,
database_ce0 => grp_match_db_contact_fu_302_database_ce0,
database_q0 => database_q0,
database_address1 => grp_match_db_contact_fu_302_database_address1,
database_ce1 => grp_match_db_contact_fu_302_database_ce1,
database_q1 => database_q1,
results_address0 => grp_match_db_contact_fu_302_results_address0,
results_ce0 => grp_match_db_contact_fu_302_results_ce0,
results_we0 => grp_match_db_contact_fu_302_results_we0,
results_d0 => grp_match_db_contact_fu_302_results_d0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state5))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond2_fu_378_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state5))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state5 xor ap_const_logic_1);
elsif ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond2_fu_378_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_match_db_contact_fu_302_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_grp_match_db_contact_fu_302_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond2_fu_378_p2))) then
ap_reg_grp_match_db_contact_fu_302_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_match_db_contact_fu_302_ap_ready)) then
ap_reg_grp_match_db_contact_fu_302_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
operation_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = database_size_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
operation_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_ap_vld_preg <= operation_ap_vld;
end if;
end if;
end if;
end process;
operation_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_preg <= operation;
end if;
end if;
end if;
end process;
contacts_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (ap_const_lv1_1 = exitcond_i_fu_448_p2))) then
contacts_size <= tmp_s_fu_474_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4))) then
contacts_size <= ap_const_lv32_0;
end if;
end if;
end process;
contacts_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
database_index_reg_233_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (grp_match_db_contact_fu_302_ap_done = ap_const_logic_1))) then
database_index_reg_233 <= database_index_1_reg_531;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_2))) then
database_index_reg_233 <= ap_const_lv13_0;
end if;
end if;
end process;
database_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (exitcond_i5_fu_407_p2 = ap_const_lv1_1))) then
database_size <= tmp_3_fu_433_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3))) then
database_size <= ap_const_lv32_0;
end if;
end if;
end process;
database_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
error_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
i_i4_reg_256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
i_i4_reg_256 <= i_3_reg_558;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_0))) then
i_i4_reg_256 <= ap_const_lv7_0;
end if;
end if;
end process;
i_i_reg_279_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
i_i_reg_279 <= i_2_reg_581;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (ap_const_lv1_0 = icmp_fu_361_p2))) then
i_i_reg_279 <= ap_const_lv7_0;
end if;
end if;
end process;
i_reg_245_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond2_fu_378_p2 = ap_const_lv1_1))) then
i_reg_245 <= ap_const_lv13_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_lv1_0 = exitcond_fu_390_p2))) then
i_reg_245 <= i_1_fu_396_p2;
end if;
end if;
end process;
matched_finished_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
storemerge1_reg_290_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
storemerge1_reg_290 <= contacts_size_load_reg_493;
elsif (((ap_const_logic_1 = ap_CS_fsm_state14) and (ap_const_lv1_1 = exitcond_i_fu_448_p2))) then
storemerge1_reg_290 <= tmp_s_fu_474_p2;
end if;
end if;
end process;
storemerge_reg_267_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
storemerge_reg_267 <= database_size_load_reg_502;
elsif (((ap_const_logic_1 = ap_CS_fsm_state9) and (exitcond_i5_fu_407_p2 = ap_const_lv1_1))) then
storemerge_reg_267 <= tmp_3_fu_433_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then
contacts_size_load_reg_493 <= contacts_size;
database_size_load_reg_502 <= database_size;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_data_reg <= contacts_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
database_index_1_reg_531 <= database_index_1_fu_384_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = database_size_out_1_vld_in) and (ap_const_logic_0 = database_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = database_size_out_1_vld_in) and (ap_const_logic_1 = database_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
database_size_out_1_data_reg <= database_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_data_reg <= error_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
exitcond_reg_536 <= exitcond_fu_390_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
i_2_reg_581 <= i_2_fu_454_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_3_reg_558 <= i_3_fu_413_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_data_reg <= matched_finished_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (ap_const_lv1_0 = exitcond_i5_fu_407_p2))) then
sum_i9_reg_568 <= sum_i9_fu_428_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (ap_const_lv1_0 = exitcond_i_fu_448_p2))) then
sum_i_reg_591 <= sum_i_fu_469_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_0))) then
tmp_2_cast_reg_514(19 downto 6) <= tmp_2_cast_fu_344_p3(19 downto 6);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_fu_390_p2))) then
tmp_4_reg_545(12 downto 0) <= tmp_4_fu_402_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (ap_const_lv1_0 = icmp_fu_361_p2))) then
tmp_9_cast_reg_522(14 downto 6) <= tmp_9_cast_fu_370_p3(14 downto 6);
end if;
end if;
end process;
tmp_2_cast_reg_514(5 downto 0) <= "000000";
tmp_9_cast_reg_522(5 downto 0) <= "000000";
tmp_4_reg_545(63 downto 13) <= "000000000000000000000000000000000000000000000000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, matched_finished_1_ack_in, error_out_1_ack_in, database_size_out_1_ack_in, contacts_size_out_1_ack_in, operation_read_read_fu_116_p2, ap_CS_fsm_state2, tmp_7_fu_336_p2, icmp_fu_361_p2, exitcond2_fu_378_p2, ap_CS_fsm_state3, exitcond_fu_390_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_state9, exitcond_i5_fu_407_p2, ap_CS_fsm_state14, exitcond_i_fu_448_p2, ap_block_pp0_stage0_flag00011011, grp_match_db_contact_fu_302_ap_done, ap_CS_fsm_state4, ap_CS_fsm_state8)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (ap_const_lv1_0 = icmp_fu_361_p2))) then
ap_NS_fsm <= ap_ST_fsm_state14;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (icmp_fu_361_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state16;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state9;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond2_fu_378_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (grp_match_db_contact_fu_302_ap_done = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_390_p2 = ap_const_lv1_1)))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_390_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = database_size_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state9 =>
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (exitcond_i5_fu_407_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state14 =>
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (ap_const_lv1_1 = exitcond_i_fu_448_p2))) then
ap_NS_fsm <= ap_ST_fsm_state17;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(8);
ap_CS_fsm_state11 <= ap_CS_fsm(9);
ap_CS_fsm_state12 <= ap_CS_fsm(10);
ap_CS_fsm_state14 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(13);
ap_CS_fsm_state16 <= ap_CS_fsm(14);
ap_CS_fsm_state17 <= ap_CS_fsm(15);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_CS_fsm_state8 <= ap_CS_fsm(6);
ap_CS_fsm_state9 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_assign_proc : process(ap_start, operation_ap_vld_in_sig)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig));
end process;
ap_block_state5_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_assign_proc : process(matched_finished_1_ack_in, error_out_1_ack_in, database_size_out_1_ack_in, contacts_size_out_1_ack_in)
begin
ap_block_state8 <= ((ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = database_size_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in));
end process;
ap_condition_pp0_exit_iter0_state5_assign_proc : process(exitcond_fu_390_p2)
begin
if ((exitcond_fu_390_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state5 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state5 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(matched_finished_1_ack_in, error_out_1_ack_in, database_size_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = database_size_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(matched_finished_1_ack_in, error_out_1_ack_in, database_size_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state8) and not(((ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = database_size_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
contact_in_address0 <= tmp_i_fu_460_p1(6 - 1 downto 0);
contact_in_ce0_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
contact_in_ce0 <= ap_const_logic_1;
else
contact_in_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_address0_assign_proc : process(grp_match_db_contact_fu_302_contacts_address0, ap_CS_fsm_state4, ap_CS_fsm_state15, sum_i_cast_fu_485_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
contacts_address0 <= sum_i_cast_fu_485_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= grp_match_db_contact_fu_302_contacts_address0;
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(grp_match_db_contact_fu_302_contacts_ce0, ap_CS_fsm_state4, ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
contacts_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_ce0 <= grp_match_db_contact_fu_302_contacts_ce0;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_ce1_assign_proc : process(grp_match_db_contact_fu_302_contacts_ce1, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_ce1 <= grp_match_db_contact_fu_302_contacts_ce1;
else
contacts_ce1 <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_ack_in <= ap_const_logic_1;
else
contacts_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_size, operation_read_read_fu_116_p2, storemerge1_reg_290, ap_CS_fsm_state17)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state17)) then
contacts_size_out_1_data_in <= storemerge1_reg_290;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)))) then
contacts_size_out_1_data_in <= contacts_size;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4))) then
contacts_size_out_1_data_in <= ap_const_lv32_0;
else
contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
contacts_size_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state17)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)) or (ap_const_logic_1 = ap_CS_fsm_state17))) then
contacts_size_out_1_vld_in <= ap_const_logic_1;
else
contacts_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
contacts_we0_assign_proc : process(ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
contacts_we0 <= ap_const_logic_1;
else
contacts_we0 <= ap_const_logic_0;
end if;
end process;
database_address0_assign_proc : process(grp_match_db_contact_fu_302_database_address0, ap_CS_fsm_state4, ap_CS_fsm_state10, sum_i9_cast_fu_444_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
database_address0 <= sum_i9_cast_fu_444_p1(19 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
database_address0 <= grp_match_db_contact_fu_302_database_address0;
else
database_address0 <= "XXXXXXXXXXXXXXXXXXX";
end if;
end process;
database_ce0_assign_proc : process(grp_match_db_contact_fu_302_database_ce0, ap_CS_fsm_state4, ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
database_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
database_ce0 <= grp_match_db_contact_fu_302_database_ce0;
else
database_ce0 <= ap_const_logic_0;
end if;
end process;
database_ce1_assign_proc : process(grp_match_db_contact_fu_302_database_ce1, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
database_ce1 <= grp_match_db_contact_fu_302_database_ce1;
else
database_ce1 <= ap_const_logic_0;
end if;
end process;
database_in_address0 <= tmp_i6_fu_419_p1(6 - 1 downto 0);
database_in_ce0_assign_proc : process(ap_CS_fsm_state9)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
database_in_ce0 <= ap_const_logic_1;
else
database_in_ce0 <= ap_const_logic_0;
end if;
end process;
database_index_1_fu_384_p2 <= std_logic_vector(unsigned(database_index_reg_233) + unsigned(ap_const_lv13_1));
database_size_out_1_ack_in_assign_proc : process(database_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = database_size_out_1_vld_reg) or ((ap_const_logic_1 = database_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
database_size_out_1_ack_in <= ap_const_logic_1;
else
database_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
database_size_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, database_size, operation_read_read_fu_116_p2, storemerge_reg_267, ap_CS_fsm_state12)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
database_size_out_1_data_in <= storemerge_reg_267;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3))) then
database_size_out_1_data_in <= ap_const_lv32_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)))) then
database_size_out_1_data_in <= database_size;
else
database_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
database_size_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state12)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)) or (ap_const_logic_1 = ap_CS_fsm_state12))) then
database_size_out_1_vld_in <= ap_const_logic_1;
else
database_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
database_we0_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
database_we0 <= ap_const_logic_1;
else
database_we0 <= ap_const_logic_0;
end if;
end process;
error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg)
begin
if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_ack_in <= ap_const_logic_1;
else
error_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
error_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state2, tmp_7_fu_336_p2, icmp_fu_361_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (icmp_fu_361_p2 = ap_const_lv1_1))) then
error_out_1_data_in <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_1))) then
error_out_1_data_in <= ap_const_lv32_2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4)))) then
error_out_1_data_in <= ap_const_lv32_3;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_0;
else
error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
error_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state2, tmp_7_fu_336_p2, icmp_fu_361_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_read_read_fu_116_p2 = ap_const_lv32_1) and (tmp_7_fu_336_p2 = ap_const_lv1_1)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_116_p2) and (icmp_fu_361_p2 = ap_const_lv1_1)))) then
error_out_1_vld_in <= ap_const_logic_1;
else
error_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_378_p2 <= "1" when (database_index_reg_233 = ap_const_lv13_1D4C) else "0";
exitcond_fu_390_p2 <= "1" when (i_reg_245 = ap_const_lv13_1D4C) else "0";
exitcond_i5_fu_407_p2 <= "1" when (i_i4_reg_256 = ap_const_lv7_40) else "0";
exitcond_i_fu_448_p2 <= "1" when (i_i_reg_279 = ap_const_lv7_40) else "0";
grp_match_db_contact_fu_302_ap_start <= ap_reg_grp_match_db_contact_fu_302_ap_start;
i_1_fu_396_p2 <= std_logic_vector(unsigned(i_reg_245) + unsigned(ap_const_lv13_1));
i_2_fu_454_p2 <= std_logic_vector(unsigned(i_i_reg_279) + unsigned(ap_const_lv7_1));
i_3_fu_413_p2 <= std_logic_vector(unsigned(i_i4_reg_256) + unsigned(ap_const_lv7_1));
icmp_fu_361_p2 <= "1" when (signed(tmp_fu_352_p4) > signed(ap_const_lv25_0)) else "0";
matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg)
begin
if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_ack_in <= ap_const_logic_1;
else
matched_finished_1_ack_in <= ap_const_logic_0;
end if;
end process;
matched_finished_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state7)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
matched_finished_1_data_in <= ap_const_lv32_1;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))))) then
matched_finished_1_data_in <= ap_const_lv32_0;
else
matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
matched_finished_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_116_p2, ap_CS_fsm_state7)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_4)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_3)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_116_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_116_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_116_p2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_2)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_3)) and not((operation_read_read_fu_116_p2 = ap_const_lv32_4))) or (ap_const_logic_1 = ap_CS_fsm_state7))) then
matched_finished_1_vld_in <= ap_const_logic_1;
else
matched_finished_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_address0 <= tmp_4_reg_545(13 - 1 downto 0);
matched_out_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
matched_out_ce0 <= ap_const_logic_1;
else
matched_out_ce0 <= ap_const_logic_0;
end if;
end process;
matched_out_we0_assign_proc : process(exitcond_reg_536, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond_reg_536))) then
matched_out_we0 <= ap_const_logic_1;
else
matched_out_we0 <= ap_const_logic_0;
end if;
end process;
operation_ap_vld_in_sig_assign_proc : process(operation_ap_vld, operation_ap_vld_preg)
begin
if ((ap_const_logic_1 = operation_ap_vld)) then
operation_ap_vld_in_sig <= operation_ap_vld;
else
operation_ap_vld_in_sig <= operation_ap_vld_preg;
end if;
end process;
operation_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
operation_blk_n <= operation_ap_vld;
else
operation_blk_n <= ap_const_logic_1;
end if;
end process;
operation_in_sig_assign_proc : process(operation, operation_preg, operation_ap_vld)
begin
if ((ap_const_logic_1 = operation_ap_vld)) then
operation_in_sig <= operation;
else
operation_in_sig <= operation_preg;
end if;
end process;
operation_read_read_fu_116_p2 <= operation_in_sig;
results_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, tmp_4_fu_402_p1, grp_match_db_contact_fu_302_results_address0, ap_CS_fsm_state4, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
results_address0 <= tmp_4_fu_402_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
results_address0 <= grp_match_db_contact_fu_302_results_address0;
else
results_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
results_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, grp_match_db_contact_fu_302_results_ce0, ap_CS_fsm_state4)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
results_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
results_ce0 <= grp_match_db_contact_fu_302_results_ce0;
else
results_ce0 <= ap_const_logic_0;
end if;
end process;
results_we0_assign_proc : process(grp_match_db_contact_fu_302_results_we0, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
results_we0 <= grp_match_db_contact_fu_302_results_we0;
else
results_we0 <= ap_const_logic_0;
end if;
end process;
sum_i9_cast_fu_444_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sum_i9_reg_568),64));
sum_i9_fu_428_p2 <= std_logic_vector(unsigned(tmp_i6_cast_fu_424_p1) + unsigned(tmp_2_cast_reg_514));
sum_i_cast_fu_485_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sum_i_reg_591),64));
sum_i_fu_469_p2 <= std_logic_vector(unsigned(tmp_i_cast_fu_465_p1) + unsigned(tmp_9_cast_reg_522));
tmp_127_fu_367_p1 <= contacts_size_load_reg_493(9 - 1 downto 0);
tmp_128_fu_341_p1 <= database_size_load_reg_502(14 - 1 downto 0);
tmp_2_cast_fu_344_p3 <= (tmp_128_fu_341_p1 & ap_const_lv6_0);
tmp_3_fu_433_p2 <= std_logic_vector(unsigned(database_size_load_reg_502) + unsigned(ap_const_lv32_1));
tmp_4_fu_402_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_245),64));
tmp_7_fu_336_p2 <= "1" when (signed(database_size_load_reg_502) > signed(ap_const_lv32_1D4B)) else "0";
tmp_9_cast_fu_370_p3 <= (tmp_127_fu_367_p1 & ap_const_lv6_0);
tmp_fu_352_p4 <= contacts_size_load_reg_493(31 downto 7);
tmp_i6_cast_fu_424_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i4_reg_256),20));
tmp_i6_fu_419_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i4_reg_256),64));
tmp_i_cast_fu_465_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_279),15));
tmp_i_fu_460_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_279),64));
tmp_s_fu_474_p2 <= std_logic_vector(unsigned(contacts_size_load_reg_493) + unsigned(ap_const_lv32_1));
end behav;
| gpl-3.0 |
JL-Grande/Ascensor_SED | ASCENSOR/tb_gestor_display.vhd | 1 | 2109 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gestor_display IS
END tb_gestor_display;
ARCHITECTURE behavior OF tb_gestor_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gestor_display
PORT(
CLK : IN std_logic;
piso_now : IN std_logic_vector(1 downto 0);
piso_obj : IN std_logic_vector(1 downto 0);
piso_seleccionado : OUT std_logic_vector(1 downto 0);
piso_actual : OUT std_logic_vector(1 downto 0);
accion : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal piso_now : std_logic_vector(1 downto 0) := (others => '0');
signal piso_obj : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal piso_seleccionado : std_logic_vector(1 downto 0);
signal piso_actual : std_logic_vector(1 downto 0);
signal accion : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gestor_display PORT MAP (
CLK => CLK,
piso_now => piso_now,
piso_obj => piso_obj,
piso_seleccionado => piso_seleccionado,
piso_actual => piso_actual,
accion => accion
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
WAIT FOR 2 ns;
piso_now <= "01";
piso_obj <= "11";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_obj <= "00";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_obj <= "01";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_now <= "00";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/srl_fifo/vhdl_source/srl_fifo.vhd | 2 | 3787 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the SRL16 properties,
-- implementing a 16-deep synchronous fifo in only one LUT per
-- bit. It is a fall-through fifo.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo is
generic (Width : integer := 32;
Depth : integer := 15; -- 15 is the maximum
Threshold : integer := 13);
port (
clock : in std_logic;
reset : in std_logic;
GetElement : in std_logic;
PutElement : in std_logic;
FlushFifo : in std_logic;
DataIn : in std_logic_vector(Width-1 downto 0);
DataOut : out std_logic_vector(Width-1 downto 0);
SpaceInFifo : out std_logic;
AlmostFull : out std_logic;
DataInFifo : out std_logic);
end srl_fifo;
architecture Gideon of srl_fifo is
signal NumElements : std_logic_vector(3 downto 0);
signal FilteredGet : std_logic;
signal FilteredPut : std_logic;
signal DataInFifo_i : std_logic;
signal SpaceInFifo_i : std_logic;
constant Depth_std : std_logic_vector(3 downto 0) := conv_std_logic_vector(Depth-1, 4);
begin
FilteredGet <= DataInFifo_i and GetElement;
FilteredPut <= SpaceInFifo_i and PutElement;
DataInFifo <= DataInFifo_i;
SpaceInFifo <= SpaceInFifo_i;
process(clock)
variable NewCnt : std_logic_vector(3 downto 0);--integer range 0 to Depth;
begin
if rising_edge(clock) then
if FlushFifo='1' then
NewCnt := "1111"; --0;
elsif (FilteredGet='1') and (FilteredPut='0') then
NewCnt := NumElements - 1;
elsif (FilteredGet='0') and (FilteredPut='1') then
NewCnt := NumElements + 1;
else
NewCnt := NumElements;
end if;
NumElements <= NewCnt;
if (NewCnt > Threshold) and (NewCnt /= "1111") then
AlmostFull <= '1';
else
AlmostFull <= '0';
end if;
if (NewCnt = "1111") then
DataInFifo_i <= '0';
else
DataInFifo_i <= '1';
end if;
if (NewCnt /= Depth_std) then
SpaceInFifo_i <= '1';
else
SpaceInFifo_i <= '0';
end if;
if Reset='1' then
NumElements <= "1111";
SpaceInFifo_i <= '1';
DataInFifo_i <= '0';
AlmostFull <= '0';
end if;
end if;
end process;
SRLs : for srl2 in 0 to Width-1 generate
i_SRL : SRL16E
port map (
CLK => clock,
CE => FilteredPut,
D => DataIn(srl2),
A3 => NumElements(3),
A2 => NumElements(2),
A1 => NumElements(1),
A0 => NumElements(0),
Q => DataOut(srl2) );
end generate;
end Gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4_u1.vhd | 5 | 14386 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4_u1 is
generic (
g_simulation : boolean := false;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
ETH_Acc_Time : integer := 9;
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 4;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
ETH_CSn : out std_logic := '1';
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z');
MEM_BEn : out std_logic );
end ext_mem_ctrl_v4_u1;
-- ADDR: 25 24 23 22 21 20 19 ...
-- 0 0 0 0 0 0 0 SRAM
-- 0 x x x x x x SDRAM
-- 1 0 x x x x x Flash
-- 1 1 x x x x x Ethernet
architecture Gideon of ext_mem_ctrl_v4_u1 is
type t_init is record
addr : std_logic_vector(23 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"000400", "010" ), -- auto precharge
( X"000220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ) );
type t_state is (boot, init, idle, setup, pulse, hold, sd_cas, sd_wait, eth_pulse);
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(7 downto 0);
signal memsel : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal dack : std_logic; -- for simulation handy to see
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
resp.data <= rdata_i;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
resp.rack <= '1';
resp.rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
mem_a_i <= std_logic_vector(req.address(MEM_A'range));
sram_d_t <= not req.read_writen;
sram_d_o <= req.data;
SRAM_CSn <= '1';
FLASH_CSn <= '1';
ETH_CSn <= '1';
SDRAM_CSn <= '1';
memsel <= '0';
if req.address(25 downto 24) = "11" then
ETH_CSn <= '0';
delay <= ETH_Acc_Time;
state <= eth_pulse;
elsif req.address(25 downto 24) = "10" then
memsel <= '1';
FLASH_CSn <= '0';
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if req.read_writen='0' then -- write
MEM_BEn <= '0';
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif req.address(25 downto 19)=0 then
SRAM_CSn <= '0';
if req.read_writen='0' then -- write
MEM_BEn <= '0';
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
else -- SDRAM
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(17 downto 16) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end if;
end procedure;
begin
if rising_edge(clock) then
resp.rack <= '0';
dack <= '0';
resp.rack_tag <= (others => '0');
resp.dack_tag <= (others => '0');
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
send_refresh_cmd;
elsif inhibit='0' then
if req.request='1' and refr_delay=0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
if memsel='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when eth_pulse =>
delay <= delay - 1;
case delay is
when 2 =>
dack <= '1';
resp.dack_tag <= tag;
MEM_WEn <= '1';
MEM_OEn <= '1';
when 1 =>
sram_d_t <= '0';
ETH_CSn <= '1';
state <= idle;
when others =>
MEM_WEn <= rwn_i;
MEM_OEn <= not rwn_i;
end case;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
ETH_CSn <= '1';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
MEM_BEn <= '1';
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm_pkg.vhd | 5 | 5996 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.slot_bus_pkg.all;
package slot_bus_master_bfm_pkg is
type t_slot_bus_master_bfm_object;
type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object;
type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read,
e_slot_io_write, e_slot_bus_write );
type t_slot_bus_master_bfm_object is record
next_bfm : p_slot_bus_master_bfm_object;
name : string(1 to 256);
command : t_slot_bus_bfm_command;
poll_time : time;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
irq_pending : boolean;
end record;
------------------------------------------------------------------------------------
shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object);
end slot_bus_master_bfm_pkg;
package body slot_bus_master_bfm_pkg is
procedure register_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_slot_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if slot_bus_master_bfms = null then -- first entry
slot_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := slot_bus_master_bfms;
slot_bus_master_bfms := pntr;
end if;
pntr.irq_pending := false;
pntr.poll_time := 10 ns;
end register_slot_bus_master_bfm;
procedure bind_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
variable p : p_slot_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := slot_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_slot_bus_master_bfm;
------------------------------------------------------------------------------
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is
begin
while not m.irq_pending loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/harness_c1541.vhd | 4 | 5613 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; | gpl-3.0 |
KB777/1541UltimateII | fpga/io/iec_interface/vhdl_sim/dual_iec_processor_tb.vhd | 5 | 5118 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity dual_iec_processor_tb is
end dual_iec_processor_tb;
architecture tb of dual_iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal master_req : t_io_req;
signal master_resp : t_io_resp;
signal slave_req : t_io_req;
signal slave_resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_master: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => master_req,
resp => master_resp,
clk_o => master_clk_o,
clk_i => iec_clock,
data_o => master_data_o,
data_i => iec_data,
atn_o => master_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
i_slave: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => slave_req,
resp => slave_resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => open,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_master" )
port map (
clock => clock,
req => master_req,
resp => master_resp );
i_io_bfm2: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_slave" )
port map (
clock => clock,
req => slave_req,
resp => slave_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_master", iom);
io_write(iom, X"3", X"01"); -- enable master
io_write(iom, X"5", X"4D"); -- switch to master mode
io_write(iom, X"4", X"2A"); -- listen 10
io_write(iom, X"4", X"F0"); -- open file on channel 0
io_write(iom, X"5", X"4C"); -- attention to TX
io_write(iom, X"4", X"41"); -- 'A'
io_write(iom, X"5", X"01"); -- EOI
io_write(iom, X"4", X"42"); -- 'B'
io_write(iom, X"5", X"4D"); -- again, be master
io_write(iom, X"4", X"3F"); -- unlisten
io_write(iom, X"4", X"4A"); -- talk #10!
io_write(iom, X"4", X"60"); -- give data from channel 0
io_write(iom, X"5", X"4A"); -- attention to RX turnaround
wait;
end process;
process
variable ios : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_slave", ios);
io_write(ios, X"3", X"01"); -- enable slave
while true loop
io_read(ios, X"2", stat);
if stat(0)='0' then -- byte available
io_read(ios, X"6", data);
if stat(7)='1' then -- control byte
report "Control byte received: " & hstr(data);
if (data = X"43") then
report "Talk back!";
io_write(ios, X"4", X"31");
io_write(ios, X"4", X"32");
io_write(ios, X"4", X"33");
io_write(ios, X"5", X"01"); -- EOI
io_write(ios, X"4", X"34");
end if;
else
report "Data byte received: " & hstr(data);
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v7.vhd | 5 | 2933 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/usb2/vhdl_sim/usb_harness_nano.vhd | 1 | 4314 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-02-14
-- Author: Gideon
-- Description: Harness for USB Host Controller with memory controller
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity usb_harness_nano is
port (
clocks_stopped : in boolean := false );
end entity;
architecture arch of usb_harness_nano is
signal sys_clock : std_logic := '1';
signal sys_clock_2x : std_logic := '1';
signal sys_reset : std_logic;
signal clock : std_logic := '0';
signal reset : std_logic;
signal sys_io_req : t_io_req;
signal sys_io_resp : t_io_resp;
signal sys_mem_req : t_mem_req_32;
signal sys_mem_resp : t_mem_resp_32;
signal ulpi_nxt : std_logic;
signal ulpi_stp : std_logic;
signal ulpi_dir : std_logic;
signal ulpi_data : std_logic_vector(7 downto 0);
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
begin
sys_clock <= not sys_clock after 10 ns when not clocks_stopped;
sys_clock_2x <= not sys_clock_2x after 5 ns when not clocks_stopped;
sys_reset <= '1', '0' after 50 ns;
clock <= not clock after 8.333 ns when not clocks_stopped;
reset <= '1', '0' after 250 ns;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io" )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp );
i_host: entity work.usb_host_nano
generic map (
g_simulation => true )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => sys_mem_req,
sys_mem_resp=> sys_mem_resp,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_ulpi_phy: entity work.ulpi_master_bfm
generic map (
g_given_name => "device" )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_device: entity work.usb_device_model;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => '0',
is_idle => open,
req => sys_mem_req,
resp => sys_mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
end arch;
| gpl-3.0 |
KB777/1541UltimateII | target/simulation/vhdl_sim/mblite_simu.vhd | 1 | 4321 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
core0 : core
port map (
imem_o => imem_o,
imem_i => imem_i,
dmem_o => dmem_o,
dmem_i => dmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if imem_o.ena_o = '1' then
imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2))));
-- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then
-- report "Suspicious CMPS" severity warning;
-- end if;
end if;
if dmem_o.ena_o = '1' then
if dmem_o.adr_o(31 downto 25) = "0000000" then
if dmem_o.we_o = '1' then
for i in 0 to 3 loop
if dmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if dmem_o.we_o = '1' then -- write
case dmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := dmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(dmem_o.adr_o) & " dropped";
end case;
else -- read
case dmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
dmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
dmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
dmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
dmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(dmem_o.adr_o) & " dropped";
dmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
imem_i.ena_i <= '1';
dmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_bus.vhd | 3 | 3037 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_decode.vhd | 4 | 9778 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_decode is
end tb_decode;
architecture tb of tb_decode is
signal i_reg : std_logic_vector(7 downto 0);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_shift : boolean;
signal s_is_alu : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_is_illegal : boolean;
signal s_select_index_y : boolean;
signal s_store_a_from_alu : boolean;
signal s_load_a : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal opcode : string(1 to 13);
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_shift <= is_shift(i_reg);
s_is_alu <= is_alu(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_is_illegal <= is_illegal(i_reg);
s_select_index_y <= select_index_y(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
s_load_a <= load_a(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
test: process
begin
for i in 0 to 255 loop
i_reg <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
assert not (opcode(4)=' ' and s_is_illegal) report "Function says it's illegal, opcode does not." severity error;
assert not (opcode(4)='*' and not s_is_illegal) report "Opcode says it's illegal, function says it's not." severity error;
end loop;
wait;
end process;
dump: process
variable inst : std_logic_vector(7 downto 0);
variable bool : boolean;
variable L : line;
type t_bool_array is array(natural range <>) of boolean;
type t_sel_array is array(natural range <>) of std_logic_vector(1 downto 0);
variable b_is_absolute : t_bool_array(0 to 255);
variable b_is_abs_jump : t_bool_array(0 to 255);
variable b_is_immediate : t_bool_array(0 to 255);
variable b_is_implied : t_bool_array(0 to 255);
variable b_is_stack : t_bool_array(0 to 255);
variable b_is_push : t_bool_array(0 to 255);
variable b_is_zeropage : t_bool_array(0 to 255);
variable b_is_indirect : t_bool_array(0 to 255);
variable b_is_relative : t_bool_array(0 to 255);
variable b_is_load : t_bool_array(0 to 255);
variable b_is_store : t_bool_array(0 to 255);
variable b_is_shift : t_bool_array(0 to 255);
variable b_is_alu : t_bool_array(0 to 255);
variable b_is_rmw : t_bool_array(0 to 255);
variable b_is_jump : t_bool_array(0 to 255);
variable b_is_postindexed : t_bool_array(0 to 255);
variable b_select_index_y : t_bool_array(0 to 255);
variable b_store_a_from_alu : t_bool_array(0 to 255);
variable b_shift_sel : t_sel_array(0 to 255);
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
procedure output_bool(bool : boolean) is
begin
if bool then
write_str(L, " (*) ");
else
write_str(L, " . ");
end if;
end procedure;
procedure output_shift_sel(bool : boolean; sel: std_logic_vector(1 downto 0)) is
type t_string_array is array(natural range <>) of string(1 to 5);
constant c_shift_sel_str : t_string_array(0 to 3) := ( "0xFF ", "data ", "accu ", " A&D " );
begin
if bool then
write_str(L, c_shift_sel_str(conv_integer(sel)));
else
write_str(L, " . ");
end if;
end procedure;
procedure print_table(b : t_bool_array; title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := conv_std_logic_vector(x*32, 8);
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := conv_std_logic_vector(y, 8);
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_bool(b(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure print_sel_table(title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := conv_std_logic_vector(x*32, 8);
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := conv_std_logic_vector(y, 8);
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_shift_sel(b_is_shift(y + x*32), b_shift_sel(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
begin
for i in 0 to 255 loop
inst := conv_std_logic_vector(i, 8);
b_is_absolute(i) := is_absolute(inst);
b_is_abs_jump(i) := is_abs_jump(inst);
b_is_immediate(i) := is_immediate(inst);
b_is_implied(i) := is_implied(inst);
b_is_stack(i) := is_stack(inst);
b_is_push(i) := is_push(inst);
b_is_zeropage(i) := is_zeropage(inst);
b_is_indirect(i) := is_indirect(inst);
b_is_relative(i) := is_relative(inst);
b_is_load(i) := is_load(inst);
b_is_store(i) := is_store(inst);
b_is_shift(i) := is_shift(inst);
b_is_alu(i) := is_alu(inst);
b_is_rmw(i) := is_rmw(inst);
b_is_jump(i) := is_jump(inst);
b_is_postindexed(i) := is_postindexed(inst);
b_select_index_y(i) := select_index_y(inst);
b_store_a_from_alu(i) := store_a_from_alu(inst);
b_shift_sel(i) := shifter_in_select(inst);
end loop;
print_table(b_is_absolute , "is_absolute");
print_table(b_is_abs_jump , "is_abs_jump");
print_table(b_is_immediate , "is_immediate");
print_table(b_is_implied , "is_implied");
print_table(b_is_stack , "is_stack");
print_table(b_is_push , "is_push");
print_table(b_is_zeropage , "is_zeropage");
print_table(b_is_indirect , "is_indirect");
print_table(b_is_relative , "is_relative");
print_table(b_is_load , "is_load");
print_table(b_is_store , "is_store");
print_table(b_is_shift , "is_shift");
print_table(b_is_alu , "is_alu");
print_table(b_is_rmw , "is_rmw");
print_table(b_is_jump , "is_jump");
print_table(b_is_postindexed , "is_postindexed");
print_table(b_select_index_y , "Select index Y");
print_table(b_store_a_from_alu , "Store A from ALU");
print_sel_table("Shifter Input");
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/ulpi_bus.vhd | 3 | 7397 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5_sdr.vhd | 5 | 14469 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_sdr is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
req : in t_mem_burst_req;
resp : out t_mem_burst_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5_sdr;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5_sdr is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002A", "000" ), -- mode register, burstlen=4, writelen=4, CAS lat = 2, interleaved
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sdram_d_t : std_logic_vector(3 downto 0) := "0000";
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal cs_n_i : std_logic;
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(3 downto 0) := "0000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal addr_row : std_logic_vector(12 downto 0);
signal addr_column : std_logic_vector(9 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of rdata : signal is "true"; -- the general memctrl/rdata must be packed in IOB
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic;
signal push_cmd : std_logic;
begin
addr_bank <= address_fifo(3 downto 2);
addr_row <= address_fifo(24 downto 12);
addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
-- addr_row <= address_fifo(24 downto 12);
-- addr_bank <= address_fifo(11 downto 10);
-- addr_column <= address_fifo(9 downto 0);
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av;
resp.ready <= not cmd_af;
push_cmd <= req.request and not cmd_af;
-- resp.rack <= rack;
-- resp.dack <= dack(0);
-- resp.dnext <= dnext(0);
-- resp.blast <= (dack(0) and not dack(1)) or (dnext(0) and not dnext(1));
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(cmd_fifo_data_out'high);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_read_fifo: entity work.srl_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => dack(0),
FlushFifo => '0',
DataIn => rdata,
DataOut => resp.data,
SpaceInFifo => open,
AlmostFull => rdata_af,
DataInFifo => resp.rdata_av );
i_write_fifo: entity work.SRL_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => dnext(0),
PutElement => req.data_push,
FlushFifo => '0',
DataIn => req.data,
DataOut => wdata,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => open );
process(clock)
procedure send_refresh_cmd is
begin
if refr_delay = 0 then
do_refresh <= '0';
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
last_bank <= addr_bank;
mem_a_i(12 downto 0) <= addr_row;
mem_a_i(14 downto 13) <= addr_bank;
col_addr <= addr_column;
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
if rwn_fifo='0' then
dnext <= "1111";
delay <= 0;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
cs_n_i <= '1';
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
sdram_d_o <= wdata;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
sdram_d_t <= '0' & sdram_d_t(3 downto 1);
dack <= '0' & dack(3 downto 1);
dnext <= '0' & dnext(3 downto 1);
rdata <= MEM_D;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
cs_n_i <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and next_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
-- we always perform auto precharge.
-- If the next access is to ANOTHER bank, then
-- we do not have to wait AFTER issuing this CAS.
-- the delay after the CAS, causes the next RAS to
-- be further away in time. If there is NO access
-- pending, then we assume the same bank, and introduce
-- the delay.
refr_delay <= 5;
if (req_i='1' and addr_bank=last_bank) or req_i='0' then
next_delay <= 5;
else
next_delay <= 2;
end if;
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
if rwn_i='0' then
if delay=0 then
-- write with auto precharge
sdram_d_t <= "1111";
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
delay <= 2;
state <= sd_wait;
end if;
else
if delay = 0 then
if rdata_af='0' then
-- read with auto precharge
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
delay <= 2;
state <= sd_wait;
end if;
end if;
end if;
when sd_wait =>
if delay=1 then
state <= idle;
end if;
if delay=1 and rwn_i='1' then
dack <= "1111";
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sdram_d_t <= (others => '0');
delay <= 0;
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
process(state, do_refresh, inhibit, inhibit_d, req_i, next_delay)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
null;
elsif inhibit='0' then
if req_i='1' and next_delay = 0 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
MEM_D <= sdram_d_o after 7 ns when sdram_d_t(0)='1' else (others => 'Z') after 7 ns;
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
SDRAM_CSn <= cs_n_i;
end Gideon;
| gpl-3.0 |
emabello42/FREAK-on-FPGA | embeddedretina_ise/rom_coe.vhd | 1 | 3818 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company: LCR
-- Engineer: Emmanuel Bello
--
-- Create Date: 16:44:33 10/24/2013
-- Design Name:
-- Module Name: rom_coe - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rom_coe is
port(
clk: in std_logic;
address: in std_logic_vector(N_GAUSS_KERNEL_BW-1 downto 0);
data_out: out std_logic_vector(KERNEL_ROM_BW-1 downto 0)
);
end rom_coe;
architecture Behavioral of rom_coe is
type rom_coe_type is array (NUMBER_OF_KERNELS-1 downto 0) of std_logic_vector (KERNEL_ROM_BW-1 downto 0);
constant rom_coe_data : rom_coe_type :=
(
0 => ("0000101001000001010010000010100010000101000000001001110"),
1 => ("0000111011000001110110000011101000000111000000001101011"),
2 => ("0001001100100010011000000100100100001000101000000000000"),
3 => ("0001101011100011010010000110000110000000000000000000000"),
4 => ("0010110000000101010000000000000000000000000000000000000"),
5 => ("0010110110000101001010000000000000000000000000000000000"),
6 => ("1000000000000000000000000000000000000000000000000000000"),
7 => ("0000111010000001110100000011100110000111000100001101111"),
8 => ("0001001011000010010101000100100100001000111000000000000"),
9 => ("0001101001000011001111000110010000000000000000000000000"),
10 => ("0010101101100101010011000000000000000000000000000000000"),
11 => ("0010110000000101010000000000000000000000000000000000000"),
12 => ("0010110110000101001010000000000000000000000000000000000"),
13 => ("1000000000000000000000000000000000000000000000000000000"),
14 => ("0001001010000010010100000100100100001001000000000000000"),
15 => ("0001001011000010010101000100100100001000111000000000000"),
16 => ("0001101001000011001111000110010000000000000000000000000"),
17 => ("0010101101100101010011000000000000000000000000000000000"),
18 => ("0010110000000101010000000000000000000000000000000000000"),
19 => ("1000000000000000000000000000000000000000000000000000000"),
20 => ("1000000000000000000000000000000000000000000000000000000")
);
begin
rom: process(clk)
begin
if rising_edge(clk) then
data_out <=rom_coe_data(to_integer(resize(unsigned(address),N_GAUSS_KERNEL_BW)));
-- data_out <=rom_coe_data(0);
end if;
end process rom;
end architecture Behavioral;
| gpl-3.0 |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/core/fetch.vhd | 1 | 2738 | ----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
signal rst_d : std_logic;
signal ena_o : std_logic;
signal possibly_valid : std_logic;
begin
fetch_o.program_counter <= r.program_counter;
fetch_o.instruction <= imem_i.dat_i;
fetch_o.inst_valid <= possibly_valid and imem_i.ena_i;
ena_o <= ena_i and imem_i.ena_i;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_o;
fetch_comb: process(fetch_i, imem_i, r, rst_d)
variable v : fetch_out_type;
begin
v := r;
if rst_d = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' or imem_i.ena_i = '0' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
rst_d <= '1';
possibly_valid <= '0';
elsif ena_i = '1' then
r <= rin;
rst_d <= '0';
if imem_i.ena_i = '1' then
possibly_valid <= ena_o;
end if;
end if;
end if;
end process;
end arch; | gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/c1541_timing.vhd | 4 | 2249 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity c1541_timing is
port (
clock : in std_logic;
reset : in std_logic;
use_c64_reset : in std_logic;
c64_reset_n : in std_logic;
iec_reset_n : in std_logic;
iec_reset_o : out std_logic;
drive_stop : in std_logic;
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic ); -- 1/50 (1 MHz)
end c1541_timing;
architecture Gideon of c1541_timing is
signal div_cnt : unsigned(3 downto 0) := "0000";
signal pre_cnt : unsigned(1 downto 0) := "00";
signal cpu_clock_en_i : std_logic := '0';
signal toggle : std_logic := '0';
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
signal c64_reset_sh : std_logic_vector(0 to 2) := "000";
begin
process(clock)
begin
if rising_edge(clock) then
drv_clock_en <= '0';
cpu_clock_en_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_clock_en_i <= '1';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_clock_en_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
c64_reset_sh(0) <= use_c64_reset and not c64_reset_n;
c64_reset_sh(1 to 2) <= c64_reset_sh(0 to 1);
end if;
if reset='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
end process;
cpu_clock_en <= cpu_clock_en_i;
iec_reset_o <= '1' when (iec_reset_sh="111") or (c64_reset_sh="111") else '0';
end Gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper.vhd | 5 | 4244 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.copper_pkg.all;
entity copper is
generic (
g_copper_size : natural := 12 );
port (
clock : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
phi2_tick : in std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp );
end entity;
architecture gideon of copper is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_gate : std_logic := '0';
signal copper_addr : unsigned(g_copper_size-1 downto 0);
signal copper_rdata : std_logic_vector(7 downto 0);
signal copper_wdata : std_logic_vector(7 downto 0);
signal copper_we : std_logic;
signal copper_en : std_logic;
signal control : t_copper_control;
signal status : t_copper_status;
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
i_regs: entity work.copper_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => g_copper_size,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(g_copper_size-1 downto 0),
a_rdata => ram_rdata,
a_wdata => io_req_ram.data,
a_en => '1',
a_we => io_req_ram.write,
b_clock => clock,
b_address => copper_addr,
b_rdata => copper_rdata,
b_wdata => copper_wdata,
b_en => copper_en,
b_we => copper_we );
process(clock)
begin
if rising_edge(clock) then
io_resp_ram.ack <= io_req_ram.read or io_req_ram.write;
ram_gate <= io_req_ram.read;
end if;
end process;
io_resp_ram.data <= ram_rdata when ram_gate='1' else X"00";
i_fsm: entity work.copper_engine
generic map (
g_copper_size => g_copper_size )
port map (
clock => clock,
reset => reset,
irq_n => irq_n,
phi2_tick => phi2_tick,
ram_address => copper_addr,
ram_rdata => copper_rdata,
ram_wdata => copper_wdata,
ram_en => copper_en,
ram_we => copper_we,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
slot_req => slot_req,
slot_resp => slot_resp,
dma_req => dma_req,
dma_resp => dma_resp,
control => control,
status => status );
end gideon;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/tb_simple_sram.vhd | 5 | 2631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_simple_sram is
end tb_simple_sram;
architecture tb of tb_simple_sram is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : std_logic := '0';
signal readwriten : std_logic := '1';
signal address : std_logic_vector(15 downto 0) := (others => '0');
signal rack : std_logic;
signal dack : std_logic;
signal wdata : std_logic_vector(31 downto 0) := X"12345678";
signal wdata_mask : std_logic_vector(3 downto 0) := X"5";
signal rdata : std_logic_vector(31 downto 0);
signal SRAM_A : std_logic_vector(15 downto 0);
signal SRAM_OEn : std_logic;
signal SRAM_WEn : std_logic;
signal SRAM_CSn : std_logic;
signal SRAM_D : std_logic_vector(31 downto 0) := (others => 'Z');
signal SRAM_BEn : std_logic_vector(3 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
mut: entity work.simple_sram
generic map (
SRAM_Byte_Lanes => 4,
SRAM_Data_Width => 32,
SRAM_WR_ASU => 1,
SRAM_WR_Pulse => 2,
SRAM_WR_Hold => 2,
SRAM_RD_ASU => 0,
SRAM_RD_Pulse => 5,
SRAM_RD_Hold => 1, -- recovery time (bus turnaround)
SRAM_A_Width => 16 )
port map (
clock => clock,
reset => reset,
req => req,
readwriten => readwriten,
address => address,
rack => rack,
dack => dack,
wdata => wdata,
wdata_mask => wdata_mask,
rdata => rdata,
--
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_D,
SRAM_BEn => SRAM_BEn );
test: process
procedure do_access(a : std_logic_vector; rw : std_logic; d : std_logic_vector) is
begin
req <= '1';
readwriten <= rw;
address <= a;
wdata <= d;
wait until clock='1';
while rack='0' loop
wait until clock='1';
end loop;
req <= '0';
-- while dack='0' loop
-- wait until clock='1';
-- end loop;
end do_access;
begin
wait until reset='0';
wait until clock='1';
do_access(X"1111", '1', X"00000000");
do_access(X"2233", '1', X"00000000");
do_access(X"4444", '0', X"55AA9933");
do_access(X"5678", '0', X"12345678");
do_access(X"9999", '1', X"00000000");
wait;
end process;
end tb;
| gpl-3.0 |
KB777/1541UltimateII | fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd | 5 | 931 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sine_osc_tb is
end sine_osc_tb;
architecture tb of sine_osc_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal sine : signed(15 downto 0);
signal cosine : signed(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
osc: entity work.sine_osc
port map (
clock => clock,
reset => reset,
sine => sine,
cosine => cosine );
process
variable n: time;
variable p: integer;
begin
wait until reset='0';
n := now;
while true loop
wait until sine(15)='1';
p := (now - n) / 20 ns;
n := now;
report "Period: " & integer'image(p) & " samples" severity note;
end loop;
end process;
end tb; | gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd | 5 | 931 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sine_osc_tb is
end sine_osc_tb;
architecture tb of sine_osc_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal sine : signed(15 downto 0);
signal cosine : signed(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
osc: entity work.sine_osc
port map (
clock => clock,
reset => reset,
sine => sine,
cosine => cosine );
process
variable n: time;
variable p: integer;
begin
wait until reset='0';
n := now;
while true loop
wait until sine(15)='1';
p := (now - n) / 20 ns;
n := now;
report "Period: " & integer'image(p) & " samples" severity note;
end loop;
end process;
end tb; | gpl-3.0 |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v6.vhd | 5 | 2933 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v6 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v6;
architecture tb of fpga_mem_test_v6 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp : t_mem_burst_16_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_v6
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
| gpl-3.0 |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_io_regs_pkg.vhd | 5 | 2668 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_io_regs_pkg is
constant c_sid_voices : unsigned(3 downto 0) := X"0";
constant c_sid_filter_div : unsigned(3 downto 0) := X"1";
constant c_sid_base_left : unsigned(3 downto 0) := X"2";
constant c_sid_base_right : unsigned(3 downto 0) := X"3";
constant c_sid_snoop_left : unsigned(3 downto 0) := X"4";
constant c_sid_snoop_right : unsigned(3 downto 0) := X"5";
constant c_sid_enable_left : unsigned(3 downto 0) := X"6";
constant c_sid_enable_right : unsigned(3 downto 0) := X"7";
constant c_sid_extend_left : unsigned(3 downto 0) := X"8";
constant c_sid_extend_right : unsigned(3 downto 0) := X"9";
constant c_sid_wavesel_left : unsigned(3 downto 0) := X"A";
constant c_sid_wavesel_right : unsigned(3 downto 0) := X"B";
type t_sid_control is record
base_left : unsigned(11 downto 4);
snoop_left : std_logic;
enable_left : std_logic;
extend_left : std_logic;
comb_wave_left : std_logic;
base_right : unsigned(11 downto 4);
snoop_right : std_logic;
enable_right : std_logic;
extend_right : std_logic;
comb_wave_right : std_logic;
end record;
constant c_sid_control_init : t_sid_control := (
base_left => X"40",
snoop_left => '1',
enable_left => '1',
extend_left => '0',
comb_wave_left => '0',
base_right => X"40",
snoop_right => '1',
enable_right => '1',
extend_right => '0',
comb_wave_right => '0' );
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 7...1 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 4...1 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 4...3 are significant)
-- .. etc
end package;
| gpl-3.0 |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate2_test.vhd | 1 | 5017 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ultimate2_test is
port (
CLOCK : in std_logic;
-- slot side
PHI2 : out std_logic;
DOTCLK : out std_logic;
RSTn : out std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : out std_logic_vector(15 downto 0);
SLOT_DATA : out std_logic_vector(7 downto 0);
RWn : out std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : out std_logic;
GAMEn : out std_logic;
ROMHn : out std_logic;
ROMLn : out std_logic;
IO1n : in std_logic;
IO2n : out std_logic;
IRQn : out std_logic;
NMIn : out std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : out std_logic := '0';
CAS_SENSE : out std_logic := 'Z';
CAS_READ : out std_logic := 'Z';
CAS_WRITE : out std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_test;
architecture structural of ultimate2_test is
signal counter : unsigned(23 downto 0) := (others => '0');
signal pulses : unsigned(23 downto 1) := (others => '0');
begin
process(CLOCK)
begin
if rising_edge(CLOCK) then
counter <= counter + 1;
pulses <= counter(23 downto 1) and counter(22 downto 0);
end if;
end process;
-- slot side
BUFFER_ENn <= '0';
SLOT_ADDR <= std_logic_vector(counter(23 downto 8));
SLOT_DATA <= std_logic_vector(counter(7 downto 0));
-- top
DMAn <= pulses(1);
--BA <= pulses(2);
ROMLn <= pulses(3);
IO2n <= pulses(4);
EXROMn <= pulses(5);
GAMEn <= pulses(6);
--IO1n <= pulses(7);
DOTCLK <= pulses(8);
RWn <= pulses(9);
IRQn <= pulses(10);
PHI2 <= pulses(11);
NMIn <= pulses(12);
RSTn <= pulses(13);
ROMHn <= pulses(14);
-- Cassette Interface
CAS_SENSE <= pulses(16);
CAS_READ <= pulses(17);
CAS_WRITE <= pulses(18);
CAS_MOTOR <= pulses(19);
-- local bus side
LB_ADDR <= (others => 'Z');
LB_DATA <= (others => 'Z');
SDRAM_CSn <= 'Z';
SDRAM_RASn <= 'Z';
SDRAM_CASn <= 'Z';
SDRAM_WEn <= 'Z';
SDRAM_DQM <= 'Z';
SDRAM_CKE <= 'Z';
SDRAM_CLK <= 'Z';
-- PWM outputs (for audio)
PWM_OUT <= "ZZ";
-- IEC bus
IEC_ATN <= 'Z';
IEC_DATA <= 'Z';
IEC_CLOCK <= 'Z';
IEC_SRQ_IN <= 'Z';
DISK_ACTn <= '0';
CART_LEDn <= '1';
SDACT_LEDn <= '0';
MOTOR_LEDn <= '1';
-- Debug UART
UART_TXD <= '1';
-- SD Card Interface
SD_SSn <= 'Z';
SD_CLK <= 'Z';
SD_MOSI <= 'Z';
SD_DATA <= "ZZ";
-- RTC Interface
RTC_CS <= '0';
RTC_SCK <= '0';
RTC_MOSI <= '0';
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= '0';
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end structural;
| gpl-3.0 |
mprska/vhdmake | test/test/b.vhd | 2 | 74 | architecture b of a is
begin -- architecture b
end architecture b;
| gpl-3.0 |
nick1au/Home-Sec-SYS | halfSecDelay.vhd | 2 | 818 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity halfSecDelay is
Port (load, clock: in std_logic;
TC: out std_logic);
End Entity halfSecDelay;
Architecture csa of halfSecDelay is
Type StateName is (idle, hold, count);
signal Prest, NxtSt, idlenxt, holdnxt, countnxt: StateName;
signal decrement_str, decrement: unsigned(1 downto 0);
begin
idlenxt <= hold when load ='1' else idle;
holdnxt <= count when load ='0' else hold;
countnxt <= idle when decrement_str = "00" ELSE count;
NxtSt <= idlenxt when prest = idle else holdnxt when prest = hold else countnxt;
Prest <= NxtSt when rising_edge (clock);
decrement <= "11" when prest /= count else decrement_str - 1;
decrement_str <= decrement when rising_edge(clock);
TC <= '1' when prest = hold and nxtSt= count else '0';
end csa; | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/te/video_io_to_hdmi/video_io_to_hdmi.vhd | 1 | 5498 | ----------------------------------------------------------------------------------
-- Company: Trenz Electronic GmbH
-- Engineer: Antti Lukats
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity video_io_to_hdmi is Port (
vid_data: in STD_LOGIC_VECTOR(23 downto 0);
vid_active_video : in STD_LOGIC;
vid_hsync : in STD_LOGIC;
vid_vsync : in STD_LOGIC;
vid_io_in_clk : in STD_LOGIC;
hdmi_data: out STD_LOGIC_VECTOR(11 downto 0);
hdmi_de : out STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC
);
end video_io_to_hdmi;
architecture Behavioral of video_io_to_hdmi is
constant Low : std_logic := '0';
constant High : std_logic := '1';
signal vid_data_i : std_logic_vector(23 downto 0);
signal DE_i : std_logic;
signal active_video_d : std_logic;
begin
-- Swap G and B
vid_data_i(7 downto 0) <= vid_data(15 downto 8);
vid_data_i(15 downto 8) <= vid_data(7 downto 0);
vid_data_i(23 downto 16) <= vid_data(23 downto 16);
--
-- delay DE 1 clock?
--
DE_FF_inst : FDRE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => active_video_d, -- Data output
C => vid_io_in_clk, -- Clock input
CE => High, -- Clock enable input
R => Low, -- Synchronous reset input
D => vid_active_video -- Data input
);
-- make DE start 1 clock later
DE_i <= active_video_d and vid_active_video;
CLK_ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hdmi_clk, -- 1-bit DDR output
C => vid_io_in_clk, -- 1-bit clock input
CE => High, -- 1-bit clock enable input
D1 => High, -- 1-bit data input (positive edge)
D2 => Low, -- 1-bit data input (negative edge)
R => Low, -- 1-bit reset input
S => Low -- 1-bit set input
);
gen_hdmi_io: for i in 0 to 11 generate
IO_ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hdmi_data(i), -- 1-bit DDR output
C => vid_io_in_clk, -- 1-bit clock input
CE => High, -- 1-bit clock enable input
D1 => vid_data_i(i), -- 1-bit data input (positive edge)
D2 => vid_data_i(i + 12), -- 1-bit data input (negative edge)
R => Low, -- 1-bit reset input
S => Low -- 1-bit set input
);
end generate gen_hdmi_io;
VSYNC_ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hdmi_vsync, -- 1-bit DDR output
C => vid_io_in_clk, -- 1-bit clock input
CE => High, -- 1-bit clock enable input
D1 => vid_vsync, -- 1-bit data input (positive edge)
D2 => vid_vsync, -- 1-bit data input (negative edge)
R => Low, -- 1-bit reset input
S => Low -- 1-bit set input
);
HSYNC_ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hdmi_hsync, -- 1-bit DDR output
C => vid_io_in_clk, -- 1-bit clock input
CE => High, -- 1-bit clock enable input
D1 => vid_hsync, -- 1-bit data input (positive edge)
D2 => vid_hsync, -- 1-bit data input (negative edge)
R => Low, -- 1-bit reset input
S => Low -- 1-bit set input
);
DE_ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => hdmi_de, -- 1-bit DDR output
C => vid_io_in_clk, -- 1-bit clock input
CE => High, -- 1-bit clock enable input
D1 => DE_i, -- 1-bit data input (positive edge)
D2 => DE_i, -- 1-bit data input (negative edge)
R => Low, -- 1-bit reset input
S => Low -- 1-bit set input
);
end Behavioral;
| gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_i2s_adi/i2s_clkgen.vhd | 8 | 4899 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
| gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_i2s_adi/i2s_tx.vhd | 8 | 4792 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_tx is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
C_NUM : integer := 1
);
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean; -- Enable TX
bclk : in std_logic; -- Bit Clock
channel_sync : in std_logic; -- Channel Sync
frame_sync : in std_logic; -- Frame Sync
sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output
ack : out std_logic; -- Request new Slot Data
stb : in std_logic; -- Request new Slot Data
data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in
);
end i2s_tx;
architecture Behavioral of i2s_tx is
type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0);
signal data_int : mem;
signal reset_int : Boolean;
signal enable_int : Boolean;
signal bit_sync : std_logic;
signal channel_sync_int : std_logic;
signal frame_sync_int : std_logic;
signal channel_sync_int_d1 : std_logic;
signal bclk_d1 : std_logic;
begin
reset_int <= resetn = '0' or not enable;
process (clk)
begin
if rising_edge(clk) then
if resetn = '0' then
bclk_d1 <= '0';
channel_sync_int_d1 <= '0';
else
bclk_d1 <= bclk;
channel_sync_int_d1 <= channel_sync_int;
end if;
end if;
end process;
bit_sync <= (bclk xor bclk_d1) and not bclk;
channel_sync_int <= channel_sync and bit_sync;
frame_sync_int <= frame_sync and bit_sync;
ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0';
gen: for i in 0 to C_NUM - 1 generate
serialize_data: process(clk)
begin
if rising_edge(clk) then
if reset_int then
data_int(i)(31 downto 0) <= (others => '0');
elsif bit_sync = '1' then
if channel_sync_int = '1' then
data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data;
data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0');
else
data_int(i) <= data_int(i)(30 downto 0) & '0';
end if;
end if;
end if;
end process serialize_data;
sdata(i) <= data_int(i)(31) when enable_int else '0';
end generate;
enable_sync: process (clk)
begin
if rising_edge(clk) then
if reset_int then
enable_int <= False;
else
if enable and frame_sync_int = '1' and stb = '1' then
enable_int <= True;
elsif not enable then
enable_int <= False;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_ulpi_bus.vhd | 2 | 7417 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of usb1_ulpi_bus : entity is "yes";
end usb1_ulpi_bus;
architecture gideon of usb1_ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/eth_filter.vhd | 1 | 13457 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : eth_filter
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_filter is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"13" );
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
-- interface to free block system
alloc_req : out std_logic;
alloc_resp : in t_alloc_resp;
used_req : out t_used_req;
used_resp : in std_logic;
-- interface to memory
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_rx_data : in std_logic_vector(7 downto 0);
eth_rx_sof : in std_logic;
eth_rx_eof : in std_logic;
eth_rx_valid : in std_logic );
end entity;
architecture gideon of eth_filter is
-- signals in the sys_clock domain
type t_mac is array(0 to 5) of std_logic_vector(7 downto 0);
signal my_mac : t_mac := (others => (others => '0'));
type t_mac_16 is array(0 to 2) of std_logic_vector(15 downto 0);
signal my_mac_16 : t_mac_16 := (others => (others => '0'));
signal eth_rx_enable : std_logic;
signal clear : std_logic;
signal rx_enable : std_logic;
signal promiscuous : std_logic;
signal rd_next : std_logic;
signal rd_dout : std_logic_vector(17 downto 0);
signal rd_valid : std_logic;
type t_receive_state is (idle, odd, even, len, ovfl);
signal receive_state : t_receive_state;
type t_state is (idle, get_block, drop, copy, valid_packet, pushing, ram_write);
signal state : t_state;
signal address_valid : std_logic;
signal start_addr : unsigned(25 downto 0);
signal mac_idx : integer range 0 to 3;
signal for_me : std_logic;
signal block_id : unsigned(7 downto 0);
-- memory signals
signal mem_addr : unsigned(25 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_req : std_logic;
-- signals in eth_clock domain
signal eth_wr_din : std_logic_vector(17 downto 0);
signal eth_wr_en : std_logic;
signal eth_wr_full : std_logic;
signal eth_length : unsigned(11 downto 0);
signal crc_ok : std_logic;
signal toggle : std_logic;
begin
-- 18 wide fifo; 16 data bits and 2 control bits
-- 00 = packet data
-- 01 = overflow detected => drop
-- 10 = packet with CRC error => drop
-- 11 = packet OK!
i_fifo: entity work.async_fifo_ft
generic map (
--g_fast => true,
g_data_width => 18,
g_depth_bits => 9
)
port map (
wr_clock => eth_clock,
wr_reset => eth_reset,
wr_en => eth_wr_en,
wr_din => eth_wr_din,
wr_full => eth_wr_full,
rd_clock => clock,
rd_reset => clear,
rd_next => rd_next,
rd_dout => rd_dout,
rd_valid => rd_valid
);
clear <= reset or not rx_enable;
process(eth_clock)
begin
if rising_edge(eth_clock) then
eth_wr_en <= '0';
case receive_state is
when idle =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_length <= to_unsigned(1, eth_length'length);
if eth_rx_sof = '1' and eth_rx_valid = '1' then
receive_state <= odd;
end if;
when odd =>
eth_wr_din(15 downto 8) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_wr_full = '1' then
receive_state <= ovfl;
else
eth_wr_en <= '1';
crc_ok <= eth_rx_data(0);
if eth_rx_eof = '1' then
receive_state <= len;
else
receive_state <= even;
end if;
end if;
end if;
when even =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_rx_eof = '1' then
receive_state <= len;
crc_ok <= eth_rx_data(0);
else
receive_state <= odd;
end if;
end if;
when len =>
if eth_wr_full = '0' then
eth_wr_din <= (others => '0');
eth_wr_din(17) <= '1';
eth_wr_din(16) <= crc_ok;
eth_wr_din(eth_length'range) <= std_logic_vector(eth_length);
eth_wr_en <= '1';
receive_state <= idle;
else
receive_state <= ovfl;
end if;
when ovfl =>
if eth_wr_full = '0' then
eth_wr_din(17 downto 16) <= "01";
eth_wr_en <= '1';
receive_state <= idle;
end if;
end case;
if eth_reset = '1' or eth_rx_enable = '0' then
receive_state <= idle;
crc_ok <= '0';
end if;
end if;
end process;
i_sync_enable: entity work.level_synchronizer
port map (
clock => eth_clock,
reset => eth_reset,
input => rx_enable,
input_c => eth_rx_enable
);
process(clock)
alias local_addr : unsigned(3 downto 0) is io_req.address(3 downto 0);
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write = '1' then
io_resp.ack <= '1';
case local_addr is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5" =>
my_mac(to_integer(local_addr)) <= io_req.data;
when X"7" =>
promiscuous <= io_req.data(0);
when X"8" =>
rx_enable <= io_req.data(0);
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case local_addr is
when others =>
null;
end case;
end if;
if reset = '1' then
promiscuous <= '0';
rx_enable <= '0';
end if;
end if;
end process;
-- condense to do 16 bit compares with data from fifo
my_mac_16(0) <= my_mac(1) & my_mac(0);
my_mac_16(1) <= my_mac(3) & my_mac(2);
my_mac_16(2) <= my_mac(5) & my_mac(4);
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
mac_idx <= 0;
toggle <= '0';
for_me <= '1';
if rx_enable = '0' then
address_valid <= '0';
end if;
if rd_valid = '1' then -- packet data available!
if rd_dout(17 downto 16) = "00" then
if rx_enable = '0' then
state <= drop;
elsif address_valid = '1' then
mem_addr <= start_addr;
state <= copy;
else
alloc_req <= '1';
state <= get_block;
end if;
else
state <= drop; -- resyncronize
end if;
end if;
when get_block =>
if alloc_resp.done = '1' then
alloc_req <= '0';
block_id <= alloc_resp.id;
if alloc_resp.error = '1' then
state <= drop;
else
start_addr <= alloc_resp.address;
mem_addr <= alloc_resp.address;
address_valid <= '1';
state <= copy;
end if;
end if;
when drop =>
if (rd_valid = '1' and rd_dout(17 downto 16) /= "00") or (rx_enable = '0') then
state <= idle;
end if;
when copy =>
if rx_enable = '0' then
state <= idle;
elsif rd_valid = '1' then
if mac_idx /= 3 then
if rd_dout(15 downto 0) /= X"FFFF" and rd_dout(15 downto 0) /= my_mac_16(mac_idx) then
for_me <= '0';
end if;
mac_idx <= mac_idx + 1;
end if;
toggle <= not toggle;
if toggle = '0' then
mem_data(31 downto 16) <= rd_dout(15 downto 0);
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= ram_write;
end if;
else
mem_data(15 downto 0) <= rd_dout(15 downto 0);
end if;
case rd_dout(17 downto 16) is
when "01" =>
-- overflow detected
write_req <= '0';
state <= idle;
when "10" =>
-- packet with bad CRC
write_req <= '0';
state <= idle;
when "11" =>
-- correct packet!
used_req.bytes <= unsigned(rd_dout(used_req.bytes'range)) - 5; -- snoop FF and CRC
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= valid_packet;
else
state <= idle;
end if;
when others =>
null;
end case;
end if;
when ram_write =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
mem_addr <= mem_addr + 4;
state <= copy;
end if;
when valid_packet =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
if for_me = '1' or promiscuous = '1' then
address_valid <= '0';
used_req.request <= '1';
used_req.id <= block_id;
state <= pushing;
else
state <= idle;
end if;
end if;
when pushing =>
if used_resp = '1' then
used_req.request <= '0';
state <= idle;
end if;
end case;
if reset = '1' then
alloc_req <= '0';
used_req <= c_used_req_init;
state <= idle;
address_valid <= '0';
write_req <= '0';
end if;
end if;
end process;
mem_req.request <= write_req;
mem_req.data <= mem_data;
mem_req.address <= mem_addr;
mem_req.read_writen <= '0';
mem_req.byte_en <= (others => '1');
mem_req.tag <= g_mem_tag;
process(state)
begin
case state is
when drop =>
rd_next <= '1';
when copy =>
rd_next <= '1'; -- do something here with memory
when others =>
rd_next <= '0';
end case;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/assert3.vhd | 5 | 177 | entity assert3 is
begin
l : assert (false)
report "should assert"
severity note;
end entity assert3;
architecture a of assert3 is
begin
end architecture a;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cia_pkg.vhd | 1 | 3109 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cia_pkg is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
type timer_t is
record
run : std_logic;
pbon : std_logic;
outmode : std_logic;
runmode : std_logic;
load : std_logic;
inmode : std_logic_vector(1 downto 0);
end record;
constant timer_default : timer_t := (
run => '0',
pbon => '0',
outmode => '0',
runmode => '0',
load => '0',
inmode => "00" );
type time_t is
record
pm : std_logic;
hr : unsigned(4 downto 0);
minh : unsigned(2 downto 0);
minl : unsigned(3 downto 0);
sech : unsigned(2 downto 0);
secl : unsigned(3 downto 0);
tenths : unsigned(3 downto 0);
end record;
constant time_default : time_t := ('1', "10001", "000", X"0", "000", X"0", X"0");
constant alarm_default : time_t := ('0', "00000", "000", X"0", "000", X"0", X"0");
type tod_t is
record
alarm_set : std_logic;
freq_sel : std_logic;
tod : time_t;
alarm : time_t;
end record;
constant tod_default : tod_t := (
alarm_set => '0',
freq_sel => '0',
tod => time_default,
alarm => alarm_default );
procedure do_tod_tick(signal t : inout time_t);
end;
package body cia_pkg is
procedure do_tod_tick(signal t : inout time_t) is
begin
if t.tenths=X"9" then
t.tenths <= X"0";
if t.secl=X"9" then
t.secl <= X"0";
if t.sech="101" then
t.sech <= "000";
if t.minl=X"9" then
t.minl <= X"0";
if t.minh="101" then
t.minh <= "000";
if t.hr="01001" then
t.hr <= "10000";
elsif t.hr="01111" then
t.hr <= "00000";
elsif t.hr="11111" then
t.hr <= "10000";
elsif t.hr="10010" then
t.hr <= "00001";
elsif t.hr="10001" then
t.hr <= "10010";
t.pm <= not t.pm;
else
t.hr <= t.hr + 1;
end if;
else
t.minh <= t.minh + 1;
end if;
else
t.minl <= t.minl + 1;
end if;
else
t.sech <= t.sech + 1;
end if;
else
t.secl <= t.secl + 1;
end if;
else
t.tenths <= t.tenths + 1;
end if;
end procedure do_tod_tick;
end; | gpl-3.0 |
markusC64/1541ultimate2 | fpga/altera/align_read_to_bram.vhd | 1 | 5884 | --------------------------------------------------------------------------------
-- Entity: align_read_to_bram
-- Date:2015-03-14
-- Author: Gideon
--
-- Description: This module aligns 32 bit reads from memory to writes to BRAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity align_read_to_bram is
port (
clock : in std_logic;
reset : in std_logic;
rdata : in std_logic_vector(31 downto 0);
rdata_valid : in std_logic;
first_word : in std_logic;
last_word : in std_logic;
offset : in unsigned(1 downto 0);
last_bytes : in unsigned(1 downto 0);
wdata : out std_logic_vector(31 downto 0);
wmask : out std_logic_vector(3 downto 0);
wnext : out std_logic );
end align_read_to_bram;
-- This unit implements data rotation. This is done to support streaming from memory.
-- Length that this unit gets is: actual length + offset + 3. This indicates the last byte that
-- is being read and thus valid for writing.
-- int (size / 4) = number of words to be accessed.
-- (size and 3) = info about byte enables of last beat 0 = 0001, 1 = 0011, 2 = 0111, 3 = 1111.
-- for writing, these byte enables shall still be rotated to the right.
-- offset = info about byte enables of first beat, and rotation value
-- Note that for an offset of 0, it doesn't really matter if we write a few extra bytes in the BRAM,
-- because we're aligned. However, for an offset other than 0, it determines whether
-- we should write the last beat or not.
architecture arch of align_read_to_bram is
type t_state is (idle, stream, last);
signal state : t_state;
signal remain : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
wmask <= X"0";
wnext <= '0';
-- we always get 3210, regardless of the offset.
-- If the offset is 0, we pass all data
-- If the offset is 1, we save 3 bytes (321x), and go to the next state
-- If the offset is 2, we save 2 bytes (32xx), and go to the next state
-- If the offset is 3, we save 1 byte (3xxx), and go to the next state
-- In case the offset was sent to the DRAM, we get:
-- If the offset is 1, we save 3 bytes (x321), and go to the next state
-- If the offset is 2, we save 2 bytes (xx32), and go to the next state
-- If the offset is 3, we save 1 byte (xxx3), and go to the next state
case state is
when idle =>
wdata <= rdata;
if rdata_valid = '1' then -- we assume first word
remain <= rdata;
case offset is
when "00" => -- aligned
wmask <= X"F";
wnext <= '1';
when others =>
if last_word = '1' then
state <= last;
else
state <= stream;
end if;
end case;
end if;
when stream =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
if rdata_valid = '1' then
remain <= rdata;
wmask <= X"F";
wnext <= '1';
if last_word = '1' then
if offset > last_bytes then
state <= idle;
else
state <= last;
end if;
end if;
end if;
when last =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
wmask <= X"F";
state <= idle;
-- case last_bytes is
-- when "01" =>
-- wmask <= "0001";
-- when "10" =>
-- wmask <= "0011";
-- when "11" =>
-- wmask <= "0111";
-- when others =>
-- wmask <= "0000";
-- end case;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
end if;
end if;
end process;
end arch;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/mult_acc.vhd | 6 | 7965 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity mult_acc is
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice3_off_l : in std_logic;
voice3_off_r : in std_logic;
filter_en : in std_logic := '0';
enveloppe : in unsigned(7 downto 0);
waveform : in unsigned(11 downto 0);
--
osc3 : out std_logic_vector(7 downto 0);
env3 : out std_logic_vector(7 downto 0);
--
valid_out : out std_logic;
direct_out_L : out signed(17 downto 0);
direct_out_R : out signed(17 downto 0);
filter_out_L : out signed(17 downto 0);
filter_out_R : out signed(17 downto 0) );
end mult_acc;
-- architecture unsigned_wave of mult_acc is
-- signal filter_m : std_logic;
-- signal voice_m : unsigned(3 downto 0);
-- signal mult_m : unsigned(19 downto 0);
-- signal accu_f : unsigned(17 downto 0);
-- signal accu_u : unsigned(17 downto 0);
-- signal enable_d : std_logic;
-- signal direct_i : unsigned(17 downto 0);
-- signal filter_i : unsigned(17 downto 0);
-- begin
-- process(clock)
-- variable mult_ext : unsigned(21 downto 0);
-- variable mult_trunc : unsigned(21 downto 4);
-- begin
-- if rising_edge(clock) then
-- -- latch outputs
-- if reset='1' then
-- osc3 <= (others => '0');
-- env3 <= (others => '0');
-- elsif voice_i = X"2" then
-- osc3 <= std_logic_vector(waveform(11 downto 4));
-- env3 <= std_logic_vector(enveloppe);
-- end if;
--
-- mult_ext := extend(mult_m, mult_ext'length);
-- mult_trunc := mult_ext(mult_trunc'range);
-- filter_m <= filter_en;
-- voice_m <= voice_i;
-- mult_m <= enveloppe * waveform;
-- valid_out <= '0';
-- enable_d <= enable_i;
--
-- if enable_d='1' then
-- if voice_m = 0 then
-- valid_out <= '1';
-- direct_i <= accu_u;
-- filter_i <= accu_f;
-- if filter_m='1' then
-- accu_f <= mult_trunc;
-- accu_u <= (others => '0');
-- else
-- accu_f <= (others => '0');
-- accu_u <= mult_trunc;
-- end if;
-- else
-- valid_out <= '0';
-- if filter_m='1' then
-- accu_f <= sum_limit(accu_f, mult_trunc);
-- else
-- if (voice_m /= 2) or (voice3_off = '0') then
-- accu_u <= sum_limit(accu_u, mult_trunc);
-- end if;
-- end if;
-- end if;
-- end if;
--
-- if reset = '1' then
-- valid_out <= '0';
-- accu_u <= (others => '0');
-- accu_f <= (others => '0');
-- direct_i <= (others => '0');
-- filter_i <= (others => '0');
-- end if;
-- end if;
-- end process;
--
-- direct_out <= '0' & signed(direct_i(17 downto 1));
-- filter_out <= '0' & signed(filter_i(17 downto 1));
-- end unsigned_wave;
--
architecture signed_wave of mult_acc is
signal filter_m : std_logic;
signal voice_m : unsigned(3 downto 0);
signal mult_m : signed(20 downto 0);
signal accu_fl : signed(17 downto 0);
signal accu_fr : signed(17 downto 0);
signal accu_ul : signed(17 downto 0);
signal accu_ur : signed(17 downto 0);
signal enable_d : std_logic;
begin
process(clock)
variable mult_ext : signed(21 downto 0);
variable mult_trunc : signed(21 downto 4);
variable env_signed : signed(8 downto 0);
variable wave_signed: signed(11 downto 0);
begin
if rising_edge(clock) then
-- latch outputs
if reset='1' then
osc3 <= (others => '0');
env3 <= (others => '0');
elsif voice_i = X"2" then
osc3 <= std_logic_vector(waveform(11 downto 4));
env3 <= std_logic_vector(enveloppe);
end if;
env_signed := '0' & signed(enveloppe);
wave_signed := not waveform(11) & signed(waveform(10 downto 0));
mult_ext := extend(mult_m, mult_ext'length);
mult_trunc := mult_ext(mult_trunc'range);
filter_m <= filter_en;
voice_m <= voice_i;
mult_m <= env_signed * wave_signed;
valid_out <= '0';
enable_d <= enable_i;
if enable_d='1' then
if voice_m = 0 then
valid_out <= '1';
direct_out_l <= accu_ul;
direct_out_r <= accu_ur;
filter_out_l <= accu_fl;
filter_out_r <= accu_fr;
accu_fr <= (others => '0');
accu_ur <= (others => '0');
if filter_m='1' then
accu_fl <= mult_trunc;
accu_ul <= (others => '0');
else
accu_fl <= (others => '0');
accu_ul <= mult_trunc;
end if;
elsif voice_m(3)='0' then
valid_out <= '0';
if filter_m='1' then
accu_fl <= sum_limit(accu_fl, mult_trunc);
else
if (voice_m /= 2) or (voice3_off_l = '0') then
accu_ul <= sum_limit(accu_ul, mult_trunc);
end if;
end if;
else -- upper 8 voices go to right
valid_out <= '0';
if filter_m='1' then
accu_fr <= sum_limit(accu_fr, mult_trunc);
else
if (voice_m /= 10) or (voice3_off_r = '0') then
accu_ur <= sum_limit(accu_ur, mult_trunc);
end if;
end if;
end if;
end if;
if reset = '1' then
valid_out <= '0';
accu_ul <= (others => '0');
accu_fl <= (others => '0');
accu_ur <= (others => '0');
accu_fr <= (others => '0');
direct_out_l <= (others => '0');
direct_out_r <= (others => '0');
filter_out_l <= (others => '0');
filter_out_r <= (others => '0');
end if;
end if;
end process;
end signed_wave;
| gpl-3.0 |
chiggs/nvc | test/regress/elab5.vhd | 5 | 749 | entity sub is
port (
x : out integer );
end entity;
architecture one of sub is
begin
x <= 1;
end architecture;
architecture two of sub is
begin
x <= 2;
end architecture;
-------------------------------------------------------------------------------
entity elab5 is
end entity;
architecture test of elab5 is
signal x1, x2, x3 : integer;
begin
sub1: entity work.sub(one)
port map ( x1 );
sub2: entity work.sub(two)
port map ( x2 );
sub3: entity work.sub -- Should select `two'
port map ( x3 );
process is
begin
wait for 1 ns;
assert x1 = 1;
assert x2 = 2;
assert x3 = 2;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4_u1.vhd | 5 | 14386 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4_u1 is
generic (
g_simulation : boolean := false;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
ETH_Acc_Time : integer := 9;
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 4;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
ETH_CSn : out std_logic := '1';
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z');
MEM_BEn : out std_logic );
end ext_mem_ctrl_v4_u1;
-- ADDR: 25 24 23 22 21 20 19 ...
-- 0 0 0 0 0 0 0 SRAM
-- 0 x x x x x x SDRAM
-- 1 0 x x x x x Flash
-- 1 1 x x x x x Ethernet
architecture Gideon of ext_mem_ctrl_v4_u1 is
type t_init is record
addr : std_logic_vector(23 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"000400", "010" ), -- auto precharge
( X"000220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ) );
type t_state is (boot, init, idle, setup, pulse, hold, sd_cas, sd_wait, eth_pulse);
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(7 downto 0);
signal memsel : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal dack : std_logic; -- for simulation handy to see
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
resp.data <= rdata_i;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
resp.rack <= '1';
resp.rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
mem_a_i <= std_logic_vector(req.address(MEM_A'range));
sram_d_t <= not req.read_writen;
sram_d_o <= req.data;
SRAM_CSn <= '1';
FLASH_CSn <= '1';
ETH_CSn <= '1';
SDRAM_CSn <= '1';
memsel <= '0';
if req.address(25 downto 24) = "11" then
ETH_CSn <= '0';
delay <= ETH_Acc_Time;
state <= eth_pulse;
elsif req.address(25 downto 24) = "10" then
memsel <= '1';
FLASH_CSn <= '0';
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if req.read_writen='0' then -- write
MEM_BEn <= '0';
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif req.address(25 downto 19)=0 then
SRAM_CSn <= '0';
if req.read_writen='0' then -- write
MEM_BEn <= '0';
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
else -- SDRAM
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(17 downto 16) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end if;
end procedure;
begin
if rising_edge(clock) then
resp.rack <= '0';
dack <= '0';
resp.rack_tag <= (others => '0');
resp.dack_tag <= (others => '0');
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
send_refresh_cmd;
elsif inhibit='0' then
if req.request='1' and refr_delay=0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
if memsel='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when eth_pulse =>
delay <= delay - 1;
case delay is
when 2 =>
dack <= '1';
resp.dack_tag <= tag;
MEM_WEn <= '1';
MEM_OEn <= '1';
when 1 =>
sram_d_t <= '0';
ETH_CSn <= '1';
state <= idle;
when others =>
MEM_WEn <= rwn_i;
MEM_OEn <= not rwn_i;
end case;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
ETH_CSn <= '1';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
MEM_BEn <= '1';
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 |
fpgaddicted/5bit-shift-register-structural- | top_module.vhd | 1 | 2301 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:49:40 04/09/2017
-- Design Name:
-- Module Name: top_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity display_controller is
Port ( seg7 : out STD_LOGIC_VECTOR (0 to 7);
clk : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
reset : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0));
end display_controller;
architecture Driver of display_controller is
COMPONENT decoder_states IS
PORT (
op : in STD_LOGIC_VECTOR (3 downto 0);
data_o : out STD_LOGIC_VECTOR (0 to 7);
anode_s : in STD_LOGIC_VECTOR (3 downto 0));
END COMPONENT;
COMPONENT anode_fsm IS
PORT (
clk : in STD_LOGIC;
anode_o : out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC);
END COMPONENT;
COMPONENT prescaler IS
PORT (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC);
END COMPONENT;
signal an : std_logic_vector (3 downto 0);
signal click : std_logic;
signal dec : std_logic_vector (3 downto 0);
begin
fsm1 : anode_fsm
PORT MAP (
clk => click,
anode_o => an,
reset => reset
);
display : decoder_states
PORT MAP (
op => dec,
data_o => seg7,
anode_s => an
);
clock : prescaler
PORT MAP (
clk_in => clk,
clk_out => click,
reset => reset
);
anodes <= an;
dec <=(reset,opcode(2),opcode(1),opcode(0));
end Driver;
| gpl-3.0 |
chiggs/nvc | test/sem/issue130.vhd | 5 | 223 | package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_ulpi_rx.vhd | 2 | 5945 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end usb1_ulpi_rx;
architecture gideon of usb1_ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.usb1_data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/ip/clock/vhdl_source/fractional_div.vhd | 1 | 3428 | --------------------------------------------------------------------------------
-- Entity: fractional_div
-- Date:2018-08-18
-- Author: gideon
--
-- Description: Fractional Divider
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_div is
generic (
g_numerator : natural := 3;
g_denominator : natural := 200 );
port (
clock : in std_logic;
tick : out std_logic; -- this should yield a 16 MHz tick
tick_by_4 : out std_logic; -- this should yield a 4 MHz tick (for drive logic)
tick_by_16 : out std_logic; -- this should yield an 1 MHz tick (i.e. for IEC processor)
one_16000 : out std_logic ); -- and thus, this should yield a 1 ms tick
end entity;
architecture arch of fractional_div is
constant c_min : integer := -g_numerator;
constant c_max : integer := g_denominator - g_numerator - 1;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
if 2**v_result < arg then
v_result := v_result + 1;
end if;
assert false report "Ceil: " & integer'image(arg) & " result: " & integer'image(v_result) severity warning;
return v_result;
end function;
function maxof2(a, b : integer) return integer is
variable res : integer;
begin
res := b;
assert false report "Max: " & integer'image(a) & " and " & integer'image(b) severity warning;
if a > b then
res := a;
end if;
return res;
end function;
signal c_bits_min : integer := 1 + log2_ceil(-c_min - 1);
signal c_bits_max : integer := 1 + log2_ceil(c_max);
signal accu : signed(7 downto 0) := (others => '0');
signal div16000 : unsigned(13 downto 0) := to_unsigned(128, 14);
begin
assert c_bits_max <= 8 report "Need more bits for accu (max:"&integer'image(c_max)&", but Xilinx doesn't let me define this dynamically:" & integer'image(c_bits_max) severity error;
assert c_bits_min <= 8 report "Need more bits for accu (max:"&integer'image(c_min)&", but Xilinx doesn't let me define this dynamically:" & integer'image(c_bits_min) severity error;
process(clock)
begin
if rising_edge(clock) then
tick <= '0';
one_16000 <= '0';
tick_by_4 <= '0';
tick_by_16 <= '0';
if accu(accu'high) = '1' then
if div16000 = 0 then
one_16000 <= '1';
div16000 <= to_unsigned(15999, 14);
else
div16000 <= div16000 - 1;
end if;
if div16000(3 downto 0) = "0001" then
tick_by_16 <= '1';
end if;
if div16000(1 downto 0) = "01" then
tick_by_4 <= '1';
end if;
tick <= '1';
accu <= accu + (g_denominator - g_numerator);
else
accu <= accu - g_numerator;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_host_nano.vhd | 1 | 9936 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-02-12
-- Author: Gideon
-- Description: Top level of second generation USB controller with memory
-- interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_nano is
generic (
g_big_endian : boolean;
g_incl_debug : boolean := false;
g_tag : std_logic_vector(7 downto 0) := X"05";
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
error_pulse : out std_logic;
--
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req_32;
sys_mem_resp: in t_mem_resp_32;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp;
sys_irq : out std_logic );
end entity;
architecture arch of usb_host_nano is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal nano_rdata_cmd : std_logic_vector(15 downto 0);
signal nano_stall : std_logic := '0';
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_address : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal reg_rdata : std_logic_vector(7 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal status : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
signal do_chirp : std_logic;
signal chirp_data : std_logic;
signal sof_enable : std_logic;
signal mem_ctrl_ready : std_logic;
signal buf_address : unsigned(10 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_addr : std_logic_vector(10 downto 2);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic_vector(3 downto 0);
signal sys_buf_wdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata_le: std_logic_vector(31 downto 0);
signal usb_tx_req : t_usb_tx_req;
signal usb_tx_resp : t_usb_tx_resp;
signal usb_rx : t_usb_rx;
signal usb_cmd_req : t_usb_cmd_req;
signal usb_cmd_resp : t_usb_cmd_resp;
signal frame_count : unsigned(15 downto 0);
signal sof_tick : std_logic;
signal interrupt : std_logic;
begin
i_intf: entity work.usb_host_interface
generic map (
g_simulation => g_simulation )
port map (
clock => clock,
reset => reset,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp,
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
reg_ack => reg_ack,
do_chirp => do_chirp,
chirp_data => chirp_data,
status => status,
speed => speed,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_seq: entity work.host_sequencer
port map (
clock => clock,
reset => reset,
buf_address => buf_address,
buf_en => buf_en,
buf_we => buf_we,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
frame_count => frame_count,
error_pulse => error_pulse,
usb_cmd_req => usb_cmd_req,
usb_cmd_resp => usb_cmd_resp,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
i_buf_ram: RAMB16BWE_S36_S9
port map (
CLKB => clock,
SSRB => reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => std_logic_vector(buf_address),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata,
DIPA => "0000",
DOA => sys_buf_rdata_le );
sys_buf_rdata <= byte_swap(sys_buf_rdata_le, g_big_endian);
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => clock,
ulpi_reset => reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_big_endian => g_big_endian,
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_sync: entity work.level_synchronizer
port map (
clock => clock,
reset => reset,
input => cmd_ready,
input_c => mem_ctrl_ready );
i_nano_io: entity work.nano_minimal_io
generic map (
g_support_suspend => false )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
cmd_response => nano_rdata_cmd,
status => status,
mem_ctrl_ready => mem_ctrl_ready,
frame_count => frame_count,
do_chirp => do_chirp,
chirp_data => chirp_data,
connected => open,
operational => open,
suspended => open,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
interrupt_out => interrupt );
i_sync2: entity work.pulse_synchronizer
port map (
clock_in => clock,
pulse_in => interrupt,
clock_out => sys_clock,
pulse_out => sys_irq );
i_cmd_io: entity work.usb_cmd_nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_wdata => nano_wdata,
io_rdata => nano_rdata_cmd,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp );
i_debug: entity work.usb_debug
generic map (
g_enabled => g_incl_debug )
port map (
clock => clock,
reset => reset,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp,
debug_data => debug_data,
debug_valid => debug_valid
);
i_nano: entity work.nano
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
end arch;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/icap/vhdl_source/icap_pkg.vhd | 5 | 312 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package icap_pkg is
constant c_icap_fpga_type : unsigned(3 downto 0) := X"0";
constant c_icap_write : unsigned(3 downto 0) := X"4";
constant c_icap_pulse : unsigned(3 downto 0) := X"8";
end package;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_32_tb.vhd | 5 | 7761 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
| gpl-3.0 |
chiggs/nvc | test/lower/proc1.vhd | 4 | 364 | entity proc1 is
end entity;
architecture test of proc1 is
procedure add1(x : in integer; y : out integer) is
begin
y := x + 1;
end procedure;
begin
process is
variable a, b : integer;
begin
add1(a, b);
assert b = 3;
add1(5, b);
assert b = 6;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/copper/vhdl_source/copper.vhd | 5 | 4244 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.copper_pkg.all;
entity copper is
generic (
g_copper_size : natural := 12 );
port (
clock : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
phi2_tick : in std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp );
end entity;
architecture gideon of copper is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_gate : std_logic := '0';
signal copper_addr : unsigned(g_copper_size-1 downto 0);
signal copper_rdata : std_logic_vector(7 downto 0);
signal copper_wdata : std_logic_vector(7 downto 0);
signal copper_we : std_logic;
signal copper_en : std_logic;
signal control : t_copper_control;
signal status : t_copper_status;
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
i_regs: entity work.copper_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => g_copper_size,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(g_copper_size-1 downto 0),
a_rdata => ram_rdata,
a_wdata => io_req_ram.data,
a_en => '1',
a_we => io_req_ram.write,
b_clock => clock,
b_address => copper_addr,
b_rdata => copper_rdata,
b_wdata => copper_wdata,
b_en => copper_en,
b_we => copper_we );
process(clock)
begin
if rising_edge(clock) then
io_resp_ram.ack <= io_req_ram.read or io_req_ram.write;
ram_gate <= io_req_ram.read;
end if;
end process;
io_resp_ram.data <= ram_rdata when ram_gate='1' else X"00";
i_fsm: entity work.copper_engine
generic map (
g_copper_size => g_copper_size )
port map (
clock => clock,
reset => reset,
irq_n => irq_n,
phi2_tick => phi2_tick,
ram_address => copper_addr,
ram_rdata => copper_rdata,
ram_wdata => copper_wdata,
ram_en => copper_en,
ram_we => copper_we,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
slot_req => slot_req,
slot_resp => slot_resp,
dma_req => dma_req,
dma_resp => dma_resp,
control => control,
status => status );
end gideon;
| gpl-3.0 |
chiggs/nvc | test/regress/record4.vhd | 5 | 883 | entity record4 is
end entity;
architecture test of record4 is
type rec is record
x, y : integer;
end record;
type rec_array is array (natural range <>) of rec;
function sum(r : in rec) return integer is
begin
return r.x + r.y;
end function;
function double(x : in integer) return integer is
begin
return x * 2;
end function;
function sum_all(a : in rec_array) return integer is
variable s : integer := 0;
begin
for i in a'range loop
s := s + sum(a(i));
end loop;
return s;
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
assert sum(ra(0)) = 3;
assert double(ra(0).x) = 2;
assert sum_all(ra) = 10;
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/c2n_playback/vhdl_sim/tape_speed_control_tb.vhd | 1 | 1162 | --------------------------------------------------------------------------------
-- Entity: tape_speed_control_tb
-- Date:2016-04-17
-- Author: Gideon
--
-- Description: Testbench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tape_speed_control_tb is
end tape_speed_control_tb;
architecture arch of tape_speed_control_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal tick_out : std_logic;
signal motor_en : std_logic;
signal clock_stop : boolean := false;
begin
clock <= not clock after 10 ns when not clock_stop;
reset <= '1', '0' after 100 ns;
i_mut: entity work.tape_speed_control
port map (
clock => clock,
reset => reset,
motor_en => motor_en,
tick_out => tick_out
);
p_test: process
begin
motor_en <= '0';
wait for 1 ms;
motor_en <= '1';
wait for 199 ms;
motor_en <= '0';
wait for 400 ms;
clock_stop <= true;
end process;
end arch;
| gpl-3.0 |
chiggs/nvc | test/regress/issue163.vhd | 5 | 1281 | package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/conv1.vhd | 5 | 416 | entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
wait for 1 ns;
assert y = X"b";
wait;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/lower/staticwait.vhd | 4 | 181 | entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
| gpl-3.0 |
chiggs/nvc | test/regress/wait4.vhd | 5 | 649 | entity wait4 is
end entity;
architecture test of wait4 is
signal x, y, z : bit;
begin
proc_a: process is
begin
wait for 1 ns;
y <= '1';
wait for 1 ns;
z <= '1';
wait for 1 ns;
assert x = '1';
wait;
end process;
proc_b: process is
begin
wait on x, y;
assert y = '1';
assert now = 1 ns;
assert y'event report "not y'event";
assert not x'event report "x'event";
wait on z;
assert not x'event;
assert z'event;
assert z = '1';
x <= '1';
wait;
end process;
end architecture;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_cmd_pkg.vhd | 1 | 3693 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2015
-- Entity: usb_cmd_pkg
-- Date:2015-01-18
-- Author: Gideon
-- Description: This package defines the commands that can be sent to the
-- sequencer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
package usb_cmd_pkg is
-- Protocol Event
type t_usb_command is ( setup, out_data, in_request, ping );
type t_usb_result is ( res_data, res_ack, res_nak, res_nyet, res_stall, res_error );
type t_usb_cmd_req is record
request : std_logic;
-- command and modifiers (4 bits?)
command : t_usb_command;
do_split : std_logic;
do_data : std_logic;
-- data buffer controls (14 bits)
buffer_index : unsigned(1 downto 0);
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
-- USB addressing (11 bits)
device_addr : unsigned(6 downto 0);
endp_addr : unsigned(3 downto 0);
-- USB addressing (15 bits)
split_hub_addr : unsigned(6 downto 0);
split_port_addr : unsigned(3 downto 0); -- hubs with more than 16 ports are not supported
split_sc : std_logic; -- 0=start 1=complete
split_sp : std_logic; -- 0=full, 1=low
split_et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
type t_usb_cmd_resp is record
done : std_logic;
result : t_usb_result;
error_code : std_logic_vector(2 downto 0);
-- data descriptor
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
end record;
-- type t_usb_result_encoded is array (t_usb_result range<>) of std_logic_vector(2 downto 0);
-- constant c_usb_result_encoded : t_usb_result_encoded := (
-- res_data => "001",
-- res_ack => "010",
-- res_nak => "011",
-- res_nyet => "100",
-- res_error => "111" );
type t_usb_command_array is array(natural range <>) of t_usb_command;
constant c_usb_commands_decoded : t_usb_command_array(0 to 3) := ( setup, out_data, in_request, ping );
constant c_usb_cmd_init : t_usb_cmd_req := (
request => '0',
command => setup,
do_split => '0',
do_data => '0',
buffer_index => "00",
data_length => "0000000000",
togglebit => '0',
no_data => '1',
device_addr => "0000000",
endp_addr => X"0",
split_hub_addr => "0000000",
split_port_addr => X"0",
split_sc => '0',
split_sp => '0',
split_et => "00" );
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result;
end package;
package body usb_cmd_pkg is
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result is
variable res : t_usb_result;
begin
case pid is
when c_pid_ack => res := res_ack;
when c_pid_nak => res := res_nak;
when c_pid_nyet => res := res_nyet;
when c_pid_stall => res := res_stall;
when others => res := res_error;
end case;
return res;
end function;
end package body;
| gpl-3.0 |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/fetch.vhd | 1 | 2752 | ----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
signal rst_d : std_logic;
signal ena_o : std_logic;
signal possibly_valid : std_logic;
begin
fetch_o.program_counter <= r.program_counter;
fetch_o.instruction <= imem_i.dat_i;
fetch_o.inst_valid <= possibly_valid and imem_i.ena_i;
ena_o <= ena_i and imem_i.ena_i and not rst_i;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_o;
fetch_comb: process(fetch_i, imem_i, r, rst_d)
variable v : fetch_out_type;
begin
v := r;
if rst_d = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' or imem_i.ena_i = '0' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
rst_d <= '1';
possibly_valid <= '0';
elsif ena_i = '1' then
r <= rin;
rst_d <= '0';
if imem_i.ena_i = '1' then
possibly_valid <= ena_o;
end if;
end if;
end if;
end process;
end arch; | gpl-3.0 |
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