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freecores/w11 | rtl/vlib/comlib/word2byte.vhd | 1 | 3814 | -- $Id: word2byte.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: word2byte - syn
-- Description: 1 word -> 2 byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.0.1 now numeric_std clean
-- 2011-07-30 400 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end word2byte;
architecture syn of word2byte is
type state_type is (
s_idle,
s_valw,
s_valh
);
type regs_type is record
datl : slv8; -- lsb data
dath : slv8; -- msb data
state : state_type; -- state
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),
(others=>'0'),
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable iodd : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ival := '0';
ibusy := '0';
iodd := '0';
case r.state is
when s_idle =>
if ENA = '1' then
n.datl := DI( 7 downto 0);
n.dath := DI(15 downto 8);
n.state := s_valw;
end if;
when s_valw =>
ibusy := '1';
ival := '1';
if HOLD = '0' then
n.datl := r.dath;
n.state := s_valh;
end if;
when s_valh =>
ival := '1';
iodd := '1';
if HOLD = '0' then
if ENA = '1' then
n.datl := DI( 7 downto 0);
n.dath := DI(15 downto 8);
n.state := s_valw;
else
n.state := s_idle;
end if;
else
ibusy := '1';
end if;
when others => null;
end case;
N_REGS <= n;
DO <= r.datl;
VAL <= ival;
BUSY <= ibusy;
ODD <= iodd;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/vlib/rlink/rlink_mon.vhd | 1 | 4763 | -- $Id: rlink_mon.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon - sim
-- Description: rlink monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rlinklib.all;
entity rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon;
architecture sim of rlink_mon is
begin
assert DWIDTH=8 or DWIDTH=9
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
proc_moni: process
variable oline : line;
variable nbusy : integer := 0;
variable nhold : integer := 0;
procedure write_val(L: inout line;
data: in slv(DWIDTH-1 downto 0);
nwait: in integer;
txt1: in string;
txt2: in string) is
variable data9 : slv9 := (others=>'0');
begin
writetimestamp(L, CLK_CYCLE, txt1);
if DWIDTH = 9 then
write(L, data(data'left), right, 1);
else
write(L, string'(" "));
end if;
write(L, data(7 downto 0), right, 9);
if nwait > 0 then
write(L, txt2);
write(L, nwait);
end if;
if DWIDTH=9 and data(data'left)='1' then
-- a copy to data9 needed to allow following case construct
-- using data directly gives a 'subtype is not locally static' error
data9 := (others=>'0');
data9(data'range) := data;
write(L, string'(" comma"));
case data9 is
when c_rlink_dat_idle => write(L, string'(" idle"));
when c_rlink_dat_sop => write(L, string'(" sop"));
when c_rlink_dat_eop => write(L, string'(" eop"));
when c_rlink_dat_nak => write(L, string'(" nak"));
when c_rlink_dat_attn => write(L, string'(" attn"));
when others => null;
end case;
end if;
writeline(output, L);
end procedure write_val;
begin
loop
if ENA='0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RL_ENA = '1' then
if RL_BUSY = '1' then
nbusy := nbusy + 1;
else
write_val(oline, RL_DI, nbusy, ": rlrx ", " nbusy=");
nbusy := 0;
end if;
else
nbusy := 0;
end if;
if RL_VAL = '1' then
if RL_HOLD = '1' then
nhold := nhold + 1;
else
write_val(oline, RL_DO, nhold, ": rltx ", " nhold=");
nhold := 0;
end if;
else
nhold := 0;
end if;
end loop;
end process proc_moni;
end sim;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd | 1 | 2119 | -- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-2.0 |
freecores/w11 | rtl/ibus/ibdr_lp11.vhd | 1 | 7529 | -- $Id: ibdr_lp11.vhd 515 2013-05-04 17:28:59Z mueller $
--
-- Copyright 2009-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11 - syn
-- Description: ibus dev(rem): LP11
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.3; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-05-04 515 1.3 BUGFIX: r.err was cleared in racc read !
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
-- 2009-05-30 220 1.0 Initial version
------------------------------------------------------------------------------
--
-- Notes:
-- - the ERR bit is just a status flag
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
-- - also no interrupt when ERR goes 1, like in simh
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_lp11;
architecture syn of ibdr_lp11 is
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant buf_ibf_val : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
buf : slv7; -- buf:
intreq : slbit; -- interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
'1', -- done !! is set !!
'0', -- ie
(others=>'0'), -- buf
'0' -- intreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- don't reset ERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(1 downto 1) is
when ibaddr_csr => -- CSR -- control status -------------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
n.ie := IB_MREQ.din(csr_ibf_ie);
if IB_MREQ.din(csr_ibf_ie) = '1' then
if r.done='1' and r.ie='0' then -- ie set while done=1
n.intreq := '1'; -- request interrupt
end if;
else
n.intreq := '0';
end if;
end if;
else -- rri
if ibw1 = '1' then
n.err := IB_MREQ.din(csr_ibf_err);
end if;
end if;
when ibaddr_buf => -- BUF -- data buffer ----------------
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
n.buf := IB_MREQ.din(n.buf'range);
if r.err = '0' then -- if online (handle via rbus)
ilam := '1'; -- request attention
n.done := '0'; -- clear done
n.intreq := '0'; -- clear interrupt
else -- if offline (discard locally)
n.done := '1'; -- set done
if r.ie = '1' then -- if interrupts enabled
n.intreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri
idout(r.buf'range) := r.buf;
idout(buf_ibf_val) := not r.done;
if ibrd = '1' then
n.done := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/bplib/nexys3/nexys3lib.vhd | 1 | 8340 | -- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: nexys3lib
-- Description: Nexys 3 components
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
-- 2011-11-25 432 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys3lib is
component nexys3_aif is -- NEXYS 3, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit -- ppcm: ...
);
end component;
component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys3lib;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd | 1 | 2580 | -- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd | 1 | 7321 | -- $Id: tst_serloop_hiomap.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-16 426 1.0.1 setup leds and dps
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3): -- unused --
-- (2): -- unused --
-- (1): load enables from SWI(7:4)
-- SWI(7) -> ENAFTDI
-- SWI(6) -> ENATHROTTLE
-- SWI(5) -> ENAESC
-- SWI(4) -> ENAXON
-- (0): reset state [!! decoded by top level design !!]
--
-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
-- (3) -- unused --
-- (2:1): mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
-- SWI(0) 0 -> main board RS232 port
-- 1 -> Pmod1 RS232 port
--
-- LED(7) enaesc
-- (6) enaxon
-- (5) rxfecnt > 0 (frame error)
-- (4) rxoecnt > 0 (overrun error)
-- (3) rxsecnt > 0 (sequence error)
-- (2) abact (shows ab activity)
-- (1) (not rxok) or (not txok) (shows back preasure)
-- (0) rxact or txact (shows activity)
--
-- DSP data as selected by SWI(7:4)
-- 0000 -> rxfecnt
-- 0001 -> rxoecnt
-- 0010 -> rxsecnt
-- 0100 -> rxcnt.l
-- 0101 -> rxcnt.h
-- 0110 -> txcnt.l
-- 0111 -> txcnt.h
-- 1000 -> rxokcnt
-- 1001 -> txokcnt
-- 1010 -> rxuicnt,rxuidat
-- 1111 -> abclkdiv
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_serloop_hiomap;
architecture syn of tst_serloop_hiomap is
type regs_type is record
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
dspdat : slv16; -- display data
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
(others=>'0') -- dspdat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- handle BTN(1) "load enables" press
if BTN(1) = '1' then
n.enaxon := SWI(4);
n.enaesc := SWI(5);
n.enathrottle := SWI(6);
n.enaftdi := SWI(7);
end if;
-- setup tester controls
icntl.mode := SWI(2 downto 1);
icntl.enaxon := r.enaxon;
icntl.enaesc := r.enaesc;
icntl.enathrottle := r.enathrottle;
icntl.enaftdi := r.enaftdi;
-- setup leds
iled(7) := icntl.enaesc;
iled(6) := icntl.enaxon;
if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
iled(2) := SER_MONI.abact;
iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
iled(0) := SER_MONI.rxact or SER_MONI.txact;
-- setup display data
case SWI(7 downto 4) is
when "0000" => idat := HIO_STAT.rxfecnt;
when "0001" => idat := HIO_STAT.rxoecnt;
when "0010" => idat := HIO_STAT.rxsecnt;
when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
when "1000" => idat := HIO_STAT.rxokcnt;
when "1001" => idat := HIO_STAT.txokcnt;
when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
when "1111" => idat := SER_MONI.abclkdiv;
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := not SER_MONI.txok; -- tx back preasure
idp(2) := SER_MONI.txact; -- tx activity
idp(1) := not SER_MONI.rxok; -- rx back preasure
idp(0) := SER_MONI.rxact; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/w11a/pdp11_vmbox.vhd | 2 | 24725 | -- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 5; -- size of access timeout counter
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
is_stackyellow := '1';
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
immu_cntl.trap_done := VM_CNTL.trap_done;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
VM_STAT <= ivm_stat;
MMU_CNTL <= immu_cntl;
EM_MREQ <= iem_mreq;
end process proc_next;
IB_MREQ_M <= IB_MREQ; -- external drive master port
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
end syn;
| gpl-2.0 |
freecores/cryptopan_core | rtl/cryptopan_unit.vhd | 1 | 6111 | --
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cryptopan.all;
entity cryptopan_unit is
port (
clk : in std_logic;
reset : in std_logic;
ready : out std_logic;
key : in std_logic_vector(255 downto 0);
key_wren : in std_logic;
ip_in : in std_logic_vector(31 downto 0);
ip_wren : in std_logic;
ip_out : out std_logic_vector(31 downto 0);
ip_dv : out std_logic
);
end cryptopan_unit;
architecture rtl of cryptopan_unit is
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
signal aes_din, aes_dout : std_logic_vector(127 downto 0);
signal aes_din_wren, aes_dout_dv : std_logic;
signal ready_int : std_logic;
signal m_pad : std_logic_vector(127 downto 0);
signal ip_reg : std_logic_vector(31 downto 0);
signal read_ip_reg : std_logic_vector(31 downto 0);
type states is (INIT, INITWAIT, IDLE, BUSY);
signal state : states;
type read_states is (INIT, IDLE, BUSY);
signal read_state : read_states;
type output_states is (IDLE, BUSY);
signal output_state : output_states;
-- signal shift_counter : std_logic_vector(31 downto 0);
signal output_counter : std_logic_vector(4 downto 0);
signal first4bytes_pad : std_logic_vector(31 downto 0);
signal first4bytes_input : std_logic_vector(31 downto 0);
signal mask_onehot : std_logic_vector(31 downto 0);
signal mask_onehot_inv : std_logic_vector(31 downto 0);
signal ip_out_int : std_logic_vector(31 downto 0);
begin
mask_onehot_inv <= not mask_onehot;
with state select
ready <=
'1' when IDLE,
'0' when others;
first4bytes_pad <= m_pad(127 downto 96);
first4bytes_input <= (ip_reg and mask_onehot_inv) or (first4bytes_pad and mask_onehot);
LOAD_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
state <= INIT;
aes_din_wren <= '0';
aes_din <= (others => '0');
mask_onehot <= (others => '0');
ip_reg <= (others => '0');
elsif clk'event and clk = '1' then
mask_onehot <= (others => '1');
aes_din_wren <= '0';
if state = INIT and ready_int = '1' then
aes_din <= key(255 downto 128);
aes_din_wren <= '1';
state <= INITWAIT;
elsif state = INITWAIT and aes_dout_dv = '1' then
state <= IDLE;
elsif state = IDLE and ip_wren = '1' then
state <= BUSY;
ip_reg <= ip_in;
elsif state = BUSY then
if mask_onehot(0) = '1' then
aes_din_wren <= '1';
aes_din <= first4bytes_input & m_pad(95 downto 0);
else
state <= IDLE;
end if;
mask_onehot(31) <= '0';
for i in 30 downto 0 loop
mask_onehot(i) <= mask_onehot(i+1);
end loop;
end if;
end if;
end process LOAD_UNIT_LOGIC;
READ_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
m_pad <= (others => '0');
read_state <= INIT;
ip_out <= (others => '0');
ip_dv <= '0';
output_state <= IDLE;
read_ip_reg <= (others => '0');
output_counter <= (others => '1');
elsif clk'event and clk = '1' then
ip_dv <= '0';
if read_state = INIT then
if aes_dout_dv = '1' then
m_pad <= aes_dout;
read_state <= IDLE;
end if;
elsif read_state = IDLE then
if aes_dout_dv = '1' then
if output_counter = "11111" then
read_ip_reg <= ip_reg;
end if;
output_counter <= output_counter - 1;
ip_out_int <= ip_out_int(30 downto 0) & aes_dout(127);
end if;
if output_counter = "00000" then
output_state <= BUSY;
end if;
end if;
if output_state = BUSY then
output_state <= IDLE;
ip_dv <= '1';
ip_out <= ip_out_int xor read_ip_reg;
end if;
end if;
end process READ_UNIT_LOGIC;
-- OUTPUT_UNIT_LOGIC : process (clk, reset)
-- begin
-- if reset = '1' then
-- ip_out <= (others => '0');
-- ip_dv <= '0';
-- output_state <= IDLE;
-- elsif clk'event and clk = '1' then
-- end if;
-- end process OUTPUT_UNIT_LOGIC;
AES0 : aes_encrypt_unit
port map (
key_in => key(127 downto 0),
key_wren => key_wren,
ready => ready_int,
data_in => aes_din,
data_wren => aes_din_wren,
data_dv => aes_dout_dv,
data_out => aes_dout,
clk => clk,
reset => reset);
end rtl;
| gpl-2.0 |
dominicgs/hackrf | firmware/cpld/sgpio_if_passthrough/top.vhd | 14 | 1910 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
SGPIO : inout std_logic_vector(15 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : in std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
type transfer_direction is (to_sgpio, from_sgpio);
signal transfer_direction_i : transfer_direction;
begin
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
else from_sgpio;
DD <= (DD'high => '1', others => '0');
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
else (others => 'Z');
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
else (others => 'Z');
end Behavioral;
| gpl-2.0 |
majutsushi/ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
rodrigosurita/new-crpuf | vhdl/src/txt_util.vhd | 1 | 19034 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- converts a string into integer
function str_to_int( s : string ) return integer ;
-- converts a character into integer
function char_to_int( c : character ) return integer ;
-- converts a string into integer
-- function str_to_real(s : string ) return real ;
function str_nextchar (str: string; str_begin: integer; char: character) return integer ;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- converts a std_logic_vector into a hex string.
-- function substring(str: string, str_begin: integer, str_end: integer) return string is
-- begin
-- return str(str_begin to str_end);
-- end substring;
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
--print(c);
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
-- procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
-- end str_write;
function str_to_int( s : string ) return integer is
variable len : integer := s'length;
variable ivalue : integer := 0;
variable digit : integer;
-- variable myline: line;
begin
for i in 1 to len loop
case s(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 10 + digit;
end loop;
return ivalue;
end;
function char_to_int( c : character ) return integer is
variable digit : integer;
begin
case c is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character in char parameter! "
SEVERITY ERROR;
end case;
return digit;
end char_to_int;
function str_nextchar(str: string; str_begin: integer; char: character) return integer is
variable ivalue : integer := -1;
begin
if(str_begin>str'length ) then
ASSERT FALSE
REPORT "Parser Error: Out of range "& char & "in string parameter! "
SEVERITY ERROR;
return -1;
else
for i in str_begin to str'length loop
if(str(i)= char) then
return i;
end if;
if i = str'length then
return i;
end if;
end loop;
end if;
return ivalue;
end str_nextchar;
-- function str_to_real( s : string ) return real is
-- variable beginner: integer:=0;
-- variable value: real:=0.0;
-- variable is_decimal_digits: boolean;
-- variable val: integer := 0;
--
-- begin
---- -- decimal_digits:=FALSE;
-- for i in 1 to s'length loop
----
-- if (s(i)='.') then
-- is_decimal_digits:=true;
--- val:= str_to_int ( s(beginner to i-1) ) ;
-- value:= val+0.0;
-- value:= value + (str_to_int(s(i+1 to s'length)))/ (10**(s'length-i) );
-- return value;
-- else
-- if(s(i)/='0' and beginner=0) then
---- beginner:=i;
-- end if;
-- end if;
--
-- end loop;
-- value:= value + str_to_int( s(beginner to s'length));
--
-- return value;
--
-- end str_to_real;
end txt_util;
| gpl-2.0 |
keith-epidev/md2x | build/code/seven_segment.vhdl | 1 | 1891 | library ieee;
use ieee.std_logic_1164.all;
entity seven_segment is
port (
clk : in std_logic;
val : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
mode: in std_logic
);
end seven_segment;
architecture arch of seven_segment is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
signal spinner : std_logic_vector(5 downto 0) := "111110";
signal spin_spinner: std_logic;
begin
p1: pulser generic map(delay=>5000000) port map(clk,'1',spin_spinner);
spinner_pro: process(spin_spinner)
begin
if(spin_spinner'event and spin_spinner = '1')then
if(spinner = "011111")then
spinner <= "111110";
else
spinner <= spinner(4 downto 0) & '1';
end if;
end if;
end process spinner_pro;
disp_pro: process(clk,val,mode)
begin
if(mode = '0') then
case val is
when "0001" => led <= "1111001";
when "0010" => led <= "0100100";
when "0011" => led <= "0110000";
when "0100" => led <= "0011001";
when "0101" => led <= "0010010";
when "0110" => led <= "0000010";
when "0111" => led <= "1111000";
when "1000" => led <= "0000000";
when "1001" => led <= "0010000";
when "1010" => led <= "0001000";
when "1011" => led <= "0000011";
when "1100" => led <= "1000110";
when "1101" => led <= "0100001";
when "1110" => led <= "0000110";
when "1111" => led <= "0001110";
when others => led <= "1000000";
end case;
else
if( val = "0001") then
led <= "1000111";
else if ( val = "0010") then
led <= "0010010";
else if ( val = "0011") then
led <= '1'&spinner;
else
led <= "1111111";
end if;
end if;
end if;
end if;
end process disp_pro;
end arch;
| gpl-2.0 |
freecores/t400 | bench/vhdl/tb_t411.vhd | 1 | 4542 | -------------------------------------------------------------------------------
--
-- Testbench for the T411 system toplevel.
--
-- $Id: tb_t411.vhd,v 1.6 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t411 is
end tb_t411;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t411;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t411 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(1 downto 0);
signal io_g_s : std_logic_vector(2 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t411_b : t411
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 2,
g_width_g => 3
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 |
freecores/t400 | rtl/vhdl/t400_io_in-c.vhd | 1 | 663 | -------------------------------------------------------------------------------
--
-- The IN port controller.
--
-- $Id: t400_io_in-c.vhd,v 1.1 2006-05-22 00:00:55 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_in_rtl_c0 of t400_io_in is
for rtl
end for;
end t400_io_in_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 |
freecores/t400 | bench/vhdl/tb_t420.vhd | 1 | 4606 | -------------------------------------------------------------------------------
--
-- Testbench for the T420 system toplevel.
--
-- $Id: tb_t420.vhd,v 1.5 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t420 is
end tb_t420;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t420 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_cko_g => t400_opt_cko_gpi_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => io_in_s,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/05/27 19:10:20 arniml
-- explicitly select clock divider 4
--
-- Revision 1.3 2006/05/24 00:48:49 arniml
-- connect cko_i to bit 2 of IN bus
--
-- Revision 1.2 2006/05/23 01:18:10 arniml
-- consider CKO and IN port
--
-- Revision 1.1 2006/05/15 22:21:59 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 |
keith-epidev/md2x | build/code/lcd.vhdl | 1 | 2056 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.my_lib.all;
entity lcd is
port(
clk: in std_logic;
reset: in std_logic;
rs: out std_logic;
rw: out std_logic;
e: out std_logic;
data: out std_logic_vector(7 downto 0);
disp: in disp_chars
);
end lcd;
architecture Behavioral of lcd is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
signal lcd_clk : std_logic;
signal state : std_logic_vector(f_log2(8)-1 downto 0);
--signal index : std_logic_vector(f_log2(16*2)-1 downto 0) := (others=>'0');
type cmd_list is array(0 to 7) of std_logic_vector(7 downto 0);
signal init_data :cmd_list := ( X"30", X"30", X"30", X"38", X"0C", X"01", X"06",X"01");
signal e_state: std_logic := '0';
signal align: std_logic := '0';
begin
p1: pulser generic map(delay=>50000) port map(clk, '1', lcd_clk);
e <= e_state;
process(lcd_clk,reset)
variable index : integer := 0;
begin
if(reset = '1')then
index:= 0;
state <= (others=>'0');
elsif(lcd_clk'event and lcd_clk = '1')then
if(e_state = '1')then
e_state <= '0';
if(state < 8) then
data <= init_data(conv_integer(state));
rs <= '0';
rw <= '0';
state <= state+1;
else
if( align = '0' and (index = 0 or index = 16 ) )then
rs <= '0';
rw <= '0';
align <= '1';
if(index = 0)then
data <=X"80";
else
data <= X"C0";
end if;
else
if( disp(index) = "00000000" )then
data <= X"20";
else
data <= disp(index);
end if;
index := index+1;
align <= '0';
rs <= '1';
rw <= '0';
if(index = 16*2)then
index := 0;
end if;
end if;
end if;
else
e_state <= not e_state;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/t400 | bench/vhdl/t410_rom-lpm-a.vhd | 1 | 3518 | -------------------------------------------------------------------------------
--
-- T410 ROM wrapper for lpm_rom.
--
-- $Id: t410_rom-lpm-a.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
architecture lpm of t410_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := "LPM_ROM";
LPM_HINT : string := "UNUSED"
);
port (
ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_WIDTHAD => 9,
LPM_OUTDATA => "UNREGISTERED",
LPM_FILE => "rom_41x.hex"
)
port map (
ADDRESS => addr_i,
INCLOCK => ck_i,
OUTCLOCK => ck_i,
MEMENAB => vdd_s,
Q => data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Signal_Trigger.vhd | 7 | 1749 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This module generates a trigger pulse every time it sees a transition
-- from 0 to 1 on signal i_signal.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Signal_Trigger is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Signal_Trigger is
-- Local wires
-- REGISTERED
signal local_reg : std_logic;
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
local_reg <= '0';
else
if (rising_edge(i_clock)) then
local_reg <= i_signal;
end if;
end if;
end process;
o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
else '0';
end rtl; | gpl-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/Altera_UP_SD_Card_Response_Receiver.vhd | 7 | 11537 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module looks at the data on the CMD line and waits to receive a response.
-- It begins examining the data lines when the i_begin signal is asserted. It then
-- waits for a first '0'. It then proceeds to store as many bits as are required by
-- the response packet. Each message bit passes through the CRC7 circuit so that
-- the CRC check sum can be verified at the end of transmission. The circuit then produces
-- the o_data and o_CRC_passed outputs to indicate the message received and if the CRC
-- check passed.
--
-- If for some reason the requested response does not arrive within 56 clock cycles
-- then the circuit will produce a '1' on the o_timeout output. In such a case the
-- o_data should be ignored.
--
-- In case of a response that is not 001, 010, 011 or 110, the circuit expects
-- no response.
--
-- A signal o_done is asserted when the circuit has completed response retrieval. In
-- a case when a response is not expected, just wait for the CD Card to process the
-- command. This is done by waiting 8 (=PROCESSING_DELAY) clock cycles.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Response_Receiver is
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Response_Receiver is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_WAIT_BEGIN, s_WAIT_END, s_WAIT_PROCESSING_DELAY, s_WAIT_BUSY, s_WAIT_BUSY_END, s_WAIT_BEGIN_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal registered_data_input : std_logic_vector(127 downto 0);
signal response_incoming : std_logic;
signal counter, timeout_counter : std_logic_vector(7 downto 0);
signal crc_shift, keep_reading_bits, shift_crc_bits : std_logic;
-- UNREGISTERED
signal limit, limit_minus_1 : std_logic_vector(7 downto 0);
signal check_crc : std_logic;
signal CRC_bits : std_logic_vector(6 downto 0);
signal start_reading_bits, operation_complete, enable_crc_unit : std_logic;
begin
-- Control FSM. Begin operation when i_begin is raised, then wait for the operation to end and i_begin to be deasserted.
state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_WAIT_BEGIN;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
state_transitions: process(current_state, i_begin, operation_complete, timeout_counter, i_wait_cmd_busy, i_scan_pulse, i_datain)
begin
case current_state is
when s_WAIT_BEGIN =>
if (i_begin = '1') then
next_state <= s_WAIT_END;
else
next_state <= s_WAIT_BEGIN;
end if;
when s_WAIT_END =>
if (operation_complete = '1') then
if (timeout_counter = TIMEOUT) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
else
next_state <= s_WAIT_END;
end if;
when s_WAIT_PROCESSING_DELAY =>
if (timeout_counter = PROCESSING_DELAY) then
if (i_wait_cmd_busy = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_WAIT_BEGIN_DEASSERT;
end if;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
when s_WAIT_BUSY =>
if ((i_scan_pulse = '1') and (i_datain = '0')) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_counter = BUSY_WAIT) then
-- If the card did not become busy, then it would not have raised the optional busy signal.
-- In such a case, proceeed further as the command has finished correctly.
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if ((i_scan_pulse = '1') and (i_datain = '1')) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_BEGIN_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BEGIN;
end if;
when others =>
next_state <= s_WAIT_BEGIN;
end case;
end process;
-- Store the response as it appears on the i_datain line.
received_data_buffer: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
registered_data_input <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
registered_data_input(127 downto 1) <= registered_data_input(126 downto 0);
registered_data_input(0) <= i_datain;
end if;
end if;
end if;
end process;
-- Counter received bits
data_read_counter: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
counter <= counter + '1';
end if;
end if;
end if;
end process;
operation_complete <= '1' when (((counter = limit) and (not (limit = "00000000"))) or
(timeout_counter = TIMEOUT) or
((timeout_counter = PROCESSING_DELAY) and (limit = "00000000"))) else '0';
-- Count the number of scan pulses before the response is received. If the counter
-- exceeds TIMEOUT value, then an error must have occured when the SD card received a message.
timeout_counter_control: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
timeout_counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset the counter every time you begin reading the response.
if ((current_state = s_WAIT_BEGIN) or ((current_state = s_WAIT_END) and (operation_complete = '1') and (not (timeout_counter = TIMEOUT)))) then
timeout_counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if (((start_reading_bits = '0') and (keep_reading_bits = '0') and (current_state = s_WAIT_END) and (not (timeout_counter = TIMEOUT))) or
(current_state = s_WAIT_PROCESSING_DELAY) or (current_state = s_WAIT_BUSY)) then
timeout_counter <= timeout_counter + '1';
end if;
end if;
end if;
end process;
-- Enable data storing only after you see the first 0.
read_enable_logic: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
keep_reading_bits <= '0';
elsif (rising_edge(i_clock)) then
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or ((keep_reading_bits = '1') and (not (counter = limit_minus_1)))) then
keep_reading_bits <= '1';
else
keep_reading_bits <= '0';
end if;
end if;
end if;
end process;
start_reading_bits <= '1' when ((current_state = s_WAIT_END) and (i_datain = '0') and
(counter = "00000000") and (not (limit = "00000000"))) else '0';
-- CRC7 checker.
crc_checker: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => enable_crc_unit,
i_shift => shift_crc_bits,
i_datain => registered_data_input(7),
o_crcout => CRC_bits
);
enable_crc_unit <= '1' when ((i_scan_pulse = '1') and (current_state = s_WAIT_END)) else '0';
-- Clear CRC7 registers before processing the response bits
crc_control_register: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_crc_bits <= '1';
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
-- clear the CRC7 contents before you process the next message.
shift_crc_bits <= '1';
end if;
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
if (counter = "00000111") then
-- Once the 7-bits of the CRC checker have been cleared you can process the message and
-- compute its CRC bits to verify the validity of the transmission.
shift_crc_bits <= '0';
end if;
end if;
end if;
end if;
end process;
-- Indicate the number of bits to expect in the response packet.
limit <= "00110000" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10001000" when (i_response_type = "010") else
"00000000"; -- No response
limit_minus_1 <=
"00101111" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10000111" when (i_response_type = "010") else
"00000000"; -- No response
check_crc <= '1' when ((i_response_type = "001") or (i_response_type = "110")) else '0';
-- Generate Circuit outputs
o_data <= (registered_data_input(127 downto 1) & '1') when (i_response_type = "010") else
(CONV_STD_LOGIC_VECTOR(0, 96) & registered_data_input(39 downto 8));
o_CRC_passed <= '1' when ((check_crc = '0') or
((registered_data_input(0) = '1') and (CRC_bits = registered_data_input(7 downto 1)))) else '0';
o_timeout <= '1' when (timeout_counter = TIMEOUT) else '0';
o_done <= '1' when (current_state = s_WAIT_BEGIN_DEASSERT) else '0';
end rtl; | gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/Altera_UP_SD_Card_Control_FSM.vhd | 7 | 13102 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that controls the SD Card interface circuitry.
--
-- On reset, the FSM will initiate a predefined set of commands in an attempt to connect to the SD Card.
-- When successful, it will allow commands to be issued to the SD Card, otherwise it will return a signal that
-- no card is present in the SD Card slot.
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Control_FSM is
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Control_FSM is
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_74_CYCLES, s_GENERATE_PREDEFINED_COMMAND, s_WAIT_PREDEFINED_COMMAND_TRANSMITTED, s_WAIT_PREDEFINED_COMMAND_RESPONSE,
s_GO_TO_NEXT_COMMAND, s_TOGGLE_CLOCK_FREQUENCY, s_AWAIT_USER_COMMAND, s_REACTIVATE_CLOCK,
s_GENERATE_COMMAND, s_SEND_COMMAND, s_WAIT_RESPONSE, s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE, s_WAIT_DEASSERT,
s_PERIODIC_STATUS_CHECK);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal SD_clock_mode, waiting_for_vdd_setup : std_logic;
signal id_sequence_step_index : std_logic_vector(3 downto 0);
signal delay_counter : std_logic_vector(6 downto 0);
signal periodic_status_check : std_logic_vector(23 downto 0);
-- UNREGISTERED
begin
-- Define state transitions.
state_transitions: process (current_state, i_command_sent, i_response_received, id_sequence_step_index,
i_response_timed_out, i_response_crc_passed, delay_counter, waiting_for_vdd_setup,
i_user_command_ready, i_clocking_pulse_enable, i_current_clock_mode,
i_user_message_valid, i_last_cmd_was_55, periodic_status_check)
begin
case current_state is
when s_RESET =>
-- Reset local registers and begin identification process.
next_state <= s_WAIT_74_CYCLES;
when s_WAIT_74_CYCLES =>
-- Wait 74 cycles before the card can be sent commands to.
if (delay_counter = "1001010") then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_WAIT_74_CYCLES;
end if;
when s_GENERATE_PREDEFINED_COMMAND =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
when s_WAIT_PREDEFINED_COMMAND_TRANSMITTED =>
-- Send a predefined command to the SD card. This is the identification process for the SD card.
if (i_command_sent = '1') then
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
end if;
when s_WAIT_PREDEFINED_COMMAND_RESPONSE =>
-- Wait for a response from SD card.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
if (waiting_for_vdd_setup = '1') then
next_state <= s_GO_TO_NEXT_COMMAND;
else
next_state <= s_RESET;
end if;
else
if (i_response_crc_passed = '0') then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_GO_TO_NEXT_COMMAND;
end if;
end if;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
end if;
when s_GO_TO_NEXT_COMMAND =>
-- Process the next command in the ID sequence.
if (id_sequence_step_index = PREDEFINED_COMMAND_GET_STATUS) then
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
else
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
when s_TOGGLE_CLOCK_FREQUENCY =>
-- Now that the card has been initialized, increase the SD card clock frequency to 25MHz.
-- Wait for the clock generator to switch operating mode before proceeding further.
if (i_current_clock_mode = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
end if;
when s_AWAIT_USER_COMMAND =>
-- Wait for the user to send a command to the SD card
if (i_user_command_ready = '1') then
next_state <= s_REACTIVATE_CLOCK;
else
-- Every 5 million cycles, or 0.1 of a second.
if (periodic_status_check = "010011000100101101000000") then
next_state <= s_PERIODIC_STATUS_CHECK;
else
next_state <= s_AWAIT_USER_COMMAND;
end if;
end if;
when s_PERIODIC_STATUS_CHECK =>
-- Update status every now and then.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
when s_REACTIVATE_CLOCK =>
-- Activate the clock signal and wait 8 clock cycles.
if (delay_counter = "0001000") then
next_state <= s_GENERATE_COMMAND;
else
next_state <= s_REACTIVATE_CLOCK;
end if;
when s_GENERATE_COMMAND =>
-- Generate user command. If valid, proceed further. Otherwise, indicate that the command is invalid.
if (i_user_message_valid = '0') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_SEND_COMMAND;
end if;
when s_SEND_COMMAND =>
-- Wait for the command to be sent.
if (i_command_sent = '1') then
next_state <= s_WAIT_RESPONSE;
else
next_state <= s_SEND_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Wait for the SD card to respond.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
else
next_state <= s_WAIT_RESPONSE;
end if;
when s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE =>
-- Wait for a positive clock edge before you disable the clock.
if (i_clocking_pulse_enable = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
when s_WAIT_DEASSERT =>
-- wait for the user to release command generation request.
if (i_user_command_ready = '1') then
next_state <= s_WAIT_DEASSERT;
else
if (i_last_cmd_was_55 = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
-- Send a get status command to obtain the result of sending the last command.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State registers.
state_registers: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- Local FFs:
local_ffs:process ( i_clock, i_reset_n, i_powerup_busy_n, current_state,
id_sequence_step_index, i_response_received, i_response_timed_out,
i_allow_partial_rw)
begin
if (i_reset_n = '0') then
SD_clock_mode <= '0';
id_sequence_step_index <= (OTHERS => '0');
periodic_status_check <= (OTHERS => '0');
waiting_for_vdd_setup <= '0';
elsif (rising_edge(i_clock)) then
-- Set SD clock mode to 0 initially, thereby using a clock with frequency between 100 kHz and 400 kHz as
-- per SD card specifications. When the card is initialized change the clock to run at 25 MHz.
if (current_state = s_WAIT_DEASSERT) then
periodic_status_check <= (OTHERS => '0');
elsif (current_state = s_AWAIT_USER_COMMAND) then
periodic_status_check <= periodic_status_check + '1';
end if;
if (current_state = s_RESET) then
SD_clock_mode <= '0';
elsif (current_state = s_TOGGLE_CLOCK_FREQUENCY) then
SD_clock_mode <= '1';
end if;
-- Update the ID sequence step as needed.
if (current_state = s_RESET) then
id_sequence_step_index <= (OTHERS => '0');
elsif (current_state = s_GO_TO_NEXT_COMMAND) then
if ((i_powerup_busy_n = '0') and (id_sequence_step_index = "0010")) then
id_sequence_step_index <= "0001";
else
if (id_sequence_step_index = "0110") then
if (i_allow_partial_rw = '0') then
-- If partial read-write not allowed, then skip SET_BLK_LEN command - it will fail.
id_sequence_step_index <= "1000";
else
id_sequence_step_index <= "0111";
end if;
else
id_sequence_step_index <= id_sequence_step_index + '1';
end if;
end if;
elsif (current_state = s_WAIT_DEASSERT) then
if (i_last_cmd_was_55 = '0') then
-- After each command execute a get status command.
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
elsif (current_state = s_PERIODIC_STATUS_CHECK) then
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
-- Do not reset the card when SD card is having its VDD set up. Wait for it to respond, this may take some time.
if (id_sequence_step_index = "0010") then
waiting_for_vdd_setup <= '1';
elsif ((id_sequence_step_index = "0011") or (current_state = s_RESET)) then
waiting_for_vdd_setup <= '0';
end if;
end if;
end process;
-- Counter that counts to 74 to delay any commands.
initial_delay_counter: process(i_clock, i_reset_n, i_clocking_pulse_enable )
begin
if (i_reset_n = '0') then
delay_counter <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_RESET) or (current_state = s_AWAIT_USER_COMMAND))then
delay_counter <= (OTHERS => '0');
elsif (((current_state = s_WAIT_74_CYCLES) or (current_state = s_REACTIVATE_CLOCK)) and
(i_clocking_pulse_enable = '1')) then
delay_counter <= delay_counter + '1';
end if;
end if;
end process;
-- FSM outputs.
o_SD_clock_mode <= SD_clock_mode;
o_generate_command <= '1' when ((current_state = s_GENERATE_PREDEFINED_COMMAND) or
(current_state = s_GENERATE_COMMAND))
else '0';
o_receive_response <= '1' when ((current_state = s_WAIT_PREDEFINED_COMMAND_RESPONSE) or
(current_state = s_WAIT_RESPONSE))
else '0';
o_drive_CMD_line <= '1' when ( (current_state = s_WAIT_PREDEFINED_COMMAND_TRANSMITTED) or
(current_state = s_SEND_COMMAND)) else '0';
o_predefined_command_ID <= id_sequence_step_index;
o_card_connected <= '1' when (id_sequence_step_index(3) = '1') and (
(id_sequence_step_index(2) = '1') or
(id_sequence_step_index(1) = '1') or
(id_sequence_step_index(0) = '1'))
else '0';
o_resetting <= '1' when (current_state = s_RESET) else '0';
o_command_completed <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_enable_clock_generator <= '0' when (current_state = s_AWAIT_USER_COMMAND) else '1';
o_clear_response_register <= '1' when (current_state = s_REACTIVATE_CLOCK) else '0';
end rtl;
| gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/abus_avalon_sdram_bridge.vhd | 4 | 58923 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(9 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '0'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
-- abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
-- & abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
-- 2020/10/04 : Demuxing is adapted to MAX 10 Board r0.7 (c).
-- I initially wanted to make An and MUXn matching, but as
-- there is a couple of mistakes on PCB schematics (around U1 and U4)
-- there is still a little need of de-spaghettizying the signals.
--Address Mapping for U4 : And for U1 : (In m10brd r07c) abus_address_latched_prepatch <= abus_address
-- A7 -> MUX12 A11 -> MUX0 & abus_addressdata_buf( 4) -- A15
-- A6 -> MUX13 A10 -> MUX1 & abus_addressdata_buf( 5) -- A14
-- A5 -> MUX14 A9 -> MUX2 & abus_addressdata_buf( 6) -- A13
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf( 7) -- A12
-- A15 -> MUX4 A3 -> MUX8 & abus_addressdata_buf( 0) -- A11
-- A14 -> MUX5 A2 -> MUX9 & abus_addressdata_buf( 1) -- A10
-- A13 -> MUX6 A1 -> MUX10 & abus_addressdata_buf( 2) -- A9
-- A12 -> MUX7 A0 -> MUX11 & abus_addressdata_buf( 3) -- A8
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(12) -- A7
-- A15 -> MUX4 & abus_addressdata_buf(13) -- A6
-- A14 -> MUX5 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX6 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX7 & abus_addressdata_buf( 8) -- A3
-- A11 -> MUX0 & abus_addressdata_buf( 9) -- A2
-- A10 -> MUX1 & abus_addressdata_buf(10) -- A1
-- A9 -> MUX2 & abus_addressdata_buf(11); -- A0
-- A8 -> MUX3
-- A7 -> MUX12
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX8
-- A2 -> MUX9
-- A1 -> MUX10
-- A0 -> MUX11
abus_address_latched_prepatch <=
abus_address(8)
& abus_address(7)
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata_buf( 4) -- A15
& abus_addressdata_buf( 5) -- A14
& abus_addressdata_buf( 6) -- A13
& abus_addressdata_buf( 7) -- A12
& abus_addressdata_buf( 0) -- A11
& abus_addressdata_buf( 1) -- A10
& abus_addressdata_buf( 2) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf(12) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 8) -- A3
& abus_addressdata_buf( 9) -- A2
& abus_addressdata_buf(10) -- A1
& abus_addressdata_buf(11) -- A0
& "0";
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched_prepatch <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata_buf(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata_buf(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata_buf( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata_buf( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata_buf( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata_buf( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata_buf( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(13) -- A6
-- A14 -> MUX11 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX12 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX9 & abus_addressdata_buf( 4) -- A3
-- A11 -> MUX10 & abus_addressdata_buf( 5) -- A2
-- A10 -> MUX2 & abus_addressdata_buf( 6) -- A1
-- A9 -> MUX1 & abus_addressdata_buf( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata <= X"00"&counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out(15 downto 0);
when X"E2" =>
avalon_regs_readdata <= sniffer_data_out(31 downto 16);
when X"E4" =>
avalon_regs_readdata <= sniffer_data_out(47 downto 32);
when X"E6" =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
when X"E8" =>
avalon_regs_readdata <= X"00"&sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata <= "00000"&sniffer_fifo_full&sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
sniffer_data_ack <= '0';
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
when X"E2" =>
null;
when X"E4" =>
null;
when X"E6" =>
sniffer_data_ack <= '1';
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(22 downto 10);
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);--avalon_sdram_pending_address(0);--only 8 bit writing for avalon
sdram_dqm(1) <= not avalon_sdram_byteenable(1);--not avalon_sdram_pending_address(0);--only 8 bit writing for avalon
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE then
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_cas_n <= '0';
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_dq <= avalon_sdram_pending_data; --(7 downto 0) & avalon_sdram_pending_data(15 downto 8) ;--&avalon_sdram_pending_data;
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
--avalon_sdram_reset_pending <= '1';
--if avalon_sdram_pending_address(0) = '0' then
avalon_sdram_readdata_latched <= sdram_dq;--(7 downto 0);
--else
--avalon_sdram_readdata_latched <= sdram_dq(15 downto 8);
--end if;
--avalon_sdram_readdatavalid <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
end if;
end if;
end process;
sniffer_data_in(15 downto 0) <= abus_data_in when abus_direction_internal='0' else
abus_data_out;
sniffer_data_in(40 downto 16) <= abus_address_latched(24 downto 0);
sniffer_data_in(41) <= not abus_chipselect_buf(0);
sniffer_data_in(42) <= not abus_chipselect_buf(1);
sniffer_data_in(43) <= not abus_chipselect_buf(2);
sniffer_data_in(44) <= not abus_write_buf(0);
sniffer_data_in(45) <= not abus_write_buf(1);
sniffer_data_in(46) <= not abus_read_buf;
sniffer_data_in(47) <= '0';--reserved
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/wasca_inst.vhd | 2 | 12850 | component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
altpll_1_areset_conduit_export : in std_logic := 'X'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic; -- export
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- export
hex0_conn_export : out std_logic_vector(6 downto 0); -- export
hex1_conn_export : out std_logic_vector(6 downto 0); -- export
hex2_conn_export : out std_logic_vector(6 downto 0); -- export
hex3_conn_export : out std_logic_vector(6 downto 0); -- export
hex4_conn_export : out std_logic_vector(6 downto 0); -- export
hex5_conn_export : out std_logic_vector(6 downto 0); -- export
hexdot_conn_export : out std_logic_vector(5 downto 0); -- export
leds_conn_export : out std_logic_vector(3 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
spi_sync_conn_export : in std_logic := 'X'; -- export
switches_conn_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address
abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read
abus_avalon_sdram_bridge_0_abus_waitrequest => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_waitrequest, -- .waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_addressdata, -- .addressdata
abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect
abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction
abus_avalon_sdram_bridge_0_abus_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_disable_out, -- .disable_out
abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt
abus_avalon_sdram_bridge_0_abus_muxing => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_muxing, -- .muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset
abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr
abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba
abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n
abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke
abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n
abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq
abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm
abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n
abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n
abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk
altpll_1_areset_conduit_export => CONNECTED_TO_altpll_1_areset_conduit_export, -- altpll_1_areset_conduit.export
altpll_1_locked_conduit_export => CONNECTED_TO_altpll_1_locked_conduit_export, -- altpll_1_locked_conduit.export
altpll_1_phasedone_conduit_export => CONNECTED_TO_altpll_1_phasedone_conduit_export, -- altpll_1_phasedone_conduit.export
buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi
buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk
buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso
buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
extra_leds_conn_export => CONNECTED_TO_extra_leds_conn_export, -- extra_leds_conn.export
hex0_conn_export => CONNECTED_TO_hex0_conn_export, -- hex0_conn.export
hex1_conn_export => CONNECTED_TO_hex1_conn_export, -- hex1_conn.export
hex2_conn_export => CONNECTED_TO_hex2_conn_export, -- hex2_conn.export
hex3_conn_export => CONNECTED_TO_hex3_conn_export, -- hex3_conn.export
hex4_conn_export => CONNECTED_TO_hex4_conn_export, -- hex4_conn.export
hex5_conn_export => CONNECTED_TO_hex5_conn_export, -- hex5_conn.export
hexdot_conn_export => CONNECTED_TO_hexdot_conn_export, -- hexdot_conn.export
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset
spi_sync_conn_export => CONNECTED_TO_spi_sync_conn_export, -- spi_sync_conn.export
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/Altera_UP_SD_Card_48_bit_Command_Generator.vhd | 7 | 25262 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module takes a command ID and data, and generates a 48-bit message for it.
-- It will first check if the command is a valid 48-bit command and produce the
-- following outputs:
-- 1. o_dataout -> a single bit output that produces the message to be sent to the
-- SD card one bit at a time. Every time the i_message_bit_out input
-- is high and the i_clock has a positive edge, a new bit is produced.
-- 2. o_message_done -> a signal that is asserted high when the entire message has been
-- produced through the o_dataout output.
-- 3. o_valid -> is a signal that is asserted high if the specified message is valid.
-- 4. o_response_type -> indicates the command response type.
-- 5. o_returning_ocr -> the response from the SD card will contain the OCR register
-- 6. o_returning_cid -> the response from the SD card will contain the CID register
-- 7. o_returning_rca -> the response from the SD card will contain the RCA register
-- 8. o_returning_csd -> the response from the SD card will contain the CSD register
-- 9. o_data_read -> asserted when the command being sent is a data read command.
-- 10. o_data_write -> asserted when the command being sent is a data write command.
-- 11. o_wait_cmd_busy -> is set high when the response to this command will be
-- followed by a busy signal.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_48_bit_Command_Generator is
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS: STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_48_bit_Command_Generator is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal last_command_id : std_logic_vector(5 downto 0);
signal message_bits : std_logic_vector(39 downto 0);
signal last_command_sent_was_CMD55, valid : std_logic;
signal bit_to_send, sending_CRC, command_valid : std_logic;
signal returning_cid_reg, returning_rca_reg, returning_csd_reg, returning_dsr_reg, returning_ocr_reg, returning_status_reg : std_logic;
-- UNREGISTERED
signal temp_4_bits : std_logic_vector(3 downto 0);
signal message_done, CRC_generator_out, produce_next_bit : std_logic;
signal app_specific_valid, regular_command_valid : std_logic;
signal response_type, response_type_reg : std_logic_vector(2 downto 0);
signal cmd_argument : std_logic_vector(31 downto 0);
begin
-- This set of bits is necessary to allow the SD card to accept a VDD level for communication.
temp_4_bits <= "1111" when ((i_OCR(23) = '1') or (i_OCR(22) = '1') or (i_OCR(21) = '1') or (i_OCR(20) = '1')) else "0000";
-- Generate the bits to be sent to the SD card. These bits must pass through the CRC generator
-- to produce error checking code. The error checking code will follow the message. The message terminates with
-- a logic '1'. Total message length is 48 bits.
message_data_generator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
message_bits <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Store type of a response.
response_type_reg <= response_type;
-- Generate a message. Please note that the predefined messages are used for initialization.
-- If executed in sequence, they will initialize the SD card to work correctly. Only once these
-- instructions are completed can the data transfer begin.
case (i_predefined_message) is
when "0000" =>
-- Generate a predefined message - CMD0.
message_bits <= ("01" & COMMAND_0_GO_IDLE & "00000000000000000000000000000000");
when "0001" =>
-- Generate a predefined message - CMD55.
message_bits <= ("01" & COMMAND_55_APP_CMD & "0000000000000000" & "0000000000000000");
when "0010" =>
-- Generate a predefined message - ACMD41.
message_bits <= ("01" & ACOMMAND_41_SEND_OP_CONDITION & "0000" & temp_4_bits & "000" & i_OCR(20) & "00000000000000000000");
when "0011" =>
-- Generate a predefined message - CMD2.
message_bits <= ("01" & COMMAND_2_ALL_SEND_CID & "00000000000000000000000000000000");
when "0100" =>
-- Generate a predefined message - CMD3.
message_bits <= ("01" & COMMAND_3_SEND_RCA & "00000000000000000000000000000000");
when "0101" =>
-- Generate a predefined message - CMD9.
message_bits <= ("01" & COMMAND_9_SEND_CSD & i_RCA & "0000000000000000");
when "0110" =>
-- Generate a predefined message - CMD4.
message_bits <= ("01" & COMMAND_4_SET_DSR & i_DSR & "0000000000000000");
when "0111" =>
-- Generate a predefined message - CMD16. Set block length to 512.
message_bits <= ("01" & COMMAND_16_SET_BLOCK_LENGTH & "0000000000000000" & "0000001000000000" );
when "1000" =>
-- Generate a predefined message - CMD7. Select the card so we can access it's data.
message_bits <= ("01" & COMMAND_7_SELECT_CARD & i_RCA & "0000001000000000" );
when "1001" =>
-- Generate a predefined message - CMD13. Send SD card status.
message_bits <= ("01" & COMMAND_13_SEND_STATUS & i_RCA & "0000000000000000");
when others =>
-- Generate a custom message
message_bits <= ("01" & i_command_ID & cmd_argument);
end case;
else
-- Shift bits out as needed
if (produce_next_bit = '1') then
-- Shift message bits.
message_bits(39 downto 1) <= message_bits(38 downto 0);
message_bits(0) <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generate command argument based on the command_ID. For most commands, the argument is user specified.
-- For some commands, it is necessary to send a particular SD Card register contents. Hence, these contents are
-- sent instead of the user data.
argument_generator: process (i_command_ID, last_command_sent_was_CMD55, i_generate, i_RCA, i_DSR, i_OCR, i_argument)
begin
cmd_argument <= i_argument;
if (i_generate = '1') then
case (i_command_ID) is
when COMMAND_4_SET_DSR =>
cmd_argument <= i_DSR & i_argument(15 downto 0);
when COMMAND_7_SELECT_CARD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_9_SEND_CSD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_10_SEND_CID =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_13_SEND_STATUS =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_15_GO_INACTIVE =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_55_APP_CMD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when ACOMMAND_41_SEND_OP_CONDITION =>
if (last_command_sent_was_CMD55 = '1') then
cmd_argument <= i_OCR;
end if;
when others =>
cmd_argument <= i_argument;
end case;
end if;
end process;
-- Validate the message ID before sending it out.
command_validator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
command_valid <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
if (("0" & i_predefined_message) >= ("0" & FIRST_NON_PREDEFINED_COMMAND)) then
-- Check the custom message
if (last_command_sent_was_CMD55 = '1') then
-- Check the application specific messages
command_valid <= app_specific_valid;
else
-- Check the default messages.
command_valid <= regular_command_valid;
end if;
else
-- A command is valid if the message is predefined.
command_valid <= '1';
end if;
end if;
end if;
end if;
end process;
-- Registers that indicate that the command sent will return contents of a control register.
-- The contents of the response should therefore be stored in the appropriate register.
responses_with_control_regs: process(i_clock, i_reset_n, last_command_sent_was_CMD55, last_command_id, message_done)
begin
if (i_reset_n = '0') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (rising_edge(i_clock)) then
if (i_generate = '1') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (message_done = '1') then
-- OCR
if ((last_command_sent_was_CMD55 = '1') and (last_command_id = ACOMMAND_41_SEND_OP_CONDITION)) then
returning_ocr_reg <= '1';
end if;
-- CID
if (last_command_id = COMMAND_2_ALL_SEND_CID) then
returning_cid_reg <= '1';
end if;
-- RCA
if (last_command_id = COMMAND_3_SEND_RCA) then
returning_rca_reg <= '1';
end if;
-- CSD
if (last_command_id = COMMAND_9_SEND_CSD) then
returning_csd_reg <= '1';
end if;
-- Status
if ((last_command_sent_was_CMD55 = '0') and (last_command_id = COMMAND_13_SEND_STATUS)) then
returning_status_reg <= '1';
end if;
end if;
end if;
end process;
-- Count the number of bits sent using a counter.
sent_bit_counter: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Reset the counter indicating the number of bits produced.
counter <= "0000000";
else
if (produce_next_bit = '1') then
-- Update the number of message bits sent.
counter <= counter + '1';
end if;
end if;
end if;
end if;
end process;
-- Select the source for the output data to be either the message data or the CRC bits.
source_selector: process(i_clock, i_reset_n, i_generate)
begin
if (i_reset_n = '0') then
sending_CRC <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Set sending CRC flag to 0.
sending_CRC <= '0';
else
-- If this is the last bit being sent, then bits that follow are the CRC bits.
if (counter = "0101000") then
sending_CRC <= '1';
end if;
end if;
end if;
end if;
end process;
-- When the message is sent, store its ID. In a special case when CMD55 is sent, the next command can be an application
-- specific command. We need to check those command IDs to verify the validity of the message.
CMD55_recognizer: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter, message_done, last_command_id)
begin
if (i_reset_n = '0') then
last_command_sent_was_CMD55 <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '0') then
-- Store the ID of the current command.
if (produce_next_bit = '1') then
if (counter = "0000000") then
last_command_id <= message_bits(37 downto 32);
end if;
end if;
-- When message has been sent then check if it was CMD55.
if (message_done = '1') then
if (last_command_id = COMMAND_55_APP_CMD) then
last_command_sent_was_CMD55 <= '1';
else
last_command_sent_was_CMD55 <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
-- Instantiate a CRC7 generator. Message bits will pass through it to create the CRC code for the message.
CRC7_Gen: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => i_message_bit_out,
i_shift => sending_CRC,
i_datain => message_bits(39),
o_dataout => CRC_generator_out
);
-- Define the source of the data produced by this module, depending on the counter value and the sending_CRC register state.
data_bit_register: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
bit_to_send <= '1';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
bit_to_send <= '1';
elsif (produce_next_bit = '1') then
-- Send data to output.
if (sending_CRC = '0') then
-- Send message bits
bit_to_send <= message_bits(39);
else
-- Send CRC bits
if ((counter = "0101111") or (counter = "0110000")) then
-- At the end of CRC bits put a 1.
bit_to_send <= '1';
else
bit_to_send <= CRC_generator_out;
end if;
end if;
end if;
end if;
end if;
end process;
-- Define conditions to produce the next message bit on the module output port o_dataout.
produce_next_bit <= i_message_bit_out and (not message_done);
-- Message is done when the last bit appears at the output.
message_done <= '1' when (counter = "0110001") else '0';
-- Check the application specific messages
app_specific_valid <= '1' when (
--(i_command_ID = COMMAND_0_GO_IDLE) or
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
--(i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = ACOMMAND_41_SEND_OP_CONDITION) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
-- Check the default messages.
regular_command_valid <= '1' when (
-------------------------------------------------------
-- Disabled to prevent malfunction of the core
-------------------------------------------------------
--(i_command_ID = COMMAND_0_GO_IDLE) or
--(i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_27_PROGRAM_CSD) or
--(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
--(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
-------------------------------------------------------
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
-------------------------------------------------------
-- Disabled to simplify the circuit
-------------------------------------------------------
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
--(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
-------------------------------------------------------
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
response_type <= "001" when -- Wait for type 1 response when
(
(i_predefined_message = "0001") or
(i_predefined_message = "0111") or
(i_predefined_message = "1000") or
(i_predefined_message = "1001") or
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD) or
((last_command_sent_was_CMD55 = '1') and
((i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR)))))
) else
"010" when -- Wait for type 2 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID))) or
(i_predefined_message = "0011") or
(i_predefined_message = "0101")
) else
"011" when -- Wait for type 3 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (last_command_sent_was_CMD55 = '1') and (i_command_ID = ACOMMAND_41_SEND_OP_CONDITION)) or
(i_predefined_message = "0010")
) else
"110" when -- Wait for type 6 response when
(((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (i_command_ID = COMMAND_3_SEND_RCA)) or
(i_predefined_message = "0100"))
else "000"; -- Otherwise there is no response pending.
-- Define circuit outputs
o_message_done <= message_done;
o_response_type <= response_type_reg;
o_valid <= command_valid;
o_dataout <= bit_to_send;
o_returning_ocr <= returning_ocr_reg;
o_returning_cid <= returning_cid_reg;
o_returning_rca <= returning_rca_reg;
o_returning_csd <= returning_csd_reg;
o_returning_status <= returning_status_reg;
o_data_read <= '1' when (last_command_id = COMMAND_17_READ_BLOCK) else '0';
o_data_write <= '1' when (last_command_id = COMMAND_24_WRITE_BLOCK) else '0';
o_last_cmd_was_55 <= last_command_sent_was_CMD55;
o_wait_cmd_busy <= '1' when (
(last_command_id = COMMAND_7_SELECT_CARD) or
(last_command_id = COMMAND_12_STOP_TRANSMISSION) or
(last_command_id = COMMAND_28_SET_WRITE_PROTECT) or
(last_command_id = COMMAND_29_CLEAR_WRITE_PROTECT) or
(last_command_id = COMMAND_38_ERASE_SELECTED_GROUPS))
else '0';
end rtl; | gpl-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/Altera_UP_SD_Card_Interface.vhd | 7 | 20738 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
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-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is an interface to the Secure Data Card. This module is intended to be
-- used with the DE2 board.
--
-- This version of the interface supports only a 1-bit serial data transfer. This
-- allows the interface to support a MultiMedia card as well.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Interface is
component Altera_UP_SD_Card_Clock
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end component;
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Signal_Trigger
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end component;
component Altera_UP_SD_Card_48_bit_Command_Generator
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end component;
component Altera_UP_SD_Card_Response_Receiver
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end component;
component Altera_UP_SD_Card_Control_FSM
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end component;
component Altera_UP_SD_Card_Buffer
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal sd_mode : std_logic;
-- SD Card Registers:
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_driver_stage_register : std_logic_vector(15 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register_valid : std_logic;
-- UNREGISTERED
signal data_from_buffer : std_logic_vector(15 downto 0);
signal clock_generator_mode, enable_generator, SD_clock, create_message : std_logic;
signal send_next_bit, receive_next_bit : std_logic;
signal timed_out, response_done, passed_crc, begin_reading_response, resetting : std_logic;
signal returning_cid, returning_rca, returning_csd, returning_ocr : std_logic;
signal response_type : std_logic_vector(2 downto 0);
signal message_valid, messange_sent, data_to_CMD_line, CMD_tristate_buffer_enable, message_sent : std_logic;
signal predef_message_ID : std_logic_vector(3 downto 0);
signal receive_data_out : std_logic_vector(127 downto 0);
signal data_line_done, data_line_crc, data_line_timeout, data_line_direction, data_line_out : std_logic;
signal data_read, data_write, wait_cmd_busy, clear_response_register : std_logic;
signal response_done_combined : std_logic;
signal timeout_combined : std_logic;
signal crc_combined, allow_partial_rw : std_logic;
signal begin_data_line_operations, last_cmd_was_55, message_sent_trigger, returning_status : std_logic;
signal data_line_sd_clock_pulse_trigger : std_logic;
begin
-- Glue logic
SD_REG_driver_stage_register <= (OTHERS => '0');
response_done_combined <= (response_done and (not data_read) and (not data_write)) or
(response_done and (data_read or data_write) and data_line_done);
timeout_combined <= (timed_out and (not data_read) and (not data_write)) or
(timed_out and (data_read or data_write) and data_line_timeout);
crc_combined <= (passed_crc and (not data_read) and (not data_write)) or
(passed_crc and (data_read or data_write) and data_line_crc);
begin_data_line_operations <= (data_read and message_sent) or (data_write and response_done);
-- Partial read and write are only allowed when both bit 79 (partial read allowed) is high and
-- bit 21 (partial write allowed) is high.
allow_partial_rw <= SD_REG_card_specific_data(79) and SD_REG_card_specific_data(21);
-- SD Card control registers
control_regs: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
SD_REG_card_identification_number <= (OTHERS => '0');
SD_REG_relative_card_address <= (OTHERS => '0');
SD_REG_card_specific_data <= (OTHERS => '0');
SD_REG_status_register <= (OTHERS => '0');
SD_REG_response_R1 <= (OTHERS => '1');
SD_REG_status_register_valid <= '0';
elsif (rising_edge(i_clock)) then
if ((response_type = "001") and (response_done = '1') and (returning_status = '0') and (clear_response_register = '0')) then
SD_REG_response_R1 <= receive_data_out(31 downto 0);
elsif (clear_response_register = '1') then
SD_REG_response_R1 <= (OTHERS => '1');
end if;
if (resetting = '1') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
elsif ((returning_ocr = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_operating_conditions_register <= receive_data_out(31 downto 0);
end if;
if ((returning_cid = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_identification_number <= receive_data_out;
end if;
if ((returning_rca = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_relative_card_address <= receive_data_out(31 downto 16);
end if;
if ((returning_csd = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_specific_data <= receive_data_out;
end if;
if (message_sent_trigger = '1') then
SD_REG_status_register_valid <= '0';
elsif ((returning_status = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_status_register <= receive_data_out(31 downto 0);
SD_REG_status_register_valid <= '1';
end if;
end if;
end process;
-- Instantiated components
command_generator: Altera_UP_SD_Card_48_bit_Command_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_message_bit_out => send_next_bit,
i_command_ID => i_command_ID,
i_argument => i_argument,
i_predefined_message => predef_message_ID,
i_generate => create_message,
i_DSR => SD_REG_driver_stage_register,
i_OCR => SD_REG_operating_conditions_register,
i_RCA => SD_REG_relative_card_address,
o_dataout => data_to_CMD_line,
o_message_done => message_sent,
o_valid => message_valid,
o_returning_ocr => returning_ocr,
o_returning_cid => returning_cid,
o_returning_rca => returning_rca,
o_returning_csd => returning_csd,
o_returning_status => returning_status,
o_data_read => data_read,
o_data_write => data_write,
o_wait_cmd_busy => wait_cmd_busy,
o_last_cmd_was_55 => last_cmd_was_55,
o_response_type => response_type
);
response_receiver: Altera_UP_SD_Card_Response_Receiver PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_begin => begin_reading_response,
i_scan_pulse => receive_next_bit,
i_datain => b_SD_cmd,
i_response_type => response_type,
i_wait_cmd_busy => wait_cmd_busy,
o_data => receive_data_out,
o_CRC_passed => passed_crc,
o_timeout => timed_out,
o_done => response_done
);
control_FSM: Altera_UP_SD_Card_Control_FSM PORT MAP
(
-- Clock and Reset signals
i_clock => i_clock,
i_reset_n => i_reset_n,
-- FSM Inputs
i_user_command_ready => i_user_command_ready,
i_clocking_pulse_enable => receive_next_bit,
i_response_received => response_done_combined,
i_response_timed_out => timeout_combined,
i_response_crc_passed => crc_combined,
i_command_sent => message_sent,
i_powerup_busy_n => SD_REG_operating_conditions_register(31),
i_current_clock_mode => clock_generator_mode,
i_user_message_valid => message_valid,
i_last_cmd_was_55 => last_cmd_was_55,
i_allow_partial_rw => allow_partial_rw,
-- FSM Outputs
o_generate_command => create_message,
o_predefined_command_ID => predef_message_ID,
o_receive_response => begin_reading_response,
o_drive_CMD_line => CMD_tristate_buffer_enable,
o_SD_clock_mode => sd_mode, -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_card_connected => o_card_connected,
o_command_completed => o_command_completed,
o_resetting => resetting,
o_clear_response_register => clear_response_register,
o_enable_clock_generator => enable_generator
);
clock_generator: Altera_UP_SD_Card_Clock PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_mode => sd_mode,
i_enable => enable_generator,
o_SD_clock => SD_clock,
o_clock_mode => clock_generator_mode,
o_trigger_receive => receive_next_bit,
o_trigger_send => send_next_bit
);
SD_clock_pulse_trigger: Altera_UP_SD_Signal_Trigger PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_signal => message_sent,
o_trigger => message_sent_trigger
);
data_line: Altera_UP_SD_Card_Buffer
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- 1 bit port to transmit and receive data on the data line.
i_begin => begin_data_line_operations,
i_sd_clock_pulse_trigger => data_line_sd_clock_pulse_trigger,
i_transmit => data_write,
i_1bit_data_in => b_SD_dat,
o_1bit_data_out => data_line_out,
o_operation_complete => data_line_done,
o_crc_passed => data_line_crc,
o_timed_out => data_line_timeout,
o_dat_direction => data_line_direction,
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port => i_buffer_enable,
i_address_16bit_port => i_buffer_address,
i_write_16bit => i_buffer_write,
i_16bit_data_in => i_buffer_data_in,
o_16bit_data_out => data_from_buffer
);
data_line_sd_clock_pulse_trigger <= (data_write and send_next_bit) or ((not data_write) and receive_next_bit);
-- Buffer output registers.
buff_regs: process(i_clock, i_reset_n, data_from_buffer)
begin
if (i_reset_n = '0') then
o_buffer_data_out <= (OTHERS=> '0');
elsif (rising_edge(i_clock)) then
o_buffer_data_out <= data_from_buffer;
end if;
end process;
-- Circuit outputs.
o_command_valid <= message_valid;
o_command_timed_out <= timeout_combined;
o_command_crc_failed <= not crc_combined;
o_SD_clock <= SD_clock;
b_SD_cmd <= data_to_CMD_line when (CMD_tristate_buffer_enable = '1') else 'Z';
b_SD_dat <= data_line_out when (data_line_direction = '1') else 'Z';
b_SD_dat3 <= 'Z'; -- Set SD card to SD mode.
-- SD card registers
o_SD_REG_card_identification_number <= SD_REG_card_identification_number;
o_SD_REG_relative_card_address <= SD_REG_relative_card_address;
o_SD_REG_operating_conditions_register <= SD_REG_operating_conditions_register;
o_SD_REG_card_specific_data <= SD_REG_card_specific_data;
o_SD_REG_status_register <= SD_REG_status_register;
o_SD_REG_response_R1 <= SD_REG_response_R1;
o_SD_REG_status_register_valid <= SD_REG_status_register_valid;
end rtl;
| gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/wasca_rst_controller.vhd | 6 | 9018 | -- wasca_rst_controller.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
| gpl-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/wasca_inst.vhd | 2 | 10448 | component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
audio_out_BCLK : in std_logic := 'X'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'X'; -- DACLRCK
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
spi_sd_card_MISO : in std_logic := 'X'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic -- SS_n
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK
audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT
audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK, -- .DACLRCK
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
spi_sd_card_MISO => CONNECTED_TO_spi_sd_card_MISO, -- spi_sd_card.MISO
spi_sd_card_MOSI => CONNECTED_TO_spi_sd_card_MOSI, -- .MOSI
spi_sd_card_SCLK => CONNECTED_TO_spi_sd_card_SCLK, -- .SCLK
spi_sd_card_SS_n => CONNECTED_TO_spi_sd_card_SS_n -- .SS_n
);
| gpl-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd | 3 | 27894 | -- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE0" then
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE2" then
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE4" then
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE6" then
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE8" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEA" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEC" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEE" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_2.vhd | 8 | 29264 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_edge_to_pulse;
architecture europa of niosII_openMac_clock_2_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_slave_FSM;
architecture europa of niosII_openMac_clock_2_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_master_FSM;
architecture europa of niosII_openMac_clock_2_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_bit_pipe;
architecture europa of niosII_openMac_clock_2_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_2
entity niosII_openMac_clock_2 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2;
architecture europa of niosII_openMac_clock_2 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_edge_to_pulse;
component niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_slave_FSM;
component niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_master_FSM;
component niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_2_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_2_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_2_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("000");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("000");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("00");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("00");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/master_handler.vhd | 5 | 13829 | -------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generated : Wed Aug 3 14:09:02 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-08 V0.02 zelenkaj Added transfer qualifiers
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- 2011-12-23 V0.04 zelenkaj Fix write hanging
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1)); --todo: verify if okay!
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if conv_integer(rx_rd_usedw) < rx_burst_size_c then
--start the smaller burst write transfer
m_burstcount_s <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if conv_integer(rx_rd_usedw) = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
| gpl-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR/auk_dspip_avalon_streaming_controller_hpfir.vhd | 2 | 3129 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Avalon Streaming Wrapper for HP FIR
--
-- Description :
--
-- This file is the Interface controller for the Avalon Streaming Wrapper.
-- The control signals between sink, core, and source modules are communicated
-- via the controller. The stall output is used as the core enable signal in
-- the wrapper.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0) := (others => '0');
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end auk_dspip_avalon_streaming_controller_hpfir;
-- hds interface_end
architecture struct of auk_dspip_avalon_streaming_controller_hpfir is
-- signal stall_int : std_logic;
-- signal stall_reg : std_logic;
-- attribute maxfan : integer;
-- attribute maxfan of stall_reg : signal is 500;
begin
reset_design <= not reset_n;
--should not stop sending data to source module when the sink module is stalled
--should only stop sending when the source module is stalled
--Disable the FIR core when backpressure
stall <= source_stall;
source_valid_ctrl <= valid;
-- Sink FIFO and FIR core are disabled at the same time
sink_ready_ctrl <= not(source_stall);
source_packet_error <= sink_packet_error;
end struct;
| gpl-2.0 |
kokx/exuberant-ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/openMAC_Ethernet.vhd | 5 | 38374 | -------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/spi_sreg.vhd | 5 | 1112 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_burst_0.vhd | 1 | 40518 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin
process (wrclock, clk) -- MG
VARIABLE rd_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
VARIABLE wr_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
begin
-- Write data
if wrclock'event and wrclock = '1' then
wr_address_internal := wraddress;
if wren = '1' then
Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
end if;
end if;
-- read data
q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal)));
IF clk'event AND clk = '1' AND rdclken = '1' THEN
rd_address_internal := rdaddress;
END IF;
end process;
end europa;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--library altera;
--use altera.altera_europa_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- port (
--
-- signal clk : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC;
-- signal reset_n : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wrclock : IN STD_LOGIC;
-- signal wren : IN STD_LOGIC;
--
--
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
--end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
--
--
--architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- component lpm_ram_dp is
--GENERIC (
-- lpm_file : STRING;
-- lpm_hint : STRING;
-- lpm_indata : STRING;
-- lpm_outdata : STRING;
-- lpm_rdaddress_control : STRING;
-- lpm_width : NATURAL;
-- lpm_widthad : NATURAL;
-- lpm_wraddress_control : STRING;
-- suppress_memory_conversion_warnings : STRING
-- );
-- PORT (
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wren : IN STD_LOGIC;
-- signal rdclock : IN STD_LOGIC;
-- signal wrclock : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC
-- );
-- end component lpm_ram_dp;
-- signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
-- signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
--
--begin
--
-- process (rdaddress)
-- begin
-- read_address <= rdaddress;
--
-- end process;
--
-- lpm_ram_dp_component : lpm_ram_dp
-- generic map(
-- lpm_file => "UNUSED",
-- lpm_hint => "USE_EAB=OFF",
-- lpm_indata => "REGISTERED",
-- lpm_outdata => "UNREGISTERED",
-- lpm_rdaddress_control => "REGISTERED",
-- lpm_width => 32,
-- lpm_widthad => 2,
-- lpm_wraddress_control => "REGISTERED",
-- suppress_memory_conversion_warnings => "ON"
-- )
-- port map(
-- data => data,
-- q => internal_q,
-- rdaddress => read_address,
-- rdclken => rdclken,
-- rdclock => clk,
-- wraddress => wraddress,
-- wrclock => wrclock,
-- wren => wren
-- );
--
--
-- q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0_fifo_module;
architecture europa of niosII_openMac_burst_0_fifo_module is
component niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component niosII_openMac_burst_0_fifo_module_fifo_ram_module;
signal estimated_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_dec : STD_LOGIC;
signal fifo_inc : STD_LOGIC;
signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_fifo_empty : STD_LOGIC;
signal internal_fifo_full : STD_LOGIC;
signal internal_p1_fifo_empty : STD_LOGIC;
signal last_write_collision : STD_LOGIC;
signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC;
signal p1_estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_fifo_full : STD_LOGIC;
signal p1_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress_reg : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_collision : STD_LOGIC;
begin
p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
wraddress <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
wraddress <= std_logic_vector'("00");
else
wraddress <= p1_wraddress;
end if;
end if;
end if;
end process;
rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
rdaddress_reg <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
rdaddress_reg <= rdaddress;
end if;
end process;
fifo_datavalid <= NOT internal_fifo_empty;
fifo_inc <= fifo_write AND NOT fifo_read;
fifo_dec <= fifo_read AND NOT fifo_write;
estimated_rdaddress <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 2);
p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
else
estimated_wraddress <= p1_estimated_wraddress;
end if;
end if;
end if;
end process;
internal_p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_empty <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_empty <= internal_p1_fifo_empty;
end if;
end if;
end process;
p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND internal_fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_full <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_full <= p1_fifo_full;
end if;
end if;
end process;
write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress)));
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_data <= fifo_wr_data;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_collision <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(fifo_read) = '1' then
last_write_collision <= std_logic'('0');
end if;
end if;
end process;
fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q);
--niosII_openMac_burst_0_fifo_module_fifo_ram, which is an e_ram
niosII_openMac_burst_0_fifo_module_fifo_ram : niosII_openMac_burst_0_fifo_module_fifo_ram_module
port map(
q => fifo_ram_q,
clk => clk,
data => fifo_wr_data,
rdaddress => rdaddress,
rdclken => module_input,
reset_n => reset_n,
wraddress => wraddress,
wrclock => clk,
wren => fifo_write
);
module_input <= std_logic'('1');
--vhdl renameroo for output signals
fifo_empty <= internal_fifo_empty;
--vhdl renameroo for output signals
fifo_full <= internal_fifo_full;
--vhdl renameroo for output signals
p1_fifo_empty <= internal_p1_fifo_empty;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
--
--Burst adapter parameters:
--adapter is mastered by: powerlink_0/MAC_DMA
--adapter masters: SRAM_0/avalon_tristate_slave
--asp_debug: 0
--byteaddr_width: 23
--ceil_data_width: 32
--data_width: 32
--dbs_shift: -1
--dbs_upstream_burstcount_width: 3
--downstream_addr_shift: 2
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 16
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 21
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 3
--upstream_max_burstcount: 4
--zero_address_width: 0
entity niosII_openMac_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0;
architecture europa of niosII_openMac_burst_0 is
component niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end component niosII_openMac_burst_0_fifo_module;
signal address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_datavalid : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal fifo_full : STD_LOGIC;
signal fifo_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_read : STD_LOGIC;
signal fifo_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : STD_LOGIC;
signal flush_fifo : STD_LOGIC;
signal full_width_rdv_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_readdatavalid : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal module_input1 : STD_LOGIC;
signal negative_dbs_rdv_counter : STD_LOGIC;
signal negative_dbs_read_expression : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal quantized_burst_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal quantized_burst_limit : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal read_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
quantized_burst_base <= A_EXT (((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000011")), 23);
quantized_burst_limit <= A_EXT (((std_logic_vector'("0") & ((((((std_logic_vector'("0") & (((std_logic_vector'("0") & ((((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000001"))))) + (std_logic_vector'("00000000000000000000000000000") & ((upstream_burstcount & A_ToStdLogicVector(std_logic'('0')))))))) - std_logic_vector'("0000000000000000000000000000000001"))) OR std_logic_vector'("0000000000000000000000000000000011"))))) + std_logic_vector'("00000000000000000000000000000000001")), 23);
negative_dbs_read_expression <= A_EXT (A_SRL((((std_logic_vector'("0") & (quantized_burst_limit)) - (std_logic_vector'("0") & (quantized_burst_base)))),std_logic_vector'("00000000000000000000000000000010")), 3);
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(upstream_read) = '1'), negative_dbs_read_expression, upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(downstream_readdatavalid) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("00000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 3);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (data_counter)))), 3);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (std_logic_vector'("00000000000000000000000000000") & ((A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining)))), std_logic_vector'("00000000000000000000000000000001")));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone) AND or_reduce(internal_downstream_byteenable(3 DOWNTO 2))))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 2);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 2);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000001"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("00000000000000000000") & ((address_offset & std_logic_vector'("00"))))), 21);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
negative_dbs_rdv_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
negative_dbs_rdv_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(upstream_address(1)))), A_WE_StdLogicVector((std_logic'(fifo_datavalid) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))));
end if;
end process;
fifo_read <= NOT fifo_empty AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) = std_logic_vector'("00000000000000000000000000000001"))) OR (((((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001"))) = (std_logic_vector'("000000000000000000000000000000") & (current_upstream_burstcount)))))));
fifo_write <= downstream_readdatavalid;
fifo_wr_data <= downstream_readdata;
flush_fifo <= std_logic'('0');
--the_niosII_openMac_burst_0_fifo_module, which is an e_instance
the_niosII_openMac_burst_0_fifo_module : niosII_openMac_burst_0_fifo_module
port map(
fifo_datavalid => fifo_datavalid,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
fifo_rd_data => fifo_rd_data,
p1_fifo_empty => p1_fifo_empty,
clk => clk,
clk_en => module_input1,
fifo_read => fifo_read,
fifo_wr_data => fifo_wr_data,
fifo_write => fifo_write,
flush_fifo => flush_fifo,
inc_pending_data => fifo_write,
reset_n => reset_n
);
module_input1 <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
full_width_rdv_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
full_width_rdv_counter <= A_EXT (A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(internal_upstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)))), 3);
end if;
end process;
internal_upstream_readdatavalid <= fifo_datavalid;
upstream_readdata <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000") = (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))), Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0)), Std_Logic_Vector'(fifo_rd_data(31 DOWNTO 16) & fifo_rd_data(31 DOWNTO 16)));
internal_downstream_byteenable <= upstream_byteenable;
internal_downstream_write <= ((upstream_write AND state_busy) AND NOT(pending_upstream_read)) AND fifo_empty;
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_byteenable <= internal_downstream_byteenable;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_readdatavalid <= internal_upstream_readdatavalid;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
--synthesis translate_off
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'((fifo_full AND fifo_write)) = '1' then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("simulation assertion failed: niosII_openMac_burst_0: illegal write into full fifo."));
write(output, write_line.all);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx/fifo_write.vhd | 2 | 5316 | ------------------------------------------------------------------------------------------------------------------------
-- write controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the write controler.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj element calculation buggy
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_write_ctrl is
generic(N: natural:=4);
port(
clkw, resetw: in std_logic;
wr: in std_logic;
r_ptr_in: in std_logic_vector(N downto 0);
w_full: out std_logic;
w_empty: out std_logic;
w_ptr_out: out std_logic_vector(N downto 0);
w_addr: out std_logic_vector(N-1 downto 0);
w_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_write_ctrl;
architecture gray_arch of fifo_write_ctrl is
signal w_ptr_reg, w_ptr_next: std_logic_vector(N downto 0);
signal r_ptr_reg, r_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal waddr_all: std_logic_vector(N-1 downto 0);
signal waddr_msb, raddr_msb: std_logic;
signal full_flag, empty_flag: std_logic;
signal w_elements_wr, w_elements_rd, w_elements_diff : std_logic_vector(N downto 0);
signal w_elements_reg, w_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkw,resetw)
begin
if (resetw='1') then
w_ptr_reg <= (others=>'0');
--r_ptr_reg <= (others => '0');
w_elements_reg <= (others => '0');
elsif (clkw'event and clkw='1') then
w_ptr_reg <= w_ptr_next;
--r_ptr_reg <= r_ptr_next;
w_elements_reg <= w_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= w_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update write pointer
w_ptr_next <= gray1 when wr='1' and full_flag='0' else
w_ptr_reg;
-- save read pointer
r_ptr_next <= r_ptr_in;
-- N-bit Gray counter
waddr_msb <= w_ptr_reg(N) xor w_ptr_reg(N-1);
waddr_all <= waddr_msb & w_ptr_reg(N-2 downto 0);
-- check for FIFO full and empty
raddr_msb <= r_ptr_in(N) xor r_ptr_in(N-1);
full_flag <=
'1' when r_ptr_in(N) /=w_ptr_reg(N) and
r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
empty_flag <=
'1' when r_ptr_in(N) =w_ptr_reg(N) and
r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
w_elements_wr <= bin;
w_elements_rd <= r_ptr_in xor ('0' & w_elements_rd(N downto 1));
w_elements_diff <= std_logic_vector(unsigned(w_elements_wr) - unsigned(w_elements_rd));
w_elements_next <= w_elements_diff(w_elements_next'range);
-- output
w_addr <= waddr_all;
w_ptr_out <= w_ptr_reg;
w_elements <= w_elements_reg;
w_full <= full_flag;
w_empty <= empty_flag;
end gray_arch; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenMAC_cmp.vhd | 5 | 4720 | -------------------------------------------------------------------------------
--
-- Title : openMAC_cmp
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_cmp.vhd
-- Generated : Wed Jul 27 10:52:27 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2012-01-11 V0.02 mairt moved registers to seperate cmp int and tog int
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openMAC_cmp is
generic(
mac_time_width_g : integer := 32;
gen2ndCmpTimer_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end openMAC_cmp;
architecture rtl of openMAC_cmp is
signal cmp_enable, tog_enable : std_logic;
signal cmp_value, tog_value : std_logic_vector(mac_time'range);
signal irq_s, toggle_s : std_logic;
begin
irq <= irq_s;
toggle <= toggle_s;
process(clk, rst)
begin
if rst = '1' then
cmp_enable <= '0'; cmp_value <= (others => '0'); irq_s <= '0';
if gen2ndCmpTimer_g = TRUE then
tog_enable <= '0'; tog_value <= (others => '0'); toggle_s <= '0';
end if;
elsif clk = '1' and clk'event then
--cmp
if cmp_enable = '1' and mac_time = cmp_value then
irq_s <= '1';
end if;
--tog
if tog_enable = '1' and mac_time = tog_value and gen2ndCmpTimer_g = TRUE then
toggle_s <= not toggle_s;
end if;
--memory mapping
if wr = '1' then
case addr is
when "00" =>
cmp_value <= din;
irq_s <= '0';
when "01" =>
cmp_enable <= din(0);
when "10" =>
if gen2ndCmpTimer_g = TRUE then
tog_value <= din;
end if;
when "11" =>
if gen2ndCmpTimer_g = TRUE then
tog_enable <= din(0);
end if;
when others =>
--go and get a coffee...
end case;
end if;
end if;
end process;
dout <=
mac_time when addr = "00" else
x"000000" & "00" & "00" & "00" & irq_s & cmp_enable when addr = "01" else
tog_value when addr = "10" and gen2ndCmpTimer_g = TRUE else
x"000000" & "00" & "00" & "00" & toggle_s & tog_enable when addr = "11" and gen2ndCmpTimer_g = TRUE else
mac_time; --otherwise give me the current time...
end rtl;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx/n_synchronizer.vhd | 2 | 3577 | ------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj add an additional sync stage
-- 2011-11-25 V0.03 mairt omitted reset out
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; | gpl-2.0 |
istankovic/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/current_source_arc.vhdl | 15 | 174 | ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_controlStatusReg.vhd | 5 | 20582 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
-- 2011-11-21 V0.02 zelenkaj added time synchronization feature
-- added 12 bytes to DPR as reserved
-- 2011-11-29 V0.03 zelenkaj led and event is optional
-- 2011-12-20 V0.04 zelenkaj changed 2xbuf switch source to ap irq
-- 2012-01-26 V0.05 zelenkaj en-/disable double buffer with genTimeSync_g
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdiControlStatusReg is
generic (
bIsPcp : boolean := true;
iAddrWidth_g : integer := 8;
iBaseDpr_g : integer := 16#4#; --base address (in external mapping) of content in dpr
iSpanDpr_g : integer := 12; --span of content in dpr
iBaseMap2_g : integer := 0; --base address in dpr
iDprAddrWidth_g : integer := 11;
iRpdos_g : integer := 3;
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--register content
---constant values
magicNumber : std_Logic_vector(31 downto 0) := (others => '0');
pdiRev : std_logic_vector(15 downto 0) := (others => '0');
tPdoBuffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo0Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo1Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo2Buffer : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Rx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Rx : std_logic_vector(31 downto 0) := (others => '0')
);
port (
--memory mapped interface
clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector(iAddrWidth_g-1 downto 0);
be : in std_logic_vector(3 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
--register content
---virtual buffer control signals
rpdo_change_tog : in std_logic_vector(2 downto 0); --change buffer from hw acc
tpdo_change_tog : in std_logic; --change buffer from hw acc
pdoVirtualBufferSel : in std_logic_vector(31 downto 0); --for debugging purpose from SW side
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
tPdoTrigger : out std_logic; --TPDO virtual buffer change trigger
rPdoTrigger : out std_logic_vector(2 downto 0); --RPDOs virtual buffer change triggers
---is used for Irq Generation and should be mapped to apIrqGen
apIrqControlOut : out std_logic_vector(15 downto 0);
apIrqControlIn : in std_logic_vector(15 downto 0);
---event registers
eventAckIn : in std_logic_vector(15 downto 0);
eventAckOut : out std_logic_vector(15 downto 0);
---async irq (by event)
asyncIrqCtrlIn : In std_logic_vector(15 downto 0); --Ap only
asyncIrqCtrlOut : out std_logic_vector(15 downto 0); --Ap only
---led stuff
ledCnfgIn : in std_logic_vector(15 downto 0);
ledCnfgOut : out std_logic_vector(15 downto 0);
ledCtrlIn : in std_logic_vector(15 downto 0);
ledCtrlOut : out std_logic_vector(15 downto 0);
---time synchronization
doubleBufSel_out : out std_logic; --Ap only
doubleBufSel_in : in std_logic := '0'; --Pcp only
timeSyncIrq : in std_logic; --SYNC IRQ to Ap (Ap only)
--dpr interface (from PCP/AP to DPR)
dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0);
dprDin : out std_logic_vector(31 downto 0);
dprDout : in std_logic_vector(31 downto 0);
dprBe : out std_logic_vector(3 downto 0);
dprWr : out std_logic
);
end entity pdiControlStatusReg;
architecture rtl of pdiControlStatusReg is
constant c_num_dbuf_dpr : integer := 4; --number of dbuf in DPR (per buffer 4 byte)
signal selDpr : std_logic; --if '1' get/write content from/to dpr
signal nonDprDout : std_logic_vector(31 downto 0);
signal addrRes : std_logic_vector(dprAddrOff'range);
--signal apIrqValue_s : std_logic_vector(31 downto 0); --pcp only
signal virtualBufferSelectTpdo : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo0 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo1 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo2 : std_logic_vector(15 downto 0);
--edge detection
signal rpdo_change_tog_l : std_logic_vector(2 downto 0); --change buffer from hw acc
signal tpdo_change_tog_l : std_logic; --change buffer from hw acc
--time synchronization
signal timeSyncIrq_rising : std_logic;
---select signals
signal sel_time_after_sync : std_logic;
signal sel_double_buffer : std_logic;
----double buffered content
signal sel_relative_time_l : std_logic;
signal sel_relative_time_h : std_logic;
signal sel_nettime_nsec : std_logic;
signal sel_nettime_sec : std_logic;
signal sel_time_sync_regs : std_logic;
---time after sync counter
constant c_time_after_sync_cnt_size : integer := 16; --revise code if changed
signal time_after_sync_cnt : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_latch : std_logic_vector(c_time_after_sync_cnt_size/2-1 downto 0);
signal time_after_sync_cnt_next : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_out : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
constant time_after_sync_res : std_logic_vector(32-c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
---address offsets
constant c_addr_time_after_sync : integer := 16#50#;
constant c_addr_relative_time_l : integer := 16#40#;
constant c_addr_relative_time_h : integer := 16#44#;
constant c_addr_nettime_nsec : integer := 16#48#;
constant c_addr_nettime_sec : integer := 16#4C#;
begin
--map to 16bit register
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
virtualBufferSelectRpdo0 <= pdoVirtualBufferSel( 7 downto 0) & pdoVirtualBufferSel( 7 downto 0);
virtualBufferSelectRpdo1 <= pdoVirtualBufferSel(15 downto 8) & pdoVirtualBufferSel(15 downto 8);
virtualBufferSelectRpdo2 <= pdoVirtualBufferSel(23 downto 16) & pdoVirtualBufferSel(23 downto 16);
virtualBufferSelectTpdo <= pdoVirtualBufferSel(31 downto 24) & pdoVirtualBufferSel(31 downto 24);
--generate dpr select signal
selDpr <= sel when (conv_integer(addr) >= iBaseDpr_g AND
conv_integer(addr) < iBaseDpr_g + iSpanDpr_g - c_num_dbuf_dpr)
else '0';
--time sync select content if the double buffer has to be generated (genTimeSync_g)
sel_time_after_sync <= '1' when conv_integer(addr)*4 = c_addr_time_after_sync and genTimeSync_g else '0';
sel_relative_time_l <= '1' when conv_integer(addr)*4 = c_addr_relative_time_l and genTimeSync_g else '0';
sel_relative_time_h <= '1' when conv_integer(addr)*4 = c_addr_relative_time_h and genTimeSync_g else '0';
sel_nettime_nsec <= '1' when conv_integer(addr)*4 = c_addr_nettime_nsec and genTimeSync_g else '0';
sel_nettime_sec <= '1' when conv_integer(addr)*4 = c_addr_nettime_sec and genTimeSync_g else '0';
---or them up...
sel_time_sync_regs <= sel_relative_time_l or sel_relative_time_h or sel_nettime_nsec or sel_nettime_sec;
genTimeSync : if genTimeSync_g generate
begin
--we need a rising edge to do magic
apSyncIrqEdgeDet : entity work.edgedet
port map (
din => timeSyncIrq,
rising => timeSyncIrq_rising,
falling => open,
any => open,
clk => clk,
rst => rst
);
genDoubleBufPcp : if bIsPcp generate
begin
--take the other buffer (Ap has already inverted, see lines below!)
sel_double_buffer <= doubleBufSel_in;
--Pcp has no timer
time_after_sync_cnt_out <= (others => '0');
end generate;
genDoubleBufAp : if not bIsPcp generate
begin
--output the inverted to the PCP
doubleBufSel_out <= not sel_double_buffer;
--switch the double buffer with the sync irq, rising edge of course
process(clk, rst)
begin
if rst = '1' then
sel_double_buffer <= '0';
elsif rising_edge(clk) then
if timeSyncIrq_rising = '1' then --rising edge
sel_double_buffer <= not sel_double_buffer;
end if;
end if;
end process;
end generate;
genTimeAfterSyncCnt : if not bIsPcp generate
constant ZEROS : std_logic_vector(time_after_sync_cnt'range) := (others => '0');
constant ONES : std_logic_vector(time_after_sync_cnt'range) := (others => '1');
begin
--TIME_AFTER_SYNC counter
process(clk, rst)
begin
if rst = '1' then
time_after_sync_cnt <= (others => '0');
elsif clk = '1' and clk'event then
time_after_sync_cnt <= time_after_sync_cnt_next;
--there are some kind of interfaces that read only the half of a word...
-- so store the half that is not read
-- and forward it to the Ap at the next read
if sel = '1' and sel_time_after_sync = '1' and be = "0001" then
time_after_sync_cnt_latch <= time_after_sync_cnt(c_time_after_sync_cnt_size-1 downto c_time_after_sync_cnt_size/2);
end if;
end if;
end process;
time_after_sync_cnt_next <= ZEROS when timeSyncIrq_rising = '1' else --rising edge
time_after_sync_cnt when time_after_sync_cnt = ONES else --saturate
time_after_sync_cnt + 1; --count for your life!
time_after_sync_cnt_out <= time_after_sync_cnt when be(3 downto 2) = "11" or be(1 downto 0) = "11" else
time_after_sync_cnt_latch & time_after_sync_cnt(time_after_sync_cnt_latch'range);
end generate;
end generate;
--assign content depending on selDpr
dprDin <= din;
dprBe <= be;
dprWr <= wr when selDpr = '1' else
'0';
dout <= dprDout when selDpr = '1' else
nonDprDout;
dprAddrOff <= addrRes + 4 when sel_double_buffer = '1' and sel_time_sync_regs = '1' and genTimeSync_g else --select 2nd double buffer
addrRes; --select 1st double buffer or other content
--address conversion
---map external address mapping into dpr
addrRes <= conv_std_logic_vector(iBaseMap2_g - iBaseDpr_g, addrRes'length);
--non dpr read
with conv_integer(addr)*4 select
nonDprDout <= magicNumber when 16#00#,
(x"0000" & pdiRev) when 16#04#,
--STORED IN DPR when 16#08#,
--STORED IN DPR when 16#0C#,
--STORED IN DPR when 16#10#,
--STORED IN DPR when 16#14#,
--STORED IN DPR when 16#18#,
--STORED IN DPR when 16#1C#,
--STORED IN DPR when 16#20#,
--STORED IN DPR when 16#24#,
--STORED IN DPR when 16#28#,
--STORED IN DPR when 16#2C#,
--STORED IN DPR when 16#30#,
--STORED IN DPR when 16#34#, --RESERVED
--STORED IN DPR when 16#38#, --RESERVED
--STORED IN DPR when 16#3C#, --RESERVED
--STORED IN DPR x2 when c_addr_relative_time_l, --RELATIVE_TIME low
--STORED IN DPR x2 when c_addr_relative_time_h, --RELATIVE_TIME high
--STORED IN DPR x2 when c_addr_nettime_nsec, --NETTIME nsec
--STORED IN DPR x2 when c_addr_nettime_sec, --NETTIME sec
(time_after_sync_res &
time_after_sync_cnt_out) when c_addr_time_after_sync, --RES / TIME_AFTER_SYNC
(eventAckIn & asyncIrqCtrlIn) when 16#54#,
tPdoBuffer when 16#58#,
rPdo0Buffer when 16#5C#,
rPdo1Buffer when 16#60#,
rPdo2Buffer when 16#64#,
asyncBuffer1Tx when 16#68#,
asyncBuffer1Rx when 16#6C#,
asyncBuffer2Tx when 16#70#,
asyncBuffer2Rx when 16#74#,
--RESERVED when 16#78#,
--RESERVED when 16#7C#,
(virtualBufferSelectRpdo0 &
virtualBufferSelectTpdo) when 16#80#,
(virtualBufferSelectRpdo2 &
virtualBufferSelectRpdo1) when 16#84#,
(x"0000" & apIrqControlIn) when 16#88#,
--RESERVED when 16#8C#,
--RESERVED when 16#90#,
(ledCnfgIn & ledCtrlIn) when 16#94#,
(others => '0') when others;
--ignored values
asyncIrqCtrlOut(14 downto 1) <= (others => '0');
eventAckOut(15 downto 8) <= (others => '0');
--non dpr write
process(clk, rst)
begin
if rst = '1' then
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
--apIrqControlOut <= (others => '0');
if bIsPcp = true then
apIrqControlOut(7) <= '0';
apIrqControlOut(6) <= '0';
end if;
if bIsPcp = false then
apIrqControlOut(15) <= '0';
end if;
apIrqControlOut(0) <= '0';
if genEvent_g then
if bIsPcp = false then
asyncIrqCtrlOut(0) <= '0';
asyncIrqCtrlOut(15) <= '0';
end if;
eventAckOut(7 downto 0) <= (others => '0');
end if;
if genLedGadget_g then
ledCtrlOut(7 downto 0) <= (others => '0');
ledCnfgOut(7 downto 0) <= (others => '0');
end if;
if bIsPcp then
rpdo_change_tog_l <= (others => '0');
tpdo_change_tog_l <= '0';
end if;
elsif clk = '1' and clk'event then
--default assignments
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
apIrqControlOut(0) <= '0'; --PCP: set pulse // AP: ack pulse
if genEvent_g then
eventAckOut(7 downto 0) <= (others => '0'); --PCP: set pulse // AP: ack pulse
end if;
if bIsPcp then
--shift register for edge det
rpdo_change_tog_l <= rpdo_change_tog;
tpdo_change_tog_l <= tpdo_change_tog;
--edge detection
---tpdo
if tpdo_change_tog_l /= tpdo_change_tog then
tPdoTrigger <= '1';
end if;
---rpdo
for i in rpdo_change_tog'range loop
if rpdo_change_tog_l(i) /= rpdo_change_tog(i) then
rPdoTrigger(i) <= '1';
end if;
end loop;
end if;
if wr = '1' and sel = '1' and selDpr = '0' then
case conv_integer(addr)*4 is
when 16#00# =>
--RO
when 16#04# =>
--RO
when 16#08# =>
--STORED IN DPR
when 16#0C# =>
--STORED IN DPR
when 16#10# =>
--STORED IN DPR
when 16#14# =>
--STORED IN DPR
when 16#18# =>
--STORED IN DPR
when 16#1C# =>
--STORED IN DPR
when 16#20# =>
--STORED IN DPR
when 16#24# =>
--STORED IN DPR
when 16#28# =>
--STORED IN DPR
when 16#2C# =>
--STORED IN DPR
when 16#30# =>
--STORED IN DPR
when 16#34# =>
--STORED IN DPR RESERVED
when 16#38# =>
--STORED IN DPR RESERVED
when 16#3C# =>
--STORED IN DPR RESERVED
when 16#40# =>
--STORED IN DPR x2
when 16#44# =>
--STORED IN DPR x2
when 16#48# =>
--STORED IN DPR x2
when 16#4C# =>
--STORED IN DPR x2
when c_addr_time_after_sync =>
--RO
when 16#54# =>
--AP ONLY
if genEvent_g then
if be(0) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(7 downto 0) <= din(7 downto 0);
asyncIrqCtrlOut(0) <= din(0); --rest is ignored
end if;
if be(1) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(15 downto 8) <= din(15 downto 8);
asyncIrqCtrlOut(15) <= din(15); --rest is ignored
end if;
if be(2) = '1' then
eventAckOut(7 downto 0) <= din(23 downto 16);
end if;
--ignore higher byte of event ack
-- if be(3) = '1' then
-- eventAckOut(15 downto 8) <= din(31 downto 24);
-- end if;
end if;
when 16#58# =>
--RO
when 16#5C# =>
--RO
when 16#60# =>
--RO
when 16#64# =>
--RO
when 16#68# =>
--RO
when 16#6C# =>
--RO
when 16#70# =>
--RO
when 16#74# =>
--RO
when 16#78# =>
--RESERVED
when 16#7C# =>
--RESERVED
when 16#80# =>
if be(0) = '1' then
tPdoTrigger <= '1';
end if;
if be(1) = '1' then
tPdoTrigger <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(0) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(0) <= '1';
end if;
when 16#84# =>
if be(0) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(1) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(2) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(2) <= '1';
end if;
when 16#88# =>
if be(0) = '1' then
--apIrqControlOut(7 downto 0) <= din(7 downto 0);
if bIsPcp = true then
apIrqControlOut(7) <= din(7);
apIrqControlOut(6) <= din(6);
end if;
apIrqControlOut(0) <= din(0);
end if;
if be(1) = '1' then
--apIrqControlOut(15 downto 8) <= din(15 downto 8);
if bIsPcp = false then
apIrqControlOut(15) <= din(15);
end if;
end if;
when 16#8C# =>
--RESERVED
when 16#90# =>
--RESERVED
when 16#94# =>
if genLedGadget_g then
if be(0) = '1' then
ledCtrlOut(7 downto 0) <= din(7 downto 0);
end if;
if be(1) = '1' then
ledCtrlOut(15 downto 8) <= din(15 downto 8);
end if;
if be(2) = '1' then
ledCnfgOut(7 downto 0) <= din(23 downto 16);
end if;
if be(3) = '1' then
ledCnfgOut(15 downto 8) <= din(31 downto 24);
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture rtl; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/pdi_controlStatusReg.vhd | 5 | 20582 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
-- 2011-11-21 V0.02 zelenkaj added time synchronization feature
-- added 12 bytes to DPR as reserved
-- 2011-11-29 V0.03 zelenkaj led and event is optional
-- 2011-12-20 V0.04 zelenkaj changed 2xbuf switch source to ap irq
-- 2012-01-26 V0.05 zelenkaj en-/disable double buffer with genTimeSync_g
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdiControlStatusReg is
generic (
bIsPcp : boolean := true;
iAddrWidth_g : integer := 8;
iBaseDpr_g : integer := 16#4#; --base address (in external mapping) of content in dpr
iSpanDpr_g : integer := 12; --span of content in dpr
iBaseMap2_g : integer := 0; --base address in dpr
iDprAddrWidth_g : integer := 11;
iRpdos_g : integer := 3;
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--register content
---constant values
magicNumber : std_Logic_vector(31 downto 0) := (others => '0');
pdiRev : std_logic_vector(15 downto 0) := (others => '0');
tPdoBuffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo0Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo1Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo2Buffer : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Rx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Rx : std_logic_vector(31 downto 0) := (others => '0')
);
port (
--memory mapped interface
clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector(iAddrWidth_g-1 downto 0);
be : in std_logic_vector(3 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
--register content
---virtual buffer control signals
rpdo_change_tog : in std_logic_vector(2 downto 0); --change buffer from hw acc
tpdo_change_tog : in std_logic; --change buffer from hw acc
pdoVirtualBufferSel : in std_logic_vector(31 downto 0); --for debugging purpose from SW side
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
tPdoTrigger : out std_logic; --TPDO virtual buffer change trigger
rPdoTrigger : out std_logic_vector(2 downto 0); --RPDOs virtual buffer change triggers
---is used for Irq Generation and should be mapped to apIrqGen
apIrqControlOut : out std_logic_vector(15 downto 0);
apIrqControlIn : in std_logic_vector(15 downto 0);
---event registers
eventAckIn : in std_logic_vector(15 downto 0);
eventAckOut : out std_logic_vector(15 downto 0);
---async irq (by event)
asyncIrqCtrlIn : In std_logic_vector(15 downto 0); --Ap only
asyncIrqCtrlOut : out std_logic_vector(15 downto 0); --Ap only
---led stuff
ledCnfgIn : in std_logic_vector(15 downto 0);
ledCnfgOut : out std_logic_vector(15 downto 0);
ledCtrlIn : in std_logic_vector(15 downto 0);
ledCtrlOut : out std_logic_vector(15 downto 0);
---time synchronization
doubleBufSel_out : out std_logic; --Ap only
doubleBufSel_in : in std_logic := '0'; --Pcp only
timeSyncIrq : in std_logic; --SYNC IRQ to Ap (Ap only)
--dpr interface (from PCP/AP to DPR)
dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0);
dprDin : out std_logic_vector(31 downto 0);
dprDout : in std_logic_vector(31 downto 0);
dprBe : out std_logic_vector(3 downto 0);
dprWr : out std_logic
);
end entity pdiControlStatusReg;
architecture rtl of pdiControlStatusReg is
constant c_num_dbuf_dpr : integer := 4; --number of dbuf in DPR (per buffer 4 byte)
signal selDpr : std_logic; --if '1' get/write content from/to dpr
signal nonDprDout : std_logic_vector(31 downto 0);
signal addrRes : std_logic_vector(dprAddrOff'range);
--signal apIrqValue_s : std_logic_vector(31 downto 0); --pcp only
signal virtualBufferSelectTpdo : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo0 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo1 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo2 : std_logic_vector(15 downto 0);
--edge detection
signal rpdo_change_tog_l : std_logic_vector(2 downto 0); --change buffer from hw acc
signal tpdo_change_tog_l : std_logic; --change buffer from hw acc
--time synchronization
signal timeSyncIrq_rising : std_logic;
---select signals
signal sel_time_after_sync : std_logic;
signal sel_double_buffer : std_logic;
----double buffered content
signal sel_relative_time_l : std_logic;
signal sel_relative_time_h : std_logic;
signal sel_nettime_nsec : std_logic;
signal sel_nettime_sec : std_logic;
signal sel_time_sync_regs : std_logic;
---time after sync counter
constant c_time_after_sync_cnt_size : integer := 16; --revise code if changed
signal time_after_sync_cnt : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_latch : std_logic_vector(c_time_after_sync_cnt_size/2-1 downto 0);
signal time_after_sync_cnt_next : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_out : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
constant time_after_sync_res : std_logic_vector(32-c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
---address offsets
constant c_addr_time_after_sync : integer := 16#50#;
constant c_addr_relative_time_l : integer := 16#40#;
constant c_addr_relative_time_h : integer := 16#44#;
constant c_addr_nettime_nsec : integer := 16#48#;
constant c_addr_nettime_sec : integer := 16#4C#;
begin
--map to 16bit register
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
virtualBufferSelectRpdo0 <= pdoVirtualBufferSel( 7 downto 0) & pdoVirtualBufferSel( 7 downto 0);
virtualBufferSelectRpdo1 <= pdoVirtualBufferSel(15 downto 8) & pdoVirtualBufferSel(15 downto 8);
virtualBufferSelectRpdo2 <= pdoVirtualBufferSel(23 downto 16) & pdoVirtualBufferSel(23 downto 16);
virtualBufferSelectTpdo <= pdoVirtualBufferSel(31 downto 24) & pdoVirtualBufferSel(31 downto 24);
--generate dpr select signal
selDpr <= sel when (conv_integer(addr) >= iBaseDpr_g AND
conv_integer(addr) < iBaseDpr_g + iSpanDpr_g - c_num_dbuf_dpr)
else '0';
--time sync select content if the double buffer has to be generated (genTimeSync_g)
sel_time_after_sync <= '1' when conv_integer(addr)*4 = c_addr_time_after_sync and genTimeSync_g else '0';
sel_relative_time_l <= '1' when conv_integer(addr)*4 = c_addr_relative_time_l and genTimeSync_g else '0';
sel_relative_time_h <= '1' when conv_integer(addr)*4 = c_addr_relative_time_h and genTimeSync_g else '0';
sel_nettime_nsec <= '1' when conv_integer(addr)*4 = c_addr_nettime_nsec and genTimeSync_g else '0';
sel_nettime_sec <= '1' when conv_integer(addr)*4 = c_addr_nettime_sec and genTimeSync_g else '0';
---or them up...
sel_time_sync_regs <= sel_relative_time_l or sel_relative_time_h or sel_nettime_nsec or sel_nettime_sec;
genTimeSync : if genTimeSync_g generate
begin
--we need a rising edge to do magic
apSyncIrqEdgeDet : entity work.edgedet
port map (
din => timeSyncIrq,
rising => timeSyncIrq_rising,
falling => open,
any => open,
clk => clk,
rst => rst
);
genDoubleBufPcp : if bIsPcp generate
begin
--take the other buffer (Ap has already inverted, see lines below!)
sel_double_buffer <= doubleBufSel_in;
--Pcp has no timer
time_after_sync_cnt_out <= (others => '0');
end generate;
genDoubleBufAp : if not bIsPcp generate
begin
--output the inverted to the PCP
doubleBufSel_out <= not sel_double_buffer;
--switch the double buffer with the sync irq, rising edge of course
process(clk, rst)
begin
if rst = '1' then
sel_double_buffer <= '0';
elsif rising_edge(clk) then
if timeSyncIrq_rising = '1' then --rising edge
sel_double_buffer <= not sel_double_buffer;
end if;
end if;
end process;
end generate;
genTimeAfterSyncCnt : if not bIsPcp generate
constant ZEROS : std_logic_vector(time_after_sync_cnt'range) := (others => '0');
constant ONES : std_logic_vector(time_after_sync_cnt'range) := (others => '1');
begin
--TIME_AFTER_SYNC counter
process(clk, rst)
begin
if rst = '1' then
time_after_sync_cnt <= (others => '0');
elsif clk = '1' and clk'event then
time_after_sync_cnt <= time_after_sync_cnt_next;
--there are some kind of interfaces that read only the half of a word...
-- so store the half that is not read
-- and forward it to the Ap at the next read
if sel = '1' and sel_time_after_sync = '1' and be = "0001" then
time_after_sync_cnt_latch <= time_after_sync_cnt(c_time_after_sync_cnt_size-1 downto c_time_after_sync_cnt_size/2);
end if;
end if;
end process;
time_after_sync_cnt_next <= ZEROS when timeSyncIrq_rising = '1' else --rising edge
time_after_sync_cnt when time_after_sync_cnt = ONES else --saturate
time_after_sync_cnt + 1; --count for your life!
time_after_sync_cnt_out <= time_after_sync_cnt when be(3 downto 2) = "11" or be(1 downto 0) = "11" else
time_after_sync_cnt_latch & time_after_sync_cnt(time_after_sync_cnt_latch'range);
end generate;
end generate;
--assign content depending on selDpr
dprDin <= din;
dprBe <= be;
dprWr <= wr when selDpr = '1' else
'0';
dout <= dprDout when selDpr = '1' else
nonDprDout;
dprAddrOff <= addrRes + 4 when sel_double_buffer = '1' and sel_time_sync_regs = '1' and genTimeSync_g else --select 2nd double buffer
addrRes; --select 1st double buffer or other content
--address conversion
---map external address mapping into dpr
addrRes <= conv_std_logic_vector(iBaseMap2_g - iBaseDpr_g, addrRes'length);
--non dpr read
with conv_integer(addr)*4 select
nonDprDout <= magicNumber when 16#00#,
(x"0000" & pdiRev) when 16#04#,
--STORED IN DPR when 16#08#,
--STORED IN DPR when 16#0C#,
--STORED IN DPR when 16#10#,
--STORED IN DPR when 16#14#,
--STORED IN DPR when 16#18#,
--STORED IN DPR when 16#1C#,
--STORED IN DPR when 16#20#,
--STORED IN DPR when 16#24#,
--STORED IN DPR when 16#28#,
--STORED IN DPR when 16#2C#,
--STORED IN DPR when 16#30#,
--STORED IN DPR when 16#34#, --RESERVED
--STORED IN DPR when 16#38#, --RESERVED
--STORED IN DPR when 16#3C#, --RESERVED
--STORED IN DPR x2 when c_addr_relative_time_l, --RELATIVE_TIME low
--STORED IN DPR x2 when c_addr_relative_time_h, --RELATIVE_TIME high
--STORED IN DPR x2 when c_addr_nettime_nsec, --NETTIME nsec
--STORED IN DPR x2 when c_addr_nettime_sec, --NETTIME sec
(time_after_sync_res &
time_after_sync_cnt_out) when c_addr_time_after_sync, --RES / TIME_AFTER_SYNC
(eventAckIn & asyncIrqCtrlIn) when 16#54#,
tPdoBuffer when 16#58#,
rPdo0Buffer when 16#5C#,
rPdo1Buffer when 16#60#,
rPdo2Buffer when 16#64#,
asyncBuffer1Tx when 16#68#,
asyncBuffer1Rx when 16#6C#,
asyncBuffer2Tx when 16#70#,
asyncBuffer2Rx when 16#74#,
--RESERVED when 16#78#,
--RESERVED when 16#7C#,
(virtualBufferSelectRpdo0 &
virtualBufferSelectTpdo) when 16#80#,
(virtualBufferSelectRpdo2 &
virtualBufferSelectRpdo1) when 16#84#,
(x"0000" & apIrqControlIn) when 16#88#,
--RESERVED when 16#8C#,
--RESERVED when 16#90#,
(ledCnfgIn & ledCtrlIn) when 16#94#,
(others => '0') when others;
--ignored values
asyncIrqCtrlOut(14 downto 1) <= (others => '0');
eventAckOut(15 downto 8) <= (others => '0');
--non dpr write
process(clk, rst)
begin
if rst = '1' then
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
--apIrqControlOut <= (others => '0');
if bIsPcp = true then
apIrqControlOut(7) <= '0';
apIrqControlOut(6) <= '0';
end if;
if bIsPcp = false then
apIrqControlOut(15) <= '0';
end if;
apIrqControlOut(0) <= '0';
if genEvent_g then
if bIsPcp = false then
asyncIrqCtrlOut(0) <= '0';
asyncIrqCtrlOut(15) <= '0';
end if;
eventAckOut(7 downto 0) <= (others => '0');
end if;
if genLedGadget_g then
ledCtrlOut(7 downto 0) <= (others => '0');
ledCnfgOut(7 downto 0) <= (others => '0');
end if;
if bIsPcp then
rpdo_change_tog_l <= (others => '0');
tpdo_change_tog_l <= '0';
end if;
elsif clk = '1' and clk'event then
--default assignments
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
apIrqControlOut(0) <= '0'; --PCP: set pulse // AP: ack pulse
if genEvent_g then
eventAckOut(7 downto 0) <= (others => '0'); --PCP: set pulse // AP: ack pulse
end if;
if bIsPcp then
--shift register for edge det
rpdo_change_tog_l <= rpdo_change_tog;
tpdo_change_tog_l <= tpdo_change_tog;
--edge detection
---tpdo
if tpdo_change_tog_l /= tpdo_change_tog then
tPdoTrigger <= '1';
end if;
---rpdo
for i in rpdo_change_tog'range loop
if rpdo_change_tog_l(i) /= rpdo_change_tog(i) then
rPdoTrigger(i) <= '1';
end if;
end loop;
end if;
if wr = '1' and sel = '1' and selDpr = '0' then
case conv_integer(addr)*4 is
when 16#00# =>
--RO
when 16#04# =>
--RO
when 16#08# =>
--STORED IN DPR
when 16#0C# =>
--STORED IN DPR
when 16#10# =>
--STORED IN DPR
when 16#14# =>
--STORED IN DPR
when 16#18# =>
--STORED IN DPR
when 16#1C# =>
--STORED IN DPR
when 16#20# =>
--STORED IN DPR
when 16#24# =>
--STORED IN DPR
when 16#28# =>
--STORED IN DPR
when 16#2C# =>
--STORED IN DPR
when 16#30# =>
--STORED IN DPR
when 16#34# =>
--STORED IN DPR RESERVED
when 16#38# =>
--STORED IN DPR RESERVED
when 16#3C# =>
--STORED IN DPR RESERVED
when 16#40# =>
--STORED IN DPR x2
when 16#44# =>
--STORED IN DPR x2
when 16#48# =>
--STORED IN DPR x2
when 16#4C# =>
--STORED IN DPR x2
when c_addr_time_after_sync =>
--RO
when 16#54# =>
--AP ONLY
if genEvent_g then
if be(0) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(7 downto 0) <= din(7 downto 0);
asyncIrqCtrlOut(0) <= din(0); --rest is ignored
end if;
if be(1) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(15 downto 8) <= din(15 downto 8);
asyncIrqCtrlOut(15) <= din(15); --rest is ignored
end if;
if be(2) = '1' then
eventAckOut(7 downto 0) <= din(23 downto 16);
end if;
--ignore higher byte of event ack
-- if be(3) = '1' then
-- eventAckOut(15 downto 8) <= din(31 downto 24);
-- end if;
end if;
when 16#58# =>
--RO
when 16#5C# =>
--RO
when 16#60# =>
--RO
when 16#64# =>
--RO
when 16#68# =>
--RO
when 16#6C# =>
--RO
when 16#70# =>
--RO
when 16#74# =>
--RO
when 16#78# =>
--RESERVED
when 16#7C# =>
--RESERVED
when 16#80# =>
if be(0) = '1' then
tPdoTrigger <= '1';
end if;
if be(1) = '1' then
tPdoTrigger <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(0) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(0) <= '1';
end if;
when 16#84# =>
if be(0) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(1) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(2) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(2) <= '1';
end if;
when 16#88# =>
if be(0) = '1' then
--apIrqControlOut(7 downto 0) <= din(7 downto 0);
if bIsPcp = true then
apIrqControlOut(7) <= din(7);
apIrqControlOut(6) <= din(6);
end if;
apIrqControlOut(0) <= din(0);
end if;
if be(1) = '1' then
--apIrqControlOut(15 downto 8) <= din(15 downto 8);
if bIsPcp = false then
apIrqControlOut(15) <= din(15);
end if;
end if;
when 16#8C# =>
--RESERVED
when 16#90# =>
--RESERVED
when 16#94# =>
if genLedGadget_g then
if be(0) = '1' then
ledCtrlOut(7 downto 0) <= din(7 downto 0);
end if;
if be(1) = '1' then
ledCtrlOut(15 downto 8) <= din(15 downto 8);
end if;
if be(2) = '1' then
ledCnfgOut(7 downto 0) <= din(23 downto 16);
end if;
if be(3) = '1' then
ledCnfgOut(15 downto 8) <= din(31 downto 24);
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture rtl; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/POWERLINK/src/lib/memMap.vhd | 5 | 3229 | ------------------------------------------------------------------------------------------------------------------------
-- memory mapping package for pdi
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 zelenkaj extracted from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- package for memory mapping
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
package memMap is
type memoryMapping_t is
record
base : integer;
span : integer;
end record;
function align32 (inVal : integer) return integer;
end package memMap;
package body memMap is
function align32 (inVal : integer) return integer is
variable tmp : std_logic_vector(31 downto 0);
variable result : integer;
begin
tmp := (conv_std_logic_vector(inVal, tmp'length) + x"00000003") and not x"00000003";
result := conv_integer(tmp);
return result;
end function;
end package body memMap;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/POWERLINK/src/OpenMAC_phyAct.vhd | 5 | 4365 | -------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/req_ack.vhd | 5 | 3613 | -------------------------------------------------------------------------------
--
-- Title : req_ack
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd
-- Generated : Mon Aug 1 15:58:57 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-01 V0.01 zelenkaj First version
-- 2011-11-30 V0.02 zelenkaj removed enable at ack output
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
entity req_ack is
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
ack : out std_logic
);
end req_ack;
architecture rtl of req_ack is
constant iMaxCnt : integer := ack_delay_g;
constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0);
signal cnt_tc : std_logic;
begin
genDelay : if zero_delay_g = false generate
theCnter : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
end if;
end process;
cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0');
cnt_tc <= '1' when cnt = iMaxCnt else '0';
ack <= cnt_tc;
end generate;
genNoDelay : if zero_delay_g = true generate
ack <= enable;
end generate;
end rtl;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_PHYMI.vhd | 5 | 5946 | ------------------------------------------------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2009-09-07 V0.02 zelenkaj Changed tristate port to In/Out and enable (Xilinx XPS doesn't like IO Ports...)
-- 2009-09-18 V0.03 zelenkaj Deleted NodeNr - isn't used by anyone...
-- 2011-11-28 V0.04 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
-- Mii_Dio : InOut std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
-- Mii_Dio <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Do <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_PHYMI.vhd | 5 | 5946 | ------------------------------------------------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2009-09-07 V0.02 zelenkaj Changed tristate port to In/Out and enable (Xilinx XPS doesn't like IO Ports...)
-- 2009-09-18 V0.03 zelenkaj Deleted NodeNr - isn't used by anyone...
-- 2011-11-28 V0.04 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
-- Mii_Dio : InOut std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
-- Mii_Dio <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Do <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenMAC_PHYMI.vhd | 5 | 5946 | ------------------------------------------------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2009-09-07 V0.02 zelenkaj Changed tristate port to In/Out and enable (Xilinx XPS doesn't like IO Ports...)
-- 2009-09-18 V0.03 zelenkaj Deleted NodeNr - isn't used by anyone...
-- 2011-11-28 V0.04 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
-- Mii_Dio : InOut std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
-- Mii_Dio <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Do <= M_Dout WHEN M_Oe = '1' ELSE 'Z';
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/POWERLINK/src/OpenMAC_DPR_Altera.vhd | 3 | 9712 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Altera FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2010-05-03 V0.02 added packet buffer dpr
-- 2011-12-22 V0.03 added initialization files
-- removed dpr_8_8
-- 2012-01-04 V0.04 replaced initialization files with mif
------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 16 / 16 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "mif/dpr_16_16.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA, wren_b => WeB,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA, byteena_b => BeB,
address_a => AddrA, address_b => AddrB,
data_a => DiA, data_b => DiB,
q_a => DoA, q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- 16 / 32 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "mif/dpr_16_32.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA,
address_a => AddrA, address_b => AddrB,
data_a => DiA,
q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- Packet buffer
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
ARCHITECTURE SYN OF openmac_dprpackets IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => memSize_g/2,
numwords_b => memSize_g/4,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => memSizeLOG2_g-1,
widthad_b => memSizeLOG2_g-2,
width_a => 16,
width_b => 32,
width_byteena_a => 2,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
rden_a => rden_a,
rden_b => rden_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/spi.vhd | 5 | 6142 | ------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-09-06 V0.01 First Implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi is
generic (
frameSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false
);
port (
-- Control Interface
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(frameSize_g-1 downto 0);
load : in std_logic; --load din
dout : out std_logic_vector(frameSize_g-1 downto 0);
valid : out std_logic; --dout is valid
-- SPI
sck : in std_logic;
ss : in std_logic;
miso : out std_logic;
mosi : in std_logic
);
end spi;
architecture rtl of spi is
--pulse generation out of spi clock (sck)
signal sckL : std_logic;
signal sckRising : std_logic;
signal sckFalling : std_logic;
signal capPulse : std_logic; --pulse to capture data
signal setPulse : std_logic; --pulse to change data
--capture data
signal capMosi : std_logic;
signal capDout : std_logic_vector(frameSize_g-1 downto 0);
--frame counter
signal cnt : integer range 0 to frameSize_g;
signal tc : std_logic;
signal miso_s : std_logic;
signal din_s : std_logic_vector(frameSize_g-1 downto 0);
begin
miso <= miso_s when ss = '1' else 'Z'; --set miso to high if slave isn't selected!
spiClkShiftReg : process(clk, rst)
begin
if rst = '1' then
if cpol_g = false then
sckL <= '0';
else
sckL <= '1';
end if;
elsif clk = '1' and clk'event then
sckL <= sck;
end if;
end process;
--generate sck rising falling edge pulse
sckRising <= '1' when sckL = '0' and sck = '1' else '0';
sckFalling <= '1' when sckL = '1' and sck = '0' else '0';
capPulse <= '0' when (ss /= '1') else
sckRising when (cpha_g = false and cpol_g = false) else
sckFalling when (cpha_g = false and cpol_g = true) else
sckFalling when (cpha_g = true and cpol_g = false) else
sckRising when (cpha_g = true and cpol_g = true) else
'0';
setPulse <= '0' when (ss /= '1') else
sckFalling when (cpha_g = false and cpol_g = false) else
sckRising when (cpha_g = false and cpol_g = true) else
sckRising when (cpha_g = true and cpol_g = false) else
sckFalling when (cpha_g = true and cpol_g = true) else
'0';
theCapLatch : process(clk, rst)
begin
if rst = '1' then
capMosi <= '0';
elsif clk = '1' and clk'event then
if capPulse = '1' then
--capture mosi data
capMosi <= mosi;
elsif load = '1' and cpha_g = true then
capMosi <= din(0);
end if;
end if;
end process;
theFrameCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' then
cnt <= 0;
elsif capPulse = '1' and cpha_g = true then
cnt <= cnt + 1;
elsif setPulse = '1' and cpha_g = false then
cnt <= cnt + 1;
end if;
end if;
end process;
tc <= '1' when cnt = frameSize_g else '0';
theDoutLatch : process(clk, rst)
begin
if rst = '1' then
dout <= (others => '0');
elsif clk = '1' and clk'event then
valid <= '0';
if tc = '1' then
if cpha_g = false then
dout <= capDout;
else
dout <= capDout(capDout'left-1 downto 0) & capMosi;
end if;
valid <= '1';
end if;
end if;
end process;
dinGenPhaF : if cpha_g = false generate
din_s <= din;
end generate;
dinGenPhaT : if cpha_g = true generate
din_s <= '0' & din(din'left downto 1);
end generate;
theShiftRegister : entity work.spi_sreg
generic map (
size_g => frameSize_g
)
port map (
clk => clk,
rst => rst,
shift => setPulse,
load => load,
din => din_s,
dout => capDout,
sin => capMosi,
sout => miso_s
);
end rtl;
| gpl-2.0 |
straywarrior/MadeCPUin21days | TwoInMuxer.vhd | 1 | 1287 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:00:30 11/14/2015
-- Design Name:
-- Module Name: TwoInMuxer_16bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TwoInMuxer_16bit is
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0));
end TwoInMuxer_16bit;
architecture Behavioral of TwoInMuxer_16bit is
begin
with opcode select
output <= input1 when '0',
input2 when '1',
input1 when others;
end Behavioral;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/p2-c.vhd | 1 | 387 | -------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_p2_rtl_c0 of t48_p2 is
for rtl
end for;
end t48_p2_rtl_c0;
| gpl-2.0 |
straywarrior/MadeCPUin21days | IF_ID_REG.vhd | 1 | 2369 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 13:39:51 11/14/2015
-- Design Name:
-- Module Name: IF_ID_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IF_ID_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
pc_in : in STD_LOGIC_VECTOR (15 downto 0);
inst_in : in STD_LOGIC_VECTOR (15 downto 0);
stall : in STD_LOGIC;
clear : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR (15 downto 0);
inst_out : out STD_LOGIC_VECTOR (15 downto 0);
rx : out STD_LOGIC_VECTOR (3 downto 0);
ry : out STD_LOGIC_VECTOR (3 downto 0)
);
end IF_ID_REG;
architecture Behavioral of IF_ID_REG is
begin
process (clear, reset, clk)
begin
if (reset = '0') then
pc_out <= (others => '0');
inst_out <= (11 => '1', others => '0');
rx <= (others => '0');
ry <= (others => '0');
elsif (clk'event and clk = '1') then
if (stall = '0' and clear = '0') then
pc_out <= pc_in;
inst_out <= inst_in;
rx(2 downto 0) <= inst_in(10 downto 8);
rx(3) <= '0';
ry(2 downto 0) <= inst_in(7 downto 5);
ry(3) <= '0';
elsif (stall = '0' and clear = '1') then
-- Clear the IF/ID
pc_out <= (others => '0');
inst_out <= (11 => '1', others => '0');
rx <= (others => '0');
ry <= (others => '0');
else
-- Insert a bubble here
null;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/t48_pack-p.vhd | 1 | 2475 | -------------------------------------------------------------------------------
--
-- $Id: t48_pack-p.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_pack is
-----------------------------------------------------------------------------
-- Global constants
-----------------------------------------------------------------------------
-- clock active level
constant clk_active_c : std_logic := '1';
-- reset active level
constant res_active_c : std_logic := '0';
-- idle level on internal data bus
constant bus_idle_level_c : std_logic := '1';
-- global data word width
constant word_width_c : natural := 8;
-- data memory address width
constant dmem_addr_width_c : natural := 8;
-- program memory address width
constant pmem_addr_width_c : natural := 12;
-----------------------------------------------------------------------------
-- Global data types
-----------------------------------------------------------------------------
-- the global data word width type
subtype word_t is std_logic_vector(word_width_c-1 downto 0);
subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0);
-- the global data memory address type
subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0);
-- the global program memory address type
subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0);
subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c);
-- the machine states
type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5);
-----------------------------------------------------------------------------
-- Global functions
-----------------------------------------------------------------------------
function to_stdLogic(input: boolean) return std_logic;
function to_boolean(input: std_logic) return boolean;
end t48_pack;
package body t48_pack is
function to_stdLogic(input: boolean) return std_logic is
begin
if input then
return '1';
else
return '0';
end if;
end to_stdLogic;
function to_boolean(input: std_logic) return boolean is
begin
if input = '1' then
return true;
else
return false;
end if;
end to_boolean;
end t48_pack;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/system/t8048.vhd | 1 | 7425 | -------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
--
-- $Id: t8048.vhd,v 1.11 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8048 is
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_b : inout std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_b : inout std_logic_vector( 7 downto 0);
t1_i : in std_logic;
p2_b : inout std_logic_vector( 7 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end t8048;
library ieee;
use ieee.numeric_std.all;
use work.t48_system_comp_pack.t8048_notri;
architecture struct of t8048 is
signal t0_s : std_logic;
signal t0_dir_s : std_logic;
signal db_s : std_logic_vector( 7 downto 0);
signal db_dir_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
t8048_notri_b : t8048_notri
generic map (
-- we don't need explicit gating of input ports
-- this is done implicitely by the bidirectional pads
gate_port_input_g => 0
)
port map (
xtal_i => xtal_i,
xtal_en_i => vdd_s,
reset_n_i => reset_n_i,
t0_i => t0_b,
t0_o => t0_s,
t0_dir_o => t0_dir_s,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_b,
db_o => db_s,
db_dir_o => db_dir_s,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_b,
p1_o => p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_o
);
-----------------------------------------------------------------------------
-- Process bidirs
--
-- Purpose:
-- Assign bidirectional signals.
--
bidirs: process (t0_b, t0_s, t0_dir_s,
db_b, db_s, db_dir_s,
p1_b, p1_s, p1_low_imp_s,
p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s)
function port_bidir_f(port_value : in std_logic_vector;
low_imp : in std_logic) return std_logic_vector is
variable result_v : std_logic_vector(port_value'range);
begin
for idx in port_value'high downto port_value'low loop
if low_imp = '1' then
result_v(idx) := port_value(idx);
elsif port_value(idx) = '0' then
result_v(idx) := '0';
else
result_v(idx) := 'Z';
end if;
end loop;
return result_v;
end;
begin
-- Test 0 -----------------------------------------------------------------
if t0_dir_s = '1' then
t0_b <= t0_s;
else
t0_b <= 'Z';
end if;
-- Data Bus ---------------------------------------------------------------
if db_dir_s = '1' then
db_b <= db_s;
else
db_b <= (others => 'Z');
end if;
-- Port 1 -----------------------------------------------------------------
p1_b <= port_bidir_f(port_value => p1_s,
low_imp => p1_low_imp_s);
-- Port 2 -----------------------------------------------------------------
p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process bidirs;
--
-----------------------------------------------------------------------------
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.10 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.9 2005/11/02 23:41:43 arniml
-- properly drive P1 and P2 with low impedance markers
--
-- Revision 1.8 2005/11/01 21:38:31 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.7 2004/12/03 19:44:36 arniml
-- removed obsolete constant
--
-- Revision 1.6 2004/12/02 22:08:42 arniml
-- introduced generic gate_port_input_g
-- forces masking of P1 and P2 input bus
--
-- Revision 1.5 2004/12/01 23:09:47 arniml
-- intruduced hierarchy t8048_notri where all system functionality
-- except bidirectional ports is handled
--
-- Revision 1.4 2004/10/24 09:10:16 arniml
-- Fix for:
-- P1 constantly in push-pull mode in t8048
--
-- Revision 1.3 2004/05/20 21:58:26 arniml
-- Fix for:
-- External Program Memory ignored when EA = 0
--
-- Revision 1.2 2004/03/29 19:40:14 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.1 2004/03/24 21:32:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_pkg.vhd | 2 | 8418 | -------------------------------------------------------------------------------
-- axi_sg_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI SG Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v4_03.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi_sg_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Convert boolean to a std_logic
function bo2int (value : boolean)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- AXI Response Values
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-- Misc Constants
constant CMD_BASE_WIDTH : integer := 40;
constant SG_BTT_WIDTH : integer := 7;
constant SG_ADDR_LSB : integer := 6;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST : integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Descriptor field bits
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_CMPLTD_BIT : integer := 31;
-- IOC Bit on descriptor update
-- Stored in LSB of TAG field then catinated on status word from primary
-- datamover (i.e. DESCTYPE & IOC & STATUS & Bytes Transferred).
constant DESC_IOC_TAG_BIT : integer := 32;
end axi_sg_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_sg_pkg is
-------------------------------------------------------------------------------
-- Boolean to Integer
-------------------------------------------------------------------------------
function bo2int ( value : boolean)
return integer is
variable value_int : integer;
begin
if(value)then
value_int := 1;
else
value_int := 0;
end if;
return value_int;
end function bo2int;
end package body axi_sg_pkg;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd | 6 | 57638 | -------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_reg_mux.vhd | 2 | 592416 | -------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/system/t8048_notri.vhd | 1 | 8377 | -------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
-- 8048 toplevel without tri-states
--
-- $Id: t8048_notri.vhd,v 1.7 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8048_notri is
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic
);
end t8048_notri;
library ieee;
use ieee.numeric_std.all;
use work.t48_core_comp_pack.t48_core;
use work.t48_core_comp_pack.t48_rom;
use work.t48_core_comp_pack.generic_ram_ena;
architecture struct of t8048_notri is
-- Address width of internal ROM
constant rom_addr_width_c : natural := 10;
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_addr_s : std_logic_vector(11 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
signal ea_s : std_logic;
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 7 downto 0);
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
reset_i => reset_n_i,
t0_i => t0_i,
t0_o => t0_o,
t0_dir_o => t0_dir_o,
int_n_i => int_n_i,
ea_i => ea_s,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o,
p1_i => p1_in_s,
p1_o => p1_out_s,
p1_low_imp_o => p1_low_imp_o,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
-----------------------------------------------------------------------------
-- Gate port 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
pass_ports: if gate_port_input_g = 0 generate
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
-----------------------------------------------------------------------------
-- Process ea
--
-- Purpose:
-- Detects access to external program memory.
-- Either by ea_i = '1' or when program memory address leaves address
-- range of internal ROM.
--
ea: process (ea_i,
pmem_addr_s)
begin
if ea_i = '1' then
-- Forced external access
ea_s <= '1';
elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then
-- Internal access
ea_s <= '0';
else
-- Access to program memory out of internal range
ea_s <= '1';
end if;
end process ea;
--
-----------------------------------------------------------------------------
rom_1k_b : t48_rom
port map (
clk_i => xtal_i,
rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0),
rom_data_o => pmem_data_s
);
ram_64_b : generic_ram_ena
generic map (
addr_width_g => 6,
data_width_g => 8
)
port map (
clk_i => xtal_i,
a_i => dmem_addr_s(5 downto 0),
we_i => dmem_we_s,
ena_i => vdd_s,
d_i => dmem_data_to_s,
d_o => dmem_data_from_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/21 01:02:16 arniml
-- replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
--
-- Revision 1.5 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.4 2005/11/01 21:38:48 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.3 2004/12/02 22:08:42 arniml
-- introduced generic gate_port_input_g
-- forces masking of P1 and P2 input bus
--
-- Revision 1.2 2004/12/01 23:08:08 arniml
-- update
--
-------------------------------------------------------------------------------
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tc_0_0/sim/tutorial_v_tc_0_0.vhd | 1 | 15469 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tc:6.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tc_v6_1;
USE v_tc_v6_1.v_tc;
ENTITY tutorial_v_tc_0_0 IS
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_v_tc_0_0;
ARCHITECTURE tutorial_v_tc_0_0_arch OF tutorial_v_tc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tc IS
GENERIC (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_INTERLACED : INTEGER;
C_GEN_HACTIVE_SIZE : INTEGER;
C_GEN_VACTIVE_SIZE : INTEGER;
C_GEN_CPARITY : INTEGER;
C_GEN_FIELDID_POLARITY : INTEGER;
C_GEN_VBLANK_POLARITY : INTEGER;
C_GEN_HBLANK_POLARITY : INTEGER;
C_GEN_VSYNC_POLARITY : INTEGER;
C_GEN_HSYNC_POLARITY : INTEGER;
C_GEN_AVIDEO_POLARITY : INTEGER;
C_GEN_ACHROMA_POLARITY : INTEGER;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_HFRAME_SIZE : INTEGER;
C_GEN_F0_VFRAME_SIZE : INTEGER;
C_GEN_F1_VFRAME_SIZE : INTEGER;
C_GEN_HSYNC_START : INTEGER;
C_GEN_HSYNC_END : INTEGER;
C_GEN_F0_VBLANK_HSTART : INTEGER;
C_GEN_F0_VBLANK_HEND : INTEGER;
C_GEN_F0_VSYNC_VSTART : INTEGER;
C_GEN_F0_VSYNC_VEND : INTEGER;
C_GEN_F0_VSYNC_HSTART : INTEGER;
C_GEN_F0_VSYNC_HEND : INTEGER;
C_GEN_F1_VBLANK_HSTART : INTEGER;
C_GEN_F1_VBLANK_HEND : INTEGER;
C_GEN_F1_VSYNC_VSTART : INTEGER;
C_GEN_F1_VSYNC_VEND : INTEGER;
C_GEN_F1_VSYNC_HSTART : INTEGER;
C_GEN_F1_VSYNC_HEND : INTEGER;
C_FSYNC_HSTART0 : INTEGER;
C_FSYNC_VSTART0 : INTEGER;
C_FSYNC_HSTART1 : INTEGER;
C_FSYNC_VSTART1 : INTEGER;
C_FSYNC_HSTART2 : INTEGER;
C_FSYNC_VSTART2 : INTEGER;
C_FSYNC_HSTART3 : INTEGER;
C_FSYNC_VSTART3 : INTEGER;
C_FSYNC_HSTART4 : INTEGER;
C_FSYNC_VSTART4 : INTEGER;
C_FSYNC_HSTART5 : INTEGER;
C_FSYNC_VSTART5 : INTEGER;
C_FSYNC_HSTART6 : INTEGER;
C_FSYNC_VSTART6 : INTEGER;
C_FSYNC_HSTART7 : INTEGER;
C_FSYNC_VSTART7 : INTEGER;
C_FSYNC_HSTART8 : INTEGER;
C_FSYNC_VSTART8 : INTEGER;
C_FSYNC_HSTART9 : INTEGER;
C_FSYNC_VSTART9 : INTEGER;
C_FSYNC_HSTART10 : INTEGER;
C_FSYNC_VSTART10 : INTEGER;
C_FSYNC_HSTART11 : INTEGER;
C_FSYNC_VSTART11 : INTEGER;
C_FSYNC_HSTART12 : INTEGER;
C_FSYNC_VSTART12 : INTEGER;
C_FSYNC_HSTART13 : INTEGER;
C_FSYNC_VSTART13 : INTEGER;
C_FSYNC_HSTART14 : INTEGER;
C_FSYNC_VSTART14 : INTEGER;
C_FSYNC_HSTART15 : INTEGER;
C_FSYNC_VSTART15 : INTEGER;
C_MAX_PIXELS : INTEGER;
C_MAX_LINES : INTEGER;
C_NUM_FSYNCS : INTEGER;
C_INTERLACE_EN : INTEGER;
C_GEN_AUTO_SWITCH : INTEGER;
C_DETECT_EN : INTEGER;
C_SYNC_EN : INTEGER;
C_GENERATE_EN : INTEGER;
C_DET_HSYNC_EN : INTEGER;
C_DET_VSYNC_EN : INTEGER;
C_DET_HBLANK_EN : INTEGER;
C_DET_VBLANK_EN : INTEGER;
C_DET_AVIDEO_EN : INTEGER;
C_DET_ACHROMA_EN : INTEGER;
C_GEN_HSYNC_EN : INTEGER;
C_GEN_VSYNC_EN : INTEGER;
C_GEN_HBLANK_EN : INTEGER;
C_GEN_VBLANK_EN : INTEGER;
C_GEN_AVIDEO_EN : INTEGER;
C_GEN_ACHROMA_EN : INTEGER;
C_GEN_FIELDID_EN : INTEGER;
C_DET_FIELDID_EN : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
det_clken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
field_id_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC;
active_chroma_in : IN STD_LOGIC;
field_id_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
active_chroma_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT v_tc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF hsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF hblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK";
ATTRIBUTE X_INTERFACE_INFO OF vsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK";
ATTRIBUTE X_INTERFACE_INFO OF active_video_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT";
BEGIN
U0 : v_tc
GENERIC MAP (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_INTERLACED => 0,
C_GEN_HACTIVE_SIZE => 1920,
C_GEN_VACTIVE_SIZE => 1080,
C_GEN_CPARITY => 0,
C_GEN_FIELDID_POLARITY => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VIDEO_FORMAT => 2,
C_GEN_HFRAME_SIZE => 2200,
C_GEN_F0_VFRAME_SIZE => 1125,
C_GEN_F1_VFRAME_SIZE => 1125,
C_GEN_HSYNC_START => 2008,
C_GEN_HSYNC_END => 2052,
C_GEN_F0_VBLANK_HSTART => 1920,
C_GEN_F0_VBLANK_HEND => 1920,
C_GEN_F0_VSYNC_VSTART => 1083,
C_GEN_F0_VSYNC_VEND => 1088,
C_GEN_F0_VSYNC_HSTART => 1920,
C_GEN_F0_VSYNC_HEND => 1920,
C_GEN_F1_VBLANK_HSTART => 1920,
C_GEN_F1_VBLANK_HEND => 1920,
C_GEN_F1_VSYNC_VSTART => 1083,
C_GEN_F1_VSYNC_VEND => 1088,
C_GEN_F1_VSYNC_HSTART => 1920,
C_GEN_F1_VSYNC_HEND => 1920,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_INTERLACE_EN => 0,
C_GEN_AUTO_SWITCH => 0,
C_DETECT_EN => 0,
C_SYNC_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_FIELDID_EN => 0,
C_DET_FIELDID_EN => 0
)
PORT MAP (
clk => clk,
clken => clken,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
det_clken => '1',
gen_clken => gen_clken,
field_id_in => '0',
hsync_in => '0',
hblank_in => '0',
vsync_in => '0',
vblank_in => '0',
active_video_in => '0',
active_chroma_in => '0',
hsync_out => hsync_out,
hblank_out => hblank_out,
vsync_out => vsync_out,
vblank_out => vblank_out,
active_video_out => active_video_out,
resetn => resetn,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
fsync_in => fsync_in,
fsync_out => fsync_out
);
END tutorial_v_tc_0_0_arch;
| gpl-2.0 |
Caneda/Caneda | libraries/hdl/vhdl/synchronous/process.vhd | 1 | 224 | process (CLK, RST)
begin
if(RST = '1') then
-- Reset asignments
...
elsif(CLK'event and CLK = '1') then
-- Concurrent asignments
...
end if;
-- Concurrent asignments
...
end process;
| gpl-2.0 |
nulldozer/purisc | Compute_Group/MAGIC_clocked/HAZARD_RESOLVE.vhd | 2 | 2329 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HAZARD_RESOLVE is
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture resolve of HAZARD_RESOLVE is
signal data_present : std_logic;
signal buffer_output : std_logic_vector(31 downto 0);
signal data_buffer : std_logic_vector(31 downto 0);
signal hazard_rising_edge : std_logic;
signal hazard_artifial_delay : std_logic;
begin
process (CLK, RESET_n) begin
if (RESET_n = '0') then
hazard_artifial_delay <= '0';
elsif (rising_edge(CLK)) then
hazard_artifial_delay <= hazard_advanced;
end if;
end process;
--edge capture
hazard_rising_edge <= hazard_advanced and (hazard_advanced xor hazard);
data_present <= select_signal(15) or select_signal(14) or select_signal(13) or select_signal(12) or
select_signal(11) or select_signal(10) or select_signal(9) or select_signal(8) or
select_signal(7) or select_signal(6) or select_signal(5) or select_signal(4) or
select_signal(3) or select_signal(2) or select_signal(1) or select_signal(0);
buffering : process (CLK, RESET_n, hazard, data_present, data) begin
if (RESET_n = '0') then
buffer_output <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (data_present = '1' and hazard = '1') then
buffer_output <= data;
end if;
end if;
end process;
hazard_detect : process (hazard, data, data_buffer, RESET_n, buffer_output, data_present, CLK) begin
if (RESET_n = '0') then
data_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK))then --was on rising edge hazard
if (hazard_rising_edge = '1') then --this if never existed
if (data_present = '1') then
data_buffer <= data;
else
data_buffer <= buffer_output;
end if;
end if;
end if;
if (hazard = '0')then
if (data_present = '1') then
data_out <= data;
else
data_out <= buffer_output;
end if;
else
data_out <= data_buffer;
end if;
end process;
end; | gpl-2.0 |
freecores/t48 | rtl/vhdl/system/wb_master-c.vhd | 1 | 457 | -------------------------------------------------------------------------------
--
-- The Wishbone master module.
--
-- $Id: wb_master-c.vhd,v 1.2 2005-06-11 10:16:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_wb_master_rtl_c0 of t48_wb_master is
for rtl
end for;
end t48_wb_master_rtl_c0;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_greycoder.vhd | 2 | 10742 | -------------------------------------------------------------------------------
-- axi_vdma_greycoder
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_greycoder.vhd
--
-- Description: This entity encompasses the grey encoder/decoder for Gen-
-- Lock operation.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_greycoder is
generic(
C_DWIDTH : integer range 1 to 16 := 1
);
port (
-- Grey Encode --
binary_in : in std_logic_vector(C_DWIDTH-1 downto 0) ; --
grey_out : out std_logic_vector(C_DWIDTH-1 downto 0) ; --
--
-- Grey Decode --
grey_in : in std_logic_vector(C_DWIDTH-1 downto 0) ; --
binary_out : out std_logic_vector(C_DWIDTH-1 downto 0) --
);
end axi_vdma_greycoder;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_greycoder is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal binary_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Binary to Grey Encoder
-- Example: DWIDTH = 4
-- Grey(3) = Binary(3)
-- Grey(2) = Binary(3) xor Binary(2)
-- Grey(1) = Binary(2) xor Binary(1)
-- Grey(0) = Binary(1) xor Binary(0)
-------------------------------------------------------------------------------
GREY_ENCODE : process(binary_in)
begin
-- MSB Grey Code Bit = MSB Binary Bit
grey_out(C_DWIDTH - 1) <= binary_in(C_DWIDTH - 1);
for i in C_DWIDTH - 2 downto 0 loop
grey_out(i) <= binary_in(i+1) xor binary_in(i);
end loop;
end process GREY_ENCODE;
-------------------------------------------------------------------------------
-- Grey to Binary Decoder
-- Example: DWIDTH = 4
-- Binary(3) = Grey(3)
-- Binary(2) = Grey(3) xor Grey(2)
-- Binary(1) = Grey(3) xor Grey(2) xor Grey(1)
-- Binary(0) = Grey(3) xor Grey(2) xor Grey(1) xor Grey(0)
-------------------------------------------------------------------------------
GREY_DECODE : process(grey_in)
variable binary_acc : std_logic_vector(C_DWIDTH - 1 downto 0) := (others => '0');
begin
-- Default to zero
binary_acc := (others => '0');
binary_out_i <= (others => '0');
-- MSB Binary Bit = MSB Grey Bit
binary_acc(C_DWIDTH - 1) := grey_in(C_DWIDTH - 1);
for i in C_DWIDTH - 2 downto 0 loop
-- Start with MSB of Grey In
binary_acc(i) := grey_in(C_DWIDTH - 1);
-- Then xor with each bit down to the bit of interest
for j in C_DWIDTH - 2 downto i loop
binary_acc(i) := binary_acc(i) xor grey_in(j);
end loop;
end loop;
binary_out_i <= binary_acc;
end process GREY_DECODE;
binary_out <= binary_out_i;
end implementation;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_noqueue.vhd | 1 | 24236 | -------------------------------------------------------------------------------
-- axi_sg_updt_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active,
s_axis_updtptr_tvalid,
s_axis_updtsts_tvalid,
s_axis_updtsts_tlast,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
write_curdesc_lsb <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= s_axis_updtsts_tvalid;
if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1'
and s_axis_updtsts_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not s_axis_updtsts_tvalid;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
| gpl-2.0 |
nulldozer/purisc | Compute_Group/MAGIC_clocked/ROUTE_SIGNAL.vhd | 2 | 4342 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE_SIGNAL is
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture signal_routing of ROUTE_SIGNAL is
component tristate_32
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end component;
component HAZARD_RESOLVE
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
signal data : std_logic_vector(31 downto 0);
begin
a_0 : tristate_32 PORT MAP (
my_in => ram_0_out_a,
sel => select_vector(15),
my_out => data
);
b_0 : tristate_32 PORT MAP (
my_in => ram_0_out_b,
sel => select_vector(14),
my_out => data
);
a_1 : tristate_32 PORT MAP (
my_in => ram_1_out_a,
sel => select_vector(13),
my_out => data
);
b_1 : tristate_32 PORT MAP (
my_in => ram_1_out_b,
sel => select_vector(12),
my_out => data
);
a_2 : tristate_32 PORT MAP (
my_in => ram_2_out_a,
sel => select_vector(11),
my_out => data
);
b_2 : tristate_32 PORT MAP (
my_in => ram_2_out_b,
sel => select_vector(10),
my_out => data
);
a_3 : tristate_32 PORT MAP (
my_in => ram_3_out_a,
sel => select_vector(9),
my_out => data
);
b_3 : tristate_32 PORT MAP (
my_in => ram_3_out_b,
sel => select_vector(8),
my_out => data
);
a_4 : tristate_32 PORT MAP (
my_in => ram_4_out_a,
sel => select_vector(7),
my_out => data
);
b_4 : tristate_32 PORT MAP (
my_in => ram_4_out_b,
sel => select_vector(6),
my_out => data
);
a_5 : tristate_32 PORT MAP (
my_in => ram_5_out_a,
sel => select_vector(5),
my_out => data
);
b_5 : tristate_32 PORT MAP (
my_in => ram_5_out_b,
sel => select_vector(4),
my_out => data
);
a_6 : tristate_32 PORT MAP (
my_in => ram_6_out_a,
sel => select_vector(3),
my_out => data
);
b_6 : tristate_32 PORT MAP (
my_in => ram_6_out_b,
sel => select_vector(2),
my_out => data
);
a_7 : tristate_32 PORT MAP (
my_in => ram_7_out_a,
sel => select_vector(1),
my_out => data
);
b_7 : tristate_32 PORT MAP (
my_in => ram_7_out_b,
sel => select_vector(0),
my_out => data
);
resolve_hazard : HAZARD_RESOLVE PORT MAP (
select_signal => select_vector,
hazard => hazard,
data => data,
CLK => CLK,
RESET_n => RESET_n,
hazard_advanced => hazard_advanced,
data_out => OUTPUT
);
end; | gpl-2.0 |
nulldozer/purisc | Compute_Group/LOAD_BALANCER.vhd | 2 | 3462 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end;
architecture balancer of LOAD_BALANCER is
begin
process (CORE_ID, ADDRESS_A_C0, ADDRESS_B_C0, ADDRESS_C_C0, ADDRESS_0_C0, ADDRESS_1_C0, ADDRESS_W_C0,
ADDRESS_A_C1, ADDRESS_B_C1, ADDRESS_C_C1, ADDRESS_0_C1, ADDRESS_1_C1, ADDRESS_W_C1,
DATA_TO_W_C0, DATA_TO_W_C1, W_EN_C0, W_EN_C1, IO_ENABLE, ADDRESS_IO, DATA_IO, global_enable) begin
if (CORE_ID = '0') then
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C0;
ADDRESS_B_MAG <= ADDRESS_B_C0;
ADDRESS_C_MAG <= ADDRESS_C_C0;
ADDRESS_0_MAG <= ADDRESS_0_C0;
ADDRESS_1_MAG <= ADDRESS_1_C0;
ADDRESS_W_MAG <= ADDRESS_W_C0;
DATA_TO_W_MAG <= DATA_TO_W_C0;
W_EN_MAG <= W_EN_C0;
end if;
else
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C1;
ADDRESS_B_MAG <= ADDRESS_B_C1;
ADDRESS_C_MAG <= ADDRESS_C_C1;
ADDRESS_0_MAG <= ADDRESS_0_C1;
ADDRESS_1_MAG <= ADDRESS_1_C1;
ADDRESS_W_MAG <= ADDRESS_W_C1;
DATA_TO_W_MAG <= DATA_TO_W_C1;
W_EN_MAG <= W_EN_C1;
end if;
end if;
end process;
end; | gpl-2.0 |
Caneda/Caneda | libraries/hdl/vhdl/testbench.vhd | 1 | 905 | -- name is the name of the component to test
-- MODE and TYPE must be those defined in the component entity
ENTITY testbenchEntity IS
END testbenchEntity;
ARCHITECTURE behav OF testbenchEntity IS
-- Declaration of the component
COMPONENT name
PORT(A: MODE TYPE;
B: MODE TYPE;
...
);
END COMPONENT;
signal sA: TYPE;
signal sB: TYPE;
...
BEGIN
-- Component instantiation
u0: name PORT MAP(A => sA,
B => sB,
...
);
-- Clock definition
clk <= not clk after 5 ns;
-- Set the inputs
process
begin
wait for 1 ns;
sA <= '1';
sB <= '0';
...
wait for 1 ns;
sA <= '1';
sB <= '1';
...
-- Wait forever = finish the simulation
wait;
end process;
END behav;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/avnet/zed_hdmi_out_v2_0/401115cc/hdl/vhdl/zed_hdmi_out.vhd | 1 | 9391 | ------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: May 19, 2012
-- Design Name: ZedBoard HDMI Output
-- Module Name: zed_hdmi_out.vhd
-- Project Name: ZedBoard HDMI Output
-- Target Devices: Zynq-7000
--
-- Tool versions: ISE 14.3
--
-- Description: ZedBoard HDMI output interface.
--
-- Dependencies:
--
-- Revision: May 19, 2012: 1.02 Initial version
-- Dec 21, 2012: 2.01 Remove XSVI bus interface
-- Remove xsvi_ prefixes to video_
-- Rename active_video to de
-- Change IP_GROUP to FMC-IMAGEON
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity zed_hdmi_out is
Generic
(
C_DATA_WIDTH : integer := 16;
C_FAMILY : string := "virtex6"
);
Port
(
clk : in std_logic;
reset : in std_logic;
-- Audio Input Port
audio_spdif : in std_logic;
-- Video Ports
video_vsync : in std_logic;
video_hsync : in std_logic;
video_de : in std_logic;
video_data : in std_logic_vector((C_DATA_WIDTH-1) downto 0);
-- I/O pins
io_hdmio_spdif : out std_logic;
io_hdmio_video : out std_logic_vector(15 downto 0);
io_hdmio_vsync : out std_logic;
io_hdmio_hsync : out std_logic;
io_hdmio_de : out std_logic;
io_hdmio_clk : out std_logic
);
end zed_hdmi_out;
architecture rtl of zed_hdmi_out is
signal clk_n : std_logic;
signal net0 : std_logic;
signal net1 : std_logic;
signal oe : std_logic;
signal oe_n : std_logic;
--
-- Audio Port
--
signal spdif_r : std_logic;
--
-- Video Port
--
signal video_r : std_logic_vector(15 downto 0);
signal vsync_r : std_logic;
signal hsync_r : std_logic;
signal de_r : std_logic;
--
-- IOB Registers
--
signal hdmi_spdif_o : std_logic;
signal hdmi_video_o : std_logic_vector(15 downto 0);
signal hdmi_vsync_o : std_logic;
signal hdmi_hsync_o : std_logic;
signal hdmi_de_o : std_logic;
signal hdmi_clk_o : std_logic;
signal hdmi_spdif_t : std_logic;
signal hdmi_video_t : std_logic_vector(15 downto 0);
signal hdmi_vsync_t : std_logic;
signal hdmi_hsync_t : std_logic;
signal hdmi_de_t : std_logic;
signal hdmi_clk_t : std_logic;
attribute IOB : string;
attribute IOB of hdmi_spdif_o : signal is "TRUE";
attribute IOB of hdmi_video_o : signal is "TRUE";
attribute IOB of hdmi_vsync_o : signal is "TRUE";
attribute IOB of hdmi_hsync_o : signal is "TRUE";
attribute IOB of hdmi_de_o : signal is "TRUE";
attribute IOB of hdmi_clk_o : signal is "TRUE";
begin
clk_n <= not clk;
oe <= '1';
oe_n <= not oe;
net0 <= '0';
net1 <= '1';
--
-- Audio Port
--
spdif_r <= audio_spdif;
--
-- Video Ports
--
VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate
video_ports_16bit_iregs_l : process (clk)
begin
if Rising_Edge(clk) then
video_r <= video_data(15 downto 0);
vsync_r <= video_vsync;
hsync_r <= video_hsync;
de_r <= video_de;
end if;
end process;
end generate VIDEO_PORTS_16BIT_GEN;
--
-- IOB Registers
--
io_oregs_l : process (clk)
begin
if Rising_Edge(clk) then
hdmi_spdif_o <= spdif_r;
hdmi_video_o <= video_r;
hdmi_vsync_o <= vsync_r;
hdmi_hsync_o <= hsync_r;
hdmi_de_o <= de_r;
--
hdmi_spdif_t <= oe_n;
hdmi_video_t <= (others => oe_n);
hdmi_vsync_t <= oe_n;
hdmi_hsync_t <= oe_n;
hdmi_de_t <= oe_n;
end if;
end process;
S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S3ADSP_GEN;
S6_GEN : if (C_FAMILY = "spartan6") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6" or C_FAMILY = "zynq" or C_FAMILY = "kintex7" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
ODDR_hdmi_clk_o : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C => clk,
CE => net1,
D1 => net0,
D2 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C => clk,
CE => net1,
D1 => oe_n,
D2 => oe_n,
R => net0,
S => net0);
end generate V6_GEN;
--
-- Tri-stateable outputs
-- Can be used to disable outputs to FMC connector
-- until FMC module is correctly identified.
--
OBUFT_hdmio_spdif : OBUFT
port map (
O => io_hdmio_spdif,
I => hdmi_spdif_o,
T => hdmi_spdif_t
);
IO1: for I in 0 to 15 generate
OBUFT_hdmio_video : OBUFT
port map (
O => io_hdmio_video(I),
I => hdmi_video_o(I),
T => hdmi_video_t(I)
);
end generate IO1;
OBUFT_hdmio_vsync : OBUFT
port map (
O => io_hdmio_vsync,
I => hdmi_vsync_o,
T => hdmi_vsync_t
);
OBUFT_hdmio_hsync : OBUFT
port map (
O => io_hdmio_hsync,
I => hdmi_hsync_o,
T => hdmi_hsync_t
);
OBUFT_hdmio_de : OBUFT
port map (
O => io_hdmio_de,
I => hdmi_de_o,
T => hdmi_de_t
);
OBUFT_hdmio_clk : OBUFT
port map (
O => io_hdmio_clk,
I => hdmi_clk_o,
T => hdmi_clk_t
);
end rtl;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/p1-c.vhd | 1 | 387 | -------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_p1_rtl_c0 of t48_p1 is
for rtl
end for;
end t48_p1_rtl_c0;
| gpl-2.0 |
purisc-group/purisc | Compute_Group/BIST_core.vhd | 2 | 3082 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BIST_core is
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end;
architecture BIST of BIST_core is
signal start_address : std_logic_vector(31 downto 0);
signal error_a : std_logic;
signal error_b : std_logic;
signal error_c : std_logic;
signal error_0 : std_logic;
signal error_1 : std_logic;
signal address_a : std_logic_vector(31 downto 0);
signal address_b : std_logic_vector(31 downto 0);
signal address_c : std_logic_vector(31 downto 0);
signal address_0 : std_logic_vector(31 downto 0);
signal address_1 : std_logic_vector(31 downto 0);
begin
process (start_address, id) begin
if (id(0) = '1') then
address_a <= start_address;
address_b <= std_logic_vector(unsigned(start_address) + 1);
address_c <= std_logic_vector(unsigned(start_address) + 2);
address_0 <= std_logic_vector(unsigned(start_address) + 3);
address_1 <= std_logic_vector(unsigned(start_address) + 4);
else
address_a <= start_address;
address_b <= std_logic_vector(unsigned(start_address) + 1);
address_c <= std_logic_vector(unsigned(start_address) + 2);
address_0 <= std_logic_vector(unsigned(start_address) + 3);
address_1 <= std_logic_vector(unsigned(start_address) + 4);
end if;
end process;
w_addr <= "00000000000000000000000000000000";
w_data <= "00000000000000000000000000000000";
we <= '0';
r_addr_a <= address_a;
r_addr_b <= address_b;
r_addr_c <= address_c;
r_addr_0 <= address_0;
r_addr_1 <= address_1;
process (reset_n, clk) begin
if (reset_n = '0') then
if (id(0) = '0') then
start_address <= "00000000000000000000000000010000";
else
start_address <= "00000000000000000000000000010000";
end if;
elsif (rising_edge(clk)) then
if (stall = '0') then
start_address <= std_logic_vector(unsigned(start_address) + 5);
end if;
end if;
end process;
process (reset_n, clk) begin
if (reset_n = '0') then
error_a <= '0';
error_b <= '0';
error_c <= '0';
error_0 <= '0';
error_1 <= '0';
elsif(rising_edge(clk)) then
if (stall = '0') then
if (r_data_a = address_a) then
error_a <= '0';
else
error_a <= '1';
end if;
if (r_data_b = address_b) then
error_b <= '0';
else
error_b <= '1';
end if;
if (r_data_c = address_c) then
error_c <= '0';
else
error_c <= '1';
end if;
if (r_data_a = address_a) then
error_0 <= '0';
else
error_0 <= '1';
end if;
if (r_data_a = address_a) then
error_1 <= '0';
else
error_1 <= '1';
end if;
end if;
end if;
end process;
end; | gpl-2.0 |
huukit/logicsynth | excercises/tb/tb_synthesizer.vhd | 1 | 4409 | -------------------------------------------------------------------------------
-- Title : Simple testbench for the audio synthesizer.
-- Note! No automatic checking!
-- You must "manually" check the waveforms, which is not nice.
-- Project :
-------------------------------------------------------------------------------
-- File : tb_synthesizer.vhd
-- Author : Erno Salminen <[email protected]>
-- Company :
-- Last update: 2009/02/24
-- Platform :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009/02/12 1.0 ege Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity tb_synthesizer is
end tb_synthesizer;
architecture structural of tb_synthesizer is
component synthesizer
generic (
clk_freq_g : INTEGER;
sample_rate_g : INTEGER;
data_width_g : INTEGER;
n_keys_g : INTEGER);
port (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
keys_in : IN STD_LOGIC_VECTOR( n_keys_g-1 DOWNTO 0 );
aud_bclk_out : OUT STD_LOGIC;
aud_lrclk_out : OUT STD_LOGIC;
aud_data_out : OUT STD_LOGIC);
end component;
component audio_codec_model
generic (
data_width_g : integer);
port (
rst_n : in std_logic;
aud_bclk_in : in std_logic;
aud_lrclk_in : in std_logic;
aud_data_in : in std_logic;
value_left_out : out std_logic_vector(data_width_g-1 downto 0);
value_right_out : out std_logic_vector(data_width_g-1 downto 0));
end component;
constant clk_freq_c : integer := 20000000;
constant sample_rate_c : integer := 48000;
constant data_width_c : integer := 16;
constant n_keys_c : integer := 4;
constant clk_period_c : time := 50 ns; -- i.e. 20 MHz
signal clk : std_logic := '0'; -- global clock
signal rst_n : std_logic := '0'; -- low active reset
signal keys_tb_synth : std_logic_vector ( n_keys_c-1 downto 0);
signal aud_bclk_synth_model : std_logic;
signal aud_lrclk_synth_model : std_logic;
signal aud_data_synth_model : std_logic;
signal value_left_model_tb : std_logic_vector ( data_width_c-1 downto 0);
signal value_right_model_tb : std_logic_vector ( data_width_c-1 downto 0);
signal counter_r : integer;
constant button_period_c : integer := 2**data_width_c * 10;
begin -- structural
clk <= not clk after clk_period_c/2; -- kellon generointi
rst_n <= '1' after 4*clk_period_c; -- reset pois neljän kellojakson jälkeen
i_duv_synth: synthesizer
generic map (
clk_freq_g => clk_freq_c,
sample_rate_g => sample_rate_c,
data_width_g => data_width_c,
n_keys_g => n_keys_c
)
port map (
clk => clk,
rst_n => rst_n,
keys_in => keys_tb_synth,
aud_bclk_out => aud_bclk_synth_model,
aud_lrclk_out => aud_lrclk_synth_model,
aud_data_out => aud_data_synth_model
);
i_acm: audio_codec_model
generic map (
data_width_g => data_width_c)
port map (
rst_n => rst_n,
aud_bclk_in => aud_bclk_synth_model,
aud_lrclk_in => aud_lrclk_synth_model,
aud_data_in => aud_data_synth_model,
value_left_out => value_left_model_tb,
value_right_out => value_right_model_tb
);
press_buttons: process (clk, rst_n)
begin -- process press_buttons
if rst_n = '0' then -- asynchronous reset (active low)
counter_r <= 0;
keys_tb_synth <= (others => '1');
elsif clk'event and clk = '1' then -- rising clock edge
if counter_r = button_period_c then
counter_r <= 0;
-- keys_tb_synth <= not std_logic_vector (unsigned(not keys_tb_synth)+1);
keys_tb_synth <= std_logic_vector (unsigned(keys_tb_synth)-1);
else
counter_r <= counter_r + 1;
end if;
end if;
end process press_buttons;
end structural;
| gpl-2.0 |
lizh06/ctags | Units/review-needed.r/test.vhd.t/input.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
huukit/logicsynth | excercises/vhd/ripple_carry_adder.vhd | 1 | 2250 | -------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 02
-- Project :
-------------------------------------------------------------------------------
-- File : ripple_carry_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 28.10.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Second excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 28.10.2015 1.0 tuhu, nikulaj Created
-------------------------------------------------------------------------------
-- TODO: Add library called ieee here
-- And use package called std_logic_1164 from the library
library ieee;
use ieee.std_logic_1164.all;
-- TODO: Declare entity here
-- Name: ripple_carry_adder
-- No generics yet
-- Ports: a_in 3-bit std_logic_vector
-- b_in 3-bit std_logic_vector
-- s_out 4-bit std_logic_vector
entity ripple_carry_adder is
PORT (
a_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end ripple_carry_adder;
-------------------------------------------------------------------------------
-- Architecture called 'gate' is already defined. Just fill it.
-- Architecture defines an implementation for an entity
architecture gate of ripple_carry_adder is
-- TODO: Add your internal signal declarations here
SIGNAL carry_ha : STD_LOGIC;
SIGNAL carry_fa : STD_LOGIC;
SIGNAL C, D, E, F, G, H : STD_LOGIC;
begin -- gate
-- Half adder.
s_out(0) <= a_in(0) XOR b_in(0);
carry_ha <= a_in(0) AND b_in(0);
-- Full adder 1.
C <= a_in(1) XOR b_in(1);
D <= carry_ha AND C;
E <= a_in(1) AND b_in(1);
s_out(1) <= carry_ha XOR C;
carry_fa <= D OR E;
-- Full adder 2.
F <= a_in(2) XOR b_in(2);
G <= carry_fa AND F;
H <= a_in(2) AND b_in(2);
s_out(2) <= carry_fa XOR F;
s_out(3) <= G OR H;
end gate;
| gpl-2.0 |
purisc-group/purisc | Compute_Group/Compute_Group.vhd | 2 | 17780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Compute_Group is
PORT (
ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
DATA_TO_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
GLOBAL_EN : OUT STD_LOGIC;
IDENT_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
DATA_OUT_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
STALL_GLOB : IN STD_LOGIC
);
end;
architecture cg of Compute_Group is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
HAZ_GLOB : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end component;
component LOAD_BALANCER
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end component;
component purisc_core
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end component;
component BIST_core
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end component;
signal address_a_sig : std_logic_vector(31 downto 0);
signal address_b_sig : std_logic_vector(31 downto 0);
signal address_c_sig : std_logic_vector(31 downto 0);
signal address_0_sig : std_logic_vector(31 downto 0);
signal address_1_sig : std_logic_vector(31 downto 0);
signal address_w_sig : std_logic_vector(31 downto 0);
signal data_to_w_sig : std_logic_vector(31 downto 0);
signal w_en_sig : std_logic;
signal w_en_local : std_logic;
signal w_en_global : std_logic;
signal address_a_sig_c0 : std_logic_vector(31 downto 0);
signal address_b_sig_c0 : std_logic_vector(31 downto 0);
signal address_c_sig_c0 : std_logic_vector(31 downto 0);
signal address_0_sig_c0 : std_logic_vector(31 downto 0);
signal address_1_sig_c0 : std_logic_vector(31 downto 0);
signal address_w_sig_c0 : std_logic_vector(31 downto 0);
signal data_to_w_sig_c0 : std_logic_vector(31 downto 0);
signal w_en_sig_c0 : std_logic;
signal address_a_sig_c1 : std_logic_vector(31 downto 0);
signal address_b_sig_c1 : std_logic_vector(31 downto 0);
signal address_c_sig_c1 : std_logic_vector(31 downto 0);
signal address_0_sig_c1 : std_logic_vector(31 downto 0);
signal address_1_sig_c1 : std_logic_vector(31 downto 0);
signal address_w_sig_c1 : std_logic_vector(31 downto 0);
signal data_to_w_sig_c1 : std_logic_vector(31 downto 0);
signal w_en_sig_c1 : std_logic;
signal data_a : std_logic_vector(31 downto 0);
signal data_b : std_logic_vector(31 downto 0);
signal data_c : std_logic_vector(31 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal data_a_final : std_logic_vector(31 downto 0);
signal data_b_final : std_logic_vector(31 downto 0);
signal data_c_final : std_logic_vector(31 downto 0);
signal data_0_final : std_logic_vector(31 downto 0);
signal data_1_final : std_logic_vector(31 downto 0);
signal data_a_c0_buff : std_logic_vector(31 downto 0);
signal data_b_c0_buff : std_logic_vector(31 downto 0);
signal data_c_c0_buff : std_logic_vector(31 downto 0);
signal data_0_c0_buff : std_logic_vector(31 downto 0);
signal data_1_c0_buff : std_logic_vector(31 downto 0);
signal data_a_c1 : std_logic_vector(31 downto 0);
signal data_b_c1 : std_logic_vector(31 downto 0);
signal data_c_c1 : std_logic_vector(31 downto 0);
signal data_0_c1 : std_logic_vector(31 downto 0);
signal data_1_c1 : std_logic_vector(31 downto 0);
signal data_a_c1_buff : std_logic_vector(31 downto 0);
signal data_b_c1_buff : std_logic_vector(31 downto 0);
signal data_c_c1_buff : std_logic_vector(31 downto 0);
signal data_0_c1_buff : std_logic_vector(31 downto 0);
signal data_1_c1_buff : std_logic_vector(31 downto 0);
signal stall_c0 : std_logic;
signal stall_c1 : std_logic;
signal stall_c0_io : std_logic;
signal stall_c1_io : std_logic;
signal core_id : std_logic;
signal io_buffer_en : std_logic;
signal flags_0 : std_logic_vector(2 downto 0);
signal flags_1 : std_logic_vector(2 downto 0);
signal global_enable : std_logic_vector(5 downto 0);
signal global_enable_delayed : std_logic_vector(5 downto 0);
signal global_enable_delayed_2 : std_logic_vector(5 downto 0);
signal global_data_buffer_flag_delay : std_logic;
signal global_data_buffer_flag : std_logic;
signal global_buffer_enable : std_logic;
signal global_data_feed_a : std_logic_vector(31 downto 0);
signal global_data_feed_b : std_logic_vector(31 downto 0);
signal global_data_feed_c : std_logic_vector(31 downto 0);
signal global_data_feed_0 : std_logic_vector(31 downto 0);
signal global_data_feed_1 : std_logic_vector(31 downto 0);
signal global_data_buffer_a : std_logic_vector(31 downto 0);
signal global_data_buffer_b : std_logic_vector(31 downto 0);
signal global_data_buffer_c : std_logic_vector(31 downto 0);
signal global_data_buffer_0 : std_logic_vector(31 downto 0);
signal global_data_buffer_1 : std_logic_vector(31 downto 0);
signal hold_local : std_logic;
signal hazard : std_logic;
signal override_global : std_logic;
signal startup_hold_1 : std_logic;
signal startup_hold_2 : std_logic;
signal startup_hold_3 : std_logic;
signal startup_hold_4 : std_logic;
signal startup_hold_5 : std_logic;
signal FUCK : std_logic;
signal dick : std_logic;
begin
core_0 : purisc_core PORT MAP(
clk => CLK,
reset_n => RESET_n,
r_addr_a => address_a_sig_c0,
r_addr_b => address_b_sig_c0,
r_addr_c => address_c_sig_c0,
r_addr_0 => address_0_sig_c0,
r_addr_1 => address_1_sig_c0,
w_addr => address_w_sig_c0,
we => w_en_sig_c0,
w_data => data_to_w_sig_c0,
stall => stall_c0_io,
id => flags_0,
r_data_a => data_a_final,
r_data_b => data_b_final,
r_data_c => data_c_final,
r_data_0 => data_0_final,
r_data_1 => data_1_final
);
core_1 : purisc_core PORT MAP(
clk => CLK,
reset_n => RESET_n,
r_addr_a => address_a_sig_c1,
r_addr_b => address_b_sig_c1,
r_addr_c => address_c_sig_c1,
r_addr_0 => address_0_sig_c1,
r_addr_1 => address_1_sig_c1,
w_addr => address_w_sig_c1,
we => w_en_sig_c1,
w_data => data_to_w_sig_c1,
stall => stall_c1_io,
id => flags_1,
r_data_a => data_a_final,
r_data_b => data_b_final,
r_data_c => data_c_final,
r_data_0 => data_0_final,
r_data_1 => data_1_final
);
cache : MAGIC PORT MAP (
ADDRESS_A => address_a_sig,
ADDRESS_B => address_b_sig,
ADDRESS_C => address_c_sig,
ADDRESS_0 => address_0_sig,
ADDRESS_1 => address_1_sig,
ADDRESS_W => address_w_sig,
DATA_TO_W => data_to_w_sig,
W_EN => w_en_local,
CLK => CLK,
RESET_n => RESET_n,
HAZ_GLOB => STALL_GLOB,
DATA_OUT_A => data_a,
DATA_OUT_B => data_b,
DATA_OUT_C => data_c,
DATA_OUT_0 => data_0,
DATA_OUT_1 => data_1,
C0_STALL => stall_c0,
C1_STALL => stall_c1,
CORE_IDENT => core_id,
IO_ENABLE => hold_local
);
balance : LOAD_BALANCER PORT MAP(
CORE_ID => core_id,
ADDRESS_A_C0 => address_a_sig_c0,
ADDRESS_B_C0 => address_b_sig_c0,
ADDRESS_C_C0 => address_c_sig_c0,
ADDRESS_0_C0 => address_0_sig_c0,
ADDRESS_1_C0 => address_1_sig_c0,
ADDRESS_W_C0 => address_w_sig_c0,
DATA_TO_W_C0 => data_to_w_sig_c0,
W_EN_C0 => w_en_sig_c0,
ADDRESS_A_C1 => address_a_sig_c1,
ADDRESS_B_C1 => address_b_sig_c1,
ADDRESS_C_C1 => address_c_sig_c1,
ADDRESS_0_C1 => address_0_sig_c1,
ADDRESS_1_C1 => address_1_sig_c1,
ADDRESS_W_C1 => address_w_sig_c1,
DATA_TO_W_C1 => data_to_w_sig_c1,
W_EN_C1 => w_en_sig_c1,
ADDRESS_IO => ADDRESS_IO,
DATA_IO => DATA_IO,
IO_ENABLE => IO_ENABLE,
global_enable => global_enable,
ADDRESS_A_MAG => address_a_sig,
ADDRESS_B_MAG => address_b_sig,
ADDRESS_C_MAG => address_c_sig,
ADDRESS_0_MAG => address_0_sig,
ADDRESS_1_MAG => address_1_sig,
ADDRESS_W_MAG => address_w_sig,
DATA_TO_W_MAG => data_to_w_sig,
W_EN_MAG => w_en_sig
);
process (CLK, RESET_n) begin
if (RESET_n = '0') then
startup_hold_1 <= '1';
startup_hold_2 <= '1';
startup_hold_3 <= '1';
startup_hold_4 <= '1';
startup_hold_5 <= '1';
elsif (rising_edge(CLK)) then
startup_hold_1 <= not RESET_n;
startup_hold_2 <= startup_hold_1;
startup_hold_3 <= startup_hold_2;
startup_hold_4 <= startup_hold_3;
startup_hold_5 <= startup_hold_4;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
override_global <= '1';
elsif (rising_edge(CLK)) then
if ((STALL_GLOB = '0') and (hazard = '1')) then
override_global <= '0';
else
override_global <= '1';
end if;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_enable_delayed <= "000000";
global_enable_delayed_2 <= "000000";
elsif (rising_edge(CLK)) then
global_enable_delayed_2 <= global_enable_delayed;
if ((stall_c0_io and stall_c1_io) = '0') then --OR STALL GLOBAL = 0
global_enable_delayed <= global_enable;
end if;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_data_buffer_flag_delay <= '0';
--FUCK <= '0';
elsif (rising_edge(CLK)) then
global_data_buffer_flag_delay <= global_data_buffer_flag;
--FUCK <= dick;
end if;
end process;
global_buffer_enable <= (global_data_buffer_flag_delay xor global_data_buffer_flag) and global_data_buffer_flag;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_data_buffer_a <= "00000000000000000000000000000000";
global_data_buffer_b <= "00000000000000000000000000000000";
global_data_buffer_c <= "00000000000000000000000000000000";
global_data_buffer_0 <= "00000000000000000000000000000000";
global_data_buffer_1 <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (global_buffer_enable = '1') then
global_data_buffer_a <= DATA_OUT_A;
global_data_buffer_b <= DATA_OUT_B;
global_data_buffer_c <= DATA_OUT_C;
global_data_buffer_0 <= DATA_OUT_0;
global_data_buffer_1 <= DATA_OUT_1;
end if;
end if;
end process;
process (global_enable, global_enable_delayed, global_enable_delayed_2, DATA_OUT_A, DATA_OUT_B, DATA_OUT_C,
DATA_OUT_0, DATA_OUT_1, global_data_buffer_a, global_data_buffer_b, global_data_buffer_c,
global_data_buffer_0, global_data_buffer_1, hazard) begin
if ((global_enable_delayed = global_enable_delayed_2) and
((global_enable(5) or global_enable(4) or global_enable(3) or global_enable(2) or
global_enable(1) or global_enable(0)) = '1')) then
global_data_buffer_flag <= hazard;
global_data_feed_a <= global_data_buffer_a;
global_data_feed_b <= global_data_buffer_b;
global_data_feed_c <= global_data_buffer_c;
global_data_feed_0 <= global_data_buffer_0;
global_data_feed_1 <= global_data_buffer_1;
else
global_data_buffer_flag <= '0';
global_data_feed_a <= DATA_OUT_A;
global_data_feed_b <= DATA_OUT_B;
global_data_feed_c <= DATA_OUT_C;
global_data_feed_0 <= DATA_OUT_0;
global_data_feed_1 <= DATA_OUT_1;
end if;
end process;
process (global_enable_delayed, data_a, data_b, data_c, data_0, data_1,
DATA_OUT_A, DATA_OUT_B, DATA_OUT_C, DATA_OUT_0, DATA_OUT_1, global_data_feed_a,
global_data_feed_b, global_data_feed_c, global_data_feed_0, global_data_feed_1) begin
if(global_enable_delayed(5) = '1') then
data_a_final <= global_data_feed_a;
else
data_a_final <= data_a;
end if;
if(global_enable_delayed(4) = '1') then
data_b_final <= global_data_feed_b;
else
data_b_final <= data_b;
end if;
if(global_enable_delayed(3) = '1') then
data_c_final <= global_data_feed_c;
else
data_c_final <= data_c;
end if;
if(global_enable_delayed(2) = '1') then
data_0_final <= global_data_feed_0;
else
data_0_final <= data_0;
end if;
if(global_enable_delayed(1) = '1') then
data_1_final <= global_data_feed_1;
else
data_1_final <= data_1;
end if;
end process;
flags_0 <= IDENT_IN & '0';
flags_1 <= IDENT_IN & '1';
ADDRESS_A <= address_a_sig;
ADDRESS_B <= address_b_sig;
ADDRESS_C <= address_c_sig;
ADDRESS_0 <= address_0_sig;
ADDRESS_1 <= address_1_sig;
ADDRESS_W <= address_w_sig;
DATA_TO_W <= data_to_w_sig;
W_EN <= w_en_global;
stall_c0_io <= (stall_c0 or IO_ENABLE or STALL_GLOB or startup_hold_5);
stall_c1_io <= (stall_c1 or IO_ENABLE or STALL_GLOB or startup_hold_5);
global_enable(5) <= address_a_sig(14) or address_a_sig(13) or address_a_sig(15); --a
global_enable(4) <= address_b_sig(14) or address_b_sig(13) or address_a_sig(15); --b
global_enable(3) <= address_c_sig(14) or address_c_sig(13) or address_a_sig(15); --c
global_enable(2) <= address_0_sig(14) or address_0_sig(13) or address_a_sig(15); --0
global_enable(1) <= address_1_sig(14) or address_1_sig(13) or address_a_sig(15); --1
global_enable(0) <= address_w_sig(14) or address_w_sig(13) or address_a_sig(15); --w
GLOBAL_EN <= dick;
dick <= (global_enable(5) or global_enable(4) or global_enable(3) or global_enable(2) or global_enable(1) or global_enable(0)) and override_global;
w_en_local <= w_en_sig and (not global_enable(0));
w_en_global <= w_en_sig and (global_enable(0));
hold_local <= IO_ENABLE or STALL_GLOB;
hazard <= stall_c0_io and stall_c1_io;
end; | gpl-2.0 |
huukit/logicsynth | excercises/tb/tb_ripple_carry_adder.vhd | 1 | 4248 | -------------------------------------------------------------------------------
-- Title : TKT-1212, Exercise 02
-- Project :
-------------------------------------------------------------------------------
-- File : tb_ripple_carry_adder.vhd
-- Author : Antti Rasmus
-- Company : TUT/DCS
-- Created : 2008-11-28
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Tests all combinations of summing two 3-bit values
-------------------------------------------------------------------------------
-- Copyright (c) 2008
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2008-11-28 1.0 ege Created
-------------------------------------------------------------------------------
-- Include default libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Include own logic (=compiled ripple_carry_adder)
use work.all;
-- Testbech needs no input or output signals
entity tb_ripple_carry_adder is
end tb_ripple_carry_adder;
-- The behavior is written inside architecture
architecture testbench of tb_ripple_carry_adder is
-- First, there are definitions
-- Define constants: bit widths and duration of clk period
constant input_w_c : integer := 3;
constant output_w_c : integer := 4;
constant clk_period_c : time := 100 ns;
-- Component declaration of Design Under Verification (DUV)
component ripple_carry_adder
port (
a_in : in std_logic_vector(2 downto 0);
b_in : in std_logic_vector(2 downto 0);
s_out : out std_logic_vector(3 downto 0));
end component;
-- Define the needed signals
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal term1_r : unsigned(input_w_c-1 downto 0);
signal term2_r : unsigned(input_w_c-1 downto 0);
signal sum : unsigned(output_w_c-1 downto 0);
signal sum_slv : std_logic_vector(output_w_c-1 downto 0);
begin -- testbench
-- The actual behavior starts here
-- Instantiate DUV and connect it to testbench's signals
i_ripple_carry_adder : ripple_carry_adder
port map (
a_in => std_logic_vector(term1_r),
b_in => std_logic_vector(term2_r),
s_out => sum_slv);
sum <= unsigned(sum_slv);
-- Generate rst signals to initialize registers
rst_n <= '1' after clk_period_c*2;
-- purpose: Generate clock signal for DUV
-- type : combinational
-- inputs : clk (this is a special case for test purposes!)
-- outputs: clk
clk_gen : process (clk)
begin -- process clk_gen
clk <= not clk after clk_period_c/2;
end process clk_gen;
-- purpose: Generate all possible inputs values and check the result
-- type : sequential
-- inputs : clk, rst_n
-- outputs: term1_r, term2_r
input_gen_output_check : process (clk, rst_n)
begin -- process input_gen_output_check
if rst_n = '0' then -- asynchronous reset (active low)
-- Reset all registers here
term1_r <= (others => '0');
term2_r <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Increment term1 on every clock cycle (else-branch)
-- Increment also term2 when term1 has max value (if-branch)
-- Simulation terminates when term2 has max value
if (to_integer(term1_r) = 2**input_w_c-1) then
term1_r <= (others => '0');
if (term2_r = 2**input_w_c-1) then
assert false report "Simulation ended!" severity failure;
-- "Failure" forces simulator to stop, so it is not dangerous in this
-- case
else
term2_r <= to_unsigned(to_integer(term2_r) + 1, input_w_c);
end if;
else
term1_r <= to_unsigned(to_integer(term1_r) + 1, input_w_c);
end if;
-- Check the result. This condition should always be true. If not, the report message will be printed.
assert to_integer(sum) = to_integer(term1_r) + to_integer(term2_r)
report "Output signal is not equal to the sum of the inputs"
severity error;
end if;
end process input_gen_output_check;
end testbench;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/grgpio.in.vhd | 6 | 208 | -- GPIO port
constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/spw/wrapper/grspw_gen.vhd | 1 | 11111 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
| gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/FIFO_B2B.vhd | 2 | 3648 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO_B2B is
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16);
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC );
end FIFO_B2B;
architecture Behavioral of FIFO_B2B is
type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';
begin
Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata;
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
-- occupancy control
-- write only
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
data_cnt <= data_cnt + 1;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;
-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;
-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
prog_full <= '1' when (data_cnt >= PROG_FULL_TH OR srst = '1') else '0';
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-1) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-arrow-bemicro-sdk/ahbrom.vhd | 3 | 8961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/esa/pci/pci_arb.vhd | 4 | 18127 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
--============================================================================--
-- Design unit : pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - nested round-robbing in two different priority levels
-- - priority assignment hard-coded or APB-programmable
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : Numbering for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
-- The arbiter considers strong signal levels ('1' and '0')
-- only. Weak levels ('H', 'L') are not considered. The
-- appropriate translation function (to_X01) must be applied
-- to the inputs. This is usually done by the pads,
-- and therefore not contained in this model.
--
-- Configuration: The arbiter can be configured to NB_AGENTS = 4, 8, 16 or 32.
-- A priority level (0 = high, 1 = low) is assigned to each device.
-- Exception is agent NB_AGENTS-1, which has always lowest priority.
--
-- a) The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- The constant ARB_LVL_C must then be set to appropriate values.
--
-- b) When APB_PRIOS = true, the levels are programmable via the
-- APB-address 0x80 (allows to be ored with the PCI interface):
-- Bit 31 (leftmost) = master 31 . . bit 0 (rightmost) = master 0.
-- Bit NB_AGENTS-1 is dont care at write and reads 1.
-- Bits NB_AGENTS to 31, if existing, are dont care and read 0.
-- The constant ARB_LVL_C is then the reset value.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by two nested round-robbing loops.
-- An agent number and a priority level is assigned to each agent.
-- The agent number determines, the pair of req_n/gnt_n lines.
-- Agents are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level 1 as a group have access
-- equal to each agent of level 0.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : LEON config package
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
-- Copyright (C): European Space Agency (ESA) 2002.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.5e on Linux RedHat 7.2
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R. W. 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
-- 0.3 R. Weigand 2002/03/19 Default assignment to owneri in find_next
-- 1.0 RW. 2002/04/08 Implementation of TMR registers
-- Removed recursive function call
-- Fixed ARB_LEVELS = 2
-- 3.0 R. Weigand 2002/04/16 Released for leon2
-- 4.0 M. Isomaki 2004/10/19 Minor changes for GRLIB integration
-- 4.1 J.Gaisler 2004/11/17 Minor changes for GRLIB integration
--$Log$
-- Revision 3.1 2002/07/31 13:22:09 weigand
-- Bugfix for cases where no valid request in level 0 (level 1 was not rearbitrated)
--
-- Revision 3.0 2002/07/24 12:19:38 weigand
-- Installed RCS with version 3.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library esa;
use esa.pci_arb_pkg.all;
entity pci_arb is
generic(NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port (clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end pci_arb;
architecture rtl of pci_arb is
subtype agent_t is std_logic_vector(ARB_SIZE-1 downto 0);
subtype arb_lvl_t is std_logic_vector(NB_AGENTS-1 downto 0);
subtype agentno_t is integer range 0 to NB_AGENTS-1;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in level 1
-- Example: x010 = prio 0 for agent 2 and 0, prio 1 for agent 3 and 1.
-- Default: start with all devices equal priority at level 1.
constant ARB_LVL_C : arb_lvl_t := (others => '1');
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
--Necessary definitions from amba.vhd and iface.vhd
--added to pci_arb package with modified names to avoid
--name clashes in GRLIB
constant APB_PRIOS : boolean := APB_EN = 1;
signal owner0, owneri0 : agent_t; -- current owner in level 0
signal owner1, owneri1 : agent_t; -- current owner in level 1
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : std_logic_vector(3 downto 0); -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t; -- := ARB_LVL_C; -- level registers
type nmstarr is array (0 to 3) of agentno_t;
type nvalarr is array (0 to 3) of boolean;
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner0, owner1, req_n, rearb, tout, turn, frame_n,
arb_lvl, rst_n)
variable owner0v, owner1v : agentno_t; -- integer variables for current owner
variable new_request : agentno_t; -- detected request
variable nmst : nmstarr;
variable nvalid : nvalarr;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri0 <= owner0;
owneri1 <= owner1;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
owner0v := conv_integer(owner0);
owner1v := conv_integer(owner1);
new_request := conv_integer(cown);
nvalid(0 to 3) := (others => false);
nmst(0 to 3) := (others => 0);
-- Determine next request in both priority levels
rob : for i in NB_AGENTS-1 downto 0 loop
-- consider all masters with valid request
if req_n(i) = '0' then
-- next in prio level 0
if arb_lvl(i) = '0' then
if i > owner0v then
nmst(0) := i; nvalid(0) := true;
elsif i < owner0v then
nmst(1) := i; nvalid(1) := true;
end if;
-- next in prio level 1
elsif arb_lvl(i) = '1' then
if i > owner1v then
nmst(2) := i; nvalid(2) := true;
elsif i < owner1v then
nmst(3) := i; nvalid(3) := true;
end if;
end if; -- arb_lvl
end if; -- req_n
end loop rob;
-- select new master
if nvalid(0) then -- consider level 0 before wrap
new_request := nmst(0);
owner0v := nmst(0);
-- consider level 1 only once, except when no request in level 0
elsif owner0v /= NB_AGENTS-1 or not nvalid(1) then
if nvalid(2) then -- level 1 before wrap
new_request := nmst(2);
owner0v := NB_AGENTS-1;
owner1v := nmst(2);
elsif nvalid(3) then -- level 1 after wrap
new_request := nmst(3);
owner0v := NB_AGENTS-1;
owner1v := nmst(3);
end if;
elsif nvalid(1) then -- level 0 after wrap
new_request := nmst(1);
owner0v := nmst(1);
end if;
owneri0 <= conv_std_logic_vector(owner0v, ARB_SIZE);
owneri1 <= conv_std_logic_vector(owner1v, ARB_SIZE);
-- rearbitration if any request asserted & different from current owner
if conv_integer(cown) /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= conv_std_logic_vector(new_request, ARB_SIZE);
touti <= "0000"; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= "1111";
elsif frame_n = '1' then -- request, but no transaction
if tout = "1111" then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= "0000"; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = conv_integer(cown) and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
-- synchronous reset
if rst_n = '0' then
touti <= "0000";
cowni <= (others => '0');
owneri0 <= (others => '0');
owneri1 <= (others => '0');
rearbi <= '0';
turni <= '0';
new_request := 0;
end if;
end process arbiter;
arb_lvl(NB_AGENTS-1) <= '1'; -- always prio 1.
fixed_prios : if not APB_PRIOS generate -- assign constant value
arb_lvl(NB_AGENTS-2 downto 0) <= ARB_LVL_C(NB_AGENTS-2 downto 0);
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl, prst_n
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl, prst_n)
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80
if pbi.PADDR(7 downto 0) = "10000000" and pbi.PSEL = '1' then -- address select
if (pbi.PWRITE and pbi.PENABLE) = '1' then -- APB write
arb_lvli <= pbi.PWDATA(NB_AGENTS-1 downto 0);
end if;
pbo.PRDATA(NB_AGENTS-1 downto 0) <= arb_lvl;
end if;
-- synchronous reset
if prst_n = '0' then
arb_lvli <= ARB_LVL_C; -- assign default value
end if;
end process config;
-- APB registers
apb_regs : process (pclk)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if pclk'event and pclk = '1' then -- '
arb_lvl(NB_AGENTS-2 downto 0) <= arb_lvli(NB_AGENTS-2 downto 0);
end if;
end process apb_regs;
end generate apbgen;
-- PCI registers
regs0 : process (clk)
begin -- process regs
if clk'event and clk = '1' then -- '
tout <= touti;
owner0 <= owneri0;
owner1 <= owneri1;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/sdctrl16.vhd | 2 | 40194 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl16
-- File: sdctrl16.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified by: Daniel Bengtsson & Richard Fång
-- Description: 16- and 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl16 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 16;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl16 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS16 : boolean := (sdbits = 16);
constant BUS32 : boolean := (sdbits = 32);
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
lhw : std_ulogic; --Lower halfword
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
if BUS16 then
if (r.lhw = '1') then --muxes read data to correct part of the register.
v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
else
v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
end if;
else
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
end if;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
if BUS16 then
case r.size is
when "00" => --bytesize
case r.haddr(0) is
when '0' => dqm := "11111101";
when others => dqm := "11111110";
end case;
when others => dqm := "11111100"; --halfword, word
end case;
else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
end if;
--
-- case r.size is
-- when "00" =>
-- case r.haddr(1 downto 0) is
-- when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
-- when "01" => dqm := "11111110"; lhw := '0';
-- when "10" => dqm := "11111101"; lhw := '1';
-- when others => dqm := "11111110"; lhw := '1';
-- end case;
-- when "01" =>
-- dqm := "11111100";
-- if r.haddr(1) = '0' then
-- lhw := '0';
-- else
-- lhw := '1';
-- end if;
-- when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
-- end case;
--
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
if BUS16 then
case r.cfg.csize is
when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
when "01" => raddr := haddr(22 downto 10);
when "10" => raddr := haddr(23 downto 11);
when others =>
if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
else raddr := haddr(24 downto 12); end if;
end case;
else
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
end if;
-- generate bank address
-- if BUS16 then --011
-- ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
-- genmux(r.cfg.bsize, haddr(25 downto 18));
-- else
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- end if;
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
-- elsif BUS32 then
-- adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
-- else
-- adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
-- end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
-- if BUS16 then
-- v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
-- else
v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
-- end if;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
if not BUS16 then
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
if BUS16 then --HW adress needed to memory
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
else
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
end if;
v.dqm := dqm; v.burst := r.hready; -- ??
if r.hwrite = '1' then
if BUS16 then --16 bit
if r.size(1) = '1' then --word
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
v.sdstate := act3_16; -- goto state for second part of word transfer
-- v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
else --halfword or byte
v.sdstate := act3_16; v.hready := '1';
end if;
else --32 bit or 64
v.sdstate := wr1;
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
end if;
v.sdwen := '0'; v.bdrive := '0'; --write
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
end if;
else v.sdstate := rd1; end if;
when act3_16 => --handle 16 bit and WORD write
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
v.lhw := '1';
if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
if( ahbsi.htrans = "11" and
not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
v.sdstate := wr1_16;
end if;
elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
else -- complete single write
v.hready := '1';
v.sdstate := act3_16; --gick till wr1 förut
end if;
when wr1_16 =>
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
v.lhw := r.haddr(1);
v.sdstate := act3_16;
v.hready := '1';
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 => --first read applied to sdram
v.casn := '1'; v.sdstate := rd7; --nop
if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd7 =>
v.casn := '1'; --nop
if BUS16 then
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
else -- 32 bit or larger
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if BUS16 then
if ahbsi.htrans /= "11" then
v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
--note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
end if;
else
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
v.casn := '1'; --if read before cas makes nop else if pre => no difference
if BUS16 then
--note if read is for halfwor or byte we dont want to read a second time but exit.
--if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
-- if r.size(1) = '1' then --word v.hready := not r.size(1)
-- v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
-- v.lhw := '1'; -- read low 16 next state
-- else --HW or byte
-- v.sdstate := rd4_16; v.hready := '1';
-- end if;
v.sdstate := rd4_16;
v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
if r.haddr(3 downto 1) = "100" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --32 bit or larger
v.sdstate := rd4; v.hready := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
--v.hready := '1';
v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
v.casn := '1';
--quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
if (ahbsi.htrans /= "11" and (r.hready = '1')) or
((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
--v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
v.dqm := (others => '1');
if r.sdcsn /= "11" then --not prechargeing
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
else--exit
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
if r.cfg.casdel = '0' then
if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
else
if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if r.cfg.renable = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
-- if writing to IO space config regs. Just mapping write data to all config values in config reg
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
--reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
-- Quick hack to get rid of undriven signal warnings. Check this for future
-- merge with main sdctrl.
drivehack : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto 16) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.dqs_gate <= '0';
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block drivehack;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
end generate;
wrdata : if not BUS16 generate
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
if BUS16 then --mux data depending on Low/High HW
if (r.lhw ='1') then
sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
else
sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
end if;
end if;
if not BUS16 then
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl16" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/netcard/netcard.vhd | 1 | 10799 | -----------------------------------------------------------------------------
-- Ethernet/PCI bridge Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use work.config.all;
entity netcard is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
emdio : inout std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_irq : out std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture rtl of netcard is
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, pciclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal dui : uart_in_type;
signal duo : uart_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal irqn, lclk, gnd : std_logic;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahb : integer := CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0,
0, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_clk, clkm, open, open, open, pciclk, cgi, cgo);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (nahbm => maxahb, nahbs => 4, ioen => 0)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e0 : greth generic map(hindex => log2x(CFG_PCI),
pindex => 0, paddr => 11, pirq => 11, memtech => memtech)
port map( rst => rstn, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo(log2x(CFG_PCI)),
apbi => apbi, apbo => apbo(0), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
irqn <= ahbso(3).hirq(11);
irq_pad : odpad generic map (tech => padtech, level => pci33)
port map (pci_irq, irqn);
----------------------------------------------------------------------
--- AHB/APB Bridge -------------------------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 0, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo );
----------------------------------------------------------------------
--- AHB RAM --------------------------------------------------------
----------------------------------------------------------------------
ram0 : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 2, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(2));
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => 0,
device_id => 16#0210#, vendor_id => 16#16E3#)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(0));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => 0,
fifodepth => 6, device_id => 16#0210#, vendor_id => 16#16E3#,
hslvndx => 1, pindex => 6, paddr => 2, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(6),
ahbmi, ahbmo(0), ahbsi, ahbso(1));
end generate;
pci_dma : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => 1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => 0,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(1),
apbi, apbo(4), ahbmi, ahbmo(0), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (memtech => memtech, pindex => 3,
paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(3));
end generate;
pcipads0 : pcipads generic map (padtech)
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
----------------------------------------------------------------------
--- Optional DSU UARTs ----------------------------------------------
----------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => log2x(CFG_PCI)+CFG_GRETH, pindex => 1, paddr => 1)
port map (rstn, clkm, dui, duo, apbi, apbo(1), ahbmi, ahbmo(log2x(CFG_PCI)+CFG_GRETH));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech,
hindex => log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi,
ahbmo(log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART), open, open, open,
open, open, open, open, gnd);
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "Ethernet/PCI Network Card Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml501/config.vhd | 1 | 7223 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000030#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (140);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (15);
constant CFG_DDR2SP_DELAY1 : integer := (15);
constant CFG_DDR2SP_DELAY2 : integer := (15);
constant CFG_DDR2SP_DELAY3 : integer := (15);
constant CFG_DDR2SP_DELAY4 : integer := (15);
constant CFG_DDR2SP_DELAY5 : integer := (15);
constant CFG_DDR2SP_DELAY6 : integer := (15);
constant CFG_DDR2SP_DELAY7 : integer := (15);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
erikd/geany | tests/ctags/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/net/edcl.in.vhd | 4 | 401 | -- Ethernet DSU
constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2sgx90-av/debugreg.vhd | 3 | 1166 | -- debugreg.vhd
-- very simple readable and adressable 64 bit (2x 32 bit)
-- purpose: debug output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity debugreg is
port (
clk : in std_logic;
rst_n : in std_logic;
bus_addr : in std_logic_vector(2 downto 0);
bus_datai : in std_logic_vector(31 downto 0);
bus_datao : out std_logic_vector(31 downto 0);
bus_wen : in std_logic;
bus_cen : in std_logic;
iopins : out std_logic_vector(63 downto 0)
);
end;
architecture rtl of debugreg is
signal iopins_r : std_logic_vector(63 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if(rst_n = '0') then
iopins_r <= (others => '0');
elsif(bus_cen='0' and bus_wen='0') then
if(bus_addr(2)='0') then
iopins_r(31 downto 0) <= bus_datai;
else
iopins_r(63 downto 32) <= bus_datai;
end if;
end if;
iopins <= iopins_r;
if(bus_addr(2)='0') then
bus_datao <= iopins_r(31 downto 0);
else
bus_datao <= iopins_r(63 downto 32);
end if;
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/cycloneiii/alt/admout.vhd | 3 | 3433 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end;
architecture rtl of admout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dm_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DM output register --------------------------------------------------------------
dm_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dm_l,
datainhi => dm_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dm_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DM) ------------------------------------------------------------------
dm_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dm_reg,
oe => vcc,
--devoe => vcc,
o => dm_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/pcie.vhd | 3 | 4261 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
dmamst : integer := NAHBMST;
fifodepth : integer := 5;
hslvndx : integer := 0;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#;
haddr : integer := 16#A00#;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcie_master_target_sp605 is
generic (
master : integer := 1;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System In terface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pciedma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 9; -- PCI device ID
vendor_id : integer := 16#10EE#; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#
);
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/mmuiface.vhd | 1 | 8132 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmuiface
-- File: mmuiface.vhd
-- Author: Konrad Eisele, Jiri Gaisler - Gaisler Research
-- Description: MMU interface types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
library techmap;
use techmap.gencomp.all;
package mmuiface is
type mmutlbcam_in_type is record
mmctrl : mmctrl_type1;
tagin : tlbcam_tfp;
tagwrite : tlbcam_reg;
trans_op : std_logic;
flush_op : std_logic;
write_op : std_logic;
wb_op : std_logic;
mmuen : std_logic;
mset : std_logic;
end record;
type mmutlbcami_a is array (natural range <>) of mmutlbcam_in_type;
type mmutlbcam_out_type is record
pteout : std_logic_vector(31 downto 0);
LVL : std_logic_vector(1 downto 0); -- level in pth
hit : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0); -- for diagnostic access
valid : std_logic; -- for diagnostic access
vaddr : std_logic_vector(31 downto 0); -- for diagnostic access
NEEDSYNC : std_logic;
WBNEEDSYNC : std_logic;
end record;
type mmutlbcamo_a is array (natural range <>) of mmutlbcam_out_type;
-- mmu i/o
type mmuidc_data_in_type is record
data : std_logic_vector(31 downto 0);
su : std_logic;
read : std_logic;
isid : mmu_idcache;
wb_data : std_logic_vector(31 downto 0);
end record;
type mmuidc_data_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
cache : std_logic;
accexc : std_logic;
end record;
constant mmuidco_zero : mmuidc_data_out_type := ('0', zero32, '0', '0');
type mmudc_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
-- dcache extra signals
flush_op : std_logic;
diag_op : std_logic;
wb_op : std_logic;
fsread : std_logic;
mmctrl1 : mmctrl_type1;
testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
end record;
type mmudc_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
-- dcache extra signals
mmctrl2 : mmctrl_type2;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
type mmuic_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
end record;
type mmuic_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
constant mmudco_zero : mmudc_out_type := ('0', mmuidco_zero,
mmctrl2_zero, mmuidco_zero, '0');
constant mmuico_zero : mmuic_out_type := ('0', mmuidco_zero, '0');
--#lrue i/o
type mmulrue_in_type is record
touch : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
clear : std_logic;
flush : std_logic;
left : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromleft : std_logic;
right : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromright : std_logic;
end record;
type mmulruei_a is array (natural range <>) of mmulrue_in_type;
type mmulrue_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
movetop : std_logic;
end record;
constant mmulrue_out_none : mmulrue_out_type := (zero32(M_ENT_MAX_LOG-1 downto 0), '0');
type mmulrueo_a is array (natural range <>) of mmulrue_out_type;
--#lru i/o
type mmulru_in_type is record
touch : std_logic;
touchmin : std_logic;
flush : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
mmctrl1 : mmctrl_type1;
end record;
type mmulru_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
end record;
--#mmu: tw i/o
type memory_mm_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
lock : std_logic;
end record;
constant mci_zero : memory_mm_in_type := (X"00000000", X"00000000",
"00", '0', '0', '0', '0');
type memory_mm_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
cache : std_logic; -- cacheable data
end record;
type mmutw_in_type is record
walk_op_ur : std_logic;
areq_ur : std_logic;
tlbmiss : std_logic;
data : std_logic_vector(31 downto 0);
adata : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
end record;
type mmutwi_a is array (natural range <>) of mmutw_in_type;
type mmutw_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
end record;
type mmutwo_a is array (natural range <>) of mmutw_out_type;
-- mmu tlb i/o
type mmutlb_in_type is record
flush_op : std_logic;
wb_op : std_logic;
trans_op : std_logic;
transdata : mmuidc_data_in_type;
s2valid : std_logic;
mmctrl1 : mmctrl_type1;
testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
end record;
type mmutlbi_a is array (natural range <>) of mmutlb_in_type;
type mmutlbfault_out_type is record
fault_pro : std_logic;
fault_pri : std_logic;
fault_access : std_logic;
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
fault_su : std_logic;
fault_read : std_logic;
fault_isid : mmu_idcache;
fault_addr : std_logic_vector(31 downto 0);
end record;
constant mmutlbfault_out_zero : mmutlbfault_out_type := (
fault_pro => '0',
fault_pri => '0',
fault_access => '0',
fault_mexc => '0',
fault_trans => '0',
fault_inv => '0',
fault_lvl => (others => '0'),
fault_su => '0',
fault_read => '0',
fault_isid => id_icache,
fault_addr => (others => '0'));
type mmutlb_out_type is record
transdata : mmuidc_data_out_type;
fault : mmutlbfault_out_type;
nexttrans : std_logic;
s1finished : std_logic;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmutlbo_a is array (natural range <>) of mmutlb_out_type;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/bscanregs.vhd | 1 | 2767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregs
-- File: bscanregs.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, single-ended IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregs is
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end;
architecture hier of bscanregs is
signal itdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable=0 generate
sigo <= sigi;
itdi <= (others => '0');
tdo <= '0';
end generate;
engen: if enable /= 0 generate
g0: for x in 0 to nsigs-1 generate
irgen: if ((dirmask / (2**x)) mod 2)=0 generate
ireg: scanregi
generic map (tech)
port map (sigi(x),sigo(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdi,bsdrive,bshighz);
end generate;
orgen: if ((dirmask / (2**x)) mod 2)/=0 generate
oreg: scanrego
generic map (tech)
port map (sigo(x),sigi(x),sigi(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdo,bsdrive);
end generate;
end generate;
itdi(0) <= tdi;
tdo <= itdi(nsigs);
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/testbench.vhd | 1 | 8561 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/jtag2.in.vhd | 4 | 92 | -- Second JTAG based DSU interface
constant CFG_AHB_JTAG2 : integer := CONFIG_DSU_JTAG2;
| gpl-2.0 |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Multiplexer_4x16.vhd | 1 | 954 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_4x16 is
Port ( Selector : in STD_LOGIC_VECTOR (3 downto 0);
input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0);
input_I, input_J, input_K, input_L, input_M, input_N, input_O, input_P: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end Multiplexer_4x16;
architecture skeleton of Multiplexer_4x16 is
begin
with Selector select
output <= input_A when "0000",
input_B when "0001",
input_C when "0010",
input_D when "0011",
input_E when "0100",
input_F when "0101",
input_G when "0110",
input_H when "0111",
input_I when "1000",
input_J when "1001",
input_K when "1010",
input_L when "1011",
input_M when "1100",
input_N when "1101",
input_O when "1110",
input_P when others;
end skeleton; | gpl-3.0 |
KimSJ/HDLC_chip | hdlcreceiver_tb.vhd | 1 | 4392 | -- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value
-- set strb 1 (11 = command "read high-nibble)
-- read the value
-- for multi-byte reads, repeat last four steps
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity hdlcreceiver_tb is
end entity hdlcreceiver_tb;
architecture behavioural of hdlcreceiver_tb is
signal q : Std_Logic_Vector (7 downto 0); -- q is the values read
signal rxLast : Std_Logic; -- the databus
signal rxRD : Std_Logic := '1';
signal rxReq : Std_Logic;
signal rst: Std_Logic :='1';
signal rxErr : Std_Logic; -- high if CRC error
signal rxUnderrun : Std_Logic; -- high if byte not read in time
signal rxAbort : Std_Logic; -- high if Abort received mid-frame
signal clock: Std_Logic := '1';
signal rxD, rxEn: Std_Logic;
signal cycle : integer :=0;
component hdlcreceiver is
generic (
rxReqChainSize : integer := 2
);
port (
-- microprocesser interface
Dout : out Std_Logic_Vector (7 downto 0); -- rx register
rxLast : out Std_Logic;
rxRD : in Std_Logic; -- read strobe
rxReq : out Std_Logic; -- high if data available
rxErr : out Std_Logic; -- high if CRC error
rxUnderrun : out Std_Logic; -- high if byte not read in time
rxAbort : out Std_Logic; -- high if Abort received mid-frame
rxRST : in Std_Logic;
-- bit clock
sysClk : in Std_Logic; -- 16MHz
-- line interface
rxD : in Std_Logic;
rxEn : buffer Std_Logic
);
end component hdlcreceiver;
type tDataItem is record
rxD: Std_Logic;
rxRST: Std_Logic;
rxRD: Std_Logic;
end record tDataItem;
type tDataList is array (0 to 44) of tDataItem;
constant dataList : tDataList := (
-- test abort (10 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
-- test reset to abort clear (1 value)
('0','1','0'),
-- test flag detect (8 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0'),
-- test inserted bit removal (9 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0'),
('0','0','0'),
('1','0','0'),
-- test normal data -- 0xAA (8 values)
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
-- test frame-end flag detect (8 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0')
);
begin
iface : hdlcreceiver
port map (
Dout => q,
rxLast => rxLast,
rxRD => rxRd,
rxReq => rxReq,
rxErr => rxErr,
rxUnderrun => rxUnderrun,
rxAbort => rxAbort,
rxRST => rst,
-- bit clock
sysClk => clock,
-- line interface
rxD => rxD,
rxEn => rxEn
);
-- rst <= '1' after 0 ns, '0' after 100 ns;
process
-- drive the txClock
begin
clock <= '0';
wait for 62 ns;
clock <= '1';
wait for 63 ns;
end process;
process (clock)
begin
if rising_edge(clock) then
cycle <= (cycle + 1) mod (64 * dataList'length);
if cycle = 0 then
-- i <= (i(0) & i(7 downto 1)) xor "0" & i(0) & "00" & i(0) & "0" & i(0) & "0";
end if;
if (cycle mod 64) = 0 then
rxD <= dataList(cycle/64).rxD;
rst <= dataList(cycle/64).rxRST;
end if;
end if;
end process;
end behavioural; | gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/dec_reg.vhd | 2 | 2295 | --Decodificar registrador para após mostrar seu conteudo no display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_reg is
generic(N: integer := 5; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_VECTOR(N-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_reg_arch of dec_reg is
-- signals
signal din : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal dout2, dout3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal we : STD_LOGIC := '0';
begin
we <= '0';
din <= (others => '0');
i1 : entity work.reg_bank
generic map(DATA_WIDTH => M, ADDRESS_WIDTH => N)
port map (
clk => clk,
wren => we,
radd1 => "00000",
radd2 => "00000",
radd3 => SW,
wadd => "UUUUU",
rdata1 => dout2,
rdata2 => dout3,
rdata3 => dout,
wdata => din
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab03/lab03/ipcore_dir/ROM_D/simulation/ROM_D_tb_pkg.vhd | 8 | 5838 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE ROM_D_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END ROM_D_TB_PKG;
PACKAGE BODY ROM_D_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END ROM_D_TB_PKG;
| gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab05/lab05/ipcore_dir/ROM_D/simulation/ROM_D_tb_pkg.vhd | 8 | 5838 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE ROM_D_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END ROM_D_TB_PKG;
PACKAGE BODY ROM_D_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END ROM_D_TB_PKG;
| gpl-3.0 |
manosaloscables/vhdl | generador_pixeles/gen_obj.vhd | 1 | 4121 | -- *************************************
-- * Circuito para generar objetos VGA *
-- *************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_obj is -- Generador de objetos estáticos
port(
obj_on : out std_logic;
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
obj_rgb : out std_logic_vector(2 downto 0)
);
end gen_obj;
--------------------
-- Pared vertical --
--------------------
architecture pared of gen_obj is
-- Coordenadas x, y (0, 0)
signal px_x, px_y: unsigned(9 downto 0);
----------------------------------------------
-- Pared vertical (4 x Resolución vertical) --
----------------------------------------------
-- Borde horizontal(x) izquierdo y derecho
constant PARED_X_I: integer := 32;
constant PARED_X_D: integer := 35;
begin
px_x <= unsigned(pixel_x);
px_y <= unsigned(pixel_y);
-- Pixel dentro de la pared
obj_on <=
'1' when (px_x >= PARED_X_I) and (px_x <= PARED_X_D) else
'0';
-- Salida RGB de la pared
obj_rgb <= "001"; -- Azul
end pared;
-----------------------------
-- Barra vertical (4 x 72) --
-----------------------------
architecture barra of gen_obj is
-- Coordenadas x, y (0, 0) hasta (639, 479)
signal px_x, px_y: unsigned(9 downto 0);
constant MAX_X: integer := 640;
constant MAX_Y: integer := 480;
constant BAR_X_DIM: integer := 4; -- Dimensión/tamaño
constant BAR_Y_DIM: integer := 72;
-- Borde horizontal(x) izquierdo y derecho
constant BAR_X_I: integer := 600;
constant BAR_X_D: integer := BAR_X_I + BAR_X_DIM - 1;
-- Borde vertical(y) superior e inferior
constant BAR_Y_S: integer := MAX_Y/2 - BAR_Y_DIM/2; -- 204
constant BAR_Y_I: integer := BAR_Y_S + BAR_Y_DIM - 1;
begin
px_x <= unsigned(pixel_x);
px_y <= unsigned(pixel_y);
-- Pixel dentro de la barra
obj_on <=
'1' when (px_x >= BAR_X_I) and (px_x <= BAR_X_D) and
(px_y >= BAR_Y_S) and (px_y <= BAR_Y_I) else
'0';
-- Salida RGB de la barra
obj_rgb <= "010"; -- Verde
end barra;
----------------------------------------------
-- Bola (delimitada por un cuadrado de 8x8) --
----------------------------------------------
architecture bola of gen_obj is
-- Coordenadas x, y (0, 0)
signal px_x, px_y: unsigned(9 downto 0);
constant BOLA_DIM: integer := 8; -- Dimensión
-- Borde horizontal(x) izquierdo y derecho
signal bola_x_i, bola_x_d: unsigned(9 downto 0);
-- Borde vertical(y) superior e inferior
signal bola_y_s, bola_y_i: unsigned(9 downto 0);
-- Señal que indica si las coordenadas del barrido se encuentran dentro de la
-- región cuadrada
signal cuadrado_on: std_logic;
----------------------------
-- Imagen ROM de una bola --
----------------------------
type tipo_rom is array (0 to 7) of std_logic_vector(0 to 7);
-- Definición de la memoria ROM
constant BOLA_ROM: tipo_rom :=
(
"00111100", -- ****
"01111110", -- ******
"11111111", -- ********
"11111111", -- ********
"11111111", -- ********
"11111111", -- ********
"01111110", -- ******
"00111100" -- ****
);
signal rom_dir, rom_col: unsigned(2 downto 0);
signal rom_datos: std_logic_vector(7 downto 0);
signal rom_bit: std_logic;
begin
px_x <= unsigned(pixel_x);
px_y <= unsigned(pixel_y);
-- Declaración temporal
bola_x_i <= to_unsigned(580, 10);
bola_x_d <= to_unsigned(587, 10);
bola_y_s <= to_unsigned(238, 10);
bola_y_i <= to_unsigned(245, 10);
-- Pixel dentro del cuadrado de 8x8
cuadrado_on <=
'1' when (px_x >= bola_x_i) and (px_x <= bola_x_d) and
(px_y >= bola_y_s) and (px_y <= bola_y_i) else
'0';
-- Mapear la ubicación del píxel actual a la dir/col ROM
rom_dir <= px_y(2 downto 0) - bola_y_s(2 downto 0);
rom_col <= px_x(2 downto 0) - bola_x_i(2 downto 0);
rom_datos <= BOLA_ROM(to_integer(rom_dir));
rom_bit <= rom_datos(to_integer(rom_col));
obj_on <=
'1' when (cuadrado_on = '1') and (rom_bit = '1') else
'0';
-- Salida RGB de la bola
obj_rgb <= "100"; -- Rojo
end bola;
| gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/RegBank/RegBank_TB.vhd | 1 | 3922 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: TestBench do Banco de Registradores
-- Descrição: TestBench para o Conjunto de registradores com largura de
-- palavra parametrizável e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade
----------------------------------
entity RegBank_TB is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
end RegBank_TB;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RegBank_TB_Op of RegBank_TB is
component RegBank is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
type vector_array1 is array (natural range <>) of std_logic_vector(ADDRESS_WIDTH-1 downto 0);
type vector_array2 is array (natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal CLK : std_logic := '0';
constant PERIOD : time := 5 ps;
signal WREN : std_logic;
signal RADD1, RADD2 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WADD : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WDATA : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal RDATA1, RDATA2 : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
CLK <= not CLK after PERIOD;
RB_TB: RegBank port map
(CLK, WREN,
RADD1, RADD2,
WADD,
WDATA,
RDATA1, RDATA2);
teste: process
variable init0 : std_logic := '0';
variable init1 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0) := (others => '0');
variable init2 : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable ender : vector_array1(7 downto 0);
variable valor : vector_array2(15 downto 0);
begin
WREN <= init0;
RADD1 <= init1;
RADD2 <= init1;
WADD <= init1;
WDATA <= init2;
RDATA1 <= init2;
RDATA2 <= init2;
ender(0) := "00000";
ender(1) := "11111";
ender(2) := "00110";
ender(3) := "01101";
ender(4) := "00011";
ender(5) := "01010";
ender(6) := "01110";
ender(7) := "00010";
valor(0) := x"00025900";
valor(1) := x"00026797";
valor(2) := x"00092430";
valor(3) := x"00059664";
valor(4) := x"00008572";
valor(5) := x"00004416";
valor(6) := x"00000016";
valor(7) := x"00030581";
valor(8) := x"00006963";
valor(9) := x"00009871";
valor(10) := x"00091257";
valor(11) := x"00082022";
valor(12) := x"00089633";
valor(13) := x"00058236";
valor(14) := x"00052965";
valor(15) := x"00000001";
for var1 in std_logic range '0' to '1' loop
WREN <= var1;
wait for PERIOD;
for var2 in ender'range loop
WADD <= ender(var2);
wait for PERIOD;
for var3 in valor'range loop
WDATA <= valor(var3);
wait for PERIOD;
report "Testando WREN = " & std_logic'image(WREN) severity NOTE;
report "Testando WADD = " & integer'image(to_integer(unsigned(WADD))) & " e WDATA = " & integer'image(to_integer(unsigned(WDATA))) severity NOTE;
end loop;
end loop;
end loop;
wait for PERIOD;
end process teste;
end architecture RegBank_TB_Op; | gpl-3.0 |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/Uniciclo_tb.vhd | 2 | 1694 | ----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Uniciclo_tb IS
generic (
DATA_WIDTH : natural := 32; --32 bits para dados
ADDRESS_WIDTH : natural := 5 --5 bits para endereco
);
END Uniciclo_tb;
ARCHITECTURE Uniciclo_arch OF Uniciclo_tb IS
--declaracao de sinais
SIGNAL clk : std_logic := '1';
SIGNAL SW : std_logic_vector(13 downto 0);
SIGNAL HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: std_logic_vector(6 downto 0);
COMPONENT Uniciclo --componente que sera testado
port (
clk : in std_logic := '1';
SW : in std_logic_vector(13 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0)
);
END COMPONENT;
BEGIN
i1 : Uniciclo
PORT MAP (
clk => clk,
SW => SW,
HEX0 =>HEX0,
HEX1 =>HEX1,
HEX2 =>HEX2,
HEX3 =>HEX3,
HEX4 =>HEX4,
HEX5 =>HEX5,
HEX6 =>HEX6,
HEX7 =>HEX7
);
Clk_process : PROCESS --geracao do clock
variable auxMod : integer;
BEGIN
for op in 0 to 16383 loop
SW <= std_logic_vector(to_signed(op, SW'length));
for i in 0 to 255 loop
clk <= not(clk);
wait for 5 ps;
end loop;
end loop;
END PROCESS Clk_process;
END Uniciclo_arch; --fim do testbench | gpl-3.0 |
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