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P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/ssd_command_fifo/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RECV_REQ_QUEUE/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN/example_design/FIFO_DDR_DATA_IN_top.vhd | 1 | 5087 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FIFO_DDR_DATA_IN_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity FIFO_DDR_DATA_IN_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end FIFO_DDR_DATA_IN_top;
architecture xilinx of FIFO_DDR_DATA_IN_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component FIFO_DDR_DATA_IN is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : FIFO_DDR_DATA_IN PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/GC_fifo/simulation/fg_tb_pkg.vhd | 1 | 11317 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT GC_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_data_send_fifo/simulation/fg_tb_pkg.vhd | 1 | 11651 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_top.vhd | 1 | 6020 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
CONSTANT rd_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/GC_fifo/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_rec_fifo/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd | 1 | 9878 | ------------------------------------------------------------------------------
-- File name: ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd
-- Date: 6/10/2009
-- (C) Copyright 2009 Gandhi Puvvada
-- Description:
-- A vhdl design for debouncing a Push Button (PB) and produce the following:
-- (1) a debounced pulse DPB (DPB = debounced PB)
-- (2) a single clock-enable pulse, SCEN, after 0.084 sec, for single-stepping user design using a push button,
-- (3) a contunuous clock-enable pulse, CCEN, after another 0.16 sec., for running at full-speed
-- (4) a sequence of (multiple of) clock-enable pulses, MCEN, after every 0.084 sec after the 0.16 sec, for multi-stepping
--
-- Once 'PB' is pressed, after the initial bouncing finishes in the WQ (wait quarter second (actaully 0.084 sec)) state, the DPB is activated,
-- and all three pulses (SCEN, CCEN, and MCEN) are produced just for *one clock* in SCEN_state.
-- Then, after waiting another half second in the WH (wait half second) (actaully 0.168 sec)) state, the MCEN goes active for 1 clock every
-- quarter second and the CCEN goes active continuously. in MCEN_state. Finally, if the PB is released, we wait in WFCR
-- (Wait for a complete release) state for a quarter second and return to the INI state. Please see the state diagram or
-- read the code to understand the exact behavior.
-- The additional half-second (actually 0.168 sec) waiting after producing the first single-clock wide pulse allows the user
-- to release the button in time to avoid multi-stepping or running at full-speed even if he/she has used MCEN or CCEN
-- in his/her design.
-- To achieve the above and generate the outputs without asny glitches (though this is not necessary), let us use output coding.
-- In output coding the state memory bits are thoughtfully chosen in order to form the needed outputs.
-- In this case DPB, SCEN, MCEN, and CCEN are thos outputs. However, the output combinations may repeat in different states.
-- So we need here two tie-breakers.
-- State State DPB SCEN MCEN CCEN Tie-Breaker1 Tie-Breaker0
-- initial INI 0 0 0 0 0 0
-- wait quarter WQ 0 0 0 0 0 1
-- SCEN_state SCEN_st 1 1 1 1 - -
-- wait half WH 1 0 0 0 0 0
-- MCEN_state MCEN_st 1 0 1 1 - -
-- CCEN_state CCEN_st 1 0 0 1 - -
-- Counter Clear CCR 1 0 0 0 0 1
-- WFCR_state WFCR 1 0 0 0 1 -
-- Timers (Counters to keep time): 2**19 clocks of 20ns = 2**20 of 10ns = approximately 10 milliseconds = accurately 10.48576 ms
-- So, instead of quarter second, let us wait for 2**22 clocks ( 0.084 sec.) and instead of half second,
-- let us wait for 2**23 clocks (0.168 seconds).
-- If we use a 24-bit counter, count(23 downto 0), and start it with 0, then the first time, count(22) goes high,
-- we know that the lower 22 bits (21:0) have gone through their 2**22 combinations. So count(22) is used as
-- the 0.084 sec timer and the count(23) is used as the 0.168 sec timer.
-- We will use a generic parameter called N_dc (dc for debounce count) in place of 23 (and N_dc-1 in place of 22),
-- so that N_dc can be made 4 during behavioral simulation to test this debouncing module.
-- As the names say, the SCEN, MCEN, and the CCEN are clock enables and are not clocks by themselves. If you use
-- SCEN (or MCEN) as a "clock" by itself, then you would be creating a lot of sckew as these outputs of the internal
-- state machine take ordinary routes and do not get to go on the special routes used for clock distribution.
-- However, when they are used as clock enables, the static timing analyzer checks timing of these signals with respect
-- to the main clock signal (50 MHz clock) properly. This results in a good timing design. Moreover, you can use different
-- clock enables in different parts of the control unit so that the system is single stepped in some critical areas and
-- multi-stepped or made to run at full speed. This will not be possible if you try to use both SCEN and MCEN as clocks
-- as you should not be using multiple clocks in a supposedly single-clock system.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ee560_debounce is
generic (N_dc: positive := 23);
port (CLK, RESETB_DEBOUNCE :in std_logic; -- CLK = 50 MHz
PB :in std_logic; -- push button
DPB, SCEN, MCEN, CCEN :out std_logic -- debounced PB, single_CEN, multi_CEN, continuous CEN
);
end ee560_debounce ;
-------------------------------------------------------------------------------
architecture debounce_RTL of ee560_debounce is
-- Note: The most common RTL coding in VHDL is to use symbolic names for states
-- and leave it to the synthesis tool to tie these symbolic names to encoded bit combinations.
-- Designers define a suitable enumerated state type as shown below.
-- type debounce_state_type is (INI, WQ, SCEN_St, WH, MCEN_St, CCEN_St, CCR, WFCR);
-- signal debounce_state: debounce_state_type;
-- However, in this design, we would like to use output coding and we want enforce state assignments.
-- Hence, we define constants bearing the symbolic state names and initialize them to the bit
-- combinations of our choice.
-- By default, the synthesis tool (with default XST option "auto" for FSM encoding) will extract the state machine and will perform
attribute fsm_encoding: string; -- Refer to XST user guide -- FSM encoding
signal debounce_state: std_logic_vector(5 downto 0); -- 6-bit combination
-- DPB SCEN MCEN CCEN TieB1 TieB0
constant INI: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '0');
constant WQ: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '1');
constant SCEN_st: std_logic_vector(5 downto 0) := ('1' & '1' & '1' & '1' & '0' & '0');
constant WH: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '0');
constant MCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '1' & '1' & '0' & '0');
constant CCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '1' & '0' & '0');
constant CCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '1');
constant WFCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '1' & '0');
attribute fsm_encoding of debounce_state: signal is "user";
-- The enumerated state type allows the display of state name in symbolic form (ASCII form) in the waveform which is easy to read.
-- So, to provide this convenience, let us define an enumerated state signal called d_state here, and later assign values to it.
type debounce_state_type is (INI_s, WQ_s, SCEN_St_s, WH_s, MCEN_St_s, CCEN_St_s, CCR_s, WFCR_s);
signal d_state: debounce_state_type;
signal debounce_count: std_logic_vector(N_dc downto 0);
-- signal DPB_int, SCEN_int, MCEN_int, CCEN_int: std_logic; -- internal signals
-- signal tie-breaker1, tie-breaker0: std_logic; -- internal signals
begin
-- concurrent signal assignment statements
(DPB, SCEN, MCEN, CCEN) <= debounce_state(5 downto 2); -- this is because of output coding
-- for the purpose of displaying in the waveform
d_state <= INI_s when (debounce_state = INI) else
WQ_s when (debounce_state = WQ) else
SCEN_St_s when (debounce_state = SCEN_St) else
WH_s when (debounce_state = WH) else
MCEN_St_s when (debounce_state = MCEN_St) else
CCEN_St_s when (debounce_state = CCEN_St) else
CCR_s when (debounce_state = CCR) else
WFCR_s; -- when (debounce_state = WFCR);
debounce: process (CLK, RESETB_DEBOUNCE)
begin
if (RESETB_DEBOUNCE = '0') then
debounce_count <= (others => 'X');
debounce_state <= INI;
elsif (CLK'event and CLK = '1') then
case debounce_state is
when INI =>
debounce_count <= (others => '0');
if (PB = '1') then
debounce_state <= WQ;
end if;
when WQ =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= INI;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= SCEN_St;
end if;
when SCEN_St =>
debounce_count <= (others => '0');
debounce_state <= WH;
when WH =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc) = '1') then
debounce_state <= MCEN_St;
end if;
when MCEN_St =>
debounce_count <= (others => '0');
debounce_state <= CCEN_St;
when CCEN_St =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= MCEN_St;
end if;
when CCR =>
debounce_count <= (others => '0');
debounce_state <= WFCR;
when others => -- when WFCR =>
debounce_count <= debounce_count + 1;
if (PB = '1') then
debounce_state <= WH;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= INI;
end if;
end case;
end if;
end process debounce;
----------------------------
end debounce_RTL ;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/gc_command_fifo/simulation/fg_tb_pkg.vhd | 1 | 11378 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT gc_command_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo/simulation/fg_tb_synth.vhd | 2 | 10029 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : ssd_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_command_rec_fifo/example_design/pcie_command_rec_fifo_top.vhd | 1 | 5850 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_rec_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_rec_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_command_rec_fifo_top;
architecture xilinx of pcie_command_rec_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_rec_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_command_rec_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/physical_register_file.vhd | 1 | 9997 | -------------------------------------------------------------------------------
--
-- Design : Physical Register File
-- Project : Tomasulo Processor
-- Entity : register_file
-- Author : Vaibhav Dhotre
-- Company : University of Southern California
-- Updated : 03/15/2010
-------------------------------------------------------------------------------
--
-- Description : 32 wide 48 deep register file. $0 is never written during circuit
-- operation. So it is replaced with hard wired 0s by synthesis tool
-- It has 8 read port and 1 write port. Reading is asynchronous and writing is synchronous.
-- When an instruction is dispatched the ready signal for new physical register for the Rd
-- is made 0.
-- When an instruction is on CDB the ready signal for new physical register for the Rd
-- is made 1.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------------------------------------
entity physicalregister_file is
generic(
tag_width : integer:= 6
);
port(
Clk : in std_logic;
Resetb : in std_logic;
---Interface with Integer Issue queue---
Iss_RsPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrAlu : in std_logic_vector(5 downto 0);
---Interface with Load Store Issue queue---
Iss_RsPhyAddrLsq : in std_logic_vector(5 downto 0);
---Interface with Multiply Issue queue---
Iss_RsPhyAddrMul : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrMul : in std_logic_vector(5 downto 0);
---Interface with Divide Issue queue---
Iss_RsPhyAddrDiv : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrDiv : in std_logic_vector(5 downto 0);
---Interface with Dispatch---
Dis_RsAddr : in std_logic_vector(5 downto 0);
PhyReg_RsDataRdy : out std_logic; -- for dispatch unit
Dis_RtAddr : in std_logic_vector(5 downto 0);
PhyReg_RtDataRdy : out std_logic; -- for dispatch unit
Dis_NewRdPhyAddr : in std_logic_vector(5 downto 0);
Dis_RegWrite : in std_logic;
---Interface with Integer Execution Unit---
PhyReg_AluRsData : out std_logic_vector(31 downto 0);
PhyReg_AluRtData : out std_logic_vector(31 downto 0);
---Interface with Load Store Execution Unit---
PhyReg_LsqRsData : out std_logic_vector(31 downto 0);
---Interface with Multiply Execution Unit---
PhyReg_MultRsData : out std_logic_vector(31 downto 0);
PhyReg_MultRtData : out std_logic_vector(31 downto 0);
---Interface with Divide Execution Unit---
PhyReg_DivRsData : out std_logic_vector(31 downto 0);
PhyReg_DivRtData : out std_logic_vector(31 downto 0);
---Interface with CDB ---
Cdb_RdData : in std_logic_vector(31 downto 0);
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0);
Cdb_Valid : in std_logic;
Cdb_PhyRegWrite : in std_logic;
---Interface with Store Buffer ---
Rob_CommitCurrPhyAddr : in std_logic_vector(5 downto 0);
PhyReg_StoreData : out std_logic_vector(31 downto 0)
);
end physicalregister_file;
architecture regfile of physicalregister_file is
-- Register file Declaration
subtype reg is std_logic_vector(31 downto 0);
type reg_file is array (0 to 47) of reg;
signal physical_register_r: reg_file ;
signal physical_reg_ready : std_logic_vector(47 downto 0);
begin
PhyReg_AluRsData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RsPhyAddrAlu and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')--cdbWrite
else physical_register_r (CONV_INTEGER(Iss_RsPhyAddrAlu)); -- Internal forwarding from write port
PhyReg_AluRtData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RtPhyAddrAlu and Cdb_Valid = '1'and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RtPhyAddrAlu)); -- Internal forwarding from write port
PhyReg_LsqRsData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RsPhyAddrLsq and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RsPhyAddrLsq)); -- Internal forwarding from write port
PhyReg_MultRsData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RsPhyAddrMul and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RsPhyAddrMul)); -- Internal forwarding from write port
PhyReg_MultRtData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RtPhyAddrMul and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RtPhyAddrMul)); -- Internal forwarding from write port
PhyReg_DivRsData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RsPhyAddrDiv and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RsPhyAddrDiv)); -- Internal forwarding from write port
PhyReg_DivRtData <= Cdb_RdData when ( Cdb_RdPhyAddr = Iss_RtPhyAddrDiv and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Iss_RtPhyAddrDiv)); -- Internal forwarding from write port
PhyReg_StoreData <= Cdb_RdData when ( Cdb_RdPhyAddr = Rob_CommitCurrPhyAddr and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1')
else physical_register_r (CONV_INTEGER(Rob_CommitCurrPhyAddr)); -- Internal forwarding from write port
reg_file_read_write: process(Clk,Resetb)
begin
-------------------------------Initialize register file contents here----------------------------------
if Resetb ='0' then
physical_register_r <= (
"00000000000000000000000000000000", -- $0
"00000000000000000000000000000001", -- $1
"00000000000000000000000000000010", -- $2
"00000000000000000000000000000011", -- $3
"00000000000000000000000000000100", -- $4
"00000000000000000000000000000101", -- $5
"00000000000000000000000000000110", -- $6
"00000000000000000000000000000111", -- $7
"00000000000000000000000000001000", -- $8
"00000000000000000000000000001001", -- $9
"00000000000000000000000000001010", -- $10
"00000000000000000000000000001011", -- $11
"00000000000000000000000000001100", -- $12
"00000000000000000000000000001101", -- $13
"00000000000000000000000000001110", -- $14
"00000000000000000000000000001111", -- $15
"00000000000000000000000000010000", -- $16
"00000000000000000000000000010001", -- $17
"00000000000000000000000000010010", -- $18
"00000000000000000000000000010011", -- $19
"00000000000000000000000000010100", -- $20
"00000000000000000000000000010101", -- $21
"00000000000000000000000000010110", -- $22
"00000000000000000000000000010111", -- $23
"00000000000000000000000000011000", -- $24
"00000000000000000000000000011001", -- $25
"00000000000000000000000000011010", -- $26
"00000000000000000000000000011011", -- $27
"00000000000000000000000000011100", -- $28
"00000000000000000000000000011101", -- $29
"00000000000000000000000000011110", -- $30
"00000000000000000000000000011111", -- $31
"00000000000000000000000000100000", -- $32
"00000000000000000000000000100001", -- $33
"00000000000000000000000000100010", -- $34
"00000000000000000000000000100011", -- $35
"00000000000000000000000000100100", -- $36
"00000000000000000000000000100101", -- $37
"00000000000000000000000000100110", -- $38
"00000000000000000000000000100111", -- $39
"00000000000000000000000000101000", -- $40
"00000000000000000000000000101001", -- $41
"00000000000000000000000000101010", -- $42
"00000000000000000000000000101011", -- $43
"00000000000000000000000000101100", -- $44
"00000000000000000000000000101101", -- $45
"00000000000000000000000000101110", -- $46
"00000000000000000000000000101111" -- $47
);
for i in 0 to 47 loop --intialization of ready signal for each location of physical register file.
if( i > 31 ) then
physical_reg_ready(i) <= '0';
else
physical_reg_ready(i) <= '1';
end if;
end loop;
elsif(Clk'event and Clk= '1') then
if(Cdb_Valid = '1')and(Cdb_PhyRegWrite = '1') then
physical_register_r(CONV_INTEGER(Cdb_RdPhyAddr))<= Cdb_RdData;
physical_reg_ready(CONV_INTEGER(Cdb_RdPhyAddr))<= '1';
end if;
if(Dis_RegWrite = '1') then
physical_reg_ready(CONV_INTEGER(Dis_NewRdPhyAddr))<= '0';--From DISPATCH
end if;
end if;
end process reg_file_read_write;
ready_signal : process(Cdb_RdPhyAddr , Dis_RsAddr , Cdb_Valid, Cdb_PhyRegWrite, Dis_RtAddr, physical_reg_ready)
begin
PhyReg_RsDataRdy <= '0' ;
PhyReg_RtDataRdy <= '0' ;
if( Cdb_RdPhyAddr = Dis_RsAddr and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1') then--CDBRegWrite
PhyReg_RsDataRdy <= '1';
else
PhyReg_RsDataRdy <= physical_reg_ready(CONV_INTEGER(Dis_RsAddr));
end if;
if( Cdb_RdPhyAddr = Dis_RtAddr and Cdb_Valid = '1' and Cdb_PhyRegWrite = '1') then--CDBRegWrite
PhyReg_RtDataRdy <= '1';
else
PhyReg_RtDataRdy <= physical_reg_ready(CONV_INTEGER(Dis_RtAddr));
end if;
end process ready_signal;
end regfile; | gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo/simulation/fg_tb_top.vhd | 2 | 5679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 69
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/i_fetch_test_stream_jal_jr_factorial_simple.vhd | 3 | 8759 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $6 : F0
-- $29: contains fixed bottom of stack for $31 values
-- The program calculates factorial of the number n
-- addi $4, $0, n ---put factorial candidate in $4
-- addi $3, $0, n ---put factorial candidate in $3
-- slt $5, $4, $2 ---check if no. is zero or one
-- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1
-- add $5, $1, $0 ---no. is 0 or 1, ans is 1
-- jump exit1 --- exit the code. $5 has final ans.
-- skiptwo: jal subroutine ---calculate factorial. goto function.
-- add $5, $3, $0 ---store final ans. in $5
-- exit1: jr $6 ---jump to exit
-- subroutine:
-- addi $29, $29, -4 --decrement address
-- sw $31,0($29) --put contents of $31 into location pointed by $29
-- sub $4, $4, $1 ---$4=$4 - 1
-- mul $3, $3, $4 ---$3=$3 * $4
-- beq $1, $4, outofloop ---check if $4 has reached 1
-- jal subroutine; --- if $4 /= 1, do 1 more iteration
-- outofloop: lw $31,0($29)
-- addi $29, $29, 4
-- jr $31 ---start exiting the loop
--($6):
-- sw $5, 0($29) -- this sw stores final ans to mem
-- add $4,$2,$2 -- load 4 into $4
-- lw $4, 0($4) -- add large latency in order to stop completion
-- add $4, $4, $4
-- add $4, $4, $4
-- add $4, $4, $4
-- add $4, $4, $4
-- jr $4
--($4):
-- exit
--- EXPECTED RESULT----
-- the stream calculates factorial 8 and puts it in $5
-- $5 is mapped to physical reg 37
-- Physical register 37 should be 40320 (d) = 9D80 (H)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"14A10002_0082282A_20030008_20040008", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi
X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add
X"00812022_AFBF0000_23BDFFFC_08000020", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump
X"00000020_00000020_10240005_00641819", -- Loc 3C, 38, 34, 30 nop_nop_beq_mul
X"00000020_0C000009_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_jal_nop_nop
X"8FBF0000_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50 lw_nop_nop_nop
X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 6C, 68, 64, 60 jr_addi
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/i_fetch_test_stream_min_finder.vhd | 3 | 8076 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
-- DATE OF LAST RIVISON: 07/28/08 BY PRASHESH
-- THE GIVEN PROGRAM FINDS MINIMUM NUMBER FROM THE FIRST 10 LOCATION OF DATA MEM
-- ADD $31, $0, $0 --$31 is set to X?00000000?.
-- ADD $11, $10, $0 --
-- ADD $30, $14, $30--
-- ADD $10, $0, $0 --
-- LW $2, 0($31) --Content of memory location 0 goes to $2
-- BEQ $A, $B, GOTO2-- $A is counter to track 10 numbers. -- INSTRUCTION WITH LABEL LOOP
-- ADD $31, $31, $4 --$31 is incremented by 4 so it can point to the next memory location
-- LW $3, 0($31) --Content of Memory location 2 goes to $3
-- SLT $5, $3, $2 --Check if ($3) < ($2)
-- ADD $10, $10, $1 --Increment counter $10
-- BEQ $5, $1, GOTO1-- If ($3) < ($2) then
-- JMP LOOP --If ($3) ? ($2) then
-- ADD $2, $3, $0 --Move ($3)-->($2) IF $3< $2 --INSTRUCTION WITH LABEL GOTO1
-- JMP LOOP --Jump to loop
-- SW $2,0($30) --Store ($2) at memory location 11. ($30)-->4 --INSTRUCTION WITH LABEL GOTO2
-- LW $6, 0($16) --Content of memory location 12 goes to $6 --> THIS BRANCH IS NEVER TAKEN
-- BEQ $2, $6, -4 --If ($2) = ($6) then ? this branch is always taken
-- JMP HERE -- LOCATION WITH LABEL HERE
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"00005020_01DEF020_01405820_0000F820", -- Loc 0C, 08, 04, 00
X"8FE30000_03E4F820_114B0008_8FE20000", -- Loc 1C, 18, 14, 10
X"08000005_10A10001_01415020_0062282A", -- Loc 2C, 28, 24, 20
X"8E060000_AFC20000_08000005_00601020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_08000011_1046FFF4", -- Loc 4C, 48, 44, 40
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/GC_fifo/simulation/fg_tb_top.vhd | 3 | 5679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 53
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_send_fifo/simulation/fg_tb_pkg.vhd | 1 | 11651 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo/simulation/fg_tb_pctrl.vhd | 2 | 16862 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & af_chk_i & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (EMPTY = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/storebuffer.vhd | 3 | 6386 | -------------------------------------------
-- CHECKED AND MODIFIED BY WALEED
-------------------------------------------
--UPDATED ON: 6/4/10
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity store_buffer is
port (
-- Global Signals
Clk : in std_logic ;
Resetb : in std_logic ;
--interface with ROB
Rob_SwAddr : in std_logic_vector (31 downto 0);
PhyReg_StoreData : in std_logic_vector (31 downto 0);
Rob_CommitMemWrite : in std_logic;
SB_Full : out std_logic;
SB_Stall : out std_logic;
Rob_TopPtr : in std_logic_vector(4 downto 0);
-- interface with lsq //addr buffer
SB_FlushSw : out std_logic;
SB_FlushSwTag : out std_logic_vector(1 downto 0);
SBTag_counter : out std_logic_vector (1 downto 0);
--interface with Data Cache Emulator
SB_DataDmem : out std_logic_vector (31 downto 0);
SB_AddrDmem : out std_logic_vector (31 downto 0);
SB_DataValid : out std_logic;
DCE_WriteBusy : in std_logic;
DCE_WriteDone : in std_logic
);
end store_buffer;
architecture struct of store_buffer is
type array_4_32 is array (0 to 3) of std_logic_vector(31 downto 0);
type array_4_2 is array (0 to 3) of std_logic_vector(1 downto 0);
type array_4_1 is array (0 to 3) of std_logic;
signal counter : std_logic_vector (1 downto 0);
signal addr, data : array_4_32;
signal valid : array_4_1;
signal SBTag : array_4_2;
signal SBTag_temp: std_logic_vector (1 downto 0); -- The internal signal for SBTag_counter
signal SB_Full_temp, send_data : std_logic;
signal DCETag : std_logic_vector(1 downto 0);
begin
-- **************************************************************************************************
-- Store buffer (SB) has 4 entries: 0,1,2,3. Entry 3 holds the oldest store instruction that will write to cache next.
-- This is why at Reset, the counter signal is initialized to 3 so that we first fill entry 3.
-- Each SB entry in the store buffer has the following fields:
-- 1) 32 bit data field which holds the value of register $rt of store instructions.
-- 2) 32 bit address field to access data cache.
-- 3) valid bit: If valid bit is 0 then entry is free and can be used otherwise the entry is busy.
-- 4) 2 bit Tag field: The Tag field is used to flush the corresponding entry in the address buffer when the store instruction leaves the store buffer.
-- **************************************************************************************************
SB_Full_temp <= '1' when (counter = "00" and valid(0) = '1') else '0';
SB_Stall <= '1' when (DCE_WriteBusy = '1' and SB_Full_temp = '1') else '0';
SB_Full <= SB_Full_temp;
SB_DataDmem <= data(3);
SB_AddrDmem <= addr(3);
SB_DataValid <= valid(3);
SB_FlushSwTag <= DCEtag;
SB_FlushSw <= DCE_WriteDone;
send_data <= (not (DCE_WriteBusy) and valid(3)) ;
SBTag_counter <= SBTag_temp;
store_buffer_update: process (Clk, Resetb)
begin
if(Resetb = '0') then
counter <= "11";
SBTag_temp <= "00";
for I in 0 to 3 loop
valid(I) <= '0';
end loop;
elsif(clk'event and clk = '1') then
if (send_data = '1') then
for I in 3 downto 1 loop
valid(I) <= valid(I - 1);
addr(I) <= addr(I - 1);
data(I) <= data(I - 1);
SBTag(I) <= SBTag(I - 1);
DCETag <= SBTag(3);
end loop;
end if;
-- **************************************************************************************************
-- Task1: You have to complete the else condition below. This if statement is resposible for adding a new
-- store instruction to the store buffer. Notice that we first check if the instruction at the top
-- the ROB is a "SW" instruction and that the store buffer is not full.
-- Hint: send_data signal is used to indicate if the cache is busy writing the value of store in entry(3) to
-- the cache. You need to understand how the counter value is updated before you fill the else part.
-- Please read carefully the counter part at the end of the file.
-- **************************************************************************************************
if (Rob_CommitMemWrite = '1' and SB_Full_temp = '0') then
if(send_data = '0') then
valid(conv_integer(unsigned(counter))) <= '1';
addr(conv_integer(unsigned(counter))) <= Rob_SwAddr;
data(conv_integer(unsigned(counter))) <= PhyReg_StoreData;
SBTag(conv_integer(unsigned(counter))) <= SBTag_temp;
SBTag_temp <= SBTag_temp + 1;
else
-- Add your code for Task1 here
--if (send_data = '1') then --above for loop will shift SB entries up
--update new SB entry
--counter stays the same
valid(conv_integer(unsigned(counter + '1'))) <= '1';
addr(conv_integer(unsigned(counter + '1'))) <= Rob_SwAddr;
data(conv_integer(unsigned(counter + '1'))) <= PhyReg_StoreData;
SBTag(conv_integer(unsigned(counter + '1'))) <= SBTag_temp;
SBTag_temp <= SBTag_temp + 1;
---------------------------------
end if;
elsif (Rob_CommitMemWrite = '0') then
if(send_data = '1') then
valid(0) <= '0';
end if;
end if;
-- **************************************************************************************************
-- We use a 2-bit up/down saturating counter to point to the next free entry in the store buffer. As we mentioned
-- the counter is initialized to "11". Whenever we add a new instruction to the store buffer, we decrement the counter
-- by 1 provided the counter value is greater than "00". On the other hand, when a store finish writing to the cache then
-- we are going to shift all store buffer entry in the up direction and hence we need to increment our counter provided that
-- that the counter is not equal to 3.
-- **************************************************************************************************
if (send_data = '1' and Rob_CommitMemWrite = '0' and not(counter="11") and not(SB_Full_temp = '1')) then
counter <= counter + 1;
elsif (send_data = '0' and Rob_CommitMemWrite = '1' and not(counter="00")) then
counter <= counter - '1' ;
end if;
end if;
end process;
end struct;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/i_fetch_test_stream_selective_flushing.vhd | 3 | 6758 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0182701B_008C6819_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"00232819_11C40006_AC0C0004_8C890000", -- Loc 1C, 18, 14, 10 -- corrected
X"0242601B_8C840000_00030820_00020820", -- Loc 2C, 28, 24, 20
X"00000020_00000020_AC0E0004_AC0C0004", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Date : 07/27/09
--0202601B DIV $12, $16, $2 $12 = 16/2 = 8
--006C6819 MUL $13, $4, $12 $13 = 8*4 = 32
--0182701B DIV $14, $12, $2 $14 = 8/2 = 4
--8C890000 LW $9, 0($4) $9 = dmem(1) = 10H
--AC0C0004 SD $12, 4($0) dmem(1) = 8
--11C40006 BEQ $14, $4, 6 IF $4 = $14, jump to the instruction after SD $12, 4($0) skips 6 instructions
--00232819 MUL $5, $1, $3 $5 = 1*3 = 3 * should be flushed*
--00020820 ADD $1, $0, $2 $1 = 0+2 = 2 *should be flushed*
--00030820 ADD $1, $0, $3 $1 = 0+3 = 3* should be flushed*
--8C840000 LD $4, 0($4) $4 = dmem(1) = 2 *should be flushed*
--0242601B DIV $12, $18, $2 $12 = 18/2 = 9 *should flushed*
--AC0C0004 SD $12, 4($0) dmem(1) = 9 *should flushed*
--AC0E0004 SD $14, 4($0) dmem(1) = 4
--************************************************
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/simulation/fg_tb_pkg.vhd | 1 | 11304 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT Command_FIFO_top IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/alu_r1.vhd | 1 | 4578 | ------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;-- for slt and not sltu
------------------------------------------------------------------------------
-- New instructions introduced in the Design
-- JR $Rs, JR $31, Bne $rt, $rs, offset, Addi $rd, $rs, Immediate
-- Other instructions same as previous design
------------------------------------------------------------------------------
entity ALU is
generic (
tag_width : integer := 6
);
port (
PhyReg_AluRsData : in std_logic_vector(31 downto 0);
PhyReg_AluRtData : in std_logic_vector(31 downto 0);
Iss_OpcodeAlu : in std_logic_vector(2 downto 0);
Iss_RobTagAlu : in std_logic_vector(4 downto 0);
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_BranchAddrAlu : in std_logic_vector(31 downto 0);
Iss_BranchAlu : in std_logic;
Iss_RegWriteAlu : in std_logic;
Iss_BranchUptAddrAlu : in std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : in std_logic;
Iss_JalInstAlu : in std_logic;
Iss_JrInstAlu : in std_logic;
Iss_JrRsInstAlu : in std_logic;
Iss_ImmediateAlu : in std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : in std_logic_vector(31 downto 0);
-- translate_on
Alu_RdData : out std_logic_vector(31 downto 0);
Alu_RdPhyAddr : out std_logic_vector(5 downto 0);
Alu_BranchAddr : out std_logic_vector(31 downto 0);
Alu_Branch : out std_logic;
Alu_BranchOutcome : out std_logic;
-- translate_off
Alu_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Alu_RobTag : out std_logic_vector(4 downto 0);
Alu_BranchUptAddr : out std_logic_vector( 2 downto 0 );
Alu_BranchPredict : out std_logic;
Alu_RdWrite : out std_logic;
Alu_JrFlush : out std_logic
);
end ALU;
architecture comput of ALU is
begin
Alu_RdPhyAddr <= Iss_RdPhyAddrAlu;
Alu_BranchPredict <= Iss_BranchPredictAlu;
Alu_BranchUptAddr <= Iss_BranchUptAddrAlu;
Alu_Branch <= Iss_BranchAlu;
Alu_RobTag <= Iss_RobTagAlu;
Alu_RdWrite <= Iss_RegWriteAlu;
-- translate_off
Alu_instruction <= Iss_instructionAlu;
-- translate_on
ALU_COMPUT: process (PhyReg_AluRtData, PhyReg_AluRsData, Iss_OpcodeAlu, Iss_BranchAddrAlu , Iss_JalInstAlu, Iss_JrRsInstAlu, Iss_JrInstAlu, Iss_ImmediateAlu)
begin
Alu_BranchOutcome <= '0';
Alu_BranchAddr <= Iss_BranchAddrAlu;
Alu_JrFlush <= '0';
case Iss_OpcodeAlu is
when "000" => -- Addition
Alu_RdData <= PhyReg_AluRsData + PhyReg_AluRtData;
when "001" => -- Subtraction
Alu_RdData <= PhyReg_AluRsData - PhyReg_AluRtData;
when "010" => -- And operation
Alu_RdData <= PhyReg_AluRsData and PhyReg_AluRtData;
when "011" => -- Or operation
Alu_RdData <= PhyReg_AluRsData or PhyReg_AluRtData;
when "100" => -- Add immediate
if (Iss_ImmediateAlu(15) = '1') then
Alu_RdData <= PhyReg_AluRsData + ("1111111111111111" & Iss_ImmediateAlu); --do sign extend
else
Alu_RdData <= PhyReg_AluRsData + ("0000000000000000" & Iss_ImmediateAlu);
end if;
when "101" => -- slt
Alu_RdData(31 downto 1) <= (others => '0');
if ( PhyReg_AluRsData < PhyReg_AluRtData ) then
Alu_RdData(0) <= '1';
else
Alu_RdData(0) <= '0';
end if;
when "110" => -- beq
if(PhyReg_AluRsData = PhyReg_AluRtData) then
Alu_BranchOutcome <= '1';
else
Alu_BranchOutcome <= '0';
end if;
Alu_RdData <= (others => '0');
when "111" => -- bne
if(PhyReg_AluRsData = PhyReg_AluRtData) then
Alu_BranchOutcome <= '0';
else
Alu_BranchOutcome <= '1';
end if;
Alu_RdData <= (others => '0');
when others =>
Alu_RdData <= (others => '0');
end case;
if(Iss_JalInstAlu = '1') then -- jal instruction
Alu_RdData <= Iss_BranchAddrAlu;
end if;
if(Iss_JrInstAlu = '1') then -- Jr $31
if(Iss_BranchAddrAlu = PhyReg_AluRsData) then
Alu_JrFlush <= '0';
else
Alu_BranchAddr <= PhyReg_AluRsData;
Alu_JrFlush <= '1';
end if;
end if;
if(Iss_JrRsInstAlu = '1') then -- Jr Rs
Alu_JrFlush <= '0';
Alu_BranchAddr <= PhyReg_AluRsData;
end if;
end process ALU_COMPUT;
end architecture comput; | gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_sort_selection_only.vhd | 3 | 10398 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/i_fetch_test_stream_sort_selection_only.vhd | 3 | 10398 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/i_fetch_test_stream_lws_sws.vhd | 3 | 6894 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (just lws and sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"00000020_AC1E0000_03C1F020_8C1E0000", -- Loc 0C, 08, 04, 00
X"00000020_AC1E0004_03C1F020_8C1E0004", -- Loc 1C, 18, 14, 10
X"00000020_AC1E0008_03C1F020_8C1E0008", -- Loc 2C, 28, 24, 20
X"00000020_AC1E000C_03C1F020_8C1E000C", -- Loc 3C, 38, 34, 30
X"00000020_AC1E0010_03C1F020_8C1E0010", -- Loc 4C, 48, 44, 40
X"00000020_AC1E0014_03C1F020_8C1E0014", -- Loc 5C, 58, 54, 50
X"00000020_AC1E0018_03C1F020_8C1E0018", -- Loc 6C, 68, 64, 60
X"00000020_AC1E001C_03C1F020_8C1E001C", -- Loc 7C, 78, 74, 70
-- Location:(00) | LW $30 ,0( $0) -- 8C1E0000
-- Location:(04) | Add $30, $30, $1 -- 03C1F020
-- Location:(08) | SW $30 ,0( $0) -- AC1E0000
-- Location:(0C) | Add $0, $0, $0 -- 00000020
-- Location:(10) | LW $30 ,4( $0) -- 8C1E0004
-- Location:(14) | Add $30, $30, $1 -- 03C1F020
-- Location:(18) | SW $30 ,4( $0) -- AC1E0004
-- Location:(1C) | Add $0, $0, $0 -- 00000020
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/i_fetch_test_stream_lws.vhd | 3 | 7214 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/spy_tb/top_tb_withIssUnitComp_r1.vhd | 1 | 8190 | -------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Reorder Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_Issue_Unit of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden Issue_Unit)
signal Resetb_gold :std_logic;
signal IssInt_Rdy_gold :std_logic;
signal IssMul_Rdy_gold :std_logic;
signal IssDiv_Rdy_gold :std_logic;
signal IssLsb_Rdy_gold :std_logic;
signal Div_ExeRdy_gold :std_logic;
signal Iss_Int_gold :std_logic;
signal Iss_Mult_gold :std_logic;
signal Iss_Div_gold :std_logic;
signal Iss_Lsb_gold :std_logic;
-- Signals for the student's DUT (Issue_Unit)
signal Resetb :std_logic;
signal IssInt_Rdy :std_logic;
signal IssMul_Rdy :std_logic;
signal IssDiv_Rdy :std_logic;
signal IssLsb_Rdy :std_logic;
signal Div_ExeRdy :std_logic;
signal Iss_Int :std_logic;
signal Iss_Mult :std_logic;
signal Iss_Div :std_logic;
signal Iss_Lsb :std_logic;
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
-- signals corresponding to Instruction memory
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component issue_unit
port (
Clk : in std_logic;
Resetb : in std_logic;
IssInt_Rdy : in std_logic;
IssMul_Rdy : in std_logic;
IssDiv_Rdy : in std_logic;
IssLsb_Rdy : in std_logic;
Div_ExeRdy : in std_logic;
Iss_Int : out std_logic;
Iss_Mult : out std_logic;
Iss_Div : out std_logic;
Iss_Lsb : out std_logic
);
end component issue_unit;
for Issue_Unit_UUT: issue_unit use entity work.issue_unit(behavioral);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
Issue_Unit_UUT: issue_unit
port map (
Clk =>Clk,
Resetb =>Resetb,
IssInt_Rdy =>IssInt_Rdy,
IssMul_Rdy =>IssMul_Rdy,
IssDiv_Rdy =>IssDiv_Rdy,
IssLsb_Rdy =>IssLsb_Rdy,
Div_ExeRdy =>Div_ExeRdy,
Iss_Int =>Iss_Int,
Iss_Mult =>Iss_Mult,
Iss_Div =>Iss_Div,
Iss_Lsb =>Iss_Lsb
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Issue_Unit only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Iss_Int_gold /=Iss_Int) then
write (my_outline, string'("ERROR! Iss_Int of TEST does not match Iss_Int_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_Mult_gold /= Iss_Mult) then
write (my_outline, string'("ERROR! Iss_Mult of TEST does not match Iss_Mult_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_Div_gold /= Iss_Div) then
write (my_outline, string'("ERROR! Iss_Div of TEST does not match Iss_Div_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_Lsb_gold /= Iss_Lsb ) then
write (my_outline, string'("ERROR! Iss_Lsb of TEST does not match Iss_Lsb_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/IssInt_Rdy","IssInt_Rdy",1,1);
enable_signal_spy("/UUT/IssInt_Rdy","IssInt_Rdy",0);
init_signal_spy("/UUT/IssMul_Rdy","IssMul_Rdy",1,1);
enable_signal_spy("/UUT/IssMul_Rdy","IssMul_Rdy",0);
init_signal_spy("/UUT/IssDiv_Rdy","IssDiv_Rdy",1,1);
enable_signal_spy("/UUT/IssDiv_Rdy","IssDiv_Rdy",0);
init_signal_spy("/UUT/IssLsb_Rdy","IssLsb_Rdy",1,1);
enable_signal_spy("/UUT/IssLsb_Rdy","IssLsb_Rdy",0);
init_signal_spy("/UUT/Div_ExeRdy","Div_ExeRdy",1,1);
enable_signal_spy("/UUT/Div_ExeRdy","Div_ExeRdy",0);
--outputs--
init_signal_spy("/UUT/Iss_Int","Iss_Int_gold",1,1);
enable_signal_spy("/UUT/Iss_Int","Iss_Int_gold",0);
init_signal_spy("/UUT/Iss_Mult","Iss_Mult_gold",1,1);
enable_signal_spy("/UUT/Iss_Mult","Iss_Mult_gold",0);
init_signal_spy("/UUT/Iss_Div","Iss_Div_gold",1,1);
enable_signal_spy("/UUT/Iss_Div","Iss_Div_gold",0);
init_signal_spy("/UUT/Iss_Lsb","Iss_Lsb_gold",1,1);
enable_signal_spy("/UUT/Iss_Lsb","Iss_Lsb_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_Issue_Unit;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/ls_buffer_r1_NEW.vhd | 1 | 13503 | -- File: ls_buffer.vhd
--
-- Tomasulo 2009
-- load-store buffer (buffer after lsq before CDB/Issue Unit)
--UPDATED ON: 7/24/09
-- Rohit Goel , Gandhi Puvvada
-- University of Southern California
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------------------------------------------------------------------
-- Originally we wanted to have a few location FIFO for the ls buffer.
-- As we ran out of time, we made a single location buffer but we retained
-- handhsake control signals on both sides of the buffer (the LSQ side and the
-- issue unit side) so that we can easily replace this with a FIFO later.
-- The selective flusing makes it a queue like LSQ (and not a pure FIFO) -- Gandhi
------------------------------------------------------------------------------
entity ls_buffer is
port (
Clk : in std_logic;
Resetb : in std_logic;
-- from ROB -- for fulsing the instruction in this buffer if appropriate.
Cdb_Flush : in std_logic ;
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector (4 downto 0 ) ;
-- interface with lsq
Iss_LdStReady : in std_logic ;
Iss_LdStOpcode : in std_logic ; -- 1 = lw , 0 = sw
Iss_LdStRobTag : in std_logic_vector(4 downto 0);
Iss_LdStAddr : in std_logic_vector(31 downto 0);
Iss_LdStData : in std_logic_vector(31 downto 0);-- data to be written to memory in the case of sw
Iss_LdStPhyAddr : in std_logic_vector(5 downto 0);
-- translate_off
DCE_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : in std_logic_vector(31 downto 0);
-- translate_on
---- interface with data cache emulator ----------------
DCE_PhyAddr : in std_logic_vector(5 downto 0);
DCE_Opcode : in std_logic ;
DCE_RobTag : in std_logic_vector(4 downto 0);
DCE_Addr : in std_logic_vector(31 downto 0);
DCE_MemData: in std_logic_vector (31 downto 0 ) ; -- data from data memory in the case of lw
DCE_ReadDone : in std_logic ; -- data memory (data cache) reporting that read finished -- from ls_buffer_ram_reg_array -- instance name DataMem
Lsbuf_LsqTaken : out std_logic; -- handshake signal to ls_queue
Lsbuf_DCETaken : out std_logic; -- handshake signal to ls_queue
Lsbuf_Full : out std_logic; -- handshake signal to ls_queue
-- interface with issue unit
-- from load buffer and store word
-- translate_off
Lsbuf_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Lsbuf_Ready : out std_logic ;
------------- changed as per CDB -------------
Lsbuf_Data : out std_logic_vector(31 downto 0);
Lsbuf_PhyAddr : out std_logic_vector(5 downto 0);
Lsbuf_RobTag : out std_logic_vector(4 downto 0) ;
Lsbuf_SwAddr : out std_logic_vector(31 downto 0);
Lsbuf_RdWrite : out std_logic;
------------------------------------------------------------
Iss_Lsb : in std_logic -- return signal from the issue unit
);
end ls_buffer;
architecture struct of ls_buffer is
type array_4_5 is array (0 to 3) of std_logic_vector(4 downto 0) ; --TAG
type array_4_6 is array (0 to 3) of std_logic_vector(5 downto 0) ;
type array_4_32 is array (0 to 3) of std_logic_vector(31 downto 0) ; --DATA
signal LsBufInstValid , LsBufInstValidTemp : std_logic_vector (3 downto 0) ; -- one bit for each location
signal LsBufOpcode : std_logic_vector ( 3 downto 0) ;
signal LsbufRobTag : array_4_5 ;
signal LsBufPhyAddr : array_4_6;
signal LsBufData , LsBufSwAddr :array_4_32;
-- translate_off
signal LsBufInstruction : array_4_32 ; -- [63:32] = address; [31:0] = data
-- translate_on
signal lsq_incoming_Depth : std_logic_vector( 4 downto 0 ) ; -- depth of incoming instruction from lsque or data emulator
signal dce_incoming_Depth : std_logic_vector( 4 downto 0 ) ; -- depth of incoming instruction from lsque or data emulator
signal lsq_flush , dce_flush : std_logic;
signal BufDepth : array_4_5 ; -- depth of each location of FIFO
signal wr_ptr , rd_ptr , wr_ptr_temp , rd_ptr_temp: std_logic_vector (2 downto 0) ; -- 3 bit read and write pointers for 4 location FIFO
signal full_temp , shift_2 , shift_3: std_logic ;
begin
lsq_incoming_Depth <= unsigned(Iss_LdStRobTag) - unsigned(Rob_TopPtr) ; -- depth of the incoming instruction (coming from lsq)
dce_incoming_Depth <= unsigned(DCE_RobTag) - unsigned(Rob_TopPtr); -- depth of the incoming instruction (coming from lsq)
BufDepth(0) <= unsigned(LsbufRobTag(0)) - unsigned(Rob_TopPtr); -- depth of the currently residing instruction
BufDepth(1) <= unsigned(LsbufRobTag(1)) - unsigned(Rob_TopPtr);
BufDepth(2) <= unsigned(LsbufRobTag(2)) - unsigned(Rob_TopPtr);
BufDepth(3) <= unsigned(LsbufRobTag(3)) - unsigned(Rob_TopPtr);
-- out to issue unit
Lsbuf_Ready <= LsBufInstValid(conv_integer(rd_ptr_temp(1 downto 0)));
Lsbuf_RobTag <= LsbufRobTag(conv_integer(rd_ptr_temp(1 downto 0))) ;
Lsbuf_Data <= LsBufData(conv_integer(rd_ptr_temp(1 downto 0))) ;
Lsbuf_SwAddr <= LsBufSwAddr(conv_integer(rd_ptr_temp(1 downto 0))) ;
Lsbuf_RdWrite <= LsBufOpcode(conv_integer(rd_ptr_temp(1 downto 0))) ;
Lsbuf_PhyAddr <= LsBufPhyAddr(conv_integer(rd_ptr_temp(1 downto 0))) ;
-- translate_off
Lsbuf_instruction <= LsBufInstruction(conv_integer(rd_ptr_temp(1 downto 0))) ;
-- translate_on
process (Cdb_Flush , LsBufInstValid , BufDepth ,Cdb_RobDepth,lsq_incoming_depth,dce_incoming_depth)
begin
if (Cdb_Flush = '1') then
for I in 0 to 3 loop
if (BufDepth(I) > Cdb_RobDepth) then
LsBufInstValidTemp(I) <= '0' ; -- flush the entry in fifo
else
LsBufInstValidTemp(I) <= LsBufInstValid(I);
end if ;
end loop ;
if (lsq_incoming_depth > Cdb_RobDepth) then
lsq_flush <= '1';
else
lsq_flush <= '0';
end if ;
if (dce_incoming_depth > Cdb_RobDepth) then
dce_flush <= '1';
else
dce_flush <= '0';
end if ;
else
lsq_flush <= '0';
dce_flush <= '0';
for I in 0 to 3 loop
LsBufInstValidTemp(I) <= LsBufInstValid(I);
end loop ;
end if ; -- end of Cdb_Flush = 1
end process ;
----------------------------------------------------------
-- Process for calculating write and read pointer in case of flush
------------------------------------------------------------------
process(Cdb_Flush , LsBufInstValidTemp, wr_ptr, rd_ptr)
begin
shift_2 <= '0';
shift_3 <= '0';
if (Cdb_Flush = '1') then
case LsBufInstValidTemp(3 downto 0) is
when "0000" =>
wr_ptr_temp <= "000";
rd_ptr_temp <= "000";
when "0001" =>
wr_ptr_temp <= "001";
rd_ptr_temp <= "000";
when "0010" =>
wr_ptr_temp <= "010";
rd_ptr_temp <= "001";
when "0011" =>
wr_ptr_temp <= "010";
rd_ptr_temp <= "000";
when "0100" =>
wr_ptr_temp <= "011";
rd_ptr_temp <= "010";
when "0101" =>
wr_ptr_temp <= "010";
rd_ptr_temp <= "000";
shift_2 <= '1';
when "0110" =>
wr_ptr_temp <= "011";
rd_ptr_temp <= "001";
when "0111" =>
wr_ptr_temp <= "011";
rd_ptr_temp <= "000";
when "1000" =>
wr_ptr_temp <= "100";
rd_ptr_temp <= "011";
when "1001" =>
wr_ptr_temp <= "101";
rd_ptr_temp <= "011";
when "1010" =>
wr_ptr_temp <= "011";
rd_ptr_temp <= "001";
shift_3 <= '1';
when "1011" =>
wr_ptr_temp <= "110";
rd_ptr_temp <= "011";
when "1100" =>
wr_ptr_temp <= "100";
rd_ptr_temp <= "010";
when "1101" =>
wr_ptr_temp <= "101";
rd_ptr_temp <= "010";
when "1110" =>
wr_ptr_temp <= "100";
rd_ptr_temp <= "001";
when "1111" =>
wr_ptr_temp <= "100";
rd_ptr_temp <= "000";
when others =>
wr_ptr_temp <= wr_ptr;
rd_ptr_temp <= rd_ptr;
end case;
else
wr_ptr_temp <= wr_ptr;
rd_ptr_temp <= rd_ptr;
end if;
end process;
-----------------------------------------------------------------
-----------------------------------------------------------------------
--- process for generating full signal
------------------------------------------------------------------------
Lsbuf_Full <= full_temp;
process (wr_ptr_temp , rd_ptr_temp , Iss_Lsb )
begin
full_temp <= '0';
if ((wr_ptr_temp(1 downto 0) = rd_ptr_temp(1 downto 0)) and (wr_ptr_temp(2) /= rd_ptr_temp(2))) then
full_temp <= '1' ;
end if ;
if (Iss_Lsb = '1') then
full_temp <= '0' ;
end if ;
end process ;
----------------------------------------------------------------------------------------------
--- Process generating signals for lsq and dce telling if the data on their outputs is taken or not
----------------------------------------------------------------------------------------------
process (full_temp , dce_flush , lsq_flush , DCE_ReadDone , Iss_LdStReady , Iss_LdStOpcode)
begin
Lsbuf_DCETaken <= '0' ;
Lsbuf_LsqTaken <= '0';
if (full_temp = '0') then
if ( Iss_LdStReady = '1' and Iss_LdStOpcode = '0') then -- sw taken from lsq
Lsbuf_LsqTaken <= '1' ;
elsif (DCE_ReadDone = '1') then
Lsbuf_DCETaken <= '1' ;
else
Lsbuf_LsqTaken <= '0';
Lsbuf_DCETaken <= '0';
end if;
end if ;
end process;
-----------------------------------------------------------------------------------------------
process ( Clk , Resetb )
variable wr_i : integer;
variable rd_i : integer;
begin
if ( Resetb = '0' ) then
wr_ptr <= (others => '0') ;
rd_ptr <= (others => '0') ;
LsBufInstValid <= "0000" ;
LsBufOpcode <= (others => '0') ; -- 1 = lw, 0 = sw
elsif ( Clk'event and Clk = '1' ) then
wr_i := conv_integer(wr_ptr_temp(1 downto 0));
rd_i := conv_integer(rd_ptr_temp(1 downto 0));
wr_ptr <= wr_ptr_temp;
rd_ptr <= rd_ptr_temp;
for I in 0 to 3 loop
LsBufInstValid(I) <= LsBufInstValidTemp(I);
end loop;
if (shift_2 = '1') then
LsBufInstValid(1) <= LsBufInstValidTemp(2);
LsBufInstValid(2) <= '0';
LsBufOpcode(1) <= LsBufOpcode(2) ;
LsbufRobTag(1) <= LsbufRobTag(2);
LsBufData(1) <= LsBufData(2);
LsBufSwAddr(1) <= LsBufSwAddr(2);
LsBufPhyAddr(1) <= LsBufPhyAddr(2);
-- translate_off
LsBufInstruction(1) <= LsBufInstruction(2);
-- translate_on
end if ;
if (shift_3 = '1') then
LsBufInstValid(2) <= LsBufInstValidTemp(3);
LsBufInstValid(3) <= '0';
LsBufOpcode(2) <= LsBufOpcode(3) ;
LsbufRobTag(2) <= LsbufRobTag(3);
LsBufData(2) <= LsBufData(3);
LsBufSwAddr(2) <= LsBufSwAddr(3);
LsBufPhyAddr(2) <= LsBufPhyAddr(3);
-- translate_off
LsBufInstruction(2) <= LsBufInstruction(3);
-- translate_on
end if ;
if (Iss_Lsb = '1') then
rd_ptr <= rd_ptr_temp + 1;
LsBufInstValid(rd_i) <= '0' ;
end if;
if (full_temp = '0') then
if ( lsq_flush = '0' and Iss_LdStReady = '1' and Iss_LdStOpcode = '0') then
LsBufInstValid(wr_i) <= '1' ;
LsBufOpcode(wr_i) <= Iss_LdStOpcode;
LsbufRobTag(wr_i) <= Iss_LdStRobTag;
LsBufData(wr_i) <= Iss_LdStData;
LsBufSwAddr(wr_i) <= Iss_LdStAddr ;
LsBufPhyAddr(wr_i) <= Iss_LdStPhyAddr ;
-- translate_off
LsBufInstruction(wr_i) <= Iss_instructionLsq ;
-- translate_on
wr_ptr <= wr_ptr_temp + 1 ;
-- Lsbuf_LsqTaken <= '1';
elsif (dce_flush = '0' and DCE_ReadDone = '1') then
LsBufInstValid(wr_i) <= '1' ;
LsBufOpcode(wr_i) <= DCE_Opcode;
LsbufRobTag(wr_i) <= DCE_RobTag;
LsBufData(wr_i) <= DCE_MemData ;
LsBufSwAddr(wr_i) <= DCE_Addr ;
LsBufPhyAddr(wr_i) <= DCE_PhyAddr ;
-- translate_off
LsBufInstruction(wr_i) <= DCE_instruction ;
-- translate_on
wr_ptr <= wr_ptr_temp + 1 ;
-- Lsbuf_DCETaken <= '1';
end if ;
end if ; -- end of full_temp = '0'
end if ; -- end of Clk'event
--------------------------------------------------------
end process ;
end architecture struct;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_command_send_fifo/simulation/fg_tb_synth.vhd | 1 | 11717 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
Daverball/reconos | pcores/reconos_hwt_idle_v1_00_a/hdl/vhdl/reconos_hwt_idle.vhd | 2 | 1657 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_hwt_idle is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end entity reconos_hwt_idle;
architecture implementation of reconos_hwt_idle is
begin
OSIF_FIFO_Sw2Hw_RE <= '0';
OSIF_FIFO_Hw2Sw_WE <= '0';
OSIF_FIFO_Hw2Sw_Data <= (others => '0');
MEMIF_FIFO_Mem2Hwt_RE <= '0';
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
end architecture;
| gpl-2.0 |
Daverball/reconos | pcores/reconos_osif_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 7380 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A AXI slave which maps the FIFOs of the HWTs to
-- registers accessible from the AXI-Bus.
-- Reg0: Read data
-- Reg1: Write data
-- Reg2: Fill - number of elements in receive-FIFO
-- Reg3: Rem - free space in send-FIFO
--
-- REMARK: The FIFOs must have the same clock than the
-- AXI-Bus.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
C_NUM_FIFOS : integer := 1;
C_FIFO_WIDTH : integer := 32;
-- Bus protocol parameters
C_SLV_DWIDTH : integer := 32
);
port (
-- FIFO ports
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i# : in std_logic_vector(31 downto 0);
FIFO_S_Fill_#i# : in std_logic_vector(15 downto 0);
FIFO_S_Empty_#i# : in std_logic;
FIFO_S_RE_#i# : out std_logic;
FIFO_M_Data_#i# : out std_logic_vector(31 downto 0);
FIFO_M_Rem_#i# : in std_logic_vector(15 downto 0);
FIFO_M_Full_#i# : in std_logic;
FIFO_M_WE_#i# : out std_logic;
-- ## END GENERATE LOOP ##
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_Addr : in std_logic_vector(31 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_CS : in std_logic_vector(0 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
end entity user_logic;
architecture implementation of user_logic is
-- Signals for user logic slave model s/w accessible register
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_bus2ip_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_addr : std_logic_vector(31 downto 0);
signal slv_rnw : std_logic;
signal slv_cs : std_logic;
type fifo_bi_t is record
s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
s_fill : std_logic_vector(15 downto 0);
s_empty : std_logic;
s_re : std_logic;
m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
m_rem : std_logic_vector(15 downto 0);
m_full : std_logic;
m_we : std_logic;
end record;
signal s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : std_logic_vector(15 downto 0);
signal s_empty : std_logic;
signal s_re : std_logic;
signal m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_rem : std_logic_vector(15 downto 0);
signal m_full : std_logic;
signal m_we : std_logic;
-- Array which contains all connected FIFOs
type fifos_t is array(0 to C_NUM_FIFOS - 1) of fifo_bi_t;
signal fifos : fifos_t;
signal fifo_bi_select : integer range 0 to C_NUM_FIFOS - 1;
signal reg_select : integer range 0 to 3;
signal pad_31 : std_logic_vector(14 downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= Bus2Ip_Clk;
rst <= not Bus2IP_Resetn;
pad_31 <= (others => '0');
IP2Bus_Data <= slv_ip2bus_data;
slv_bus2ip_data <= Bus2IP_Data;
slv_addr <= Bus2IP_Addr;
slv_rnw <= Bus2IP_RNW;
slv_cs <= Bus2IP_CS(0);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
fifo_bi_select <= CONV_INTEGER(slv_addr(19 downto 4));
reg_select <= CONV_INTEGER(slv_addr(3 downto 2));
mux_proc : process(fifos,fifo_bi_select,pad_31,
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i#,FIFO_S_Fill_#i#,FIFO_S_Empty_#i#,
FIFO_M_Rem_#i#,FIFO_M_Full_#i#,
-- ## END GENERATE LOOP ##
s_re,m_data,m_we) is
begin
-- Assign FIFOs to array
-- ## BEGIN GENERATE LOOP ##
fifos(#i#).s_data <= FIFO_S_Data_#i#;
fifos(#i#).s_fill <= FIFO_S_Fill_#i#;
fifos(#i#).s_empty <= FIFO_S_Empty_#i#;
FIFO_S_RE_#i# <= fifos(#i#).s_re;
FIFO_M_Data_#i# <= fifos(#i#).m_data;
fifos(#i#).m_rem <= FIFO_M_Rem_#i#;
fifos(#i#).m_full <= FIFO_M_Full_#i#;
FIFO_M_WE_#i# <= fifos(#i#).m_we;
-- ## END GENERATE LOOP ##
-- default values for not connected ports
-- later assignments will override this defaults
for i in 0 to C_NUM_FIFOS - 1 loop
fifos(i).s_re <= '0';
fifos(i).m_we <= '0';
fifos(i).m_data <= (others => '0');
end loop;
s_data <= fifos(fifo_bi_select).s_data;
s_fill <= fifos(fifo_bi_select).s_fill;
s_empty <= fifos(fifo_bi_select).s_empty;
fifos(fifo_bi_select).s_re <= s_re;
fifos(fifo_bi_select).m_data <= m_data;
m_rem <= fifos(fifo_bi_select).m_rem;
m_full <= fifos(fifo_bi_select).m_full;
fifos(fifo_bi_select).m_we <= m_we;
end process;
slv_read_ack <= '1' when slv_cs = '1' and slv_rnw = '1' else '0';
slv_write_ack <= '1' when slv_cs = '1' and slv_rnw = '0' else '0';
-- REMARK: This is not totally right. Normally we need to
-- set the RE of the FIFO and read the next cycle.
-- Since we do not read data in the next cycle this
-- is totally fine.
s_re <= '1' when slv_cs = '1' and (reg_select = 0 and slv_rnw = '1') else '0';
m_we <= '1' when slv_cs = '1' and (reg_select = 1 and slv_rnw = '0') else '0';
bus_reg_read_proc : process(reg_select,s_data,
s_empty,s_fill,
m_full,m_rem) is
begin
case reg_select is
when 0 => slv_ip2bus_data <= s_data;
when 1 => slv_ip2bus_data <= (others => '0');
when 2 => slv_ip2bus_data <= s_empty & pad_31 & s_fill;
when 3 => slv_ip2bus_data <= m_full & pad_31 & m_rem;
end case;
end process bus_reg_read_proc;
bus_reg_write_proc : process(reg_select,slv_bus2ip_data) is
begin
case reg_select is
when 1 => m_data <= slv_bus2ip_data;
when others => m_data <= (others => '0');
end case;
end process bus_reg_write_proc;
end implementation;
| gpl-2.0 |
Daverball/reconos | demos/reconf_sort_matrix/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/hwt_matrixmul.vhd | 2 | 14921 | ------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
constant C_LINE_LEN_MATRIX : integer := 64;
-- Use the following line for testing purposes.
--constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_sa1_test1.vhd | 8 | 2573 | library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
-- doing nothing at the moment
constant N: integer range 0 to 16 := 4;
end package work6;
-- a 1-bit Moore-type adder to be used in
-- a serial adder FSM-driven architecture
-- ________ _____
-- a_i -->| |------>|D Q|---> s_o
-- b_i -->| FA1 | | |
-- | |--- | |
-- ---> |_______| | |_____|
--rst __|_______________________|
-- | | |
-- | | |
-- | | | ______
-- | | ---->|D Q|---
-- | | | | |
-- | | | | |
-- | | |_____| |
-- | |____________| |
-- |________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity sa1 is
port (clk, reset: in std_logic;
a_i, b_i: in std_logic;
s_o: out std_logic
);
end entity sa1;
architecture sa1_rtl of sa1 is
signal sum, carry, carry_reg: std_logic;
begin
a1: fa1 port map (c_i => carry_reg,
a_i => a_i,
b_i => b_i,
s_o => sum,
c_o => carry
);
f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o);
f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg);
end architecture sa1_rtl;
-- a one bit full adder written according to
-- textbook's boolean equations
library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
techee/ctags | Units/test.vhd.t/input.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
techee/ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/tbd_rr_base.vhd | 1 | 7425 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spi2rgb_pkg.all;
entity tbd_rr_base is
generic
(
use_sdram_pll : std_ulogic := '1'
);
port
(
clock_50mhz : in std_ulogic;
keys : in std_ulogic_vector(1 downto 0);
switches : in std_ulogic_vector(3 downto 0);
leds : out std_ulogic_vector(7 downto 0);
uart_rx : in std_ulogic;
uart_tx : out std_ulogic;
spi_cs : in std_ulogic_vector(1 downto 0);
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
spi_epcs_cs : out std_ulogic;
spi_epcs_clk : out std_ulogic;
spi_epcs_mosi : out std_ulogic;
spi_epcs_miso : in std_ulogic;
arReconf : in std_ulogic;
pwm_red : out std_ulogic;
pwm_green : out std_ulogic;
pwm_blue : out std_ulogic;
sdram_addr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_cke : out std_logic;
sdram_clk : out std_logic;
sdram_cs_n : out std_logic;
--sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dq : in std_logic_vector(15 downto 0);
sdram_dqm : out std_logic_vector(1 downto 0);
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_we_n : out std_logic
);
end tbd_rr_base;
architecture rtl of tbd_rr_base is
signal reset_done : std_ulogic := '0';
signal n_reset_async : std_logic;
signal inputs_unsynced : std_ulogic_vector(switches'length downto 0);
signal inputs_synced : std_ulogic_vector(inputs_unsynced'range);
signal inputs_synced_debounced : std_ulogic_vector(inputs_synced'range);
signal key_0_synced_debounced : std_ulogic;
signal switches_synced_debounced : std_ulogic_vector(switches'range);
signal spi_unsynced : std_ulogic_vector(2 downto 0);
signal spi_synced : std_ulogic_vector(2 downto 0);
signal spi_cs_user_synced : std_ulogic;
signal spi_clk_synced : std_ulogic;
signal spi_mosi_synced : std_ulogic;
signal spi2rgb_data : SPI2RGB_DATA_TYPE;
signal spi2rgb_valid_bits : std_ulogic_vector(SPI2RGB_NUM_DATA_BYTES - 1 downto 0);
begin
-- Reconfiguration unit
reconfUnit: entity work.altremotePulsed(rtl)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
reconf => arReconf
);
-- Give epcs64 signals to external user
-- No need to synchronize. Signals are not used within system clock
spi_epcs_cs <= spi_cs(0);
spi_epcs_clk <= spi_clk;
spi_epcs_mosi <= spi_mosi;
-- Important: MISO must not drive signal if epcs64 is not selected
spi_miso <= spi_epcs_miso when spi_cs(0) = '0' else 'Z';
-- Synchronize inputs
inputs_unsynced <= switches & keys(0);
key_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => inputs_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => inputs_unsynced,
synced_outputs => inputs_synced
);
-- Debounce inputs
key_debounce: entity work.input_debounce(rtl)
generic map
(
num_inputs => inputs_synced'length
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
synced_inputs => inputs_synced,
debounced_outputs => inputs_synced_debounced
);
key_0_synced_debounced <= inputs_synced_debounced(0);
switches_synced_debounced <= inputs_synced_debounced(inputs_synced_debounced'high downto 1);
-- Synchronize SPI
spi_unsynced <= spi_cs(1) & spi_clk & spi_mosi;
spi_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => spi_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => spi_unsynced,
synced_outputs => spi_synced
);
spi_cs_user_synced <= spi_synced(2);
spi_clk_synced <= spi_synced(1);
spi_mosi_synced <= spi_synced(0);
-- Hardware-is-alive-LED
hardware_is_alive_led: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 25E7
)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
output => leds(0)
);
-- SPI-Slave
spislave: entity work.spi2rgb(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
spi_clk => spi_clk_synced,
spi_mosi => spi_mosi_synced,
data => spi2rgb_data,
valid_bits => spi2rgb_valid_bits
);
-- RGB PWMs
pwmred: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(2),
data_valid => spi2rgb_valid_bits(2),
led_pwm => pwm_red
);
pwmgreen: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(1),
data_valid => spi2rgb_valid_bits(1),
led_pwm => pwm_green
);
pwmblue: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(0),
data_valid => spi2rgb_valid_bits(0),
led_pwm => pwm_blue
);
-- Reset
proc_reset: process(clock_50mhz)
begin
if clock_50mhz'event and clock_50mhz = '1' then
reset_done <= '1';
end if;
end process;
n_reset_async <= reset_done and keys(1);
end architecture rtl;
| gpl-2.0 |
ju994lo/syko_proj | reg_a.vhd | 1 | 922 | library ieee;
use ieee.std_logic_1164.all;
entity reg_a is
generic
(
LW : integer := 8
);
port
(
clk, ie, oe, reset : in std_logic;
data_in : in std_logic_vector(LW-1 downto 0);
data_out : out std_logic_vector(LW-1 downto 0)
);
end reg_a;
architecture behav of reg_a is
--signal reg: std_logic_vector(LW-1 downto 0);
begin
process(reset, clk, ie, oe)
variable reg : std_logic_vector(LW-1 downto 0);
begin
if falling_edge(clk) then
if(reset = '1') then
reg := "00000000";
elsif(ie = '1') then
reg := data_in;
elsif(oe = '1') then
data_out <= reg;
elsif (oe = '0') then
data_out <= (others => 'Z');
-- if(reset = '1') then
-- reg <= (others => '0');
-- elsif(ie = '1') then
-- reg <= data_in;
-- elsif(oe = '1') then
-- data_out <= reg;
-- elsif (oe = '0') then
-- data_out <= (others => 'Z');
end if;
end if;
end process;
end behav;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_sadd23_bit.vhd | 4 | 275 | library ieee;
use ieee.numeric_bit.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_smul23_stdlogic.vhd | 4 | 304 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
| gpl-2.0 |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/project/altremote/simulation/submodules/altremote_remote_update_0.vhd | 3 | 113598 | --altremote_update CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" check_app_pof="false" config_device_addr_width=24 DEVICE_FAMILY="Cyclone IV E" in_data_width=24 is_epcq="false" operation_mode="remote" out_data_width=29 busy clock data_in data_out param read_param read_source reconfig reset reset_timer write_param
--VERSION_BEGIN 14.0 cbx_altremote_update 2014:06:05:09:45:41:SJ cbx_cycloneii 2014:06:05:09:45:41:SJ cbx_lpm_add_sub 2014:06:05:09:45:41:SJ cbx_lpm_compare 2014:06:05:09:45:41:SJ cbx_lpm_counter 2014:06:05:09:45:41:SJ cbx_lpm_decode 2014:06:05:09:45:41:SJ cbx_lpm_shiftreg 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_nightfury 2014:06:05:09:45:41:SJ cbx_stratix 2014:06:05:09:45:41:SJ cbx_stratixii 2014:06:05:09:45:41:SJ VERSION_END
-- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY cycloneive;
USE cycloneive.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = cycloneive_rublock 1 lpm_counter 2 reg 62
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altremote_remote_update_0 IS
PORT
(
busy : OUT STD_LOGIC;
clock : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => '0');
data_out : OUT STD_LOGIC_VECTOR (28 DOWNTO 0);
param : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
read_param : IN STD_LOGIC := '0';
read_source : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
reconfig : IN STD_LOGIC := '0';
reset : IN STD_LOGIC;
reset_timer : IN STD_LOGIC := '0';
write_param : IN STD_LOGIC := '0'
);
END altremote_remote_update_0;
ARCHITECTURE RTL OF altremote_remote_update_0 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103";
SIGNAL check_busy_dffe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dffe1a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe1a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe1a_ena : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL dffe2a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe2a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe2a2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe2a_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL dffe3a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe3a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe3a2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe3a_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL dffe7a : STD_LOGIC_VECTOR(28 DOWNTO 0)
-- synopsys translate_off
:= "00000000000000000000000000000"
-- synopsys translate_on
;
SIGNAL wire_dffe7a_ena : STD_LOGIC_VECTOR(28 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dffe8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe9a : STD_LOGIC_VECTOR(6 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_dffe9a_ena : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL idle_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL idle_write_wait : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_address_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_read_address_state_ena : STD_LOGIC;
SIGNAL read_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_init_counter_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_post_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_pre_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_source_update_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_init_counter_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_load_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_post_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_pre_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_source_update_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_wait_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_cntr5_w_lg_w_q_range39w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_w_lg_w_q_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cntr5_w_q_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr6_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_sd4_regout : STD_LOGIC;
SIGNAL wire_w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1072w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1054w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1049w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1076w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1082w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1061w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1098w1099w1100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1098w1124w1125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1110w1111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1065w1066w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1065w1133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1084w1092w1093w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1084w1085w1086w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1031w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1031w1051w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1045w1046w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1045w1079w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1057w1105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1057w1058w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1118w1119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1118w1141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1098w1099w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1098w1124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1064w1110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1064w1065w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1084w1092w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1084w1085w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1028w1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1028w1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1056w1057w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1056w1118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_idle1179w1180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_param_range109w110w111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1098w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1064w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1084w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1028w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1056w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_source_update1237w1238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_idle1179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_data1196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init_counter1192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_post1202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_pre_data1191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rublock_regout_reg1243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_data1214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init_counter1211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_post_data1220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_pre_data1210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range109w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1097w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1063w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_w4w_range1264w1265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_w4w_range1268w1269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bit_counter_all_done1213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bit_counter_param_start_match1190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_idle1160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_data1155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init1159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init_counter1157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_post1154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_pre_data1156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_source_update1158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_update_done1187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_select_shift_nloop1242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1w1178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2w1177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w8w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_width_counter_all_done1194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_width_counter_param_width_match1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_data1149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init1153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init_counter1152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_load1147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_post_data1148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_pre_data1150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_source_update1151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_wait1146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_wsource_update_done1207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range107w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1025w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1026w1027w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1029w1030w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1032w1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1041w1102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_idle1179w1180w1181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address287w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address342w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address347w348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address352w353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address357w358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address362w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address367w368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address372w373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address377w378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address382w383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address292w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address387w388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address392w393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address397w398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address402w403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address407w408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address412w413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address417w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address297w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address302w303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address307w308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address312w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address317w318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address322w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address327w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address332w333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_w4w_range1264w1265w1266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_w4w_range1268w1269w1270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_source_update1237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL bit_counter_all_done : STD_LOGIC;
SIGNAL bit_counter_clear : STD_LOGIC;
SIGNAL bit_counter_enable : STD_LOGIC;
SIGNAL bit_counter_param_start : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL bit_counter_param_start_match : STD_LOGIC;
SIGNAL combine_port : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL global_gnd : STD_LOGIC;
SIGNAL global_vcc : STD_LOGIC;
SIGNAL idle : STD_LOGIC;
SIGNAL param_decoder_param_latch : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL param_decoder_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL power_up : STD_LOGIC;
SIGNAL read_address : STD_LOGIC;
SIGNAL read_data : STD_LOGIC;
SIGNAL read_init : STD_LOGIC;
SIGNAL read_init_counter : STD_LOGIC;
SIGNAL read_post : STD_LOGIC;
SIGNAL read_pre_data : STD_LOGIC;
SIGNAL read_source_update : STD_LOGIC;
SIGNAL rsource_load : STD_LOGIC;
SIGNAL rsource_parallel_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rsource_serial_out : STD_LOGIC;
SIGNAL rsource_shift_enable : STD_LOGIC;
SIGNAL rsource_state_par_ini : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rsource_update_done : STD_LOGIC;
SIGNAL rublock_captnupdt : STD_LOGIC;
SIGNAL rublock_clock : STD_LOGIC;
SIGNAL rublock_reconfig : STD_LOGIC;
SIGNAL rublock_reconfig_st : STD_LOGIC;
SIGNAL rublock_regin : STD_LOGIC;
SIGNAL rublock_regout : STD_LOGIC;
SIGNAL rublock_regout_reg : STD_LOGIC;
SIGNAL rublock_shiftnld : STD_LOGIC;
SIGNAL select_shift_nloop : STD_LOGIC;
SIGNAL shift_reg_clear : STD_LOGIC;
SIGNAL shift_reg_load_enable : STD_LOGIC;
SIGNAL shift_reg_serial_in : STD_LOGIC;
SIGNAL shift_reg_serial_out : STD_LOGIC;
SIGNAL shift_reg_shift_enable : STD_LOGIC;
SIGNAL start_bit_decoder_out : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL start_bit_decoder_param_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL w1w : STD_LOGIC;
SIGNAL w2w : STD_LOGIC;
SIGNAL w4w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL w53w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL w83w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL w8w : STD_LOGIC;
SIGNAL width_counter_all_done : STD_LOGIC;
SIGNAL width_counter_clear : STD_LOGIC;
SIGNAL width_counter_enable : STD_LOGIC;
SIGNAL width_counter_param_width : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_counter_param_width_match : STD_LOGIC;
SIGNAL width_decoder_out : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_decoder_param_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL write_data : STD_LOGIC;
SIGNAL write_init : STD_LOGIC;
SIGNAL write_init_counter : STD_LOGIC;
SIGNAL write_load : STD_LOGIC;
SIGNAL write_post_data : STD_LOGIC;
SIGNAL write_pre_data : STD_LOGIC;
SIGNAL write_source_update : STD_LOGIC;
SIGNAL write_wait : STD_LOGIC;
SIGNAL wsource_state_par_ini : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wsource_update_done : STD_LOGIC;
SIGNAL wire_w_data_in_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1026w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_parallel_in_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_state_par_ini_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_state_par_ini_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_w4w_range1264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_w4w_range1268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_wsource_state_par_ini_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_wsource_state_par_ini_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT cycloneive_rublock
PORT
(
captnupdt : IN STD_LOGIC;
clk : IN STD_LOGIC;
rconfig : IN STD_LOGIC;
regin : IN STD_LOGIC;
regout : OUT STD_LOGIC;
rsttimer : IN STD_LOGIC;
shiftnld : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wire_w1042w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1072w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1054w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1049w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1116w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1076w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1082w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1139w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1108w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1061w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1131w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1122w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1144w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w(0) <= wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w(0) <= wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w(0) <= wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w(0) <= wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w(0) <= wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w(0) <= wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w(0) <= wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w(0) <= wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w(0) <= wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w(0) <= wire_w_lg_w_lg_w1098w1099w1100w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w(0) <= wire_w_lg_w_lg_w1098w1124w1125w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w(0) <= wire_w_lg_w_lg_w1064w1110w1111w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w(0) <= wire_w_lg_w_lg_w1064w1065w1066w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w(0) <= wire_w_lg_w_lg_w1064w1065w1133w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w(0) <= wire_w_lg_w_lg_w1084w1092w1093w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w(0) <= wire_w_lg_w_lg_w1084w1085w1086w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w(0) <= wire_w_lg_w_lg_w1028w1031w1034w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w(0) <= wire_w_lg_w_lg_w1028w1031w1034w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w(0) <= wire_w_lg_w_lg_w1028w1031w1051w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) <= wire_w_lg_w_lg_w1028w1045w1046w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w(0) <= wire_w_lg_w_lg_w1028w1045w1046w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w(0) <= wire_w_lg_w_lg_w1028w1045w1079w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w(0) <= wire_w_lg_w_lg_w1028w1045w1079w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w(0) <= wire_w_lg_w_lg_w1056w1057w1105w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w(0) <= wire_w_lg_w_lg_w1056w1057w1058w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w(0) <= wire_w_lg_w_lg_w1056w1057w1058w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w(0) <= wire_w_lg_w_lg_w1056w1118w1119w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w(0) <= wire_w_lg_w_lg_w1056w1118w1141w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1098w1099w1100w(0) <= wire_w_lg_w1098w1099w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1098w1124w1125w(0) <= wire_w_lg_w1098w1124w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1064w1110w1111w(0) <= wire_w_lg_w1064w1110w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1064w1065w1066w(0) <= wire_w_lg_w1064w1065w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1064w1065w1133w(0) <= wire_w_lg_w1064w1065w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1084w1092w1093w(0) <= wire_w_lg_w1084w1092w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1084w1085w1086w(0) <= wire_w_lg_w1084w1085w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1028w1031w1034w(0) <= wire_w_lg_w1028w1031w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1028w1031w1051w(0) <= wire_w_lg_w1028w1031w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1028w1045w1046w(0) <= wire_w_lg_w1028w1045w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1028w1045w1079w(0) <= wire_w_lg_w1028w1045w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1056w1057w1105w(0) <= wire_w_lg_w1056w1057w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1056w1057w1058w(0) <= wire_w_lg_w1056w1057w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1056w1118w1119w(0) <= wire_w_lg_w1056w1118w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1056w1118w1141w(0) <= wire_w_lg_w1056w1118w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range171w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range178w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range185w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range192w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range199w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range206w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range213w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range220w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range227w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range234w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range241w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range248w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range255w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range262w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range114w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range122w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range129w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range136w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range143w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range150w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range157w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range164w(0);
wire_w_lg_w1098w1099w(0) <= wire_w1098w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1098w1124w(0) <= wire_w1098w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1064w1110w(0) <= wire_w1064w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1064w1065w(0) <= wire_w1064w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1084w1092w(0) <= wire_w1084w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1084w1085w(0) <= wire_w1084w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1028w1031w(0) <= wire_w1028w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w_lg_w1028w1045w(0) <= wire_w1028w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w1056w1057w(0) <= wire_w1056w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w_lg_w1056w1118w(0) <= wire_w1056w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w_lg_idle1179w1180w(0) <= wire_w_lg_idle1179w(0) AND wire_w_lg_w2w1177w(0);
wire_w_lg_w_lg_w_param_range109w110w111w(0) <= wire_w_lg_w_param_range109w110w(0) AND wire_w_lg_w_param_range105w106w(0);
wire_w1098w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1097w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w1064w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w1084w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w113w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range104w(0);
wire_w184w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range171w(0);
wire_w191w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range178w(0);
wire_w198w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range185w(0);
wire_w205w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range192w(0);
wire_w212w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range199w(0);
wire_w219w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range206w(0);
wire_w226w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range213w(0);
wire_w233w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range220w(0);
wire_w240w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range227w(0);
wire_w247w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range234w(0);
wire_w121w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range120w(0);
wire_w254w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range241w(0);
wire_w261w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range248w(0);
wire_w128w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range114w(0);
wire_w135w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range122w(0);
wire_w142w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range129w(0);
wire_w149w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range136w(0);
wire_w156w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range143w(0);
wire_w163w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range150w(0);
wire_w170w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range157w(0);
wire_w177w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range164w(0);
wire_w_lg_w_lg_read_address278w279w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range277w(0);
wire_w_lg_w_lg_read_address278w326w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range325w(0);
wire_w_lg_w_lg_read_address278w331w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range330w(0);
wire_w_lg_w_lg_read_address278w336w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range335w(0);
wire_w_lg_w_lg_read_address278w341w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range340w(0);
wire_w_lg_w_lg_read_address278w346w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range345w(0);
wire_w_lg_w_lg_read_address278w351w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range350w(0);
wire_w_lg_w_lg_read_address278w356w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range355w(0);
wire_w_lg_w_lg_read_address278w361w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range360w(0);
wire_w_lg_w_lg_read_address278w366w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range365w(0);
wire_w_lg_w_lg_read_address278w371w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range370w(0);
wire_w_lg_w_lg_read_address278w283w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range282w(0);
wire_w_lg_w_lg_read_address278w376w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range375w(0);
wire_w_lg_w_lg_read_address278w381w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range380w(0);
wire_w_lg_w_lg_read_address278w386w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range385w(0);
wire_w_lg_w_lg_read_address278w391w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range390w(0);
wire_w_lg_w_lg_read_address278w396w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range395w(0);
wire_w_lg_w_lg_read_address278w401w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range400w(0);
wire_w_lg_w_lg_read_address278w406w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range405w(0);
wire_w_lg_w_lg_read_address278w411w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range410w(0);
wire_w_lg_w_lg_read_address278w416w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range415w(0);
wire_w_lg_w_lg_read_address278w286w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range285w(0);
wire_w_lg_w_lg_read_address278w291w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range290w(0);
wire_w_lg_w_lg_read_address278w296w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range295w(0);
wire_w_lg_w_lg_read_address278w301w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range300w(0);
wire_w_lg_w_lg_read_address278w306w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range305w(0);
wire_w_lg_w_lg_read_address278w311w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range310w(0);
wire_w_lg_w_lg_read_address278w316w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range315w(0);
wire_w_lg_w_lg_read_address278w321w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range320w(0);
wire_w_lg_w_lg_rsource_load13w14w(0) <= wire_w_lg_rsource_load13w(0) AND dffe1a1;
wire_w_lg_w_lg_rsource_load13w21w(0) <= wire_w_lg_rsource_load13w(0) AND dffe2a1;
wire_w_lg_w_lg_rsource_load13w25w(0) <= wire_w_lg_rsource_load13w(0) AND dffe2a2;
wire_w_lg_w_lg_rsource_load13w31w(0) <= wire_w_lg_rsource_load13w(0) AND dffe3a1;
wire_w_lg_w_lg_rsource_load13w35w(0) <= wire_w_lg_rsource_load13w(0) AND dffe3a2;
wire_w_lg_w_lg_shift_reg_load_enable101w103w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(1);
wire_w_lg_w_lg_shift_reg_load_enable101w176w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(10);
wire_w_lg_w_lg_shift_reg_load_enable101w183w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(11);
wire_w_lg_w_lg_shift_reg_load_enable101w190w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(12);
wire_w_lg_w_lg_shift_reg_load_enable101w197w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(13);
wire_w_lg_w_lg_shift_reg_load_enable101w204w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(14);
wire_w_lg_w_lg_shift_reg_load_enable101w211w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(15);
wire_w_lg_w_lg_shift_reg_load_enable101w218w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(16);
wire_w_lg_w_lg_shift_reg_load_enable101w225w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(17);
wire_w_lg_w_lg_shift_reg_load_enable101w232w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(18);
wire_w_lg_w_lg_shift_reg_load_enable101w239w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(19);
wire_w_lg_w_lg_shift_reg_load_enable101w119w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(2);
wire_w_lg_w_lg_shift_reg_load_enable101w246w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(20);
wire_w_lg_w_lg_shift_reg_load_enable101w253w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(21);
wire_w_lg_w_lg_shift_reg_load_enable101w260w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(22);
wire_w_lg_w_lg_shift_reg_load_enable101w127w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(3);
wire_w_lg_w_lg_shift_reg_load_enable101w134w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(4);
wire_w_lg_w_lg_shift_reg_load_enable101w141w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(5);
wire_w_lg_w_lg_shift_reg_load_enable101w148w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(6);
wire_w_lg_w_lg_shift_reg_load_enable101w155w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(7);
wire_w_lg_w_lg_shift_reg_load_enable101w162w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(8);
wire_w_lg_w_lg_shift_reg_load_enable101w169w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(9);
wire_w1028w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) AND wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0);
wire_w1056w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) AND wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_lg_read_source_update1237w1238w(0) <= wire_w_lg_read_source_update1237w(0) AND rsource_serial_out;
wire_w_lg_idle1179w(0) <= idle AND wire_w_lg_w1w1178w(0);
wire_w_lg_read_address287w(0) <= read_address AND wire_dffe7a_w_q_range277w(0);
wire_w_lg_read_address337w(0) <= read_address AND wire_dffe7a_w_q_range325w(0);
wire_w_lg_read_address342w(0) <= read_address AND wire_dffe7a_w_q_range330w(0);
wire_w_lg_read_address347w(0) <= read_address AND wire_dffe7a_w_q_range335w(0);
wire_w_lg_read_address352w(0) <= read_address AND wire_dffe7a_w_q_range340w(0);
wire_w_lg_read_address357w(0) <= read_address AND wire_dffe7a_w_q_range345w(0);
wire_w_lg_read_address362w(0) <= read_address AND wire_dffe7a_w_q_range350w(0);
wire_w_lg_read_address367w(0) <= read_address AND wire_dffe7a_w_q_range355w(0);
wire_w_lg_read_address372w(0) <= read_address AND wire_dffe7a_w_q_range360w(0);
wire_w_lg_read_address377w(0) <= read_address AND wire_dffe7a_w_q_range365w(0);
wire_w_lg_read_address382w(0) <= read_address AND wire_dffe7a_w_q_range370w(0);
wire_w_lg_read_address292w(0) <= read_address AND wire_dffe7a_w_q_range282w(0);
wire_w_lg_read_address387w(0) <= read_address AND wire_dffe7a_w_q_range375w(0);
wire_w_lg_read_address392w(0) <= read_address AND wire_dffe7a_w_q_range380w(0);
wire_w_lg_read_address397w(0) <= read_address AND wire_dffe7a_w_q_range385w(0);
wire_w_lg_read_address402w(0) <= read_address AND wire_dffe7a_w_q_range390w(0);
wire_w_lg_read_address407w(0) <= read_address AND wire_dffe7a_w_q_range395w(0);
wire_w_lg_read_address412w(0) <= read_address AND wire_dffe7a_w_q_range400w(0);
wire_w_lg_read_address417w(0) <= read_address AND wire_dffe7a_w_q_range405w(0);
wire_w_lg_read_address297w(0) <= read_address AND wire_dffe7a_w_q_range285w(0);
wire_w_lg_read_address302w(0) <= read_address AND wire_dffe7a_w_q_range290w(0);
wire_w_lg_read_address307w(0) <= read_address AND wire_dffe7a_w_q_range295w(0);
wire_w_lg_read_address312w(0) <= read_address AND wire_dffe7a_w_q_range300w(0);
wire_w_lg_read_address317w(0) <= read_address AND wire_dffe7a_w_q_range305w(0);
wire_w_lg_read_address322w(0) <= read_address AND wire_dffe7a_w_q_range310w(0);
wire_w_lg_read_address327w(0) <= read_address AND wire_dffe7a_w_q_range315w(0);
wire_w_lg_read_address332w(0) <= read_address AND wire_dffe7a_w_q_range320w(0);
wire_w_lg_read_data1196w(0) <= read_data AND wire_w_lg_width_counter_param_width_match1195w(0);
wire_w_lg_read_init_counter1192w(0) <= read_init_counter AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_read_post1202w(0) <= read_post AND wire_w_lg_width_counter_all_done1194w(0);
wire_w_lg_read_pre_data1191w(0) <= read_pre_data AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_rsource_load16w(0) <= rsource_load AND wire_w_rsource_parallel_in_range15w(0);
wire_w_lg_rsource_load23w(0) <= rsource_load AND wire_w_rsource_state_par_ini_range22w(0);
wire_w_lg_rsource_load27w(0) <= rsource_load AND wire_w_rsource_state_par_ini_range26w(0);
wire_w_lg_rsource_load33w(0) <= rsource_load AND wire_w_wsource_state_par_ini_range32w(0);
wire_w_lg_rsource_load37w(0) <= rsource_load AND wire_w_wsource_state_par_ini_range36w(0);
wire_w_lg_rublock_regout_reg1243w(0) <= rublock_regout_reg AND wire_w_lg_select_shift_nloop1242w(0);
wire_w_lg_shift_reg_load_enable174w(0) <= shift_reg_load_enable AND wire_w173w(0);
wire_w_lg_shift_reg_load_enable181w(0) <= shift_reg_load_enable AND wire_w180w(0);
wire_w_lg_shift_reg_load_enable188w(0) <= shift_reg_load_enable AND wire_w187w(0);
wire_w_lg_shift_reg_load_enable195w(0) <= shift_reg_load_enable AND wire_w194w(0);
wire_w_lg_shift_reg_load_enable202w(0) <= shift_reg_load_enable AND wire_w201w(0);
wire_w_lg_shift_reg_load_enable209w(0) <= shift_reg_load_enable AND wire_w208w(0);
wire_w_lg_shift_reg_load_enable216w(0) <= shift_reg_load_enable AND wire_w215w(0);
wire_w_lg_shift_reg_load_enable223w(0) <= shift_reg_load_enable AND wire_w222w(0);
wire_w_lg_shift_reg_load_enable230w(0) <= shift_reg_load_enable AND wire_w229w(0);
wire_w_lg_shift_reg_load_enable237w(0) <= shift_reg_load_enable AND wire_w236w(0);
wire_w_lg_shift_reg_load_enable244w(0) <= shift_reg_load_enable AND wire_w243w(0);
wire_w_lg_shift_reg_load_enable251w(0) <= shift_reg_load_enable AND wire_w250w(0);
wire_w_lg_shift_reg_load_enable258w(0) <= shift_reg_load_enable AND wire_w257w(0);
wire_w_lg_shift_reg_load_enable265w(0) <= shift_reg_load_enable AND wire_w264w(0);
wire_w_lg_shift_reg_load_enable117w(0) <= shift_reg_load_enable AND wire_w116w(0);
wire_w_lg_shift_reg_load_enable125w(0) <= shift_reg_load_enable AND wire_w124w(0);
wire_w_lg_shift_reg_load_enable132w(0) <= shift_reg_load_enable AND wire_w131w(0);
wire_w_lg_shift_reg_load_enable139w(0) <= shift_reg_load_enable AND wire_w138w(0);
wire_w_lg_shift_reg_load_enable146w(0) <= shift_reg_load_enable AND wire_w145w(0);
wire_w_lg_shift_reg_load_enable153w(0) <= shift_reg_load_enable AND wire_w152w(0);
wire_w_lg_shift_reg_load_enable160w(0) <= shift_reg_load_enable AND wire_w159w(0);
wire_w_lg_shift_reg_load_enable167w(0) <= shift_reg_load_enable AND wire_w166w(0);
wire_w_lg_write_data1214w(0) <= write_data AND wire_w_lg_width_counter_param_width_match1195w(0);
wire_w_lg_write_init_counter1211w(0) <= write_init_counter AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_write_post_data1220w(0) <= write_post_data AND wire_w_lg_bit_counter_all_done1213w(0);
wire_w_lg_write_pre_data1210w(0) <= write_pre_data AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_w_param_range109w110w(0) <= wire_w_param_range109w(0) AND wire_w_lg_w_param_range107w108w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1097w(0) <= wire_w_param_decoder_param_latch_range1024w(0) AND wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) <= wire_w_param_decoder_param_latch_range1024w(0) AND wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_w4w_range1264w1265w(0) <= wire_w_w4w_range1264w(0) AND w1w;
wire_w_lg_w_w4w_range1268w1269w(0) <= wire_w_w4w_range1268w(0) AND w1w;
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) <= NOT wire_w_lg_w_lg_w_param_range109w110w111w(0);
wire_w_lg_bit_counter_all_done1213w(0) <= NOT bit_counter_all_done;
wire_w_lg_bit_counter_param_start_match1190w(0) <= NOT bit_counter_param_start_match;
wire_w_lg_idle1160w(0) <= NOT idle;
wire_w_lg_read_address278w(0) <= NOT read_address;
wire_w_lg_read_data1155w(0) <= NOT read_data;
wire_w_lg_read_init1159w(0) <= NOT read_init;
wire_w_lg_read_init_counter1157w(0) <= NOT read_init_counter;
wire_w_lg_read_post1154w(0) <= NOT read_post;
wire_w_lg_read_pre_data1156w(0) <= NOT read_pre_data;
wire_w_lg_read_source_update1158w(0) <= NOT read_source_update;
wire_w_lg_rsource_load13w(0) <= NOT rsource_load;
wire_w_lg_rsource_update_done1187w(0) <= NOT rsource_update_done;
wire_w_lg_select_shift_nloop1242w(0) <= NOT select_shift_nloop;
wire_w_lg_shift_reg_load_enable101w(0) <= NOT shift_reg_load_enable;
wire_w_lg_w1w1178w(0) <= NOT w1w;
wire_w_lg_w2w1177w(0) <= NOT w2w;
wire_w_lg_w8w274w(0) <= NOT w8w;
wire_w_lg_width_counter_all_done1194w(0) <= NOT width_counter_all_done;
wire_w_lg_width_counter_param_width_match1195w(0) <= NOT width_counter_param_width_match;
wire_w_lg_write_data1149w(0) <= NOT write_data;
wire_w_lg_write_init1153w(0) <= NOT write_init;
wire_w_lg_write_init_counter1152w(0) <= NOT write_init_counter;
wire_w_lg_write_load1147w(0) <= NOT write_load;
wire_w_lg_write_post_data1148w(0) <= NOT write_post_data;
wire_w_lg_write_pre_data1150w(0) <= NOT write_pre_data;
wire_w_lg_write_source_update1151w(0) <= NOT write_source_update;
wire_w_lg_write_wait1146w(0) <= NOT write_wait;
wire_w_lg_wsource_update_done1207w(0) <= NOT wsource_update_done;
wire_w_lg_w_param_range105w106w(0) <= NOT wire_w_param_range105w(0);
wire_w_lg_w_param_range107w108w(0) <= NOT wire_w_param_range107w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) <= NOT wire_w_param_decoder_param_latch_range1024w(0);
wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0) <= NOT wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0) <= NOT wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0) <= NOT wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0) <= NOT wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0) <= NOT wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0) <= NOT wire_w_param_decoder_param_latch_range1041w(0);
wire_w173w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w(0) OR wire_w170w(0);
wire_w180w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w(0) OR wire_w177w(0);
wire_w187w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w(0) OR wire_w184w(0);
wire_w194w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w(0) OR wire_w191w(0);
wire_w201w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w(0) OR wire_w198w(0);
wire_w208w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w(0) OR wire_w205w(0);
wire_w215w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w(0) OR wire_w212w(0);
wire_w222w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w(0) OR wire_w219w(0);
wire_w229w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w(0) OR wire_w226w(0);
wire_w236w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w(0) OR wire_w233w(0);
wire_w243w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w(0) OR wire_w240w(0);
wire_w250w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w(0) OR wire_w247w(0);
wire_w257w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w(0) OR wire_w254w(0);
wire_w264w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w(0) OR wire_w261w(0);
wire_w116w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w(0) OR wire_w113w(0);
wire_w124w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w(0) OR wire_w121w(0);
wire_w131w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w(0) OR wire_w128w(0);
wire_w138w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w(0) OR wire_w135w(0);
wire_w145w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w(0) OR wire_w142w(0);
wire_w152w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w(0) OR wire_w149w(0);
wire_w159w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w(0) OR wire_w156w(0);
wire_w166w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w(0) OR wire_w163w(0);
wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) <= wire_w_lg_w_lg_idle1179w1180w(0) OR write_wait;
wire_w_lg_w_lg_read_address287w288w(0) <= wire_w_lg_read_address287w(0) OR wire_w_lg_w_lg_read_address278w286w(0);
wire_w_lg_w_lg_read_address337w338w(0) <= wire_w_lg_read_address337w(0) OR wire_w_lg_w_lg_read_address278w336w(0);
wire_w_lg_w_lg_read_address342w343w(0) <= wire_w_lg_read_address342w(0) OR wire_w_lg_w_lg_read_address278w341w(0);
wire_w_lg_w_lg_read_address347w348w(0) <= wire_w_lg_read_address347w(0) OR wire_w_lg_w_lg_read_address278w346w(0);
wire_w_lg_w_lg_read_address352w353w(0) <= wire_w_lg_read_address352w(0) OR wire_w_lg_w_lg_read_address278w351w(0);
wire_w_lg_w_lg_read_address357w358w(0) <= wire_w_lg_read_address357w(0) OR wire_w_lg_w_lg_read_address278w356w(0);
wire_w_lg_w_lg_read_address362w363w(0) <= wire_w_lg_read_address362w(0) OR wire_w_lg_w_lg_read_address278w361w(0);
wire_w_lg_w_lg_read_address367w368w(0) <= wire_w_lg_read_address367w(0) OR wire_w_lg_w_lg_read_address278w366w(0);
wire_w_lg_w_lg_read_address372w373w(0) <= wire_w_lg_read_address372w(0) OR wire_w_lg_w_lg_read_address278w371w(0);
wire_w_lg_w_lg_read_address377w378w(0) <= wire_w_lg_read_address377w(0) OR wire_w_lg_w_lg_read_address278w376w(0);
wire_w_lg_w_lg_read_address382w383w(0) <= wire_w_lg_read_address382w(0) OR wire_w_lg_w_lg_read_address278w381w(0);
wire_w_lg_w_lg_read_address292w293w(0) <= wire_w_lg_read_address292w(0) OR wire_w_lg_w_lg_read_address278w291w(0);
wire_w_lg_w_lg_read_address387w388w(0) <= wire_w_lg_read_address387w(0) OR wire_w_lg_w_lg_read_address278w386w(0);
wire_w_lg_w_lg_read_address392w393w(0) <= wire_w_lg_read_address392w(0) OR wire_w_lg_w_lg_read_address278w391w(0);
wire_w_lg_w_lg_read_address397w398w(0) <= wire_w_lg_read_address397w(0) OR wire_w_lg_w_lg_read_address278w396w(0);
wire_w_lg_w_lg_read_address402w403w(0) <= wire_w_lg_read_address402w(0) OR wire_w_lg_w_lg_read_address278w401w(0);
wire_w_lg_w_lg_read_address407w408w(0) <= wire_w_lg_read_address407w(0) OR wire_w_lg_w_lg_read_address278w406w(0);
wire_w_lg_w_lg_read_address412w413w(0) <= wire_w_lg_read_address412w(0) OR wire_w_lg_w_lg_read_address278w411w(0);
wire_w_lg_w_lg_read_address417w418w(0) <= wire_w_lg_read_address417w(0) OR wire_w_lg_w_lg_read_address278w416w(0);
wire_w_lg_w_lg_read_address297w298w(0) <= wire_w_lg_read_address297w(0) OR wire_w_lg_w_lg_read_address278w296w(0);
wire_w_lg_w_lg_read_address302w303w(0) <= wire_w_lg_read_address302w(0) OR wire_w_lg_w_lg_read_address278w301w(0);
wire_w_lg_w_lg_read_address307w308w(0) <= wire_w_lg_read_address307w(0) OR wire_w_lg_w_lg_read_address278w306w(0);
wire_w_lg_w_lg_read_address312w313w(0) <= wire_w_lg_read_address312w(0) OR wire_w_lg_w_lg_read_address278w311w(0);
wire_w_lg_w_lg_read_address317w318w(0) <= wire_w_lg_read_address317w(0) OR wire_w_lg_w_lg_read_address278w316w(0);
wire_w_lg_w_lg_read_address322w323w(0) <= wire_w_lg_read_address322w(0) OR wire_w_lg_w_lg_read_address278w321w(0);
wire_w_lg_w_lg_read_address327w328w(0) <= wire_w_lg_read_address327w(0) OR wire_w_lg_w_lg_read_address278w326w(0);
wire_w_lg_w_lg_read_address332w333w(0) <= wire_w_lg_read_address332w(0) OR wire_w_lg_w_lg_read_address278w331w(0);
wire_w_lg_w_lg_w_w4w_range1264w1265w1266w(0) <= wire_w_lg_w_w4w_range1264w1265w(0) OR w2w;
wire_w_lg_w_lg_w_w4w_range1268w1269w1270w(0) <= wire_w_lg_w_w4w_range1268w1269w(0) OR w2w;
wire_w_lg_w_lg_shift_reg_load_enable99w100w(0) <= wire_w_lg_shift_reg_load_enable99w(0) OR shift_reg_clear;
wire_w_lg_read_source_update1237w(0) <= read_source_update OR write_source_update;
wire_w_lg_rsource_load18w(0) <= rsource_load OR global_vcc;
wire_w_lg_rsource_load9w(0) <= rsource_load OR rsource_shift_enable;
wire_w_lg_shift_reg_load_enable99w(0) <= shift_reg_load_enable OR shift_reg_shift_enable;
bit_counter_all_done <= ((((wire_cntr5_w_lg_w_q_range39w42w(0) AND (NOT wire_cntr5_q(2))) AND wire_cntr5_q(3)) AND (NOT wire_cntr5_q(4))) AND wire_cntr5_q(5));
bit_counter_clear <= (rsource_update_done OR wsource_update_done);
bit_counter_enable <= (((((((((rsource_update_done OR wsource_update_done) OR read_init_counter) OR write_init_counter) OR read_pre_data) OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data);
bit_counter_param_start <= start_bit_decoder_out;
bit_counter_param_start_match <= ((((((NOT w53w(0)) AND (NOT w53w(1))) AND (NOT w53w(2))) AND (NOT w53w(3))) AND (NOT w53w(4))) AND (NOT w53w(5)));
busy <= wire_w_lg_idle1160w(0);
combine_port <= ( read_param & write_param & read_source & param);
data_out <= ( wire_w_lg_w_lg_read_address417w418w & wire_w_lg_w_lg_read_address412w413w & wire_w_lg_w_lg_read_address407w408w & wire_w_lg_w_lg_read_address402w403w & wire_w_lg_w_lg_read_address397w398w & wire_w_lg_w_lg_read_address392w393w & wire_w_lg_w_lg_read_address387w388w & wire_w_lg_w_lg_read_address382w383w & wire_w_lg_w_lg_read_address377w378w & wire_w_lg_w_lg_read_address372w373w & wire_w_lg_w_lg_read_address367w368w & wire_w_lg_w_lg_read_address362w363w & wire_w_lg_w_lg_read_address357w358w & wire_w_lg_w_lg_read_address352w353w & wire_w_lg_w_lg_read_address347w348w & wire_w_lg_w_lg_read_address342w343w & wire_w_lg_w_lg_read_address337w338w & wire_w_lg_w_lg_read_address332w333w & wire_w_lg_w_lg_read_address327w328w & wire_w_lg_w_lg_read_address322w323w & wire_w_lg_w_lg_read_address317w318w & wire_w_lg_w_lg_read_address312w313w & wire_w_lg_w_lg_read_address307w308w & wire_w_lg_w_lg_read_address302w303w & wire_w_lg_w_lg_read_address297w298w & wire_w_lg_w_lg_read_address292w293w & wire_w_lg_w_lg_read_address287w288w & wire_w_lg_w_lg_read_address278w283w & wire_w_lg_w_lg_read_address278w279w);
global_gnd <= '0';
global_vcc <= '1';
idle <= idle_state;
param_decoder_param_latch <= dffe9a;
param_decoder_select <= ( wire_w1144w & wire_w1139w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w & wire_w1131w & wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w & wire_w1122w & wire_w1116w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w & wire_w1108w & wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w & wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w & wire_w1076w & wire_w1072w & wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w & wire_w1082w & wire_w1054w & wire_w1076w & wire_w1072w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w & wire_w1061w & wire_w1054w & wire_w1049w & wire_w1042w);
power_up <= ((((((((((((((wire_w_lg_idle1160w(0) AND wire_w_lg_read_init1159w(0)) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_read_init_counter1157w(0)) AND wire_w_lg_read_pre_data1156w(0)) AND wire_w_lg_read_data1155w(0)) AND wire_w_lg_read_post1154w(0)) AND wire_w_lg_write_init1153w(0)) AND wire_w_lg_write_init_counter1152w(0)) AND wire_w_lg_write_source_update1151w(0)) AND wire_w_lg_write_pre_data1150w(0)) AND wire_w_lg_write_data1149w(0)) AND wire_w_lg_write_post_data1148w(0)) AND wire_w_lg_write_load1147w(0)) AND wire_w_lg_write_wait1146w(0));
read_address <= read_address_state;
read_data <= read_data_state;
read_init <= read_init_state;
read_init_counter <= read_init_counter_state;
read_post <= read_post_state;
read_pre_data <= read_pre_data_state;
read_source_update <= read_source_update_state;
rsource_load <= (idle AND (write_param OR read_param));
rsource_parallel_in <= ( wire_w_lg_w_lg_w_w4w_range1268w1269w1270w & wire_w_lg_w_lg_w_w4w_range1264w1265w1266w);
rsource_serial_out <= dffe1a0;
rsource_shift_enable <= wire_w_lg_read_source_update1237w(0);
rsource_state_par_ini <= ( read_param & global_gnd & global_gnd);
rsource_update_done <= dffe2a0;
rublock_captnupdt <= wire_w_lg_write_load1147w(0);
rublock_clock <= (NOT (clock OR idle_write_wait));
rublock_reconfig <= rublock_reconfig_st;
rublock_reconfig_st <= (idle AND reconfig);
rublock_regin <= ((((wire_w_lg_rublock_regout_reg1243w(0) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_write_source_update1151w(0)) OR (((shift_reg_serial_out AND select_shift_nloop) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_write_source_update1151w(0))) OR wire_w_lg_w_lg_read_source_update1237w1238w(0));
rublock_regout <= wire_sd4_regout;
rublock_regout_reg <= dffe8;
rublock_shiftnld <= (((((((read_pre_data OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data) OR read_source_update) OR write_source_update);
select_shift_nloop <= (wire_w_lg_read_data1196w(0) OR wire_w_lg_write_data1214w(0));
shift_reg_clear <= rsource_update_done;
shift_reg_load_enable <= (idle AND write_param);
shift_reg_serial_in <= (rublock_regout_reg AND select_shift_nloop);
shift_reg_serial_out <= dffe7a(0);
shift_reg_shift_enable <= (((read_data OR write_data) OR read_post) OR write_post_data);
start_bit_decoder_out <= ((((((((((((((((((((((( "0" & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & "0") OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(4) & start_bit_decoder_param_select(4) & start_bit_decoder_param_select(4) & "0" & start_bit_decoder_param_select(4))) OR ( "0" & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(7) & start_bit_decoder_param_select(7) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(9) & start_bit_decoder_param_select(9) & "0" & start_bit_decoder_param_select(9) & "0")) OR ( "0" & start_bit_decoder_param_select(10) & start_bit_decoder_param_select(10) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(12) & start_bit_decoder_param_select(12) & "0" & start_bit_decoder_param_select(12) & "0")) OR ( start_bit_decoder_param_select(13) & "0" & "0" & start_bit_decoder_param_select(13) & "0" & start_bit_decoder_param_select(13))) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( start_bit_decoder_param_select(15) & "0" & "0" & "0" & start_bit_decoder_param_select(15) & start_bit_decoder_param_select(15))) OR ( "0" & "0" & start_bit_decoder_param_select(16) & start_bit_decoder_param_select(16) & "0" & "0")) OR ( start_bit_decoder_param_select(17) & "0" & "0" & start_bit_decoder_param_select(17) & "0" & "0")) OR ( start_bit_decoder_param_select(18) & "0" & "0" & start_bit_decoder_param_select(18) & "0" & start_bit_decoder_param_select(18))) OR ( "0" & "0" & "0" & "0" & "0" & "0"
)) OR ( start_bit_decoder_param_select(20) & "0" & "0" & "0" & start_bit_decoder_param_select(20) & start_bit_decoder_param_select(20))) OR ( "0" & "0" & start_bit_decoder_param_select(21) & start_bit_decoder_param_select(21) & "0" & "0")) OR ( start_bit_decoder_param_select(22) & "0" & "0" & start_bit_decoder_param_select(22) & "0" & "0"));
start_bit_decoder_param_select <= param_decoder_select;
w1w <= read_param;
w2w <= write_param;
w4w <= read_source;
w53w <= (wire_cntr5_q XOR bit_counter_param_start);
w83w <= (wire_cntr6_q XOR width_counter_param_width);
w8w <= wire_w_lg_idle1160w(0);
width_counter_all_done <= (((((NOT wire_cntr6_q(0)) AND (NOT wire_cntr6_q(1))) AND wire_cntr6_q(2)) AND wire_cntr6_q(3)) AND wire_cntr6_q(4));
width_counter_clear <= (rsource_update_done OR wsource_update_done);
width_counter_enable <= ((read_data OR write_data) OR read_post);
width_counter_param_width <= width_decoder_out;
width_counter_param_width_match <= (((((NOT w83w(0)) AND (NOT w83w(1))) AND (NOT w83w(2))) AND (NOT w83w(3))) AND (NOT w83w(4)));
width_decoder_out <= ((((((((((((((((((((((( "0" & "0" & "0" & width_decoder_param_select(0) & "0") OR ( width_decoder_param_select(1) & width_decoder_param_select(1) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & width_decoder_param_select(2) & "0")) OR ( width_decoder_param_select(3) & width_decoder_param_select(3) & width_decoder_param_select(3) & "0" & width_decoder_param_select(3))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(4))) OR ( "0" & "0" & "0" & width_decoder_param_select(5) & "0")) OR ( width_decoder_param_select(6) & width_decoder_param_select(6) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & width_decoder_param_select(7) & "0")) OR ( width_decoder_param_select(8) & width_decoder_param_select(8) & "0" & "0" & "0")) OR ( "0" & "0" & width_decoder_param_select(9) & "0" & width_decoder_param_select(9))) OR ( "0" & "0" & "0" & width_decoder_param_select(10) & "0")) OR ( width_decoder_param_select(11) & width_decoder_param_select(11) & "0" & "0" & "0")) OR ( "0" & "0" & width_decoder_param_select(12) & "0" & width_decoder_param_select(12))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(13))) OR ( "0" & width_decoder_param_select(14) & width_decoder_param_select(14) & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(15))) OR ( width_decoder_param_select(16) & "0" & width_decoder_param_select(16) & width_decoder_param_select(16) & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(17))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(18))) OR ( "0" & width_decoder_param_select(19) & width_decoder_param_select(19) & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(20))) OR ( width_decoder_param_select(21) & "0" & width_decoder_param_select(21) & width_decoder_param_select(21) & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(22)));
width_decoder_param_select <= param_decoder_select;
write_data <= write_data_state;
write_init <= write_init_state;
write_init_counter <= write_init_counter_state;
write_load <= write_load_state;
write_post_data <= write_post_data_state;
write_pre_data <= write_pre_data_state;
write_source_update <= write_source_update_state;
write_wait <= write_wait_state;
wsource_state_par_ini <= ( write_param & global_gnd & global_gnd);
wsource_update_done <= dffe3a0;
wire_w_data_in_range104w(0) <= data_in(0);
wire_w_data_in_range171w(0) <= data_in(10);
wire_w_data_in_range178w(0) <= data_in(11);
wire_w_data_in_range185w(0) <= data_in(12);
wire_w_data_in_range192w(0) <= data_in(13);
wire_w_data_in_range199w(0) <= data_in(14);
wire_w_data_in_range206w(0) <= data_in(15);
wire_w_data_in_range213w(0) <= data_in(16);
wire_w_data_in_range220w(0) <= data_in(17);
wire_w_data_in_range227w(0) <= data_in(18);
wire_w_data_in_range234w(0) <= data_in(19);
wire_w_data_in_range120w(0) <= data_in(1);
wire_w_data_in_range241w(0) <= data_in(20);
wire_w_data_in_range248w(0) <= data_in(21);
wire_w_data_in_range255w(0) <= data_in(22);
wire_w_data_in_range262w(0) <= data_in(23);
wire_w_data_in_range114w(0) <= data_in(2);
wire_w_data_in_range122w(0) <= data_in(3);
wire_w_data_in_range129w(0) <= data_in(4);
wire_w_data_in_range136w(0) <= data_in(5);
wire_w_data_in_range143w(0) <= data_in(6);
wire_w_data_in_range150w(0) <= data_in(7);
wire_w_data_in_range157w(0) <= data_in(8);
wire_w_data_in_range164w(0) <= data_in(9);
wire_w_param_range105w(0) <= param(0);
wire_w_param_range107w(0) <= param(1);
wire_w_param_range109w(0) <= param(2);
wire_w_param_decoder_param_latch_range1024w(0) <= param_decoder_param_latch(0);
wire_w_param_decoder_param_latch_range1026w(0) <= param_decoder_param_latch(1);
wire_w_param_decoder_param_latch_range1029w(0) <= param_decoder_param_latch(2);
wire_w_param_decoder_param_latch_range1032w(0) <= param_decoder_param_latch(3);
wire_w_param_decoder_param_latch_range1035w(0) <= param_decoder_param_latch(4);
wire_w_param_decoder_param_latch_range1038w(0) <= param_decoder_param_latch(5);
wire_w_param_decoder_param_latch_range1041w(0) <= param_decoder_param_latch(6);
wire_w_rsource_parallel_in_range15w(0) <= rsource_parallel_in(0);
wire_w_rsource_state_par_ini_range22w(0) <= rsource_state_par_ini(0);
wire_w_rsource_state_par_ini_range26w(0) <= rsource_state_par_ini(1);
wire_w_w4w_range1264w(0) <= w4w(0);
wire_w_w4w_range1268w(0) <= w4w(1);
wire_w_wsource_state_par_ini_range32w(0) <= wsource_state_par_ini(0);
wire_w_wsource_state_par_ini_range36w(0) <= wsource_state_par_ini(1);
check_busy_dffe <= (OTHERS => '0');
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe1a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe1a_ena(0) = '1') THEN dffe1a0 <= (wire_w_lg_rsource_load16w(0) OR wire_w_lg_w_lg_rsource_load13w14w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe1a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe1a_ena(1) = '1') THEN dffe1a1 <= (rsource_parallel_in(1) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop0 : FOR i IN 0 TO 1 GENERATE
wire_dffe1a_ena(i) <= wire_w_lg_rsource_load9w(0);
END GENERATE loop0;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(0) = '1') THEN dffe2a0 <= (wire_w_lg_rsource_load23w(0) OR wire_w_lg_w_lg_rsource_load13w21w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(1) = '1') THEN dffe2a1 <= (wire_w_lg_rsource_load27w(0) OR wire_w_lg_w_lg_rsource_load13w25w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(2) = '1') THEN dffe2a2 <= (rsource_state_par_ini(2) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop1 : FOR i IN 0 TO 2 GENERATE
wire_dffe2a_ena(i) <= wire_w_lg_rsource_load18w(0);
END GENERATE loop1;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(0) = '1') THEN dffe3a0 <= (wire_w_lg_rsource_load33w(0) OR wire_w_lg_w_lg_rsource_load13w31w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(1) = '1') THEN dffe3a1 <= (wire_w_lg_rsource_load37w(0) OR wire_w_lg_w_lg_rsource_load13w35w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(2) = '1') THEN dffe3a2 <= (wsource_state_par_ini(2) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop2 : FOR i IN 0 TO 2 GENERATE
wire_dffe3a_ena(i) <= wire_w_lg_rsource_load18w(0);
END GENERATE loop2;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(0) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(0) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(0) <= '0';
ELSE dffe7a(0) <= (wire_w_lg_shift_reg_load_enable117w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w103w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(1) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(1) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(1) <= '0';
ELSE dffe7a(1) <= (wire_w_lg_shift_reg_load_enable125w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w119w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(2) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(2) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(2) <= '0';
ELSE dffe7a(2) <= (wire_w_lg_shift_reg_load_enable132w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w127w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(3) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(3) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(3) <= '0';
ELSE dffe7a(3) <= (wire_w_lg_shift_reg_load_enable139w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w134w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(4) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(4) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(4) <= '0';
ELSE dffe7a(4) <= (wire_w_lg_shift_reg_load_enable146w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w141w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(5) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(5) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(5) <= '0';
ELSE dffe7a(5) <= (wire_w_lg_shift_reg_load_enable153w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w148w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(6) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(6) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(6) <= '0';
ELSE dffe7a(6) <= (wire_w_lg_shift_reg_load_enable160w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w155w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(7) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(7) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(7) <= '0';
ELSE dffe7a(7) <= (wire_w_lg_shift_reg_load_enable167w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w162w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(8) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(8) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(8) <= '0';
ELSE dffe7a(8) <= (wire_w_lg_shift_reg_load_enable174w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w169w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(9) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(9) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(9) <= '0';
ELSE dffe7a(9) <= (wire_w_lg_shift_reg_load_enable181w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w176w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(10) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(10) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(10) <= '0';
ELSE dffe7a(10) <= (wire_w_lg_shift_reg_load_enable188w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w183w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(11) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(11) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(11) <= '0';
ELSE dffe7a(11) <= (wire_w_lg_shift_reg_load_enable195w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w190w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(12) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(12) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(12) <= '0';
ELSE dffe7a(12) <= (wire_w_lg_shift_reg_load_enable202w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w197w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(13) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(13) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(13) <= '0';
ELSE dffe7a(13) <= (wire_w_lg_shift_reg_load_enable209w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w204w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(14) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(14) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(14) <= '0';
ELSE dffe7a(14) <= (wire_w_lg_shift_reg_load_enable216w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w211w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(15) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(15) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(15) <= '0';
ELSE dffe7a(15) <= (wire_w_lg_shift_reg_load_enable223w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w218w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(16) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(16) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(16) <= '0';
ELSE dffe7a(16) <= (wire_w_lg_shift_reg_load_enable230w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w225w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(17) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(17) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(17) <= '0';
ELSE dffe7a(17) <= (wire_w_lg_shift_reg_load_enable237w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w232w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(18) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(18) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(18) <= '0';
ELSE dffe7a(18) <= (wire_w_lg_shift_reg_load_enable244w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w239w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(19) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(19) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(19) <= '0';
ELSE dffe7a(19) <= (wire_w_lg_shift_reg_load_enable251w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w246w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(20) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(20) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(20) <= '0';
ELSE dffe7a(20) <= (wire_w_lg_shift_reg_load_enable258w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w253w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(21) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(21) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(21) <= '0';
ELSE dffe7a(21) <= (wire_w_lg_shift_reg_load_enable265w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w260w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(22) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(22) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(22) <= '0';
ELSE dffe7a(22) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(23));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(23) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(23) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(23) <= '0';
ELSE dffe7a(23) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(24));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(24) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(24) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(24) <= '0';
ELSE dffe7a(24) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(25));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(25) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(25) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(25) <= '0';
ELSE dffe7a(25) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(26));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(26) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(26) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(26) <= '0';
ELSE dffe7a(26) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(27));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(27) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(27) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(27) <= '0';
ELSE dffe7a(27) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(28));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(28) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(28) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(28) <= '0';
ELSE dffe7a(28) <= (wire_w_lg_shift_reg_load_enable101w(0) AND shift_reg_serial_in);
END IF;
END IF;
END IF;
END PROCESS;
loop3 : FOR i IN 0 TO 28 GENERATE
wire_dffe7a_ena(i) <= wire_w_lg_w_lg_shift_reg_load_enable99w100w(0);
END GENERATE loop3;
wire_dffe7a_w_q_range277w(0) <= dffe7a(0);
wire_dffe7a_w_q_range325w(0) <= dffe7a(10);
wire_dffe7a_w_q_range330w(0) <= dffe7a(11);
wire_dffe7a_w_q_range335w(0) <= dffe7a(12);
wire_dffe7a_w_q_range340w(0) <= dffe7a(13);
wire_dffe7a_w_q_range345w(0) <= dffe7a(14);
wire_dffe7a_w_q_range350w(0) <= dffe7a(15);
wire_dffe7a_w_q_range355w(0) <= dffe7a(16);
wire_dffe7a_w_q_range360w(0) <= dffe7a(17);
wire_dffe7a_w_q_range365w(0) <= dffe7a(18);
wire_dffe7a_w_q_range370w(0) <= dffe7a(19);
wire_dffe7a_w_q_range282w(0) <= dffe7a(1);
wire_dffe7a_w_q_range375w(0) <= dffe7a(20);
wire_dffe7a_w_q_range380w(0) <= dffe7a(21);
wire_dffe7a_w_q_range385w(0) <= dffe7a(22);
wire_dffe7a_w_q_range390w(0) <= dffe7a(23);
wire_dffe7a_w_q_range395w(0) <= dffe7a(24);
wire_dffe7a_w_q_range400w(0) <= dffe7a(25);
wire_dffe7a_w_q_range405w(0) <= dffe7a(26);
wire_dffe7a_w_q_range410w(0) <= dffe7a(27);
wire_dffe7a_w_q_range415w(0) <= dffe7a(28);
wire_dffe7a_w_q_range285w(0) <= dffe7a(2);
wire_dffe7a_w_q_range290w(0) <= dffe7a(3);
wire_dffe7a_w_q_range295w(0) <= dffe7a(4);
wire_dffe7a_w_q_range300w(0) <= dffe7a(5);
wire_dffe7a_w_q_range305w(0) <= dffe7a(6);
wire_dffe7a_w_q_range310w(0) <= dffe7a(7);
wire_dffe7a_w_q_range315w(0) <= dffe7a(8);
wire_dffe7a_w_q_range320w(0) <= dffe7a(9);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN dffe8 <= rublock_regout;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(0) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(0) = '1') THEN dffe9a(0) <= combine_port(0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(1) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(1) = '1') THEN dffe9a(1) <= combine_port(1);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(2) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(2) = '1') THEN dffe9a(2) <= combine_port(2);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(3) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(3) = '1') THEN dffe9a(3) <= combine_port(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(4) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(4) = '1') THEN dffe9a(4) <= combine_port(4);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(5) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(5) = '1') THEN dffe9a(5) <= combine_port(5);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(6) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(6) = '1') THEN dffe9a(6) <= combine_port(6);
END IF;
END IF;
END PROCESS;
loop4 : FOR i IN 0 TO 6 GENERATE
wire_dffe9a_ena(i) <= (idle AND (write_param OR read_param));
END GENERATE loop4;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN idle_state <= '1';
ELSIF (clock = '1' AND clock'event) THEN idle_state <= (((wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN idle_write_wait <= '0';
ELSIF (clock = '1' AND clock'event) THEN idle_write_wait <= ((((wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up) AND write_load);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_address_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_read_address_state_ena = '1') THEN read_address_state <= (((read_param OR write_param) AND wire_w_lg_w_lg_w_param_range109w110w111w(0)) AND wire_w_lg_w8w274w(0));
END IF;
END IF;
END PROCESS;
wire_read_address_state_ena <= (read_param OR write_param);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (((read_init_counter AND bit_counter_param_start_match) OR (read_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_read_data1196w(0) AND wire_w_lg_width_counter_all_done1194w(0)));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_counter_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_counter_state <= rsource_update_done;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_state <= (idle AND read_param);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_post_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_post_state <= (((read_data AND width_counter_param_width_match) AND wire_w_lg_width_counter_all_done1194w(0)) OR wire_w_lg_read_post1202w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_pre_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_pre_data_state <= (wire_w_lg_read_init_counter1192w(0) OR wire_w_lg_read_pre_data1191w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_source_update_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_source_update_state <= ((read_init OR read_source_update) AND wire_w_lg_rsource_update_done1187w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (((write_init_counter AND bit_counter_param_start_match) OR (write_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_write_data1214w(0) AND wire_w_lg_bit_counter_all_done1213w(0)));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_counter_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_counter_state <= wsource_update_done;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_state <= (idle AND write_param);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_load_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_load_state <= ((write_data AND bit_counter_all_done) OR (write_post_data AND bit_counter_all_done));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_post_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_post_data_state <= (((write_data AND width_counter_param_width_match) AND wire_w_lg_bit_counter_all_done1213w(0)) OR wire_w_lg_write_post_data1220w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_pre_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_pre_data_state <= (wire_w_lg_write_init_counter1211w(0) OR wire_w_lg_write_pre_data1210w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_source_update_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_source_update_state <= ((write_init OR write_source_update) AND wire_w_lg_wsource_update_done1207w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_wait_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_wait_state <= write_load;
END IF;
END PROCESS;
wire_cntr5_w_lg_w_q_range39w42w(0) <= wire_cntr5_w_q_range39w(0) AND wire_cntr5_w_lg_w_q_range40w41w(0);
wire_cntr5_w_lg_w_q_range40w41w(0) <= NOT wire_cntr5_w_q_range40w(0);
wire_cntr5_w_q_range39w(0) <= wire_cntr5_q(0);
wire_cntr5_w_q_range40w(0) <= wire_cntr5_q(1);
cntr5 : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
aclr => reset,
clock => clock,
cnt_en => bit_counter_enable,
q => wire_cntr5_q,
sclr => bit_counter_clear
);
cntr6 : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 5
)
PORT MAP (
aclr => reset,
clock => clock,
cnt_en => width_counter_enable,
q => wire_cntr6_q,
sclr => width_counter_clear
);
sd4 : cycloneive_rublock
PORT MAP (
captnupdt => rublock_captnupdt,
clk => rublock_clock,
rconfig => rublock_reconfig,
regin => rublock_regin,
regout => wire_sd4_regout,
rsttimer => reset_timer,
shiftnld => rublock_shiftnld
);
END RTL; --altremote_remote_update_0
--VALID FILE
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_sa1_test3.vhd | 4 | 3028 | library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end component;
end package work6;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated
entity TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second
signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= '0' & x"000000";
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
DSP-Crowd/software | _install/de0_nano/src/frequency_divider_tb.vhd | 3 | 3247 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity frequencyDividerTb is
end frequencyDividerTb;
architecture rtl of frequencyDividerTb is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
constant cSystemClock : natural := 50E6;
constant cDivider1 : natural := 4;
constant cDivider2 : natural := 6;
signal clock : std_ulogic := '0';
signal reset : std_ulogic := '0';
signal dutOutput1 : std_ulogic;
signal dutOutput2 : std_ulogic;
begin
clock <= not clock after 1E9 ns / (2 * cSystemClock);
reset <= '1' after 200 ns;
-- DUT
DUT1: entity work.frequencyDivider(rtl)
generic map
(
divideBy => cDivider1
)
port map
(
clock => clock,
nResetAsync => reset,
output => dutOutput1
);
DUT2: entity work.frequencyDivider(rtl)
generic map
(
divideBy => cDivider2
)
port map
(
clock => clock,
nResetAsync => reset,
output => dutOutput2
);
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_xnorg_bit.vhd | 4 | 278 | library IEEE;
use IEEE.numeric_bit.all;
entity xnor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_org_stdlogic.vhd | 4 | 291 | library IEEE;
use IEEE.std_logic_1164.all;
entity or_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity or_gate;
architecture rtl of or_gate is
begin
c_o <= a_i or b_i;
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/gxor.vhd | 4 | 909 | library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
port (a: in std_logic_vector (2*half_width-1 downto 0);
ar: out std_logic);
end gxor_reduce;
architecture gxor_reduce_rtl of gxor_reduce is
component gxor is
port (a, b: in std_logic;
z : out std_logic);
end component;
--type path is array (0 to size/2) of std_logic;
signal x_int: std_logic_vector (2*half_width downto 0);
begin
x_int(2*half_width) <= '0'; -- MSB
gen_xor: for i in 2*half_width downto 1 generate
each_gate: gxor port map (a => x_int(i), b => a(i-1), z => x_int(i-1) );
end generate;
ar <= x_int(0);
end architecture gxor_reduce_rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/mux2to1.vhd | 4 | 356 | library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port (i0, i1, s: in std_logic;
y: out std_logic);
end mux2to1;
architecture mux2to1_rtl of mux2to1 is
begin
process (i0, i1, s)
begin
case (s) is
when '0' => y <= i0;
when others => y <= i1;
end case;
end process;
end mux2to1_rtl;
| gpl-2.0 |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/project/altremote/simulation/altremote.vhd | 6 | 2971 | -- altremote.vhd
-- Generated using ACDS version 16.1 196
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altremote is
port (
busy : out std_logic; -- busy.busy
clock : in std_logic := '0'; -- clock.clk
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.data_in
data_out : out std_logic_vector(28 downto 0); -- data_out.data_out
param : in std_logic_vector(2 downto 0) := (others => '0'); -- param.param
read_param : in std_logic := '0'; -- read_param.read_param
read_source : in std_logic_vector(1 downto 0) := (others => '0'); -- read_source.read_source
reconfig : in std_logic := '0'; -- reconfig.reconfig
reset : in std_logic := '0'; -- reset.reset
reset_timer : in std_logic := '0'; -- reset_timer.reset_timer
write_param : in std_logic := '0' -- write_param.write_param
);
end entity altremote;
architecture rtl of altremote is
component altremote_remote_update_0 is
port (
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
read_param : in std_logic := 'X'; -- read_param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
write_param : in std_logic := 'X'; -- write_param
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- data_in
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X' -- reset
);
end component altremote_remote_update_0;
begin
remote_update_0 : component altremote_remote_update_0
port map (
busy => busy, -- busy.busy
data_out => data_out, -- data_out.data_out
param => param, -- param.param
read_param => read_param, -- read_param.read_param
reconfig => reconfig, -- reconfig.reconfig
reset_timer => reset_timer, -- reset_timer.reset_timer
write_param => write_param, -- write_param.write_param
data_in => data_in, -- data_in.data_in
read_source => read_source, -- read_source.read_source
clock => clock, -- clock.clk
reset => reset -- reset.reset
);
end architecture rtl; -- of altremote
| gpl-2.0 |
DSP-Crowd/software | _install/de0_nano/src/input_sync.vhd | 1 | 3385 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_sync is
generic
(
num_inputs : integer := 1;
num_sync_stages : integer := 1
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
unsynced_inputs : in std_ulogic_vector(num_inputs - 1 downto 0);
synced_outputs : out std_ulogic_vector(num_inputs - 1 downto 0)
);
begin
assert 0 < num_inputs report "'num_inputs' must be greater than zero" severity error;
assert 0 < num_sync_stages report "'num_sync_stages' must be greater than zero" severity error;
end input_sync;
architecture rtl of input_sync is
type stages is array (0 to num_sync_stages - 1) of std_ulogic_vector(num_inputs - 1 downto 0);
signal q : stages;
begin
process(clock, n_reset_async)
begin
if(n_reset_async = '0') then
q(0) <= (others => '0');
elsif(clock'event and clock = '1') then
q(0) <= unsynced_inputs;
end if;
end process;
lbl_stages: for i in 0 to num_sync_stages - 2 generate
process(clock)
begin
if(clock'event and clock = '1') then
q(i + 1) <= q(i);
end if;
end process;
end generate;
synced_outputs <= q(num_sync_stages - 1);
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_notg_stdlogic.vhd | 4 | 264 | library IEEE;
use IEEE.std_logic_1164.all;
entity not_gate is
port (
a_i : in std_logic; -- inputs
c_o : out std_logic -- output
);
end entity not_gate;
architecture rtl of not_gate is
begin
c_o <= not a_i;
end architecture rtl;
| gpl-2.0 |
diecaptain/unscented_kalman_mppt | k_ukf_b.vhd | 1 | 1290 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_b is
port (
q : in std_logic_vector(31 downto 0);
A : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
clock : in std_logic;
B : out std_logic_vector(31 downto 0)
);
end k_ukf_b;
architecture struct of k_ukf_b is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_div IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => q,
datab => A,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => k,
datab => T,
result => Z2);
M3 : k_ukf_div port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => B);
end struct; | gpl-2.0 |
edgd1er/M1S1_INFO | S1_AEO/TP2/ipcore_dir/timer.vhd | 1 | 6526 | -- file: timer.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 100.000 0.000 50.0 200.000 50.000
-- CLK_OUT2 100.000 0.000 50.0 200.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 100.000 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity timer is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end timer;
architecture xilinx of timer is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "timer,clk_wiz_v1_8,{component_name=timer,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clk0);
end xilinx;
| gpl-2.0 |
diecaptain/unscented_kalman_mppt | k_ukf_Vsigactofkofone.vhd | 1 | 1381 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigactofkofone is
port (
clock : in std_logic;
Vactcapofkofone : in std_logic_vector(31 downto 0);
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Vsigactofkofone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigactofkofone;
architecture struct of k_ukf_Vsigactofkofone is
component k_ukf_Vsigactofkofzero is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Vsigactofkofzero : out std_logic_vector(31 downto 0)
);
end component;
begin
M1 : k_ukf_Vsigactofkofzero port map
( clock => clock,
I => I,
Isc => Isc,
Vactcapofk => Vactcapofkofone,
M => M,
D => D,
B => B,
Vsigactofkofzero => Vsigactofkofone);
end struct; | gpl-2.0 |
tmeissner/cryptocores | cbcaes/sim/vhdl/tb_cbcaes.vhd | 1 | 5429 | -- ======================================================================
-- AES Counter mode testbench
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use std.env.all;
entity tb_cbcaes is
end entity tb_cbcaes;
architecture sim of tb_cbcaes is
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_mode : std_logic := '0';
signal s_iv : std_logic_vector(0 to 127) := (others => '0');
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptin : std_logic;
signal s_dataout : std_logic_vector(0 to 127);
signal s_validout : std_logic := '0';
signal s_acceptout : std_logic := '0';
procedure cryptData(datain : in std_logic_vector(0 to 127);
key : in std_logic_vector(0 to 127);
iv : in std_logic_vector(0 to 127);
mode : in boolean;
start : in boolean;
final : in boolean;
dataout : out std_logic_vector(0 to 127);
bytelen : in integer) is
begin
report "VHPIDIRECT cryptData" severity failure;
end procedure;
attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
variable v_data : std_logic_vector(0 to 127);
begin
for i in 0 to 15 loop
for y in 0 to 7 loop
v_data((i*8)+y) := datain((i*8)+7-y);
end loop;
end loop;
return v_data;
end function;
begin
i_cbcaes : entity work.cbcaes
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
mode_i => s_mode,
key_i => s_key,
iv_i => s_iv,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptin,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptout
);
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
process is
variable v_key : std_logic_vector(0 to 127);
variable v_iv : std_logic_vector(0 to 127);
variable v_datain : std_logic_vector(0 to 127);
variable v_dataout : std_logic_vector(0 to 127);
variable v_random : RandomPType;
begin
v_random.InitSeed(v_random'instance_name);
wait until s_reset = '1' and rising_edge(s_clk);
-- ENCRYPTION TESTs
report "Test CBC-AES encryption";
s_start <= '1';
s_mode <= '0';
v_iv := v_random.RandSlv(128);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_iv <= v_iv;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_iv), false, i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Encryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
-- DECRYPTION TESTs
report "Test CBC-AES decryption";
s_start <= '1';
s_mode <= '1';
v_iv := v_random.RandSlv(128);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_iv <= v_iv;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_iv), true, i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Decryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
wait for 100 ns;
report "Simulation finished without errors";
finish(0);
end process;
end architecture sim;
| gpl-2.0 |
tmeissner/cryptocores | cbcmac_des/rtl/vhdl/cbcmac_des.vhd | 1 | 4087 | -- ======================================================================
-- CBC-MAC-DES
-- Copyright (C) 2015 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity cbcmac_des is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity cbcmac_des;
architecture rtl of cbcmac_des is
component des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
mode_i : in std_logic;
key_i : in std_logic_vector(0 to 63);
data_i : in std_logic_vector(0 to 63);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63);
valid_o : out std_logic;
accept_i : in std_logic
);
end component des;
-- CBCMAC must have fix IV for security reasons
constant C_IV : std_logic_vector(0 to 63) := (others => '0');
signal s_des_datain : std_logic_vector(0 to 63);
signal s_des_dataout : std_logic_vector(0 to 63);
signal s_des_dataout_d : std_logic_vector(0 to 63);
signal s_des_key : std_logic_vector(0 to 63);
signal s_key : std_logic_vector(0 to 63);
signal s_des_accept : std_logic;
signal s_des_validout : std_logic;
begin
s_des_datain <= C_IV xor data_i when start_i = '1' else
s_des_dataout_d xor data_i;
data_o <= s_des_dataout;
s_des_key <= key_i when start_i = '1' else s_key;
accept_o <= s_des_accept;
valid_o <= s_des_validout;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_key <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_des_accept = '1' and start_i = '1') then
s_key <= key_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_des_dataout_d <= (others => '0');
elsif(rising_edge(clk_i)) then
if(s_des_validout = '1') then
s_des_dataout_d <= s_des_dataout;
end if;
end if;
end process outputregister;
i_des : des
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => '0',
key_i => s_des_key,
data_i => s_des_datain,
valid_i => valid_i,
accept_o => s_des_accept,
data_o => s_des_dataout,
valid_o => s_des_validout,
accept_i => accept_i
);
end architecture rtl;
| gpl-2.0 |
edgd1er/M1S1_INFO | S1_AEO/TP_Bonus_feu_rouge/L3TP5/controleur_tb.vhd | 1 | 1036 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 20 ns; -- wait until global set/reset completes
clk<=not clk;
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| gpl-2.0 |
edgd1er/M1S1_INFO | S1_AEO/TP_Bonus_feu_rouge/L3TP5/fsmtravaux_tb.vhd | 1 | 2244 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 10/06/2014
-- Design Name:
-- Module Name: /home/m1/dubiez/Documents/AEO_TP/TP_Bonus/L3TP5/fsmtravaux_tb.vhd
-- Project Name: L3TP5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fsm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fsmtravaux_tb IS
END fsmtravaux_tb;
ARCHITECTURE behavior OF fsmtravaux_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fsm
PORT(
clk : IN std_logic;
travaux : IN std_logic;
Led : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal travaux : std_logic := '0';
--Outputs
signal Led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fsm PORT MAP (
clk => clk,
travaux => travaux,
Led => Led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*13;
travaux<= '1';
wait for clk_period*10;
travaux<= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
diecaptain/unscented_kalman_mppt | k_ukf_PofVactofVref.vhd | 1 | 3496 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_PofVactofVref is
port (
clock : in std_logic;
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
PofVactofVref : out std_logic_vector(31 downto 0)
);
end k_ukf_PofVactofVref;
architecture struct of k_ukf_PofVactofVref is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11,Z12,Z13 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofzero,
datab => Vactcapdashofkplusone,
result => Z1);
M2 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofone,
datab => Vactcapdashofkplusone,
result => Z3);
M3 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkoftwo,
datab => Vactcapdashofkplusone,
result => Z5);
M4 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkofzero,
datab => Vrefcapofkplusone,
result => Z2);
M5 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkofone,
datab => Vrefcapofkplusone,
result => Z4);
M6 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkoftwo,
datab => Vrefcapofkplusone,
result => Z6);
M7 : k_ukf_mult port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => Z7);
M8 : k_ukf_mult port map
( clock => clock,
dataa => Z3,
datab => Z4,
result => Z8);
M9 : k_ukf_mult port map
( clock => clock,
dataa => Z5,
datab => Z6,
result => Z9);
M10 : k_ukf_mult port map
( clock => clock,
dataa => Wofcofzero,
datab => Z7,
result => Z10);
M11 : k_ukf_mult port map
( clock => clock,
dataa => Wofcofone,
datab => Z8,
result => Z11);
M12 : k_ukf_mult port map
( clock => clock,
dataa => Wofcoftwo,
datab => Z9,
result => Z12);
M13 : k_ukf_add port map
( clock => clock,
dataa => Z10,
datab => Z11,
result => Z13);
M14 : k_ukf_add port map
( clock => clock,
dataa => Z12,
datab => Z13,
result => PofVactofVref);
end struct;
| gpl-2.0 |
siam28/neppielight | dvid_in/serialiser_in.vhd | 2 | 4703 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: input_serialiser
--
-- Description: A 5-bits per cycle SDR input serialiser
--
-- Maybe in the future the 'bitslip' funciton can be implemented.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity input_serialiser is
Port ( clk_fabric_x2 : in STD_LOGIC;
clk_input : in STD_LOGIC;
strobe : in STD_LOGIC;
ser_data : out STD_LOGIC_VECTOR (4 downto 0);
ser_input : in STD_LOGIC);
end input_serialiser;
architecture Behavioral of input_serialiser is
signal clk0, clk1, clkdiv : std_logic;
signal cascade : std_logic;
constant bitslip : std_logic := '0';
begin
clkdiv <= clk_fabric_x2;
clk0 <= clk_input;
clk1 <= '0';
ISERDES2_master : ISERDES2
generic map (
BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "MASTER" -- "NONE", "MASTER" or "SLAVE"
)
port map (
CFB0 => open, -- 1-bit output: Clock feed-through route output
CFB1 => open, -- 1-bit output: Clock feed-through route output
DFB => open, -- 1-bit output: Feed-through clock output
FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output
INCDEC => open, -- 1-bit output: Phase detector output
-- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
Q1 => ser_data(1),
Q2 => ser_data(2),
Q3 => ser_data(3),
Q4 => ser_data(4),
SHIFTOUT => cascade, -- 1-bit output: Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output: Output status of the phase detector
BITSLIP => bitslip , -- 1-bit input: Bitslip enable input
CE0 => '1', -- 1-bit input: Clock enable input
CLK0 => clk0, -- 1-bit input: I/O clock network input
CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input
CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input
D => ser_input, -- 1-bit input: Input data
IOCE => strobe, -- 1-bit input: Data strobe input
RST => '0', -- 1-bit input: Asynchronous reset input
SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O
);
ISERDES2_slave : ISERDES2
generic map (
BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "SLAVE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
CFB0 => open, -- 1-bit output: Clock feed-through route output
CFB1 => open, -- 1-bit output: Clock feed-through route output
DFB => open, -- 1-bit output: Feed-through clock output
FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output
INCDEC => open, -- 1-bit output: Phase detector output
-- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
Q1 => open,
Q2 => open,
Q3 => open,
Q4 => ser_data(0),
SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output: Output status of the phase detector
BITSLIP => bitslip, -- 1-bit input: Bitslip enable input
CE0 => '1', -- 1-bit input: Clock enable input
CLK0 => clk0, -- 1-bit input: I/O clock network input
CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input
CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input
D => '0', -- 1-bit input: Input data
IOCE => '1', -- 1-bit input: Data strobe input
RST => '0', -- 1-bit input: Asynchronous reset input
SHIFTIN => cascade -- 1-bit input: Cascade input signal for master/slave I/O
);
end Behavioral;
| gpl-2.0 |
siam28/neppielight | dvid_in/dvid_input_channel.vhd | 2 | 4904 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: input_channel - Behavioral
-- Description: The end-to-end processing of a TMDS input channel
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity input_channel is
GENERIC(
fixed_delay : in natural
);
Port ( clk_fabric : in STD_LOGIC;
clk_fabric_x2 : in STD_LOGIC;
clk_input : in STD_LOGIC;
strobe : in STD_LOGIC;
tmds_p : in STD_LOGIC;
tmds_n : in STD_LOGIC;
invert : in STD_LOGIC;
framing : in std_logic_vector(3 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
control : out STD_LOGIC_VECTOR (1 downto 0);
active_data : out std_logic;
sync_seen : out std_logic;
adjust_delay : IN std_logic;
increase_delay : IN std_logic;
reset_delay : IN std_logic;
start_calibrate : IN std_logic;
calibrate_busy : OUT std_logic
);
end input_channel;
architecture Behavioral of input_channel is
COMPONENT input_delay
GENERIC(
fixed_delay : in natural
);
PORT(
bit_clock : IN std_logic;
data_in : IN std_logic;
data_out : OUT std_logic;
control_clock : IN std_logic;
adjust_delay : IN std_logic;
increase_delay : IN std_logic;
reset_delay : IN std_logic;
start_calibrate : IN std_logic;
calibrate_busy : OUT std_logic
);
END COMPONENT;
COMPONENT input_serialiser
PORT(
clk_fabric_x2 : IN std_logic;
clk_input : IN std_logic;
strobe : IN std_logic;
ser_input : IN std_logic;
ser_data : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT gearbox
PORT(
clk_fabric_x2 : IN std_logic;
framing : IN std_logic_vector(3 downto 0);
invert : IN std_logic;
data_in : IN std_logic_vector(4 downto 0);
data_out : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
COMPONENT tmds_decode
PORT(
clk : IN std_logic;
data_in : IN std_logic_vector(9 downto 0);
data_out : OUT std_logic_vector(7 downto 0);
c : OUT std_logic_vector(1 downto 0);
active_data : OUT std_logic
);
END COMPONENT;
signal serial_data : std_logic;
signal delayed_serial_data : std_logic;
signal raw_tmds_word : std_logic_vector(9 downto 0);
signal half_words : std_logic_vector(4 downto 0);
begin
diff_input : IBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "TMDS_33")
port map (
O => serial_data,
I => tmds_p,
IB => tmds_n
);
--i_input_delay: input_delay GENERIC MAP(
-- fixed_delay => fixed_delay
-- ) PORT MAP(
-- bit_clock => clk_input,
-- data_in => serial_data,
-- data_out => delayed_serial_data,
-- control_clock => clk_fabric_x2,
-- adjust_delay => adjust_delay,
-- increase_delay => increase_delay,
-- reset_delay => reset_delay,
-- start_calibrate => start_calibrate,
-- calibrate_busy => calibrate_busy
-- );
i_input_serialiser: input_serialiser PORT MAP(
clk_fabric_x2 => clk_fabric_x2,
clk_input => clk_input,
strobe => strobe,
-- ser_input => delayed_serial_data,
ser_input => serial_data,
ser_data => half_words
);
i_gearbox: gearbox PORT MAP(
clk_fabric_x2 => clk_fabric_x2,
invert => invert,
framing => framing,
data_in => half_words,
data_out => raw_tmds_word
);
i_tmds_decode: tmds_decode PORT MAP(
clk => clk_fabric,
data_in => raw_tmds_word,
data_out => data_out,
c => control,
active_data => active_data
);
look_for_sync: process (clk_fabric)
begin
if rising_edge(clk_fabric) then
------------------------------------------------------------
-- Is the TMDS data one of two special sync codewords?
------------------------------------------------------------
if raw_tmds_word = "1101010100" or raw_tmds_word = "0010101011" then
sync_seen <= '1';
else
sync_seen <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
ineb9/Siemensdoc | examples/mux.vhdl | 22 | 857 | -------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
| gpl-2.0 |
devnulling/portapack-hackrf | hardware/portapack_h1/cpld/top.vhd | 2 | 5027 | --
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WR : in std_logic;
MCU_ADDR : in std_logic;
MCU_ROT_A : out std_logic;
MCU_ROT_B : out std_logic;
MCU_LCD_RD : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_ROT_A <= LCD_TE; -- not SW_ROT_A;
MCU_ROT_B <= '0'; -- not SW_ROT_B;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
io_write_strobe <= io_strobe and dir_write;
lcd_read_strobe <= (MCU_LCD_RD = '1');
lcd_write_strobe <= (MCU_LCD_WR = '1');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= not MCU_LCD_RD;
LCD_WRX <= not MCU_LCD_WR;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WR, mcu_data_in)
begin
if rising_edge(MCU_LCD_WR) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RD, lcd_data_in)
begin
if falling_edge(MCU_LCD_RD) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
ErikAndren/SG90-PWM | Clk1Hz.vhd | 1 | 876 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Types.all;
use ieee.std_logic_unsigned.all;
entity clk1Hz is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end;
architecture Behavioral of clk1Hz is
signal temporal: STD_LOGIC;
constant HalfPeriod : positive := 25000000;
signal counter : word(bits(HalfPeriod)-1 downto 0);
begin
freq_divider: process (reset, clk) begin
if (reset = '0') then
temporal <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if (counter = HalfPeriod) then
temporal <= not temporal;
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | gpl-2.0 |
ErikAndren/SG90-PWM | ClkDiv.vhd | 1 | 996 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Types.all;
use ieee.std_logic_unsigned.all;
entity ClkDiv is
generic (
SourceFreq : positive;
SinkFreq : positive
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end;
architecture Behavioral of ClkDiv is
signal temporal: STD_LOGIC;
constant Period : positive := SourceFreq / SinkFreq;
constant HalfPeriod : positive := Period / 2;
signal counter : word(bits(HalfPeriod)-1 downto 0);
begin
freq_divider: process (reset, clk) begin
if (reset = '0') then
temporal <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if (counter = HalfPeriod-1) then
temporal <= not temporal;
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | gpl-2.0 |
eht16/geany | data/filedefs/filetypes.vhdl | 22 | 3042 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
block_comment=comment
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# MIME type
mime_type=text/x-vhdl
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 |
Liorkoren/Verilog-IDE | AntlrGrammer/grammar/com/koltem/antlr/grammer/vhdl/examples/std_logic_1164_body.vhd | 7 | 34613 | -- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-V93
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-V93
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-V93
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_sa1_test2.vhd | 8 | 2573 | library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
-- doing nothing at the moment
constant N: integer range 0 to 16 := 4;
end package work6;
-- a 1-bit Moore-type adder to be used in
-- a serial adder FSM-driven architecture
-- ________ _____
-- a_i -->| |------>|D Q|---> s_o
-- b_i -->| FA1 | | |
-- | |--- | |
-- ---> |_______| | |_____|
--rst __|_______________________|
-- | | |
-- | | |
-- | | | ______
-- | | ---->|D Q|---
-- | | | | |
-- | | | | |
-- | | |_____| |
-- | |____________| |
-- |________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity sa1 is
port (clk, reset: in std_logic;
a_i, b_i: in std_logic;
s_o: out std_logic
);
end entity sa1;
architecture sa1_rtl of sa1 is
signal sum, carry, carry_reg: std_logic;
begin
a1: fa1 port map (c_i => carry_reg,
a_i => a_i,
b_i => b_i,
s_o => sum,
c_o => carry
);
f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o);
f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg);
end architecture sa1_rtl;
-- a one bit full adder written according to
-- textbook's boolean equations
library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_generic_eval.vhd | 3 | 2192 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics evaluation.
library ieee;
use ieee.std_logic_1164.all;
entity eval_generic is
generic(
msb : integer range 1 to 7 := 7;
bit_select : integer range 0 to 7 := 3
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end entity eval_generic;
architecture test of eval_generic is
begin
out_bit <= in_word(bit_select);
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
entity test_eval_generic is
port(
in_word : in std_logic_vector(7 downto 0);
out_bit_def, out_bit_ovr : out std_logic
);
end entity test_eval_generic;
architecture test of test_eval_generic is
constant const_int : integer := 7;
component eval_generic is
generic(
msb : integer range 1 to 7;
bit_select : integer range 0 to 7
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end component eval_generic;
begin
override_test_unit: eval_generic
generic map(bit_select => 2,
msb => const_int)
port map(
in_word => (others => '1'),
out_bit => out_bit_ovr
);
default_test_unit: eval_generic
port map(
in_word => in_word,
out_bit => out_bit_def
);
end architecture test;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_wait.vhd | 1 | 1396 | -- Copyright (c) 2015 CERN
-- @author Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- 'wait on' & 'wait until' test
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_wait is
port(a : in std_logic_vector(1 downto 0);
b : out std_logic_vector(1 downto 0));
end vhdl_wait;
architecture test of vhdl_wait is
begin
process begin
wait on a(0);
report "wait 1 completed";
-- acknowledge wait 1
b(0) <= '1';
end process;
process begin
wait until(a(1) = '1' and a(1)'event);
report "wait 2 completed";
-- acknowledge wait 2
b(1) <= '1';
end process;
end test;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_range_func.vhd | 3 | 1466 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'left and 'right attributes in VHDL subprograms.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.range_func_pkg.all;
entity range_func is
end range_func;
architecture test of range_func is
signal neg_inp : std_logic_vector(3 downto 0);
signal neg_out : std_logic_vector(3 downto 0);
signal rev_inp : std_logic_vector(3 downto 0);
signal rev_out : std_logic_vector(3 downto 0);
begin
neg_inp <= "1100";
rev_inp <= "1000";
process(neg_inp)
begin
neg_out <= negator(neg_inp);
end process;
process(rev_inp)
begin
rev_out <= reverse(rev_inp);
end process;
end test;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_umul23_stdlogic.vhd | 4 | 310 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_time.vhd | 3 | 2038 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_sadd23_bit.vhd | 4 | 275 | library ieee;
use ieee.numeric_bit.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/irqGenRtl.vhd | 2 | 7158 | -------------------------------------------------------------------------------
--! @file irqGenRtl.vhd
--
--! @brief irq generator with sync latch feature
--
--! @details The irq generator is similar to a ordinary interrupt controller,
--! however, it is extended with a "sync-latch" feature. This enables to
--! throttle the interrupt requests and assert the general irq with the sync
--! input signal. Hence, any irq source is deferred to the sync assertion.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity irqGen is
generic (
--! number of interrupt sources
gIrqSourceCount : natural := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- Irq
--! sync source
iSync : in std_logic;
--! interrupt source vector (pulse)
iIrqSource : in std_logic_vector(gIrqSourceCount downto 1);
--! interrupt signal
oIrq : out std_logic;
-- Control
--! master enable
iIrqMasterEnable : in std_logic;
--! interrupt source enable vector ('right is sync)
iIrqSourceEnable : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
iIrqAcknowledge : in std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source pending
oIrgPending : out std_logic_vector(gIrqSourceCount downto 0)
);
end irqGen;
architecture Rtl of irqGen is
--! sync rising edge
signal syncRising : std_logic;
--! interrupt register latch
signal irqRegLatch, irqRegLatch_next : std_logic_vector(gIrqSourceCount downto 0);
--! interrupt source store
signal irqSourceStore, irqSourceStore_next : std_logic_vector(gIrqSourceCount downto 1);
--! unregistered irq out signal
signal unregIrq, irq_reg : std_logic;
begin
--! generate pulse for rising edge of sync
syncEdgeDet : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iSync,
oRising => syncRising,
oFalling => open,
oAny => open
);
--! irq registers
clkdReg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
irqRegLatch <= (others => cInactivated);
irqSourceStore <= (others => cInactivated);
irq_reg <= cInactivated;
else
irqRegLatch <= irqRegLatch_next;
irqSourceStore <= irqSourceStore_next;
irq_reg <= unregIrq;
end if;
end if;
end process;
oIrq <= irq_reg;
--! irq register control
combIrqRegCont : process (
iIrqSource,
iIrqAcknowledge,
irqRegLatch,
irqSourceStore,
syncRising,
iIrqSourceEnable(iIrqSourceEnable'right)
)
begin
--default
irqRegLatch_next <= irqRegLatch;
irqSourceStore_next <= irqSourceStore;
-- do acknowledge with latched and source register
for i in gIrqSourceCount downto 1 loop
if iIrqAcknowledge(i) = cActivated then
irqRegLatch_next(i) <= cInactivated;
irqSourceStore_next(i) <= cInactivated;
end if;
end loop;
if iIrqAcknowledge(irqRegLatch'right) = cActivated then
irqRegLatch_next(irqRegLatch'right) <= cInactivated;
end if;
for i in gIrqSourceCount downto 1 loop
if iIrqSource(i) = cActivated then
irqSourceStore_next(i) <= cActivated;
end if;
end loop;
-- trigger irq with sync
if syncRising = cActivated then
-- loop through all irq sources
for i in gIrqSourceCount downto 1 loop
irqRegLatch_next(i) <= irqSourceStore(i);
end loop;
-- activate sync irq if it is enabled
-- (sync irqs in the past are not of interest!)
irqRegLatch_next(irqRegLatch'right) <= iIrqSourceEnable(iIrqSourceEnable'right);
end if;
end process;
--! output irq register
oIrgPending <= irqRegLatch;
--! irq signal generation
combIrqGen : process (
irqRegLatch,
iIrqMasterEnable,
iIrqSourceEnable
)
variable vTmp : std_logic;
begin
--default
unregIrq <= cInactivated;
-- the master enable overrules everything
if iIrqMasterEnable = cActivated then
-- check individual irqs
vTmp := cInactivated;
for i in gIrqSourceCount downto 0 loop
vTmp := vTmp or (iIrqSourceEnable(i) and irqRegLatch(i));
end loop;
-- variable holds irq state
unregIrq <= vTmp;
end if;
end process;
end Rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_case_multi.vhd | 1 | 1387 | -- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for multiple choices in case alternative statements.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_case_multi is
port ( inp: in std_logic_vector (0 to 2);
parity: out std_logic );
end vhdl_case_multi;
architecture vhdl_case_multi_rtl of vhdl_case_multi is
begin
process (inp)
begin
case inp is
when "000"|"011"|"101"|"110" => parity <= "0";
when "001"|"010"|"100"|"111" => parity <= "1";
when others => parity <= "Z";
end case;
end process;
end vhdl_case_multi_rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_xnor104_stdlogic.vhd | 4 | 317 | library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | staging/fpga/boards/altera/SYSTEC_ECUcore-EP3C/design_nios2_directIO/altpll0.vhd | 8 | 16616 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_test1.vhd | 2 | 607 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mask is
port (input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0)
);
end;
architecture behaviour of mask is
begin
L: process(input)
variable tmp : std_logic_vector(15 downto 0);
begin
output <= tmp; --this shouln't really change anything
tmp := input;
tmp := tmp and "1010101010101010";
output <= tmp;
end process;
end;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openmacPkg-p.vhd | 2 | 13981 | -------------------------------------------------------------------------------
--! @file openmacPkg-p.vhd
--
--! @brief OpenMAC package
--
--! @details This is the openMAC package providing common types.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
package openmacPkg is
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
--! Packet buffer is internal (e.g. memory blocks)
constant cPktBufLocal : natural := 1;
--! Packet buffer is external
constant cPktBufExtern : natural := 2;
--! Phy port(s) are Rmii
constant cPhyPortRmii : natural := 1;
--! Phy port(s) are Mii
constant cPhyPortMii : natural := 2;
---------------------------------------------------------------------------
-- (R)MII types and constants
---------------------------------------------------------------------------
--! RMII data width
constant cRmiiDataWidth : natural := 2;
--! MII data width
constant cMiiDataWidth : natural := 4;
--! RMII path
type tRmiiPath is record
enable : std_logic;
data : std_logic_vector(cRmiiDataWidth-1 downto 0);
end record;
--! MII path
type tMiiPath is record
enable : std_logic;
data : std_logic_vector(cMiiDataWidth-1 downto 0);
end record;
--! RMII path array
type tRmiiPathArray is array (natural range <>) of tRmiiPath;
--! MII path array
type tMiiPathArray is array (natural range <>) of tMiiPath;
--! RMII link
type tRmii is record
rx : tRmiiPath;
tx : tRmiiPath;
end record;
--! MII link
type tMii is record
rx : tMiiPath;
tx : tMiiPath;
end record;
--! RMII link array
type tRmiiArray is array (natural range <>) of tRmii;
--! MII link array
type tMiiArray is array (natural range <>) of tMii;
--! RMII path initialization
constant cRmiiPathInit : tRmiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! MII path initialization
constant cMiiPathInit : tMiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! RMII link initialization
constant cRmiiInit : tRmii := (
rx => cRmiiPathInit,
tx => cRmiiPathInit
);
--! MII link initialization
constant cMiiInit : tMii := (
rx => cMiiPathInit,
tx => cMiiPathInit
);
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
);
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
);
---------------------------------------------------------------------------
-- Memory mapping
---------------------------------------------------------------------------
--! Memory range type
type tMemRange is record
base : natural;
high : natural;
end record;
--! openMAC memory mapping type
type tMemMap is array (natural range <>) of tMemRange;
--! openMAC memory map count
constant cMemMapCount : natural := 6;
--! openMAC memory map index for DMA Error
constant cMemMapIndex_dmaError : natural := 5;
--! openMAC memory map index for IRQ Table
constant cMemMapIndex_irqTable : natural := 4;
--! openMAC memory map index for SMI
constant cMemMapIndex_smi : natural := 3;
--! openMAC memory map index for MAC RAM
constant cMemMapIndex_macRam : natural := 2;
--! openMAC memory map index for MAC Filter
constant cMemMapIndex_macFilter : natural := 1;
--! openMAC memory map index for MAC Content
constant cMemMapIndex_macCont : natural := 0;
--! openMAC memory mapping table
constant cMemMapTable : tMemMap(cMemMapCount-1 downto 0) := (
(base => 16#1020#, high => 16#102F#), -- DMA error
(base => 16#1010#, high => 16#101F#), -- IRQ table
(base => 16#1000#, high => 16#100F#), -- SMI
(base => 16#0800#, high => 16#0FFF#), -- MAC ram
(base => 16#0800#, high => 16#0BFF#), -- MAC filter
(base => 16#0000#, high => 16#03FF#) -- MAC content
);
---------------------------------------------------------------------------
-- Access delay
---------------------------------------------------------------------------
--! Access delay type
type tMemAccessDelay is record
write : natural;
read : natural;
end record;
--! Access delay type
type tMemAccessDelayArray is array (natural range <>) of tMemAccessDelay;
--! Access delay count
constant cMemAccessDelayCount : natural := 3;
--! Access delay index for PKT BUFFER
constant cMemAccessDelayIndex_pktBuf : natural := 2;
--! Access delay index for MAC TIMER
constant cMemAccessDelayIndex_macTimer : natural := 1;
--! Access delay index for MAC REG
constant cMemAccessDelayIndex_macReg : natural := 0;
--! Access delay table
constant cMemAccessDelayTable : tMemAccessDelayArray(cMemAccessDelayCount-1 downto 0) := (
(write => 0, read => 1), -- PKT BUFFER
(write => 0, read => 1), -- MAC TIMER
(write => 0, read => 1) -- MAC REG
);
--! Access acknowlegde type
type tMemAccessAck is record
write : std_logic;
read : std_logic;
end record;
--! Access acknowledge array type
type tMemAccessAckArray is array (natural range <>) of tMemAccessAck;
---------------------------------------------------------------------------
-- Constants for openmac
---------------------------------------------------------------------------
--! MAC REGISTER address width
constant cMacRegAddrWidth : natural := 13;
--! MAC REGISTER data width
constant cMacRegDataWidth : natural := 16;
--! MAC TIMER address width
constant cMacTimerAddrWidth : natural := 4;
--! MAC TIMER data width
constant cMacTimerDataWidth : natural := 32;
--! MAC PACKET BUFFER data width
constant cPktBufDataWidth : natural := 32;
--! MAC TIME width
constant cMacTimeWidth : natural := 32;
---------------------------------------------------------------------------
-- Constants for activity blinking
---------------------------------------------------------------------------
--! The activity blink frequency [Hz]
constant cActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
constant cClkFreq : natural := 50e6;
---------------------------------------------------------------------------
-- Constants for openhub
---------------------------------------------------------------------------
--! Internal port number
constant cHubIntPort : natural := 1;
---------------------------------------------------------------------------
-- Interrupt table
---------------------------------------------------------------------------
--! Interrupt table subtype
subtype tMacRegIrqTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MAC Tx interrupt offset
constant cMacRegIrqTable_macTx : natural := 0;
--! MAC Rx interrupt offset
constant cMacRegIrqTable_macRx : natural := 1;
---------------------------------------------------------------------------
-- DMA Error table
---------------------------------------------------------------------------
--! DMA error table subtype
subtype tMacDmaErrorTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! DMA error write (Rx packet transfer)
constant cMacDmaErrorTable_write : natural := 0;
--! DMA error read (Tx packet transfer)
constant cMacDmaErrorTable_read : natural := 8;
end package openmacPkg;
package body openmacPkg is
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector is
variable vRes_tmp : std_logic_vector(iArray'range);
begin
vRes_tmp := (others => cInactivated);
for i in iArray'range loop
vRes_tmp(i) := iArray(i).enable;
end loop;
return vRes_tmp;
end function;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tRmiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cRmiiDataWidth-1 downto 0 loop
oData(i*cRmiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
) is
variable vVector_tmp : tRmiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cRmiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cRmiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tMiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cMiiDataWidth-1 downto 0 loop
oData(i*cMiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
) is
variable vVector_tmp : tMiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cMiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cMiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
end package body openmacPkg;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_xnor23_bit.vhd | 4 | 290 | library ieee;
use ieee.numeric_bit.all;
entity xnor23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity xnor23;
architecture rtl of xnor23 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/boards/terasic-de2-115/common/ipcore/pll.vhd | 8 | 19524 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 2,
clk3_phase_shift => "-2000",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/registerFileRtl.vhd | 2 | 5353 | -------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/cntRtl.vhd | 2 | 3792 | -------------------------------------------------------------------------------
--! @file cntRtl.vhd
--
--! @brief Terminal Counter
--
--! @details The terminal counter is a synchronous counter configured
--! by several generics.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
entity cnt is
generic (
--! Width of counter
gCntWidth : natural := 32;
--! Value that triggers the counter reset
gTcntVal : natural := 1000
);
port (
iArst : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iSrst : in std_logic;
oCnt : out std_logic_vector(gCntWidth-1 downto 0);
oTcnt : out std_logic
);
end entity;
architecture rtl of cnt is
constant cTcntVal : std_logic_vector(gCntWidth-1 downto 0) :=
std_logic_vector(to_unsigned(gTcntVal, gCntWidth));
signal cnt, cnt_next : std_logic_vector(gCntWidth-1 downto 0);
signal tc : std_logic;
begin
-- handle wrong generics
assert (gTcntVal > 0)
report "Terminal count value of 0 makes no sense!"
severity failure;
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
cnt <= (others => cInactivated);
elsif rising_edge(iClk) then
cnt <= cnt_next;
end if;
end process;
tc <= cActivated when cnt = cTcntVal else
cInactivated;
oCnt <= cnt;
oTcnt <= tc;
comb : process(iSrst, iEnable, cnt, tc)
begin
--default
cnt_next <= cnt;
if iSrst = cActivated then
cnt_next <= (others => cInactivated);
elsif iEnable = cActivated then
if tc = cActivated then
cnt_next <= (others => cInactivated);
else
cnt_next <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/lib/src/dpRamSplxNbe-rtl-a.vhd | 2 | 3948 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_test8.vhd | 2 | 503 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity match_bits is
port (a,b: in std_logic_vector(7 downto 0);
matches : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of match_bits is
begin
process(a, b) begin
for i in 7 downto 0 loop
matches(i) <= not (a(i) xor b(i));
end loop;
end process;
end;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/work7/fdc.vhd | 8 | 432 | -- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/work7b/fdc.vhd | 8 | 432 | -- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/lib/src/dpRam-rtl-a.vhd | 2 | 5447 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of dpRam is
--! Width of a byte
constant cByte : natural := 8;
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port A readport
signal readdataA : tDataPort;
--! Port B readport
signal readdataB : tDataPort;
begin
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
-- assign readdata to ports
oReaddata_A <= readdataA;
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A and iByteenable_A. The read process is done with every
--! rising iClk_A edge.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
for i in iByteenable_A'range loop
if iByteenable_A(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_A(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataA <= vDpram(to_integer(unsigned(iAddress_A)));
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The write process considers
--! iWriteEnable_B and iByteenable_B. The read process is done with every
--! rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
if iWriteEnable_B = cActivated then
for i in iByteenable_B'range loop
if iByteenable_B(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_B)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_B(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/utils_v1_00_a/sim/ipif_monitor.vhd | 1 | 2340 | -- ipif_monitor.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ipif_monitor is
generic (
DWIDTH : integer := 32
);
port (
CLK : in std_logic;
RST : in std_logic;
IP2Bus_Data : in std_logic_vector(DWIDTH - 1 downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
IPIF_BUSY : in std_logic;
IPIF_READ : in std_logic;
IPIF_DONE : out std_logic
);
end entity;
architecture full of ipif_monitor is
signal ack_active : std_logic;
begin
ack_active <= IP2Bus_WrAck or IP2Bus_RdAck;
IPIF_DONE <= ack_active;
assert (ack_active = '1' and IP2Bus_Error = '0') or ack_active = '0'
report "Error is asserted durning Ack"
severity warning;
checkp : process(CLK, RST)
begin
if rising_edge(CLK) then
if RST = '0' then
if IP2Bus_WrAck = '1' then
assert IPIF_BUSY = '1'
report "WrAck asserted when no transaction is active"
severity failure;
assert IPIF_READ = '0'
report "Invalid acknowladge, expected RdAck"
severity failure;
end if;
if IP2Bus_RdAck = '1' then
assert IPIF_BUSY = '1'
report "RdAck asserted when no transaction is active"
severity failure;
assert IPIF_READ = '1'
report "Invalid acknowladge, expected WrAck"
severity failure;
end if;
if IP2Bus_WrAck = IP2Bus_RdAck and ack_active = '1' then
assert false
report "WrAck and RdAck are asserted at once"
severity failure;
end if;
end if;
end if;
end process;
writep : process(CLK, RST, IP2Bus_RdAck, IP2Bus_Error, IP2Bus_Data)
variable i : integer := 0;
begin
if rising_edge(CLK) then
if RST = '0' then
if IP2Bus_RdAck = '1' and IP2Bus_Error = '0' then
report "Data (OK): "
& integer'image(conv_integer(IP2Bus_Data(31 downto 16))) & " "
& integer'image(conv_integer(IP2Bus_Data(15 downto 0)));
elsif IP2Bus_RdAck = '1' and IP2Bus_Error = '1' then
report "Data (ER): "
& integer'image(conv_integer(IP2Bus_Data(31 downto 16))) & " "
& integer'image(conv_integer(IP2Bus_Data(15 downto 0)));
end if;
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_eth/qmfir_udp/EDK_project/hdl/plb_v46_0_wrapper.vhd | 1 | 14640 | -------------------------------------------------------------------------------
-- plb_v46_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_04_a;
use plb_v46_v1_04_a.all;
entity plb_v46_0_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 9);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 9);
Sl_MRdErr : in std_logic_vector(0 to 9);
Sl_MWrErr : in std_logic_vector(0 to 9);
Sl_MBusy : in std_logic_vector(0 to 9);
Sl_rdBTerm : in std_logic_vector(0 to 9);
Sl_rdComp : in std_logic_vector(0 to 9);
Sl_rdDAck : in std_logic_vector(0 to 9);
Sl_rdDBus : in std_logic_vector(0 to 1279);
Sl_rdWdAddr : in std_logic_vector(0 to 39);
Sl_rearbitrate : in std_logic_vector(0 to 9);
Sl_SSize : in std_logic_vector(0 to 19);
Sl_wait : in std_logic_vector(0 to 9);
Sl_wrBTerm : in std_logic_vector(0 to 9);
Sl_wrComp : in std_logic_vector(0 to 9);
Sl_wrDAck : in std_logic_vector(0 to 9);
Sl_MIRQ : in std_logic_vector(0 to 9);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 9);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 9);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of plb_v46_0_wrapper : entity is "plb_v46_v1_04_a";
end plb_v46_0_wrapper;
architecture STRUCTURE of plb_v46_0_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
plb_v46_0 : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 1,
C_PLBV46_NUM_SLAVES => 10,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 128,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/highpass_filter_v1_00_a/sim/vga_matrix_gen.vhd | 1 | 1634 | -- vga_matrix_gen.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library rgb_gen_v1_00_a;
use rgb_gen_v1_00_a.rgbctl_gen;
entity vga_matrix_gen is
port (
CLK : in std_logic;
RST : in std_logic;
R : out std_logic_vector(71 downto 0);
G : out std_logic_vector(71 downto 0);
B : out std_logic_vector(71 downto 0);
HS : out std_logic_vector(8 downto 0);
VS : out std_logic_vector(8 downto 0);
DE : out std_logic_vector(8 downto 0)
);
end entity;
architecture full of vga_matrix_gen is
signal hs_vec : std_logic_vector(8 downto 0);
signal vs_vec : std_logic_vector(8 downto 0);
signal de_vec : std_logic_vector(8 downto 0);
signal hs_in : std_logic;
signal vs_in : std_logic;
signal de_in : std_logic;
begin
matrix_gen_i : entity work.matrix_pixel_gen
port map (
CLK => CLK,
RST => RST,
R => R,
G => G,
B => B,
PX_REQ => de_vec(4)
);
rgbctl_gen_i : entity rgb_gen_v1_00_a.rgbctl_gen
port map (
CLK => CLK,
RST => RST,
HS => hs_in,
VS => vs_in,
DE => de_in
);
HS <= hs_vec;
VS <= vs_vec;
DE <= de_vec;
ctl_shiftp : process(CLK, RST, hs_in, vs_in, de_in)
begin
if rising_edge(CLK) then
for i in hs_vec'range loop
if i = 0 then
hs_vec(i) <= hs_in;
vs_vec(i) <= vs_in;
de_vec(i) <= de_in;
else
hs_vec(i) <= hs_vec(i - 1);
vs_vec(i) <= vs_vec(i - 1);
de_vec(i) <= de_vec(i - 1);
end if;
end loop;
end if;
end process;
end architecture;
| gpl-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_eth/qmfir_udp/EDK_project/hdl/clock_generator_0_wrapper.vhd | 1 | 39980 | -------------------------------------------------------------------------------
-- clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_v3_02_a;
use clock_generator_v3_02_a.all;
entity clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKFBIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of clock_generator_0_wrapper : entity is "clock_generator_v3_02_a";
end clock_generator_0_wrapper;
architecture STRUCTURE of clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_SPEEDGRADE : STRING;
C_EXT_RESET_HIGH : INTEGER;
C_CLK_GEN : STRING;
C_CLKOUT0_MODULE : STRING;
C_CLKOUT0_PORT : STRING;
C_CLKOUT1_MODULE : STRING;
C_CLKOUT1_PORT : STRING;
C_CLKOUT2_MODULE : STRING;
C_CLKOUT2_PORT : STRING;
C_CLKOUT3_MODULE : STRING;
C_CLKOUT3_PORT : STRING;
C_CLKOUT4_MODULE : STRING;
C_CLKOUT4_PORT : STRING;
C_CLKOUT5_MODULE : STRING;
C_CLKOUT5_PORT : STRING;
C_CLKOUT6_MODULE : STRING;
C_CLKOUT6_PORT : STRING;
C_CLKOUT7_MODULE : STRING;
C_CLKOUT7_PORT : STRING;
C_CLKOUT8_MODULE : STRING;
C_CLKOUT8_PORT : STRING;
C_CLKOUT9_MODULE : STRING;
C_CLKOUT9_PORT : STRING;
C_CLKOUT10_MODULE : STRING;
C_CLKOUT10_PORT : STRING;
C_CLKOUT11_MODULE : STRING;
C_CLKOUT11_PORT : STRING;
C_CLKOUT12_MODULE : STRING;
C_CLKOUT12_PORT : STRING;
C_CLKOUT13_MODULE : STRING;
C_CLKOUT13_PORT : STRING;
C_CLKOUT14_MODULE : STRING;
C_CLKOUT14_PORT : STRING;
C_CLKOUT15_MODULE : STRING;
C_CLKOUT15_PORT : STRING;
C_CLKFBOUT_MODULE : STRING;
C_CLKFBOUT_PORT : STRING;
C_PSDONE_MODULE : STRING;
C_PLL0_DIVCLK_DIVIDE : INTEGER;
C_PLL0_CLKFBOUT_MULT : INTEGER;
C_PLL0_CLKFBOUT_PHASE : REAL;
C_PLL0_CLKIN1_PERIOD : REAL;
C_PLL0_CLKOUT0_DIVIDE : INTEGER;
C_PLL0_CLKOUT0_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT0_PHASE : REAL;
C_PLL0_CLKOUT1_DIVIDE : INTEGER;
C_PLL0_CLKOUT1_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT1_PHASE : REAL;
C_PLL0_CLKOUT2_DIVIDE : INTEGER;
C_PLL0_CLKOUT2_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT2_PHASE : REAL;
C_PLL0_CLKOUT3_DIVIDE : INTEGER;
C_PLL0_CLKOUT3_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT3_PHASE : REAL;
C_PLL0_CLKOUT4_DIVIDE : INTEGER;
C_PLL0_CLKOUT4_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT4_PHASE : REAL;
C_PLL0_CLKOUT5_DIVIDE : INTEGER;
C_PLL0_CLKOUT5_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT5_PHASE : REAL;
C_PLL0_BANDWIDTH : STRING;
C_PLL0_COMPENSATION : STRING;
C_PLL0_REF_JITTER : REAL;
C_PLL0_RESET_ON_LOSS_OF_LOCK : BOOLEAN;
C_PLL0_RST_DEASSERT_CLK : STRING;
C_PLL0_EXT_RESET_HIGH : INTEGER;
C_PLL0_FAMILY : STRING;
C_PLL0_CLKOUT0_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT1_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT2_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT3_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT4_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT5_DESKEW_ADJUST : STRING;
C_PLL0_CLKFBOUT_DESKEW_ADJUST : STRING;
C_PLL0_CLKIN1_BUF : BOOLEAN;
C_PLL0_CLKFBOUT_BUF : BOOLEAN;
C_PLL0_CLKOUT0_BUF : BOOLEAN;
C_PLL0_CLKOUT1_BUF : BOOLEAN;
C_PLL0_CLKOUT2_BUF : BOOLEAN;
C_PLL0_CLKOUT3_BUF : BOOLEAN;
C_PLL0_CLKOUT4_BUF : BOOLEAN;
C_PLL0_CLKOUT5_BUF : BOOLEAN;
C_PLL0_CLKIN1_MODULE : STRING;
C_PLL0_CLKIN1_PORT : STRING;
C_PLL0_CLKFBIN_MODULE : STRING;
C_PLL0_CLKFBIN_PORT : STRING;
C_PLL0_RST_MODULE : STRING;
C_PLL1_DIVCLK_DIVIDE : INTEGER;
C_PLL1_CLKFBOUT_MULT : INTEGER;
C_PLL1_CLKFBOUT_PHASE : REAL;
C_PLL1_CLKIN1_PERIOD : REAL;
C_PLL1_CLKOUT0_DIVIDE : INTEGER;
C_PLL1_CLKOUT0_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT0_PHASE : REAL;
C_PLL1_CLKOUT1_DIVIDE : INTEGER;
C_PLL1_CLKOUT1_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT1_PHASE : REAL;
C_PLL1_CLKOUT2_DIVIDE : INTEGER;
C_PLL1_CLKOUT2_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT2_PHASE : REAL;
C_PLL1_CLKOUT3_DIVIDE : INTEGER;
C_PLL1_CLKOUT3_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT3_PHASE : REAL;
C_PLL1_CLKOUT4_DIVIDE : INTEGER;
C_PLL1_CLKOUT4_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT4_PHASE : REAL;
C_PLL1_CLKOUT5_DIVIDE : INTEGER;
C_PLL1_CLKOUT5_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT5_PHASE : REAL;
C_PLL1_BANDWIDTH : STRING;
C_PLL1_COMPENSATION : STRING;
C_PLL1_REF_JITTER : REAL;
C_PLL1_RESET_ON_LOSS_OF_LOCK : BOOLEAN;
C_PLL1_RST_DEASSERT_CLK : STRING;
C_PLL1_EXT_RESET_HIGH : INTEGER;
C_PLL1_FAMILY : STRING;
C_PLL1_CLKOUT0_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT1_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT2_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT3_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT4_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT5_DESKEW_ADJUST : STRING;
C_PLL1_CLKFBOUT_DESKEW_ADJUST : STRING;
C_PLL1_CLKIN1_BUF : BOOLEAN;
C_PLL1_CLKFBOUT_BUF : BOOLEAN;
C_PLL1_CLKOUT0_BUF : BOOLEAN;
C_PLL1_CLKOUT1_BUF : BOOLEAN;
C_PLL1_CLKOUT2_BUF : BOOLEAN;
C_PLL1_CLKOUT3_BUF : BOOLEAN;
C_PLL1_CLKOUT4_BUF : BOOLEAN;
C_PLL1_CLKOUT5_BUF : BOOLEAN;
C_PLL1_CLKIN1_MODULE : STRING;
C_PLL1_CLKIN1_PORT : STRING;
C_PLL1_CLKFBIN_MODULE : STRING;
C_PLL1_CLKFBIN_PORT : STRING;
C_PLL1_RST_MODULE : STRING;
C_DCM0_DFS_FREQUENCY_MODE : STRING;
C_DCM0_DLL_FREQUENCY_MODE : STRING;
C_DCM0_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM0_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM0_CLK_FEEDBACK : STRING;
C_DCM0_CLKOUT_PHASE_SHIFT : STRING;
C_DCM0_DSS_MODE : STRING;
C_DCM0_STARTUP_WAIT : BOOLEAN;
C_DCM0_PHASE_SHIFT : INTEGER;
C_DCM0_CLKFX_MULTIPLY : INTEGER;
C_DCM0_CLKFX_DIVIDE : INTEGER;
C_DCM0_CLKDV_DIVIDE : REAL;
C_DCM0_CLKIN_PERIOD : REAL;
C_DCM0_DESKEW_ADJUST : STRING;
C_DCM0_CLKIN_BUF : BOOLEAN;
C_DCM0_CLKFB_BUF : BOOLEAN;
C_DCM0_CLK0_BUF : BOOLEAN;
C_DCM0_CLK90_BUF : BOOLEAN;
C_DCM0_CLK180_BUF : BOOLEAN;
C_DCM0_CLK270_BUF : BOOLEAN;
C_DCM0_CLKDV_BUF : BOOLEAN;
C_DCM0_CLKDV180_BUF : BOOLEAN;
C_DCM0_CLK2X_BUF : BOOLEAN;
C_DCM0_CLK2X180_BUF : BOOLEAN;
C_DCM0_CLKFX_BUF : BOOLEAN;
C_DCM0_CLKFX180_BUF : BOOLEAN;
C_DCM0_EXT_RESET_HIGH : INTEGER;
C_DCM0_FAMILY : STRING;
C_DCM0_CLKIN_MODULE : STRING;
C_DCM0_CLKIN_PORT : STRING;
C_DCM0_CLKFB_MODULE : STRING;
C_DCM0_CLKFB_PORT : STRING;
C_DCM0_RST_MODULE : STRING;
C_DCM1_DFS_FREQUENCY_MODE : STRING;
C_DCM1_DLL_FREQUENCY_MODE : STRING;
C_DCM1_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM1_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM1_CLK_FEEDBACK : STRING;
C_DCM1_CLKOUT_PHASE_SHIFT : STRING;
C_DCM1_DSS_MODE : STRING;
C_DCM1_STARTUP_WAIT : BOOLEAN;
C_DCM1_PHASE_SHIFT : INTEGER;
C_DCM1_CLKFX_MULTIPLY : INTEGER;
C_DCM1_CLKFX_DIVIDE : INTEGER;
C_DCM1_CLKDV_DIVIDE : REAL;
C_DCM1_CLKIN_PERIOD : REAL;
C_DCM1_DESKEW_ADJUST : STRING;
C_DCM1_CLKIN_BUF : BOOLEAN;
C_DCM1_CLKFB_BUF : BOOLEAN;
C_DCM1_CLK0_BUF : BOOLEAN;
C_DCM1_CLK90_BUF : BOOLEAN;
C_DCM1_CLK180_BUF : BOOLEAN;
C_DCM1_CLK270_BUF : BOOLEAN;
C_DCM1_CLKDV_BUF : BOOLEAN;
C_DCM1_CLKDV180_BUF : BOOLEAN;
C_DCM1_CLK2X_BUF : BOOLEAN;
C_DCM1_CLK2X180_BUF : BOOLEAN;
C_DCM1_CLKFX_BUF : BOOLEAN;
C_DCM1_CLKFX180_BUF : BOOLEAN;
C_DCM1_EXT_RESET_HIGH : INTEGER;
C_DCM1_FAMILY : STRING;
C_DCM1_CLKIN_MODULE : STRING;
C_DCM1_CLKIN_PORT : STRING;
C_DCM1_CLKFB_MODULE : STRING;
C_DCM1_CLKFB_PORT : STRING;
C_DCM1_RST_MODULE : STRING;
C_DCM2_DFS_FREQUENCY_MODE : STRING;
C_DCM2_DLL_FREQUENCY_MODE : STRING;
C_DCM2_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM2_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM2_CLK_FEEDBACK : STRING;
C_DCM2_CLKOUT_PHASE_SHIFT : STRING;
C_DCM2_DSS_MODE : STRING;
C_DCM2_STARTUP_WAIT : BOOLEAN;
C_DCM2_PHASE_SHIFT : INTEGER;
C_DCM2_CLKFX_MULTIPLY : INTEGER;
C_DCM2_CLKFX_DIVIDE : INTEGER;
C_DCM2_CLKDV_DIVIDE : REAL;
C_DCM2_CLKIN_PERIOD : REAL;
C_DCM2_DESKEW_ADJUST : STRING;
C_DCM2_CLKIN_BUF : BOOLEAN;
C_DCM2_CLKFB_BUF : BOOLEAN;
C_DCM2_CLK0_BUF : BOOLEAN;
C_DCM2_CLK90_BUF : BOOLEAN;
C_DCM2_CLK180_BUF : BOOLEAN;
C_DCM2_CLK270_BUF : BOOLEAN;
C_DCM2_CLKDV_BUF : BOOLEAN;
C_DCM2_CLKDV180_BUF : BOOLEAN;
C_DCM2_CLK2X_BUF : BOOLEAN;
C_DCM2_CLK2X180_BUF : BOOLEAN;
C_DCM2_CLKFX_BUF : BOOLEAN;
C_DCM2_CLKFX180_BUF : BOOLEAN;
C_DCM2_EXT_RESET_HIGH : INTEGER;
C_DCM2_FAMILY : STRING;
C_DCM2_CLKIN_MODULE : STRING;
C_DCM2_CLKIN_PORT : STRING;
C_DCM2_CLKFB_MODULE : STRING;
C_DCM2_CLKFB_PORT : STRING;
C_DCM2_RST_MODULE : STRING;
C_DCM3_DFS_FREQUENCY_MODE : STRING;
C_DCM3_DLL_FREQUENCY_MODE : STRING;
C_DCM3_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM3_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM3_CLK_FEEDBACK : STRING;
C_DCM3_CLKOUT_PHASE_SHIFT : STRING;
C_DCM3_DSS_MODE : STRING;
C_DCM3_STARTUP_WAIT : BOOLEAN;
C_DCM3_PHASE_SHIFT : INTEGER;
C_DCM3_CLKFX_MULTIPLY : INTEGER;
C_DCM3_CLKFX_DIVIDE : INTEGER;
C_DCM3_CLKDV_DIVIDE : REAL;
C_DCM3_CLKIN_PERIOD : REAL;
C_DCM3_DESKEW_ADJUST : STRING;
C_DCM3_CLKIN_BUF : BOOLEAN;
C_DCM3_CLKFB_BUF : BOOLEAN;
C_DCM3_CLK0_BUF : BOOLEAN;
C_DCM3_CLK90_BUF : BOOLEAN;
C_DCM3_CLK180_BUF : BOOLEAN;
C_DCM3_CLK270_BUF : BOOLEAN;
C_DCM3_CLKDV_BUF : BOOLEAN;
C_DCM3_CLKDV180_BUF : BOOLEAN;
C_DCM3_CLK2X_BUF : BOOLEAN;
C_DCM3_CLK2X180_BUF : BOOLEAN;
C_DCM3_CLKFX_BUF : BOOLEAN;
C_DCM3_CLKFX180_BUF : BOOLEAN;
C_DCM3_EXT_RESET_HIGH : INTEGER;
C_DCM3_FAMILY : STRING;
C_DCM3_CLKIN_MODULE : STRING;
C_DCM3_CLKIN_PORT : STRING;
C_DCM3_CLKFB_MODULE : STRING;
C_DCM3_CLKFB_PORT : STRING;
C_DCM3_RST_MODULE : STRING;
C_MMCM0_BANDWIDTH : STRING;
C_MMCM0_CLKFBOUT_MULT_F : REAL;
C_MMCM0_CLKFBOUT_PHASE : REAL;
C_MMCM0_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKIN1_PERIOD : REAL;
C_MMCM0_CLKOUT0_DIVIDE_F : REAL;
C_MMCM0_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT0_PHASE : REAL;
C_MMCM0_CLKOUT1_DIVIDE : INTEGER;
C_MMCM0_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT1_PHASE : REAL;
C_MMCM0_CLKOUT2_DIVIDE : INTEGER;
C_MMCM0_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT2_PHASE : REAL;
C_MMCM0_CLKOUT3_DIVIDE : INTEGER;
C_MMCM0_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT3_PHASE : REAL;
C_MMCM0_CLKOUT4_DIVIDE : INTEGER;
C_MMCM0_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT4_PHASE : REAL;
C_MMCM0_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM0_CLKOUT5_DIVIDE : INTEGER;
C_MMCM0_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT5_PHASE : REAL;
C_MMCM0_CLKOUT6_DIVIDE : INTEGER;
C_MMCM0_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT6_PHASE : REAL;
C_MMCM0_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM0_COMPENSATION : STRING;
C_MMCM0_DIVCLK_DIVIDE : INTEGER;
C_MMCM0_REF_JITTER1 : REAL;
C_MMCM0_CLKIN1_BUF : BOOLEAN;
C_MMCM0_CLKFBOUT_BUF : BOOLEAN;
C_MMCM0_CLOCK_HOLD : BOOLEAN;
C_MMCM0_STARTUP_WAIT : BOOLEAN;
C_MMCM0_EXT_RESET_HIGH : INTEGER;
C_MMCM0_FAMILY : STRING;
C_MMCM0_CLKOUT0_BUF : BOOLEAN;
C_MMCM0_CLKOUT1_BUF : BOOLEAN;
C_MMCM0_CLKOUT2_BUF : BOOLEAN;
C_MMCM0_CLKOUT3_BUF : BOOLEAN;
C_MMCM0_CLKOUT4_BUF : BOOLEAN;
C_MMCM0_CLKOUT5_BUF : BOOLEAN;
C_MMCM0_CLKOUT6_BUF : BOOLEAN;
C_MMCM0_CLKIN1_MODULE : STRING;
C_MMCM0_CLKIN1_PORT : STRING;
C_MMCM0_CLKFBIN_MODULE : STRING;
C_MMCM0_CLKFBIN_PORT : STRING;
C_MMCM0_RST_MODULE : STRING;
C_MMCM1_BANDWIDTH : STRING;
C_MMCM1_CLKFBOUT_MULT_F : REAL;
C_MMCM1_CLKFBOUT_PHASE : REAL;
C_MMCM1_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKIN1_PERIOD : REAL;
C_MMCM1_CLKOUT0_DIVIDE_F : REAL;
C_MMCM1_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT0_PHASE : REAL;
C_MMCM1_CLKOUT1_DIVIDE : INTEGER;
C_MMCM1_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT1_PHASE : REAL;
C_MMCM1_CLKOUT2_DIVIDE : INTEGER;
C_MMCM1_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT2_PHASE : REAL;
C_MMCM1_CLKOUT3_DIVIDE : INTEGER;
C_MMCM1_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT3_PHASE : REAL;
C_MMCM1_CLKOUT4_DIVIDE : INTEGER;
C_MMCM1_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT4_PHASE : REAL;
C_MMCM1_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM1_CLKOUT5_DIVIDE : INTEGER;
C_MMCM1_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT5_PHASE : REAL;
C_MMCM1_CLKOUT6_DIVIDE : INTEGER;
C_MMCM1_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT6_PHASE : REAL;
C_MMCM1_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM1_COMPENSATION : STRING;
C_MMCM1_DIVCLK_DIVIDE : INTEGER;
C_MMCM1_REF_JITTER1 : REAL;
C_MMCM1_CLKIN1_BUF : BOOLEAN;
C_MMCM1_CLKFBOUT_BUF : BOOLEAN;
C_MMCM1_CLOCK_HOLD : BOOLEAN;
C_MMCM1_STARTUP_WAIT : BOOLEAN;
C_MMCM1_EXT_RESET_HIGH : INTEGER;
C_MMCM1_FAMILY : STRING;
C_MMCM1_CLKOUT0_BUF : BOOLEAN;
C_MMCM1_CLKOUT1_BUF : BOOLEAN;
C_MMCM1_CLKOUT2_BUF : BOOLEAN;
C_MMCM1_CLKOUT3_BUF : BOOLEAN;
C_MMCM1_CLKOUT4_BUF : BOOLEAN;
C_MMCM1_CLKOUT5_BUF : BOOLEAN;
C_MMCM1_CLKOUT6_BUF : BOOLEAN;
C_MMCM1_CLKIN1_MODULE : STRING;
C_MMCM1_CLKIN1_PORT : STRING;
C_MMCM1_CLKFBIN_MODULE : STRING;
C_MMCM1_CLKFBIN_PORT : STRING;
C_MMCM1_RST_MODULE : STRING;
C_MMCM2_BANDWIDTH : STRING;
C_MMCM2_CLKFBOUT_MULT_F : REAL;
C_MMCM2_CLKFBOUT_PHASE : REAL;
C_MMCM2_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKIN1_PERIOD : REAL;
C_MMCM2_CLKOUT0_DIVIDE_F : REAL;
C_MMCM2_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT0_PHASE : REAL;
C_MMCM2_CLKOUT1_DIVIDE : INTEGER;
C_MMCM2_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT1_PHASE : REAL;
C_MMCM2_CLKOUT2_DIVIDE : INTEGER;
C_MMCM2_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT2_PHASE : REAL;
C_MMCM2_CLKOUT3_DIVIDE : INTEGER;
C_MMCM2_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT3_PHASE : REAL;
C_MMCM2_CLKOUT4_DIVIDE : INTEGER;
C_MMCM2_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT4_PHASE : REAL;
C_MMCM2_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM2_CLKOUT5_DIVIDE : INTEGER;
C_MMCM2_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT5_PHASE : REAL;
C_MMCM2_CLKOUT6_DIVIDE : INTEGER;
C_MMCM2_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT6_PHASE : REAL;
C_MMCM2_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM2_COMPENSATION : STRING;
C_MMCM2_DIVCLK_DIVIDE : INTEGER;
C_MMCM2_REF_JITTER1 : REAL;
C_MMCM2_CLKIN1_BUF : BOOLEAN;
C_MMCM2_CLKFBOUT_BUF : BOOLEAN;
C_MMCM2_CLOCK_HOLD : BOOLEAN;
C_MMCM2_STARTUP_WAIT : BOOLEAN;
C_MMCM2_EXT_RESET_HIGH : INTEGER;
C_MMCM2_FAMILY : STRING;
C_MMCM2_CLKOUT0_BUF : BOOLEAN;
C_MMCM2_CLKOUT1_BUF : BOOLEAN;
C_MMCM2_CLKOUT2_BUF : BOOLEAN;
C_MMCM2_CLKOUT3_BUF : BOOLEAN;
C_MMCM2_CLKOUT4_BUF : BOOLEAN;
C_MMCM2_CLKOUT5_BUF : BOOLEAN;
C_MMCM2_CLKOUT6_BUF : BOOLEAN;
C_MMCM2_CLKIN1_MODULE : STRING;
C_MMCM2_CLKIN1_PORT : STRING;
C_MMCM2_CLKFBIN_MODULE : STRING;
C_MMCM2_CLKFBIN_PORT : STRING;
C_MMCM2_RST_MODULE : STRING;
C_MMCM3_BANDWIDTH : STRING;
C_MMCM3_CLKFBOUT_MULT_F : REAL;
C_MMCM3_CLKFBOUT_PHASE : REAL;
C_MMCM3_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKIN1_PERIOD : REAL;
C_MMCM3_CLKOUT0_DIVIDE_F : REAL;
C_MMCM3_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT0_PHASE : REAL;
C_MMCM3_CLKOUT1_DIVIDE : INTEGER;
C_MMCM3_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT1_PHASE : REAL;
C_MMCM3_CLKOUT2_DIVIDE : INTEGER;
C_MMCM3_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT2_PHASE : REAL;
C_MMCM3_CLKOUT3_DIVIDE : INTEGER;
C_MMCM3_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT3_PHASE : REAL;
C_MMCM3_CLKOUT4_DIVIDE : INTEGER;
C_MMCM3_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT4_PHASE : REAL;
C_MMCM3_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM3_CLKOUT5_DIVIDE : INTEGER;
C_MMCM3_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT5_PHASE : REAL;
C_MMCM3_CLKOUT6_DIVIDE : INTEGER;
C_MMCM3_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT6_PHASE : REAL;
C_MMCM3_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM3_COMPENSATION : STRING;
C_MMCM3_DIVCLK_DIVIDE : INTEGER;
C_MMCM3_REF_JITTER1 : REAL;
C_MMCM3_CLKIN1_BUF : BOOLEAN;
C_MMCM3_CLKFBOUT_BUF : BOOLEAN;
C_MMCM3_CLOCK_HOLD : BOOLEAN;
C_MMCM3_STARTUP_WAIT : BOOLEAN;
C_MMCM3_EXT_RESET_HIGH : INTEGER;
C_MMCM3_FAMILY : STRING;
C_MMCM3_CLKOUT0_BUF : BOOLEAN;
C_MMCM3_CLKOUT1_BUF : BOOLEAN;
C_MMCM3_CLKOUT2_BUF : BOOLEAN;
C_MMCM3_CLKOUT3_BUF : BOOLEAN;
C_MMCM3_CLKOUT4_BUF : BOOLEAN;
C_MMCM3_CLKOUT5_BUF : BOOLEAN;
C_MMCM3_CLKOUT6_BUF : BOOLEAN;
C_MMCM3_CLKIN1_MODULE : STRING;
C_MMCM3_CLKIN1_PORT : STRING;
C_MMCM3_CLKFBIN_MODULE : STRING;
C_MMCM3_CLKFBIN_PORT : STRING;
C_MMCM3_RST_MODULE : STRING
);
port (
CLKIN : in std_logic;
CLKFBIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "virtex5",
C_SPEEDGRADE => "-1",
C_EXT_RESET_HIGH => 0,
C_CLK_GEN => "PASSED",
C_CLKOUT0_MODULE => "PLL0",
C_CLKOUT0_PORT => "CLKOUT0B",
C_CLKOUT1_MODULE => "PLL0",
C_CLKOUT1_PORT => "CLKOUT1B",
C_CLKOUT2_MODULE => "PLL0",
C_CLKOUT2_PORT => "CLKOUT2B",
C_CLKOUT3_MODULE => "PLL0",
C_CLKOUT3_PORT => "CLKOUT3B",
C_CLKOUT4_MODULE => "NONE",
C_CLKOUT4_PORT => "NONE",
C_CLKOUT5_MODULE => "NONE",
C_CLKOUT5_PORT => "NONE",
C_CLKOUT6_MODULE => "NONE",
C_CLKOUT6_PORT => "NONE",
C_CLKOUT7_MODULE => "NONE",
C_CLKOUT7_PORT => "NONE",
C_CLKOUT8_MODULE => "NONE",
C_CLKOUT8_PORT => "NONE",
C_CLKOUT9_MODULE => "NONE",
C_CLKOUT9_PORT => "NONE",
C_CLKOUT10_MODULE => "NONE",
C_CLKOUT10_PORT => "NONE",
C_CLKOUT11_MODULE => "NONE",
C_CLKOUT11_PORT => "NONE",
C_CLKOUT12_MODULE => "NONE",
C_CLKOUT12_PORT => "NONE",
C_CLKOUT13_MODULE => "NONE",
C_CLKOUT13_PORT => "NONE",
C_CLKOUT14_MODULE => "NONE",
C_CLKOUT14_PORT => "NONE",
C_CLKOUT15_MODULE => "NONE",
C_CLKOUT15_PORT => "NONE",
C_CLKFBOUT_MODULE => "NONE",
C_CLKFBOUT_PORT => "NONE",
C_PSDONE_MODULE => "NONE",
C_PLL0_DIVCLK_DIVIDE => 1,
C_PLL0_CLKFBOUT_MULT => 10,
C_PLL0_CLKFBOUT_PHASE => 0.000000,
C_PLL0_CLKIN1_PERIOD => 10.000000,
C_PLL0_CLKOUT0_DIVIDE => 8,
C_PLL0_CLKOUT0_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT0_PHASE => 90.000000,
C_PLL0_CLKOUT1_DIVIDE => 8,
C_PLL0_CLKOUT1_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT1_PHASE => 0.000000,
C_PLL0_CLKOUT2_DIVIDE => 5,
C_PLL0_CLKOUT2_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT2_PHASE => 0.000000,
C_PLL0_CLKOUT3_DIVIDE => 4,
C_PLL0_CLKOUT3_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT3_PHASE => 0.000000,
C_PLL0_CLKOUT4_DIVIDE => 1,
C_PLL0_CLKOUT4_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT4_PHASE => 0.000000,
C_PLL0_CLKOUT5_DIVIDE => 1,
C_PLL0_CLKOUT5_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT5_PHASE => 0.000000,
C_PLL0_BANDWIDTH => "OPTIMIZED",
C_PLL0_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_PLL0_REF_JITTER => 0.100000,
C_PLL0_RESET_ON_LOSS_OF_LOCK => false,
C_PLL0_RST_DEASSERT_CLK => "CLKIN1",
C_PLL0_EXT_RESET_HIGH => 0,
C_PLL0_FAMILY => "virtex5",
C_PLL0_CLKOUT0_DESKEW_ADJUST => "PPC",
C_PLL0_CLKOUT1_DESKEW_ADJUST => "PPC",
C_PLL0_CLKOUT2_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT3_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT4_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT5_DESKEW_ADJUST => "NONE",
C_PLL0_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_PLL0_CLKIN1_BUF => false,
C_PLL0_CLKFBOUT_BUF => TRUE,
C_PLL0_CLKOUT0_BUF => TRUE,
C_PLL0_CLKOUT1_BUF => TRUE,
C_PLL0_CLKOUT2_BUF => TRUE,
C_PLL0_CLKOUT3_BUF => TRUE,
C_PLL0_CLKOUT4_BUF => false,
C_PLL0_CLKOUT5_BUF => false,
C_PLL0_CLKIN1_MODULE => "CLKGEN",
C_PLL0_CLKIN1_PORT => "CLKIN",
C_PLL0_CLKFBIN_MODULE => "PLL0",
C_PLL0_CLKFBIN_PORT => "CLKFBOUT",
C_PLL0_RST_MODULE => "CLKGEN",
C_PLL1_DIVCLK_DIVIDE => 1,
C_PLL1_CLKFBOUT_MULT => 1,
C_PLL1_CLKFBOUT_PHASE => 0.000000,
C_PLL1_CLKIN1_PERIOD => 0.000000,
C_PLL1_CLKOUT0_DIVIDE => 1,
C_PLL1_CLKOUT0_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT0_PHASE => 0.000000,
C_PLL1_CLKOUT1_DIVIDE => 1,
C_PLL1_CLKOUT1_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT1_PHASE => 0.000000,
C_PLL1_CLKOUT2_DIVIDE => 1,
C_PLL1_CLKOUT2_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT2_PHASE => 0.000000,
C_PLL1_CLKOUT3_DIVIDE => 1,
C_PLL1_CLKOUT3_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT3_PHASE => 0.000000,
C_PLL1_CLKOUT4_DIVIDE => 1,
C_PLL1_CLKOUT4_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT4_PHASE => 0.000000,
C_PLL1_CLKOUT5_DIVIDE => 1,
C_PLL1_CLKOUT5_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT5_PHASE => 0.000000,
C_PLL1_BANDWIDTH => "OPTIMIZED",
C_PLL1_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_PLL1_REF_JITTER => 0.100000,
C_PLL1_RESET_ON_LOSS_OF_LOCK => false,
C_PLL1_RST_DEASSERT_CLK => "CLKIN1",
C_PLL1_EXT_RESET_HIGH => 1,
C_PLL1_FAMILY => "virtex5",
C_PLL1_CLKOUT0_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT1_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT2_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT3_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT4_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT5_DESKEW_ADJUST => "NONE",
C_PLL1_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_PLL1_CLKIN1_BUF => false,
C_PLL1_CLKFBOUT_BUF => false,
C_PLL1_CLKOUT0_BUF => false,
C_PLL1_CLKOUT1_BUF => false,
C_PLL1_CLKOUT2_BUF => false,
C_PLL1_CLKOUT3_BUF => false,
C_PLL1_CLKOUT4_BUF => false,
C_PLL1_CLKOUT5_BUF => false,
C_PLL1_CLKIN1_MODULE => "NONE",
C_PLL1_CLKIN1_PORT => "NONE",
C_PLL1_CLKFBIN_MODULE => "NONE",
C_PLL1_CLKFBIN_PORT => "NONE",
C_PLL1_RST_MODULE => "NONE",
C_DCM0_DFS_FREQUENCY_MODE => "LOW",
C_DCM0_DLL_FREQUENCY_MODE => "LOW",
C_DCM0_DUTY_CYCLE_CORRECTION => true,
C_DCM0_CLKIN_DIVIDE_BY_2 => false,
C_DCM0_CLK_FEEDBACK => "1X",
C_DCM0_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM0_DSS_MODE => "NONE",
C_DCM0_STARTUP_WAIT => false,
C_DCM0_PHASE_SHIFT => 0,
C_DCM0_CLKFX_MULTIPLY => 4,
C_DCM0_CLKFX_DIVIDE => 1,
C_DCM0_CLKDV_DIVIDE => 2.000000,
C_DCM0_CLKIN_PERIOD => 0.000000,
C_DCM0_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM0_CLKIN_BUF => false,
C_DCM0_CLKFB_BUF => false,
C_DCM0_CLK0_BUF => false,
C_DCM0_CLK90_BUF => false,
C_DCM0_CLK180_BUF => false,
C_DCM0_CLK270_BUF => false,
C_DCM0_CLKDV_BUF => false,
C_DCM0_CLKDV180_BUF => false,
C_DCM0_CLK2X_BUF => false,
C_DCM0_CLK2X180_BUF => false,
C_DCM0_CLKFX_BUF => false,
C_DCM0_CLKFX180_BUF => false,
C_DCM0_EXT_RESET_HIGH => 1,
C_DCM0_FAMILY => "virtex5",
C_DCM0_CLKIN_MODULE => "NONE",
C_DCM0_CLKIN_PORT => "NONE",
C_DCM0_CLKFB_MODULE => "NONE",
C_DCM0_CLKFB_PORT => "NONE",
C_DCM0_RST_MODULE => "NONE",
C_DCM1_DFS_FREQUENCY_MODE => "LOW",
C_DCM1_DLL_FREQUENCY_MODE => "LOW",
C_DCM1_DUTY_CYCLE_CORRECTION => true,
C_DCM1_CLKIN_DIVIDE_BY_2 => false,
C_DCM1_CLK_FEEDBACK => "1X",
C_DCM1_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM1_DSS_MODE => "NONE",
C_DCM1_STARTUP_WAIT => false,
C_DCM1_PHASE_SHIFT => 0,
C_DCM1_CLKFX_MULTIPLY => 4,
C_DCM1_CLKFX_DIVIDE => 1,
C_DCM1_CLKDV_DIVIDE => 2.000000,
C_DCM1_CLKIN_PERIOD => 0.000000,
C_DCM1_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM1_CLKIN_BUF => false,
C_DCM1_CLKFB_BUF => false,
C_DCM1_CLK0_BUF => false,
C_DCM1_CLK90_BUF => false,
C_DCM1_CLK180_BUF => false,
C_DCM1_CLK270_BUF => false,
C_DCM1_CLKDV_BUF => false,
C_DCM1_CLKDV180_BUF => false,
C_DCM1_CLK2X_BUF => false,
C_DCM1_CLK2X180_BUF => false,
C_DCM1_CLKFX_BUF => false,
C_DCM1_CLKFX180_BUF => false,
C_DCM1_EXT_RESET_HIGH => 1,
C_DCM1_FAMILY => "virtex5",
C_DCM1_CLKIN_MODULE => "NONE",
C_DCM1_CLKIN_PORT => "NONE",
C_DCM1_CLKFB_MODULE => "NONE",
C_DCM1_CLKFB_PORT => "NONE",
C_DCM1_RST_MODULE => "NONE",
C_DCM2_DFS_FREQUENCY_MODE => "LOW",
C_DCM2_DLL_FREQUENCY_MODE => "LOW",
C_DCM2_DUTY_CYCLE_CORRECTION => true,
C_DCM2_CLKIN_DIVIDE_BY_2 => false,
C_DCM2_CLK_FEEDBACK => "1X",
C_DCM2_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM2_DSS_MODE => "NONE",
C_DCM2_STARTUP_WAIT => false,
C_DCM2_PHASE_SHIFT => 0,
C_DCM2_CLKFX_MULTIPLY => 4,
C_DCM2_CLKFX_DIVIDE => 1,
C_DCM2_CLKDV_DIVIDE => 2.000000,
C_DCM2_CLKIN_PERIOD => 0.000000,
C_DCM2_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM2_CLKIN_BUF => false,
C_DCM2_CLKFB_BUF => false,
C_DCM2_CLK0_BUF => false,
C_DCM2_CLK90_BUF => false,
C_DCM2_CLK180_BUF => false,
C_DCM2_CLK270_BUF => false,
C_DCM2_CLKDV_BUF => false,
C_DCM2_CLKDV180_BUF => false,
C_DCM2_CLK2X_BUF => false,
C_DCM2_CLK2X180_BUF => false,
C_DCM2_CLKFX_BUF => false,
C_DCM2_CLKFX180_BUF => false,
C_DCM2_EXT_RESET_HIGH => 1,
C_DCM2_FAMILY => "virtex5",
C_DCM2_CLKIN_MODULE => "NONE",
C_DCM2_CLKIN_PORT => "NONE",
C_DCM2_CLKFB_MODULE => "NONE",
C_DCM2_CLKFB_PORT => "NONE",
C_DCM2_RST_MODULE => "NONE",
C_DCM3_DFS_FREQUENCY_MODE => "LOW",
C_DCM3_DLL_FREQUENCY_MODE => "LOW",
C_DCM3_DUTY_CYCLE_CORRECTION => true,
C_DCM3_CLKIN_DIVIDE_BY_2 => false,
C_DCM3_CLK_FEEDBACK => "1X",
C_DCM3_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM3_DSS_MODE => "NONE",
C_DCM3_STARTUP_WAIT => false,
C_DCM3_PHASE_SHIFT => 0,
C_DCM3_CLKFX_MULTIPLY => 4,
C_DCM3_CLKFX_DIVIDE => 1,
C_DCM3_CLKDV_DIVIDE => 2.000000,
C_DCM3_CLKIN_PERIOD => 0.000000,
C_DCM3_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM3_CLKIN_BUF => false,
C_DCM3_CLKFB_BUF => false,
C_DCM3_CLK0_BUF => false,
C_DCM3_CLK90_BUF => false,
C_DCM3_CLK180_BUF => false,
C_DCM3_CLK270_BUF => false,
C_DCM3_CLKDV_BUF => false,
C_DCM3_CLKDV180_BUF => false,
C_DCM3_CLK2X_BUF => false,
C_DCM3_CLK2X180_BUF => false,
C_DCM3_CLKFX_BUF => false,
C_DCM3_CLKFX180_BUF => false,
C_DCM3_EXT_RESET_HIGH => 1,
C_DCM3_FAMILY => "virtex5",
C_DCM3_CLKIN_MODULE => "NONE",
C_DCM3_CLKIN_PORT => "NONE",
C_DCM3_CLKFB_MODULE => "NONE",
C_DCM3_CLKFB_PORT => "NONE",
C_DCM3_RST_MODULE => "NONE",
C_MMCM0_BANDWIDTH => "OPTIMIZED",
C_MMCM0_CLKFBOUT_MULT_F => 1.000000,
C_MMCM0_CLKFBOUT_PHASE => 0.000000,
C_MMCM0_CLKFBOUT_USE_FINE_PS => false,
C_MMCM0_CLKIN1_PERIOD => 0.000000,
C_MMCM0_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM0_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT0_PHASE => 0.000000,
C_MMCM0_CLKOUT1_DIVIDE => 1,
C_MMCM0_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT1_PHASE => 0.000000,
C_MMCM0_CLKOUT2_DIVIDE => 1,
C_MMCM0_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT2_PHASE => 0.000000,
C_MMCM0_CLKOUT3_DIVIDE => 1,
C_MMCM0_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT3_PHASE => 0.000000,
C_MMCM0_CLKOUT4_DIVIDE => 1,
C_MMCM0_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT4_PHASE => 0.000000,
C_MMCM0_CLKOUT4_CASCADE => false,
C_MMCM0_CLKOUT5_DIVIDE => 1,
C_MMCM0_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT5_PHASE => 0.000000,
C_MMCM0_CLKOUT6_DIVIDE => 1,
C_MMCM0_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT6_PHASE => 0.000000,
C_MMCM0_CLKOUT0_USE_FINE_PS => false,
C_MMCM0_CLKOUT1_USE_FINE_PS => false,
C_MMCM0_CLKOUT2_USE_FINE_PS => false,
C_MMCM0_CLKOUT3_USE_FINE_PS => false,
C_MMCM0_CLKOUT4_USE_FINE_PS => false,
C_MMCM0_CLKOUT5_USE_FINE_PS => false,
C_MMCM0_CLKOUT6_USE_FINE_PS => false,
C_MMCM0_COMPENSATION => "ZHOLD",
C_MMCM0_DIVCLK_DIVIDE => 1,
C_MMCM0_REF_JITTER1 => 0.010000,
C_MMCM0_CLKIN1_BUF => false,
C_MMCM0_CLKFBOUT_BUF => false,
C_MMCM0_CLOCK_HOLD => false,
C_MMCM0_STARTUP_WAIT => false,
C_MMCM0_EXT_RESET_HIGH => 1,
C_MMCM0_FAMILY => "virtex5",
C_MMCM0_CLKOUT0_BUF => false,
C_MMCM0_CLKOUT1_BUF => false,
C_MMCM0_CLKOUT2_BUF => false,
C_MMCM0_CLKOUT3_BUF => false,
C_MMCM0_CLKOUT4_BUF => false,
C_MMCM0_CLKOUT5_BUF => false,
C_MMCM0_CLKOUT6_BUF => false,
C_MMCM0_CLKIN1_MODULE => "NONE",
C_MMCM0_CLKIN1_PORT => "NONE",
C_MMCM0_CLKFBIN_MODULE => "NONE",
C_MMCM0_CLKFBIN_PORT => "NONE",
C_MMCM0_RST_MODULE => "NONE",
C_MMCM1_BANDWIDTH => "OPTIMIZED",
C_MMCM1_CLKFBOUT_MULT_F => 1.000000,
C_MMCM1_CLKFBOUT_PHASE => 0.000000,
C_MMCM1_CLKFBOUT_USE_FINE_PS => false,
C_MMCM1_CLKIN1_PERIOD => 0.000000,
C_MMCM1_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM1_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT0_PHASE => 0.000000,
C_MMCM1_CLKOUT1_DIVIDE => 1,
C_MMCM1_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT1_PHASE => 0.000000,
C_MMCM1_CLKOUT2_DIVIDE => 1,
C_MMCM1_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT2_PHASE => 0.000000,
C_MMCM1_CLKOUT3_DIVIDE => 1,
C_MMCM1_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT3_PHASE => 0.000000,
C_MMCM1_CLKOUT4_DIVIDE => 1,
C_MMCM1_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT4_PHASE => 0.000000,
C_MMCM1_CLKOUT4_CASCADE => false,
C_MMCM1_CLKOUT5_DIVIDE => 1,
C_MMCM1_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT5_PHASE => 0.000000,
C_MMCM1_CLKOUT6_DIVIDE => 1,
C_MMCM1_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT6_PHASE => 0.000000,
C_MMCM1_CLKOUT0_USE_FINE_PS => false,
C_MMCM1_CLKOUT1_USE_FINE_PS => false,
C_MMCM1_CLKOUT2_USE_FINE_PS => false,
C_MMCM1_CLKOUT3_USE_FINE_PS => false,
C_MMCM1_CLKOUT4_USE_FINE_PS => false,
C_MMCM1_CLKOUT5_USE_FINE_PS => false,
C_MMCM1_CLKOUT6_USE_FINE_PS => false,
C_MMCM1_COMPENSATION => "ZHOLD",
C_MMCM1_DIVCLK_DIVIDE => 1,
C_MMCM1_REF_JITTER1 => 0.010000,
C_MMCM1_CLKIN1_BUF => false,
C_MMCM1_CLKFBOUT_BUF => false,
C_MMCM1_CLOCK_HOLD => false,
C_MMCM1_STARTUP_WAIT => false,
C_MMCM1_EXT_RESET_HIGH => 1,
C_MMCM1_FAMILY => "virtex5",
C_MMCM1_CLKOUT0_BUF => false,
C_MMCM1_CLKOUT1_BUF => false,
C_MMCM1_CLKOUT2_BUF => false,
C_MMCM1_CLKOUT3_BUF => false,
C_MMCM1_CLKOUT4_BUF => false,
C_MMCM1_CLKOUT5_BUF => false,
C_MMCM1_CLKOUT6_BUF => false,
C_MMCM1_CLKIN1_MODULE => "NONE",
C_MMCM1_CLKIN1_PORT => "NONE",
C_MMCM1_CLKFBIN_MODULE => "NONE",
C_MMCM1_CLKFBIN_PORT => "NONE",
C_MMCM1_RST_MODULE => "NONE",
C_MMCM2_BANDWIDTH => "OPTIMIZED",
C_MMCM2_CLKFBOUT_MULT_F => 1.000000,
C_MMCM2_CLKFBOUT_PHASE => 0.000000,
C_MMCM2_CLKFBOUT_USE_FINE_PS => false,
C_MMCM2_CLKIN1_PERIOD => 0.000000,
C_MMCM2_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM2_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT0_PHASE => 0.000000,
C_MMCM2_CLKOUT1_DIVIDE => 1,
C_MMCM2_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT1_PHASE => 0.000000,
C_MMCM2_CLKOUT2_DIVIDE => 1,
C_MMCM2_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT2_PHASE => 0.000000,
C_MMCM2_CLKOUT3_DIVIDE => 1,
C_MMCM2_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT3_PHASE => 0.000000,
C_MMCM2_CLKOUT4_DIVIDE => 1,
C_MMCM2_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT4_PHASE => 0.000000,
C_MMCM2_CLKOUT4_CASCADE => false,
C_MMCM2_CLKOUT5_DIVIDE => 1,
C_MMCM2_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT5_PHASE => 0.000000,
C_MMCM2_CLKOUT6_DIVIDE => 1,
C_MMCM2_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT6_PHASE => 0.000000,
C_MMCM2_CLKOUT0_USE_FINE_PS => false,
C_MMCM2_CLKOUT1_USE_FINE_PS => false,
C_MMCM2_CLKOUT2_USE_FINE_PS => false,
C_MMCM2_CLKOUT3_USE_FINE_PS => false,
C_MMCM2_CLKOUT4_USE_FINE_PS => false,
C_MMCM2_CLKOUT5_USE_FINE_PS => false,
C_MMCM2_CLKOUT6_USE_FINE_PS => false,
C_MMCM2_COMPENSATION => "ZHOLD",
C_MMCM2_DIVCLK_DIVIDE => 1,
C_MMCM2_REF_JITTER1 => 0.010000,
C_MMCM2_CLKIN1_BUF => false,
C_MMCM2_CLKFBOUT_BUF => false,
C_MMCM2_CLOCK_HOLD => false,
C_MMCM2_STARTUP_WAIT => false,
C_MMCM2_EXT_RESET_HIGH => 1,
C_MMCM2_FAMILY => "virtex5",
C_MMCM2_CLKOUT0_BUF => false,
C_MMCM2_CLKOUT1_BUF => false,
C_MMCM2_CLKOUT2_BUF => false,
C_MMCM2_CLKOUT3_BUF => false,
C_MMCM2_CLKOUT4_BUF => false,
C_MMCM2_CLKOUT5_BUF => false,
C_MMCM2_CLKOUT6_BUF => false,
C_MMCM2_CLKIN1_MODULE => "NONE",
C_MMCM2_CLKIN1_PORT => "NONE",
C_MMCM2_CLKFBIN_MODULE => "NONE",
C_MMCM2_CLKFBIN_PORT => "NONE",
C_MMCM2_RST_MODULE => "NONE",
C_MMCM3_BANDWIDTH => "OPTIMIZED",
C_MMCM3_CLKFBOUT_MULT_F => 1.000000,
C_MMCM3_CLKFBOUT_PHASE => 0.000000,
C_MMCM3_CLKFBOUT_USE_FINE_PS => false,
C_MMCM3_CLKIN1_PERIOD => 0.000000,
C_MMCM3_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM3_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT0_PHASE => 0.000000,
C_MMCM3_CLKOUT1_DIVIDE => 1,
C_MMCM3_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT1_PHASE => 0.000000,
C_MMCM3_CLKOUT2_DIVIDE => 1,
C_MMCM3_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT2_PHASE => 0.000000,
C_MMCM3_CLKOUT3_DIVIDE => 1,
C_MMCM3_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT3_PHASE => 0.000000,
C_MMCM3_CLKOUT4_DIVIDE => 1,
C_MMCM3_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT4_PHASE => 0.000000,
C_MMCM3_CLKOUT4_CASCADE => false,
C_MMCM3_CLKOUT5_DIVIDE => 1,
C_MMCM3_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT5_PHASE => 0.000000,
C_MMCM3_CLKOUT6_DIVIDE => 1,
C_MMCM3_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT6_PHASE => 0.000000,
C_MMCM3_CLKOUT0_USE_FINE_PS => false,
C_MMCM3_CLKOUT1_USE_FINE_PS => false,
C_MMCM3_CLKOUT2_USE_FINE_PS => false,
C_MMCM3_CLKOUT3_USE_FINE_PS => false,
C_MMCM3_CLKOUT4_USE_FINE_PS => false,
C_MMCM3_CLKOUT5_USE_FINE_PS => false,
C_MMCM3_CLKOUT6_USE_FINE_PS => false,
C_MMCM3_COMPENSATION => "ZHOLD",
C_MMCM3_DIVCLK_DIVIDE => 1,
C_MMCM3_REF_JITTER1 => 0.010000,
C_MMCM3_CLKIN1_BUF => false,
C_MMCM3_CLKFBOUT_BUF => false,
C_MMCM3_CLOCK_HOLD => false,
C_MMCM3_STARTUP_WAIT => false,
C_MMCM3_EXT_RESET_HIGH => 1,
C_MMCM3_FAMILY => "virtex5",
C_MMCM3_CLKOUT0_BUF => false,
C_MMCM3_CLKOUT1_BUF => false,
C_MMCM3_CLKOUT2_BUF => false,
C_MMCM3_CLKOUT3_BUF => false,
C_MMCM3_CLKOUT4_BUF => false,
C_MMCM3_CLKOUT5_BUF => false,
C_MMCM3_CLKOUT6_BUF => false,
C_MMCM3_CLKIN1_MODULE => "NONE",
C_MMCM3_CLKIN1_PORT => "NONE",
C_MMCM3_CLKFBIN_MODULE => "NONE",
C_MMCM3_CLKFBIN_PORT => "NONE",
C_MMCM3_RST_MODULE => "NONE"
)
port map (
CLKIN => CLKIN,
CLKFBIN => CLKFBIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/highpass_filter_v1_00_a/sim/matrix_gen.vhd | 1 | 3520 | -- matrix_pixel_gen.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity matrix_pixel_gen is
port (
CLK : in std_logic;
RST : in std_logic;
R : out std_logic_vector(71 downto 0);
G : out std_logic_vector(71 downto 0);
B : out std_logic_vector(71 downto 0);
PX_REQ : in std_logic
);
end entity;
architecture plain_numbers of matrix_pixel_gen is
begin
read_file : process(CLK, RST, PX_REQ)
file infile : text;
variable l : line;
variable vr0 : integer;
variable vg0 : integer;
variable vb0 : integer;
variable vr1 : integer;
variable vg1 : integer;
variable vb1 : integer;
variable vr2 : integer;
variable vg2 : integer;
variable vb2 : integer;
variable vr3 : integer;
variable vg3 : integer;
variable vb3 : integer;
variable vr4 : integer;
variable vg4 : integer;
variable vb4 : integer;
variable vr5 : integer;
variable vg5 : integer;
variable vb5 : integer;
variable vr6 : integer;
variable vg6 : integer;
variable vb6 : integer;
variable vr7 : integer;
variable vg7 : integer;
variable vb7 : integer;
variable vr8 : integer;
variable vg8 : integer;
variable vb8 : integer;
procedure read_matrix is
begin
readline(infile, l);
read(l, vr0); read(l, vg0); read(l, vb0);
read(l, vr1); read(l, vg1); read(l, vb1);
read(l, vr2); read(l, vg2); read(l, vb2);
read(l, vr3); read(l, vg3); read(l, vb3);
read(l, vr4); read(l, vg4); read(l, vb4);
read(l, vr5); read(l, vg5); read(l, vb5);
read(l, vr6); read(l, vg6); read(l, vb6);
read(l, vr7); read(l, vg7); read(l, vb7);
read(l, vr8); read(l, vg8); read(l, vb8);
R( 7 downto 0) <= conv_std_logic_vector(vr0, 8);
G( 7 downto 0) <= conv_std_logic_vector(vg0, 8);
B( 7 downto 0) <= conv_std_logic_vector(vb0, 8);
R(15 downto 8) <= conv_std_logic_vector(vr1, 8);
G(15 downto 8) <= conv_std_logic_vector(vg1, 8);
B(15 downto 8) <= conv_std_logic_vector(vb1, 8);
R(23 downto 16) <= conv_std_logic_vector(vr2, 8);
G(23 downto 16) <= conv_std_logic_vector(vg2, 8);
B(23 downto 16) <= conv_std_logic_vector(vb2, 8);
R(31 downto 24) <= conv_std_logic_vector(vr3, 8);
G(31 downto 24) <= conv_std_logic_vector(vg3, 8);
B(31 downto 24) <= conv_std_logic_vector(vb3, 8);
R(39 downto 32) <= conv_std_logic_vector(vr4, 8);
G(39 downto 32) <= conv_std_logic_vector(vg4, 8);
B(39 downto 32) <= conv_std_logic_vector(vb4, 8);
R(47 downto 40) <= conv_std_logic_vector(vr5, 8);
G(47 downto 40) <= conv_std_logic_vector(vg5, 8);
B(47 downto 40) <= conv_std_logic_vector(vb5, 8);
R(55 downto 48) <= conv_std_logic_vector(vr6, 8);
G(55 downto 48) <= conv_std_logic_vector(vg6, 8);
B(55 downto 48) <= conv_std_logic_vector(vb6, 8);
R(63 downto 56) <= conv_std_logic_vector(vr7, 8);
G(63 downto 56) <= conv_std_logic_vector(vg7, 8);
B(63 downto 56) <= conv_std_logic_vector(vb7, 8);
R(71 downto 64) <= conv_std_logic_vector(vr8, 8);
G(71 downto 64) <= conv_std_logic_vector(vg8, 8);
B(71 downto 64) <= conv_std_logic_vector(vb8, 8);
end procedure;
begin
if rising_edge(CLK) then
if RST = '1' or endfile(infile) then
file_close(infile);
file_open(infile, "input_file.txt", READ_MODE);
read_matrix;
elsif PX_REQ = '1' then
read_matrix;
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
sandeshghimire/model-based-fpga-desing | matlab_model/hdlsrc/hdlcodercpu_eml/Program_Counter.vhd | 1 | 2820 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Program_Counter.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Program_Counter
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Program Counter
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Program_Counter IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
func : IN std_logic_vector(1 DOWNTO 0); -- ufix2
addr_in : IN std_logic_vector(7 DOWNTO 0); -- uint8
addr_out : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END Program_Counter;
ARCHITECTURE rtl OF Program_Counter IS
-- Signals
SIGNAL func_unsigned : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL addr_in_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL addr_out_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL PC_value : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL PC_value_next : unsigned(7 DOWNTO 0); -- ufix8
BEGIN
func_unsigned <= unsigned(func);
addr_in_unsigned <= unsigned(addr_in);
Program_Counter_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
PC_value <= to_unsigned(2#00000000#, 8);
ELSIF enb = '1' THEN
PC_value <= PC_value_next;
END IF;
END IF;
END PROCESS Program_Counter_1_process;
Program_Counter_1_output : PROCESS (func_unsigned, addr_in_unsigned, PC_value)
BEGIN
PC_value_next <= PC_value;
--MATLAB Function 'CPU_Subsystem_8_bit/Program Counter': '<S10>:1'
-- Program Counter
-- func = 0 => reset PC
-- func = 1 => load PC
-- func = 2 => increment PC
-- HDL specific fimath
--'<S10>:1:20'
addr_out_tmp <= PC_value;
CASE func_unsigned IS
WHEN "00" =>
-- reset
--'<S10>:1:25'
PC_value_next <= to_unsigned(2#00000000#, 8);
WHEN "01" =>
-- store into PC
--'<S10>:1:28'
PC_value_next <= addr_in_unsigned;
WHEN "10" =>
-- increment PC
--'<S10>:1:31'
PC_value_next <= PC_value + 1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS Program_Counter_1_output;
addr_out <= std_logic_vector(addr_out_tmp);
END rtl;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/rgb_shreg_v1_00_a/hdl/vhdl/rgb_shreg.vhd | 1 | 2940 | -- rgb_shreg.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---
-- Introduces delay of DEPTH clk to the RGB line.
-- Can be used to delay some signals to stay in sync.
-- It is an example unit and starting point for
-- more advanced ones.
---
entity rgb_shreg is
generic (
DEPTH : integer := 1
);
port (
CLK : in std_logic;
CE : in std_logic;
IN_R : in std_logic_vector(7 downto 0);
IN_B : in std_logic_vector(7 downto 0);
IN_G : in std_logic_vector(7 downto 0);
IN_DE : in std_logic;
IN_HS : in std_logic;
IN_VS : in std_logic;
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
architecture custom of rgb_shreg is
begin
gen_use_core797: if DEPTH = 797 generate
gen_block: block
component shift_ram
port (
d: in std_logic_vector(26 downto 0);
clk: in std_logic;
ce: in std_logic;
q: out std_logic_vector(26 downto 0));
end component;
begin
impl_i : shift_ram
port map (
clk => CLK,
ce => CE,
d( 7 downto 0) => IN_R,
d(15 downto 8) => IN_G,
d(23 downto 16) => IN_B,
d(24) => IN_DE,
d(25) => IN_HS,
d(26) => IN_VS,
q( 7 downto 0) => OUT_R,
q(15 downto 8) => OUT_G,
q(23 downto 16) => OUT_B,
q(24) => OUT_DE,
q(25) => OUT_HS,
q(26) => OUT_VS
);
end block;
end generate;
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
gen_custom_vhdl: if DEPTH /= 797 generate
gen_block: block
type color_t is array(0 to DEPTH - 1) of std_logic_vector(7 downto 0);
signal reg_r : color_t;
signal reg_g : color_t;
signal reg_b : color_t;
signal reg_de : std_logic_vector(DEPTH - 1 downto 0) := (others => '0');
signal reg_hs : std_logic_vector(DEPTH - 1 downto 0) := (others => '0');
signal reg_vs : std_logic_vector(DEPTH - 1 downto 0) := (others => '0');
begin
rgb_shregp : process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
reg_r(0) <= IN_R;
reg_g(0) <= IN_G;
reg_b(0) <= IN_B;
reg_de(0) <= IN_DE;
reg_hs(0) <= IN_HS;
reg_vs(0) <= IN_VS;
for i in 1 to DEPTH - 1 loop
reg_r(i) <= reg_r(i - 1);
reg_g(i) <= reg_g(i - 1);
reg_b(i) <= reg_b(i - 1);
reg_de(i) <= reg_de(i - 1);
reg_hs(i) <= reg_hs(i - 1);
reg_vs(i) <= reg_vs(i - 1);
end loop;
end if;
end if;
end process;
------------------
OUT_R <= reg_r(DEPTH - 1);
OUT_G <= reg_g(DEPTH - 1);
OUT_B <= reg_b(DEPTH - 1);
OUT_DE <= reg_de(DEPTH - 1);
OUT_HS <= reg_hs(DEPTH - 1);
OUT_VS <= reg_vs(DEPTH - 1);
end block;
end generate;
end architecture;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/median_filter_v1_00_a/hdl/vhdl/median9.vhd | 1 | 841 | -- median9.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity median9 is
port (
CLK : in std_logic;
CE : in std_logic;
DI : in std_logic_vector(9 * 8 - 1 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end entity;
architecture sort9 of median9 is
component sort9 is
port (
CLK : in std_logic;
CE : in std_logic;
DI : in std_logic_vector(9 * 8 - 1 downto 0);
DO : out std_logic_vector(9 * 8 - 1 downto 0)
);
end component;
signal sorted_data : std_logic_vector(9 * 8 - 1 downto 0);
begin
sorter_i : sort9
port map (
CLK => CLK,
CE => CE,
DI => DI,
DO => sorted_data
);
DO <= sorted_data(39 downto 32); -- median
end architecture;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/highpass_filter_v1_00_a/hdl/vhdl/highpass_filter.vhd | 1 | 3919 | -- highpass_filter.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
library utils_v1_00_a;
use utils_v1_00_a.ctl_bypass;
use utils_v1_00_a.adder_tree;
entity highpass_filter is
port (
CLK : in std_logic;
CE : in std_logic;
WIN_R : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_G : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_B : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_DE : in std_logic_vector(8 downto 0);
WIN_HS : in std_logic_vector(8 downto 0);
WIN_VS : in std_logic_vector(8 downto 0);
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
architecture impl_n1_2_n1 of highpass_filter is
constant VECTOR_LENGTH : integer := 3;
constant ADDER_LEVELS_COUNT : integer := log2(VECTOR_LENGTH);
---------------------------------
subtype mapped_t is std_logic_vector(7 downto 0);
---
-- Maps the input 10 bit signed number to output 8 bit unsigned number.
-- Mapping of x:
-- x > 0: y := x / 4
-- x < 0: y := abs(x) / 4
-- x = 0: y := 127
--
-- The value x = 0 should be mapped to 127.5. It is floored down to 127.
---
function map_to_range8(a : in std_logic_vector(9 downto 0)) return mapped_t is
variable val : integer;
variable res : std_logic_vector(9 downto 0);
variable y : std_logic_vector(7 downto 0);
begin
val := conv_integer(signed(a));
res := conv_std_logic_vector(val - (-510), 10);
y := res(9 downto 2);
return y;
end function;
---------------------------------
signal mul_r : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal mul_g : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal mul_b : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal sum_r : std_logic_vector(9 downto 0);
signal sum_g : std_logic_vector(9 downto 0);
signal sum_b : std_logic_vector(9 downto 0);
signal sum_ce : std_logic;
begin
mul_r( 9 downto 0) <= not("00" & WIN_R(15 downto 8)) + 1;
mul_g( 9 downto 0) <= not("00" & WIN_G(15 downto 8)) + 1;
mul_b( 9 downto 0) <= not("00" & WIN_B(15 downto 8)) + 1;
mul_r(19 downto 10) <= "0" & WIN_R(39 downto 32) & "0";
mul_g(19 downto 10) <= "0" & WIN_G(39 downto 32) & "0";
mul_b(19 downto 10) <= "0" & WIN_B(39 downto 32) & "0";
mul_r(29 downto 20) <= not("00" & WIN_R(63 downto 56)) + 1;
mul_g(29 downto 20) <= not("00" & WIN_G(63 downto 56)) + 1;
mul_b(29 downto 20) <= not("00" & WIN_B(63 downto 56)) + 1;
---------------------------------
---
-- Sum of the results
---
adder_tree_r_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_r,
DOUT => sum_r
);
adder_tree_g_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_g,
DOUT => sum_g
);
adder_tree_b_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_b,
DOUT => sum_b
);
---------------------------------
OUT_R <= map_to_range8(sum_r);
OUT_G <= map_to_range8(sum_g);
OUT_B <= map_to_range8(sum_b);
---------------------------------
ctl_bypass_i : entity utils_v1_00_a.ctl_bypass
generic map (
DWIDTH => 3,
DEPTH => ADDER_LEVELS_COUNT
)
port map (
CLK => CLK,
CE => CE,
DI(0) => WIN_DE(4),
DI(1) => WIN_HS(4),
DI(2) => WIN_VS(4),
DO(0) => OUT_DE,
DO(1) => OUT_HS,
DO(2) => OUT_VS
);
end architecture;
| gpl-2.0 |
zzhou007/161lab | lab04/cpu_constant_library.vhd | 1 | 894 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_constant_library is
-- opcodes
constant OPCODE_R_TYPE : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_LOAD_WORD : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_STORE_WORD : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_BRANCH_EQ : std_logic_vector(5 downto 0) := (others => '0');
-- funct
constant FUNCT_AND : std_logic_vector(5 downto 0) := (others => '0');
constant FUNCT_OR : std_logic_vector(5 downto 0) := (others => '0');
-- ALU signals
constant ALU_AND : std_logic_vector(3 downto 0) := (others => '0');
constant ALU_OR : std_logic_vector(3 downto 0) := (others => '0');
end cpu_constant_library;
package body cpu_constant_library is
end cpu_constant_library;
| gpl-2.0 |
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