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diogodanielsoaresferreira/VHDLExercises | Exercícios/BasicWatchWithBugs/Resolução/BasicWatch.vhd | 1 | 999 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatch is
port(SW : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(2 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDG : out std_logic_vector(8 downto 7));
end BasicWatch;
architecture Shell of BasicWatch is
begin
system_core : entity work.BasicWatchCore(RTL)
port map(reset => SW(0),
clk => CLOCK_50,
mode => not KEY(1),
hSet => not KEY(2),
mSet => not KEY(0),
hTens => HEX7,
hUnits => HEX6,
mTens => HEX5,
mUnits => HEX4,
sTens => HEX3,
sUnits => HEX2,
sTick => LEDG(8),
ledOut => LEDG(7));
end Shell;
| gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/common/lib/src/sync.vhd | 3 | 2543 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Projeto/Projeto-MasterMind-final/RandomNumberTb.vhd | 1 | 922 | -- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumberTb is
end RandomNumberTb;
-- Testes funcionais à entidade RandomNumber
architecture Stimulus of RandomNumberTb is
signal s_clock, s_stop, s_reseti, s_resetO, s_counter : std_logic;
begin
uut: entity work.RandomNumber(Behavioral)
port map(clock => s_clock,
stop_signal => s_stop,
reset => s_reseti,
resetOut => s_resetO,
count => s_counter);
clk_process:process
begin
s_clock <= '1';
wait for 20 ns;
s_clock <= '0';
wait for 20 ns;
end process;
comb_process:process
begin
s_stop <= '0';
s_reseti <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 50 ns;
s_stop <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 50 ns;
s_reseti <= '1';
wait for 50 ns;
end process;
end Stimulus; | gpl-2.0 |
tutugordillo/Computer-Technology | TOC/mips as state machine/with screen/MIPSconPantallaME/bitx.vhd | 1 | 1859 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:35 12/21/2012
-- Design Name:
-- Module Name: bitx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bitx is
port ( hcnt: in std_logic_vector(8 downto 0); -- horizontal pixel counter
vcnt: in std_logic_vector(9 downto 0);
encendido: in std_logic;
pintar: out std_logic;
pos_x:in std_logic_vector (8 downto 0);
pos_y: in std_logic_vector(9 downto 0)
);
end bitx;
architecture Behavioral of bitx is
signal Px: std_logic_vector(2 downto 0);
signal Py: std_logic_vector(3 downto 0);
begin
Px<=hcnt(2 downto 0);
Py<=vcnt(3 downto 0);
process(hcnt, vcnt)
begin
pintar<='0';
if hcnt >= pos_x and hcnt < pos_x + 8 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if encendido='1' then
if(UNO(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
else
if(CERO(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/xilinx/openmac/src/n_synchronizer.vhd | 3 | 3037 | -------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; | gpl-2.0 |
spoorcc/realtimestagram | src/gamma_tb.vhd | 2 | 4094 | -- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity gamma_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/gamma_output.pgm"; --! Output file of test
gamma: real := 0.5; --! Amount of contrast adjustment
c_factor: real := 1.0 --! Amount of contrast adjustment
);
end entity;
--======================================================================================--
architecture structural of gamma_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 3
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
pixel_from_file: out std_logic_vector((wordsize-1) downto 0);
pixel_to_file: in std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
component lookup_table is
generic (
wordsize: integer := const_wordsize;
lut: array_pixel := create_gamma_lut(2**const_wordsize, gamma, c_factor)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
pixel_i: in std_logic_vector((wordsize-1) downto 0);
pixel_o: out std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: lookup_table
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 9/Parte V/Ram2_N_Demo.vhd | 1 | 605 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram2_N_Demo is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(3 downto 0));
end Ram2_N_demo;
architecture Structural of Ram2_N_Demo is
begin
ram: entity work.Ram2_n(Behavioral)
generic map(data => 4,
addr => 2)
port map(clk => KEY(0),
writeEnable => SW(0),
writeData => SW(17 downto 14),
writeAddress => SW(2 downto 1),
readAddress => SW(4 downto 3),
dataOut => LEDG(3 downto 0));
end Structural; | gpl-2.0 |
ncareol/nidas | src/firmware/usb2d/Fast2D/new2d.vhd | 1 | 11522 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity new2d is
port(
in1_bus:in std_logic_vector(15 downto 0);
in2_bus:in std_logic_vector(15 downto 0);
in3_bus:in std_logic_vector(15 downto 0);
in4_bus:in std_logic_vector(15 downto 0);
fullflag:in std_logic;
emptyflag: in std_logic;
add_bus_hi:in std_logic;
add_bus_lo:in std_logic_vector(3 downto 0);
data_bus:inout std_logic_vector(7 downto 0);
fd_bus:inout std_logic_vector(15 downto 0);
clkin:in std_logic; -- 48 MHz
psen:in std_logic;
rd:in std_logic;
wr:in std_logic;
reset:in std_logic;
particle: in std_logic;
dof:in std_logic;
ram_ce:out std_logic;
ram_rd:out std_logic;
ram_wr:out std_logic;
tasbase:in std_logic;
tas:out std_logic;
slwr: out std_logic;
fifoadr0: out std_logic;
fifoadr1: out std_logic;
pktend: out std_logic;
oscdiv: out std_logic;
debug:out std_logic);
end new2d;
Architecture behavior of new2d is
--Below here is 2dmuxusb1
signal sync_pattern: std_logic_vector(15 downto 0);
signal time_count: std_logic_vector(39 downto 0);
signal in1_latch: std_logic_vector(15 downto 0);
signal in2_latch: std_logic_vector(15 downto 0);
signal in3_latch: std_logic_vector(15 downto 0);
signal in4_latch: std_logic_vector(15 downto 0);
signal particle_flag: std_logic;
signal tas_old2: std_logic;
signal tas_old1: std_logic;
signal sreset: std_logic:='0';
signal progtas: std_logic;
signal tdiv: std_logic_vector(1 downto 0);
signal tcnt: std_logic_vector(1 downto 0);
signal shdwor: std_logic_vector(15 downto 0):=X"0000";
signal particle_old2: std_logic:='0';
signal particle_old1: std_logic:='0';
signal tasbase_old2: std_logic:='0';
signal tasbase_old1: std_logic:='0';
signal sread0: std_logic;
signal sread1: std_logic;
signal pkend: std_logic;
signal div2clk: std_logic;
signal div4clk: std_logic;
signal div8clk: std_logic;
signal clkcount: std_logic_vector(2 downto 0):="000";
signal start_flag: std_logic:='0';
signal stateflag: std_logic;
signal shadflag: std_logic;
signal shadflag_old2: std_logic;
signal shadflag_old1: std_logic;
signal sync: std_logic:='1';
signal ifclk: std_logic;
type state_value is (s0,s1,s2,s3,s4,s5,s6,s7);
signal state: state_value;
signal next_state: state_value;
begin
sync_pattern <= "1010101010101010";
fifoadr0 <= '0';
fifoadr1 <= '0';
pktend <= pkend;
ifclk <= not clkin;
--0x000
progtas <= psen and add_bus_hi
and not add_bus_lo(3)
and not add_bus_lo(2)
and not add_bus_lo(1)
and not add_bus_lo(0)
and not wr;
--0x011
-- debug <= psen and add_bus_hi
-- and not add_bus_lo(3)
-- and not add_bus_lo(2)
-- and add_bus_lo(1)
-- and add_bus_lo(0)
-- and not wr;
--0x100
sreset <= psen and add_bus_hi
and not add_bus_lo(3)
and add_bus_lo(2)
and not add_bus_lo(1)
and not add_bus_lo(0)
and not wr;
--0x1001
sread0 <= psen and add_bus_hi
and add_bus_lo(3)
and not add_bus_lo(2)
and not add_bus_lo(1)
and add_bus_lo(0)
and not rd;
--0x1010
sread1 <= psen and add_bus_hi
and add_bus_lo(3)
and not add_bus_lo(2)
and add_bus_lo(1)
and not add_bus_lo(0)
and not rd;
clock2: process(ifclk,reset,sreset) --Divide 48 MHz by 2 = 24 MHz
begin
if reset = '1' or sreset = '1' then
div2clk <= '0';
div4clk <= '0';
div8clk <= '0';
clkcount <= "000";
else
if rising_edge(ifclk) then
clkcount <= clkcount + 1;
if clkcount(0) = '0' then
div2clk <= '0';
else
div2clk <= '1';
end if;
if clkcount(0) = '0' and clkcount(1) = '0' then
div4clk <= '1';
else
if clkcount(0) = '0' and clkcount(1) = '1' then
div4clk <= '0';
end if;
end if;
if clkcount = "000" then
div8clk <= '1';
else
if clkcount = "100" then
div8clk <= '0';
end if;
end if;
end if;
end if;
end process clock2;
ram: process(ifclk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
ram_ce <= '1';
ram_rd <= '1';
ram_wr <= '1';
else
ram_ce <= not add_bus_hi;
ram_rd <= rd or psen;
ram_wr <= wr;
end if;
end process ram;
nextstate: process(ifclk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
state <= s0;
if emptyflag = '1' then
pkend <= '0';
end if;
else
pkend <= '1';
if falling_edge(ifclk) then
state <= next_state;
end if;
end if;
end process nextstate;
machine: process(ifclk,reset,sreset)
begin
slwr <= '1';
if reset = '1' or sreset = '1' then
next_state <= s0;
elsif rising_edge(ifclk) then
tasbase_old2 <= tasbase_old1;
tasbase_old1 <= tasbase;
if tasbase_old2 = '0' and tasbase_old1 = '1' then
in1_latch <= in1_bus;
in2_latch <= in2_bus;
in3_latch <= in3_bus;
in4_latch <= in4_bus;
end if;
case state is
when s0=> -- wait for particle strobe
if tasbase_old2 = '0' and tasbase_old1 = '1' and
particle_flag = '1' then
if fullflag = '1' then
fd_bus(15 downto 8) <= in4_latch(7 downto 0);
fd_bus(7 downto 0) <= in4_latch(15 downto 8);
slwr <= '0';
start_flag <= '1';
next_state <= s1;
else
sync <= '0';
next_state <= s0;
end if;
else
if particle_flag = '0' and start_flag = '1' then
next_state <= s4;
else
next_state <= s0;
end if;
end if;
when s1=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in3_latch(7 downto 0);
fd_bus(7 downto 0) <= in3_latch(15 downto 8);
slwr <= '0';
next_state <= s2;
else
sync <= '0';
next_state <= s1;
end if;
when s2=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in2_latch(7 downto 0);
fd_bus(7 downto 0) <= in2_latch(15 downto 8);
slwr <= '0';
next_state <= s3;
else
sync <= '0';
next_state <= s2;
end if;
when s3=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in1_latch(7 downto 0);
fd_bus(7 downto 0) <= in1_latch(15 downto 8);
slwr <= '0';
if particle_flag = '0' then
next_state <= s4;
else
next_state <= s0;
end if;
else
sync <= '0';
next_state <= s3;
end if;
when s4=> -- write sync and time stamp
if fullflag = '1' then
start_flag <= '0';
if sync = '1' then
fd_bus(15 downto 0) <= sync_pattern(15 downto 0);
else
fd_bus(15 downto 0) <= not sync_pattern(15 downto 0);
end if;
slwr <= '0';
next_state <= s5;
else
next_state <= s4;
end if;
when s5=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(39 downto 32);
fd_bus(7 downto 0) <= sync_pattern(7 downto 0);
slwr <= '0';
next_state <= s6;
else
next_state <= s5;
end if;
when s6=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(23 downto 16);
fd_bus(7 downto 0) <= time_count(31 downto 24);
slwr <= '0';
next_state <= s7;
else
next_state <= s6;
end if;
when s7=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(7 downto 0);
fd_bus(7 downto 0) <= time_count(15 downto 8);
slwr <= '0';
sync <= '1';
next_state <= s0;
else
next_state <= s7;
end if;
end case;
else
next_state <= next_state;
end if;
end process machine;
tascnt: process(tasbase, reset, sreset)
begin
if reset = '1' or sreset = '1' then
tcnt <= "00";
else
if rising_edge(tasbase) then
tcnt <= tcnt + 1;
end if;
end if;
end process tascnt;
databus: process(reset,progtas,sreset,sread0,sread1)
begin
if reset = '1' or sreset = '1' then
tdiv(1 downto 0) <= "00";
end if;
if progtas = '1' then
tdiv(1 downto 0) <= data_bus(1 downto 0);
else
tdiv(1 downto 0) <= tdiv(1 downto 0);
end if;
if sread0 = '1' then
data_bus(7 downto 0) <= shdwor(7 downto 0);
shadflag <= '0';
elsif sread1 = '1' then
data_bus(7 downto 0) <= shdwor(15 downto 8);
shadflag <= '1';
else
data_bus(7 downto 0) <= "ZZZZZZZZ";
end if;
end process databus;
airspeed: process(reset,tdiv,sreset)
begin
if reset = '1' or sreset = '1' then
tas <= '0';
oscdiv <= '0';
else
case tdiv(1 downto 0) is
when "00" =>
tas <= tcnt(1);
oscdiv <= '0';
when "01" =>
tas <= tcnt(1);
oscdiv <= 'Z';
when others =>
tas <= '0';
end case;
end if;
end process airspeed;
ParticleCounter: process (ifclk)
begin
if falling_edge(ifclk) then
particle_old2 <= particle_old1;
particle_old1 <= particle;
shadflag_old2 <= shadflag_old1;
shadflag_old1 <= shadflag;
if particle_old2 = '1' and particle_old1 = '0' then
shdwor <= shdwor + 1;
if dof = '1' then
debug <= '1';
particle_flag <= '1';
end if;
end if;
if particle_old2 = '0' and particle_old1 = '1' then
particle_flag <= '0';
debug <= '0';
end if;
if shadflag_old2 = '0' and shadflag_old1 = '1' then
shdwor(15 downto 0) <= X"0000";
end if;
end if;
end process ParticleCounter;
-- count_time: process(tasbase,reset,sreset)
count_time: process(div4clk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
-- time_count (37 downto 36) <= "00";
time_count(39 downto 0) <= X"0000000000";
else
if time_count(39 downto 0) = X"FFFFFFFFFF" then
-- time_count (37 downto 36) <= "00";
time_count(39 downto 0) <= X"0000000000";
-- elsif rising_edge(tasbase) then
elsif rising_edge(div4clk) then
time_count <= time_count + 1;
else
time_count(39 downto 0) <= time_count(39 downto 0);
end if;
end if;
end process count_time;
end behavior;
| gpl-2.0 |
tutugordillo/Computer-Technology | TOC/mips as state machine/without screen/MIPScomoME/simu_controlSaltos.vhd | 2 | 2740 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:35:42 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/simu_controlSaltos.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ControlBranch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY simu_controlSaltos IS
END simu_controlSaltos;
ARCHITECTURE behavior OF simu_controlSaltos IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ControlBranch
PORT(
cero : IN std_logic;
mayorque : IN std_logic;
saltar : IN std_logic;
EscrPC : IN std_logic;
EscrPC_Cond1 : IN std_logic;
EscrPC_Cond2 : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal cero : std_logic := '0';
signal mayorque : std_logic := '0';
signal saltar : std_logic := '0';
signal EscrPC : std_logic := '0';
signal EscrPC_Cond1 : std_logic := '0';
signal EscrPC_Cond2 : std_logic := '0';
--Outputs
signal salida : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ControlBranch PORT MAP (
cero => cero,
mayorque => mayorque,
saltar => saltar,
EscrPC => EscrPC,
EscrPC_Cond1 => EscrPC_Cond1,
EscrPC_Cond2 => EscrPC_Cond2,
salida => salida
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
EscrPc<='1';
wait for 100 ns;
EscrPc<='0';
cero<='1';
mayorque<='0';
saltar<='1';
EscrPC_Cond2 <= '0';
EscrPC_Cond1 <= '1';
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
tutugordillo/Computer-Technology | TOC/mips as state machine/with screen/MIPSconPantallaME/ALU.vhd | 2 | 1358 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:03 11/21/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit IS
port(a, b : in std_logic_vector(31 downto 0);
op : in std_logic_vector(1 downto 0);
zero, bigthan : out std_logic;
result : out std_logic_vector(31 downto 0));
END alu8bit;
architecture behavioral of alu8bit is
signal temp : std_logic_vector(31 downto 0);
begin
temp <= a and b when op = "00" else
a or b when op ="01" else
a + b when op = "10" else
a - b when op = "11" else
(others => ('0'));
result <= temp;
process(op, temp)
begin
if(op = "11" and temp = 0) then
zero <= '1';
bigthan <= '0';
elsif(op = "11" and temp > 0) then
zero <= '0';
bigthan <= '1';
else
zero <= '0';
bigthan <= '0';
end if;
end process;
end behavioral;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 2/Bin7SegDecoder.vhd | 2 | 1114 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0);
ledOut : out std_logic_vector(3 downto 0);
enable : in std_logic);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when enable='0' else
"1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"0001110" when binInput="1111" else --F
"1000000"; --0
ledOut <= binInput;
end Behavioral; | gpl-2.0 |
ncareol/nidas | src/firmware/analog/d2aio.vhd | 1 | 7464 | --------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity d2aio is
port ( AEN : in std_logic;
D2A0 : in std_logic;
D2A1 : in std_logic;
D2A2 : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
BRDSEL : in std_logic;
SIOW : in std_logic;
clk : in std_logic; -- 50 MHz
BSD : in std_logic_vector (15 downto 0);
D2ACAL : out std_logic_vector (4 downto 0);
SDIN : out std_logic;
CLKIN : out std_logic;
FSIN : out std_logic;
LDAC : out std_logic;
BRDSELO : out std_logic
);
end d2aio;
architecture BEHAVIORAL of d2aio is
signal d2a0_old2 : std_logic:='0';
signal d2a0_old1 : std_logic:='0';
signal d2a1_old2 : std_logic:='0';
signal d2a1_old1 : std_logic:='0';
-- signal d2a2_old2 : std_logic:='0';
-- signal d2a2_old1 : std_logic:='0';
signal data_old2 : std_logic:='0';
signal data_old1 : std_logic:='0';
signal flag: std_logic:='0';
signal fsin1: std_logic:='1';
signal fsin2: std_logic:='1';
signal shift_data : std_logic_vector(15 downto 0):=X"0000";
signal shift_count : std_logic_vector(4 downto 0):="00000";
signal clk_count : std_logic_vector(1 downto 0):="00";
-- signal cal: std_logic_vector(4 downto 0):="00000";
-- signal cal_snatch: std_logic_vector(4 downto 0):="00000";
-- signal cal_flag: std_logic:='0';
-- signal cal1: std_logic:='0';
-- signal cal2: std_logic:='0';
-- signal cal3: std_logic:='0';
-- signal cal4: std_logic:='0';
-- signal cal5: std_logic:='0';
signal snatch: std_logic_vector(4 downto 0):="00001";
signal state1: std_logic:='0';
signal state2: std_logic:='0';
signal state3: std_logic:='0';
signal sig_CLKIN: std_logic:='0';
signal data_index: integer:=0;
type state_value is (s1,s2);
signal state: state_value:=s1;
signal next_state: state_value;
attribute keep: string;
attribute keep of AEN: signal is "true";
begin
-- D2ACAL(4 downto 0) <= cal(4 downto 0);
D2ACAL(4 downto 0) <= snatch(4 downto 0);
-- D2ACAL(4 downto 0) <= "00001";
FSIN <= fsin1 and fsin2;
CLKIN <= sig_CLKIN;
select_card: process(BRDSEL,AEN)
begin
if BRDSEL = '0' and AEN = '0' then
BRDSELO <= '0';
else
BRDSELO <= '1';
end if;
end process select_card;
-- calproc: process(clk)
-- begin
-- if rising_edge(clk) then
-- if cal_flag = '1' then
-- cal <= cal_snatch;
-- cal_flag <= '0';
-- elsif snatch = "00001" and cal1 = '0' then
-- cal_snatch <= "00000";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal1 <= '1';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00010" and cal2 = '0' then
-- cal_snatch <= "00011";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal2 <= '1';
-- cal1 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00100" and cal3 = '0' then
-- cal_snatch <= "00101";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal3 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "01000" and cal4 = '0' then
-- cal_snatch <= "01001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal4 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal5 <= '0';
-- elsif snatch = "10000" and cal5 = '0' then
-- cal_snatch <= "10001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal5 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- else
-- cal_snatch <= "00001";
-- cal <= "00001";
-- cal_flag <= '1';
---- cal1 <= '0';
---- cal2 <= '0';
---- cal3 <= '0';
---- cal4 <= '0';
---- cal5 <= '0';
-- end if;
-- end if;
-- end process calproc;
dacproc: process(clk)
begin
if rising_edge(clk) then
d2a0_old2 <= d2a0_old1;
d2a0_old1 <= D2A0;
d2a1_old2 <= d2a1_old1;
d2a1_old1 <= D2A1;
-- d2a2_old2 <= d2a2_old1;
-- d2a2_old1 <= D2A2;
data_old2 <= data_old1;
data_old1 <= SIOW;
if d2a0_old2 = '0' and d2a0_old1 ='1' then
state1 <= '1';
elsif BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0' then
if data_old2 = '0' and data_old1 = '1' then
shift_data <= BSD;
state2 <= state1;
end if;
else
if state3 = '1' then
state1 <= '0';
state2 <= '0';
end if;
end if;
if d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '0' then
fsin1 <= '0';
LDAC <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '0' then
flag <= '1';
fsin1 <= '1';
LDAC <= '1';
elsif d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '1' then
LDAC <= '0';
fsin1 <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '1' then
flag <= '0';
LDAC <= '1';
fsin1 <= '1';
else
fsin1 <= '1';
LDAC <= '1';
end if;
end if;
end process dacproc;
busproc: process(clk)
begin
if rising_edge(clk) then
if D2A2 = '1' and (BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0') then
if data_old2 = '0' and data_old1 = '1' then
snatch (4 downto 0) <= BSD(4 downto 0);
-- snatch (4 downto 0) <= BSD(15 downto 11);
end if;
else
snatch(4 downto 0) <= snatch(4 downto 0);
end if;
end if;
end process busproc;
states: process(clk)
begin
if falling_edge(clk) then
state <= next_state;
end if;
end process states;
machine: process(sig_CLKIN)
begin
if rising_edge(sig_CLKIN) then
case state is
when s1 => -- latch data
shift_count <= "00000";
data_index <= 0;
state3 <= '0';
fsin2 <= '1';
SDIN <= '0';
if state1 = '1' and state2 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
if shift_count = "10000" then
state3 <= '1';
fsin2 <= '1';
SDIN <= '0';
shift_count <= "00000";
data_index <= 0;
next_state <= s1;
else
state3 <= '0';
fsin2 <= '0';
data_index <= data_index + 1;
SDIN <= shift_data(15 - data_index);
shift_count <= shift_count + 1;
next_state <= s2;
end if;
end case;
end if;
end process machine;
DAC_CLK: process(clk)
begin
if rising_edge (clk) then
if clk_count = "00" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "01" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "10" then
sig_CLKIN <= '0';
clk_count <= clk_count + 1;
elsif clk_count = "11" then
sig_CLKIN <= '0';
clk_count <= "00";
else
sig_CLKIN <= '0';
clk_count <= "00";
end if;
end if;
end process DAC_CLK;
end BEHAVIORAL;
| gpl-2.0 |
tutugordillo/Computer-Technology | TOC/mips as state machine/without screen/MIPScomoME/ExtensorSigno.vhd | 2 | 1125 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:08 11/21/2012
-- Design Name:
-- Module Name: ExtensorSigno - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ExtensorSigno is port (A: in std_logic_vector (15 downto 0);
S: out std_logic_vector (31 downto 0));
end ExtensorSigno;
architecture Behavioral of ExtensorSigno is
begin
S(15 downto 0)<=A;
S(31 downto 16)<= (others => A(15));
end Behavioral;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Exercícios/BasicWatchWithBugs/Problema Inicial/BasicWatch.vhd | 1 | 968 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatch is
port(SW : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(2 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDG : out std_logic_vector(8 downto 8));
end BasicWatch;
architecture Shell of BasicWatch is
begin
system_core : entity work.BasicWatchCore(RTL)
port map(reset => SW(0),
clk => CLOCK_50,
mode => not KEY(1),
hSet => not KEY(2),
mSet => not KEY(0),
hTens => HEX7,
hUnits => HEX6,
mTens => HEX5,
mUnits => HEX4,
sTens => HEX3,
sUnits => HEX2,
sTick => LEDG(8));
end Shell;
| gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/common/pdi/src/pdi_par.vhd | 3 | 14711 | -------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
| gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/common/openmac/src/openMAC_16to32conv.vhd | 3 | 6703 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Projeto/Projeto-MasterMind-final/RandomNumberw_counter_Tb.vhd | 1 | 1319 | -- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumberw_counter_Tb is
end RandomNumberw_counter_Tb;
-- Testes unitários para a sincronização das entidade RandomNumber e counter9999
architecture Stimulus of RandomNumberw_counter_Tb is
signal s_reset, s_stop, s_clock, s_count, s_resetOut : std_logic;
signal s_random0, s_random3,s_random2,s_random1 : std_logic_vector(3 downto 0);
begin
uutrandom: entity work.RandomNumber(Behavioral)
port map(clock => s_clock,
stop_signal => s_stop,
reset => s_reset,
count => s_count,
resetOut => s_resetOut);
uutcounter: entity work.Counter9999(Behavioral)
port map(clk => s_clock,
reset => s_resetOut,
enable => s_count,
count0 => s_random0,
count1 => s_random1,
count2 => s_random2,
count3 => s_random3);
clk_proc:process
begin
s_clock <= '1';
wait for 13 ns;
s_clock <= '0';
wait for 13 ns;
end process;
comb_process:process
begin
s_stop <= '0';
s_reset <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 25 ns;
s_stop <= '0';
wait for 25 ns;
s_reset <= '1';
wait for 25 ns;
end process;
end Stimulus; | gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/common/pdi/src/pdi_simpleReg.vhd | 3 | 4047 | -------------------------------------------------------------------------------
-- Process Data Interface (PDI) simple register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdiSimpleReg is
generic (
iAddrWidth_g : integer := 10; --only use effective addr range (e.g. 2kB leads to iAddrWidth_g := 10)
iBaseMap2_g : integer := 0; --base address in dpr
iDprAddrWidth_g : integer := 12
);
port (
--memory mapped interface
sel : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector(iAddrWidth_g-1 downto 0);
be : in std_logic_vector(3 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
--dpr interface (from PCP/AP to DPR)
dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0);
dprDin : out std_logic_vector(31 downto 0);
dprDout : in std_logic_vector(31 downto 0);
dprBe : out std_logic_vector(3 downto 0);
dprWr : out std_logic
);
end entity pdiSimpleReg;
architecture rtl of pdiSimpleReg is
signal addrRes : std_logic_vector(dprAddrOff'range);
begin
--assign content to dpr
dprDin <= din;
dprBe <= be;
dprWr <= wr when sel = '1' else
'0';
dout <= dprDout when sel = '1' else
(others => '0');
dprAddrOff <= addrRes when sel = '1' else
(others => '0');
--address conversion
---map external address mapping into dpr
addrRes <= '0' & conv_std_logic_vector(iBaseMap2_g, addrRes'length - 1);
end architecture rtl; | gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 6/Parte 4/SeqShiftUnit.vhd | 2 | 1257 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SeqShiftUnit is
port( clk : in std_logic;
dataIn: in std_logic_vector(7 downto 0);
siLeft: in std_logic;
siRight: in std_logic;
loadEn: in std_logic;
rotate: in std_logic;
dirLeft: in std_logic;
shArith: in std_logic;
dataOut: out std_logic_vector(7 downto 0));
end SeqShiftUnit;
architecture RTL of SeqShiftUnit is
signal s_shiftReg : std_logic_vector(7 downto 0);
signal s_left : std_logic;
begin
process(clk)
begin
if(falling_edge(clk)) then
if(loadEn='1') then
s_shiftReg <= dataIn;
elsif(rotate='1') then
if(dirLeft='1') then
s_shiftReg <= s_shiftReg(6 downto 0) & s_shiftReg(7);
else
s_shiftReg <= s_ShiftReg(0) & s_shiftReg(7 downto 1);
end if;
elsif(shArith ='1') then
if(dirLeft='1') then
s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
else
s_left <= s_shiftReg(7);
s_shiftReg <= s_left & s_shiftReg(7 downto 1);
end if;
else
if(dirLeft='1') then
s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
else
s_shiftReg <= siRight & s_shiftReg(7 downto 1);
end if;
end if;
end if;
end process;
dataOut <= s_shiftReg;
end RTL; | gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Exercícios/BasicWatchWithBugs/Resolução/Counter4Bits.vhd | 2 | 889 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter4Bits is
generic(MAX : natural);
port(reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
valOut : out std_logic_vector(3 downto 0);
termCnt : out std_logic);
end Counter4Bits;
architecture RTL of Counter4Bits is
signal s_value : unsigned(3 downto 0);
begin
process(reset, clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_value <= (others => '0');
termCnt <= '0';
elsif (enable = '1') then
if (to_integer(s_value) = MAX) then
s_value <= (others => '0');
termCnt <= '0';
else
s_value <= s_value + 1;
if (to_integer(s_value) = MAX - 1) then
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end if;
end if;
end process;
valOut <= std_logic_vector(s_value);
end RTL;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Exercícios/Debouncer/Debouncer_Demo.vhd | 1 | 755 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Debouncer_Demo is
port (CLOCK_50 : in std_logic;
KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(3 downto 0));
end Debouncer_Demo;
architecture Shell of Debouncer_Demo is
signal s_clk : std_logic;
begin
Deb_core: entity work.Debouncer(Behavioral)
generic map(N => 20)
port map(clk => CLOCK_50,
dirty_In => KEY(0),
cleanOut => s_clk);
Count_core: entity work.CounterLoadUpDown4(Behavioral)
port map(clk => s_clk,
updown=> SW(0),
reset => SW(1),
enable=> SW(2),
load => SW(3),
dataIn=> SW(7 downto 4),
count => LEDR(3 downto 0));
end Shell; | gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 5/Parte I/ShiftRegisterN.vhd | 1 | 820 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ShiftRegisterN is
generic (N : positive := 4);
port( clk : in std_logic;
si : in std_logic;
dataOut : out std_logic_vector(N-1 downto 0);
so : out std_logic;
reset : in std_logic;
load : in std_logic;
dataIn : in std_logic_vector(N-1 downto 0));
end ShiftRegisterN;
architecture Behavioral of ShiftRegisterN is
signal s_dataOut : std_logic_vector(N-1 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
s_dataOut <= (others=>'0');
elsif(load='1') then
s_dataOut <= dataIn;
else
s_dataOut <= s_dataOut(N-2 downto 0) & si;
end if;
end if;
end process;
dataOut <= s_dataOut(N-1 downto 0);
so <= s_dataOut(N-1);
end Behavioral; | gpl-2.0 |
ncareol/nidas | src/firmware/analog/ISAintfc.vhd | 1 | 16022 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : ISAintfc.vhf
-- /___/ /\ Timestamp : 01/05/2006 10:51:23
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w ISAintfc.sch ISAintfc.vhf
--Design Name: ISAintfc
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD_MXILINX_ISAintfc is
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end FD_MXILINX_ISAintfc;
architecture BEHAVIORAL of FD_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
signal XLXN_4 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_43 : GND
port map (G=>XLXN_4);
U0 : FDCP
port map (C=>C,
CLR=>XLXN_4,
D=>D,
PRE=>XLXN_4,
Q=>Q);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity D3_8E_MXILINX_ISAintfc is
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end D3_8E_MXILINX_ISAintfc;
architecture BEHAVIORAL of D3_8E_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
begin
I_36_30 : AND4
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D7);
I_36_31 : AND4B1
port map (I0=>A0,
I1=>A2,
I2=>A1,
I3=>E,
O=>D6);
I_36_32 : AND4B1
port map (I0=>A1,
I1=>A2,
I2=>A0,
I3=>E,
O=>D5);
I_36_33 : AND4B2
port map (I0=>A1,
I1=>A0,
I2=>A2,
I3=>E,
O=>D4);
I_36_34 : AND4B1
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D3);
I_36_35 : AND4B2
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D2);
I_36_36 : AND4B2
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D1);
I_36_37 : AND4B3
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD4CE_MXILINX_ISAintfc is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end FD4CE_MXILINX_ISAintfc;
architecture BEHAVIORAL of FD4CE_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
U0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D0,
Q=>Q0);
U1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D1,
Q=>Q1);
U2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D2,
Q=>Q2);
U3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D3,
Q=>Q3);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity ISAintfc is
port ( BRDSELO : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
IORN : in std_logic;
IOWN : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
SA3 : in std_logic;
SA4 : in std_logic;
PLLOUT : in std_logic;
A2DDATA : out std_logic;
A2DSTAT : out std_logic;
D2A0 : out std_logic;
D2A1 : out std_logic;
D2A2 : out std_logic;
FIFO : out std_logic;
FIFOSTAT : out std_logic;
IOCS16N : out std_logic;
I2CSCL : out std_logic;
LBSD3 : out std_logic;
SIOR : out std_logic;
SIORN : out std_logic;
SIORW : out std_logic;
SIOW : out std_logic;
SIOWN : out std_logic;
SYSCTL : out std_logic;
BSD : inout std_logic_vector (15 downto 0);
I2CSDA : inout std_logic);
end ISAintfc;
architecture BEHAVIORAL of ISAintfc is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal BRDSELI : std_logic;
signal FSEL : std_logic;
signal XLXN_157 : std_logic;
signal XLXN_158 : std_logic;
signal XLXN_159 : std_logic;
signal XLXN_161 : std_logic;
signal XLXN_206 : std_logic;
signal XLXN_210 : std_logic;
signal XLXN_212 : std_logic;
signal XLXN_214 : std_logic;
signal XLXN_216 : std_logic;
signal XLXN_221 : std_logic;
signal XLXN_222 : std_logic;
signal XLXN_370 : std_logic;
-- signal XLXN_223a : std_logic;
-- signal XLXN_223b : std_logic;
-- signal XLXN_223c : std_logic;
-- signal XLXN_223d : std_logic;
-- signal XLXN_223e : std_logic;
-- signal XLXN_223f : std_logic;
signal XLXN_225 : std_logic;
signal XLXN_229 : std_logic;
signal XLXN_230 : std_logic;
signal XLXN_231 : std_logic;
signal XLXN_232 : std_logic;
signal A2DSTAT_DUMMY : std_logic;
signal A2DDATA_DUMMY : std_logic;
signal SIOWN_DUMMY : std_logic;
signal SIOR_DUMMY : std_logic;
signal SIORN_DUMMY : std_logic;
signal SIOW_DUMMY : std_logic;
signal SIORW_DUMMY : std_logic;
signal D2A2_DUMMY : std_logic;
-- signal MY_SIORW : std_logic;
-- signal cnt : std_logic_vector(1 downto 0):="00";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component FD4CE_MXILINX_ISAintfc
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end component;
component D3_8E_MXILINX_ISAintfc
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component NAND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
component NOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NOR2 : component is "BLACK_BOX";
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
component AND5
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component FD_MXILINX_ISAintfc
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of XLXI_60 : label is "XLXI_60_0";
attribute HU_SET of XLXI_61 : label is "XLXI_61_1";
attribute HU_SET of XLXI_102 : label is "XLXI_102_2";
attribute HU_SET of XLXI_103 : label is "XLXI_103_3";
begin
A2DSTAT <= A2DSTAT_DUMMY;
A2DDATA <= A2DDATA_DUMMY;
SIOR <= SIOR_DUMMY;
SIORN <= SIORN_DUMMY;
SIOW <= SIOW_DUMMY;
SIOWN <= SIOWN_DUMMY;
D2A2 <= D2A2_DUMMY;
XLXI_30 : INV
port map (I=>SIOW_DUMMY,
O=>SIOWN_DUMMY);
XLXI_143 : VCC
port map (P=>XLXN_370);
XLXI_60 : FD4CE_MXILINX_ISAintfc
port map (C=>SIOWN_DUMMY,
CE=>FSEL,
CLR=>XLXN_210,
D0=>BSD(0),
D1=>BSD(1),
D2=>BSD(2),
D3=>BSD(3),
Q0=>XLXN_157,
Q1=>XLXN_158,
Q2=>XLXN_159,
Q3=>LBSD3);
XLXI_61 : D3_8E_MXILINX_ISAintfc
port map (A0=>XLXN_157,
A1=>XLXN_158,
A2=>XLXN_159,
E=>XLXN_206,
D0=>FIFO,
D1=>A2DSTAT_DUMMY,
D2=>A2DDATA_DUMMY,
D3=>D2A0,
D4=>D2A1,
D5=>D2A2_DUMMY,
D6=>SYSCTL,
D7=>FIFOSTAT);
XLXI_63 : GND
port map (G=>XLXN_210);
XLXI_66 : NAND2
port map (I0=>SIORN_DUMMY,
I1=>SIOWN_DUMMY,
O=>SIORW);
XLXI_69 : INV
port map (I=>SIOR_DUMMY,
O=>SIORN_DUMMY);
XLXI_75 : NOR2
port map (I0=>IOWN,
I1=>BRDSELO,
O=>SIOW_DUMMY);
XLXI_76 : NOR2
port map (I0=>IORN,
I1=>BRDSELO,
O=>SIOR_DUMMY);
XLXI_80 : BUFE
port map (E=>BRDSELI,
I=>XLXN_161,
O=>IOCS16N);
XLXI_81 : INV
port map (I=>BRDSELO,
O=>BRDSELI);
XLXI_82 : GND
port map (G=>XLXN_161);
XLXI_89 : INV
port map (I=>XLXN_229,
O=>XLXN_232);
XLXI_90 : INV
port map (I=>FSEL,
O=>XLXN_206);
XLXI_91 : AND2
port map (I0=>XLXN_232,
I1=>XLXN_221,
O=>XLXN_231);
XLXI_92 : AND5
port map (I0=>BRDSELI,
I1=>SA3,
I2=>SA2,
I3=>SA1,
I4=>SA0, --Uncomment for Viper
-- I4=>SA4, --Uncomment for Vulcan
O=>FSEL);
XLXI_93 : AND2
-- port map (I0=>FIFOCTL(1),
-- I1=>A2DSTAT_DUMMY,
-- port map (I0=>FIFOCTL(7),
-- I1=>D2A2_DUMMY,
port map (I0=>A2DDATA_DUMMY,
I1=>A2DDATA_DUMMY,
O=>XLXN_230);
XLXI_94 : AND2
port map (I0=>SIOR_DUMMY,
I1=>XLXN_230,
O=>XLXN_229);
XLXI_95 : NAND2
port map (I0=>SIOW_DUMMY,
I1=>XLXN_230,
O=>XLXN_216);
XLXI_96 : INV
port map (I=>BSD(0),
O=>XLXN_212);
XLXI_97 : INV
port map (I=>BSD(1),
O=>XLXN_214);
XLXI_98 : INV
port map (I=>XLXN_221,
O=>XLXN_222);
XLXI_99 : INV
port map (I=>XLXN_225,
O=>I2CSCL);
XLXI_100 : BUFE
port map (E=>XLXN_229,
I=>I2CSDA,
O=>BSD(0));
XLXI_101 : BUFE
port map (E=>XLXN_231,
I=>XLXN_222,
O=>I2CSDA);
XLXI_102 : FD_MXILINX_ISAintfc
port map (C=>XLXN_216,
D=>XLXN_212,
Q=>XLXN_221);
XLXI_103 : FD_MXILINX_ISAintfc
port map (C=>XLXN_216,
D=>XLXN_214,
Q=>XLXN_225);
-- delay: process(pllout,FSEL)
-- begin
-- if FSEL = '1' then
-- cnt <= "00";
-- elsif cnt = "00" and FSEL = '0' then
-- cnt <= "01";
-- elsif cnt = "01" and FSEL = '0' then
-- cnt <= "10";
-- else
-- cnt <= cnt;
-- end if;
-- end process delay;
end BEHAVIORAL;
| gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/xilinx/openmac/src/openMAC_DPR.vhd | 3 | 12638 | -------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
constant SIZE : natural := 2**ADDRWIDTH;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
constant SIZE : natural := 2**ADDRWIDTH;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 |
samvartaka/simon_vhdl | ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/tb_ram.vhd | 5 | 2692 | ----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; | gpl-2.0 |
samvartaka/simon_vhdl | ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/tb_round.vhd | 3 | 1726 | -- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- Do round
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
| gpl-2.0 |
sksavant/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/capacitor.vhdl | 15 | 320 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
| gpl-2.0 |
twasiluk/hdmilight | fpga/ipcore_dir/configRam.vhd | 2 | 6113 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file configRam.vhd when simulating
-- the core, configRam. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY configRam IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END configRam;
ARCHITECTURE configRam_a OF configRam IS
-- synthesis translate_off
COMPONENT wrapped_configRam
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_configRam USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_configRam
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END configRam_a;
| gpl-2.0 |
sksavant/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/transitest.vhdl | 15 | 192 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY top_entity IS
END ENTITY top_entity;
| gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | utils/PatternGen/sim/work/step_curve/_primary.vhd | 1 | 698 | library verilog;
use verilog.vl_types.all;
entity step_curve is
port(
clk : in vl_logic;
CAL : out vl_logic;
SBI : out vl_logic;
SPHI1 : out vl_logic;
SPHI2 : out vl_logic;
SEB : out vl_logic;
ISSR : out vl_logic;
RESET : out vl_logic;
R12 : out vl_logic;
RBI : out vl_logic;
RPHI1 : out vl_logic;
RPHI2 : out vl_logic;
LE : out vl_logic;
reset_gen : in vl_logic
);
end step_curve;
| gpl-2.0 |
eivindkv/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/resistor.vhdl | 15 | 289 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
| gpl-2.0 |
samvartaka/simon_vhdl | INNER_ROUND_PIPELINING/K_1/simon.vhd | 2 | 4591 | -- SIMON 64/128
-- Simon core component
--
-- K=1 inner-round pipelining based of iterative cache-routing architecture
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (clk, rst, v_in_s, key_s(0), v_out_s);
RAM_0 : ram port map (key_s(0), ram_rw, clk, r_s, ram_data_out);
-- SIMON round index regulation
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = '1' then
if enc = '0' then
if (r_s = X"00") then
r_s <= X"01";
else
r_s <= (others => '0');
end if;
else
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
else
-- in preparation for subsequent decryption
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON key cache rotation
pr_ks : process(clk, rst, key_s, key, ram_data_out, subkey_out_s)
begin
if rising_edge(clk) then
if enc = '0' then
if rst = '1' then
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
else
-- final iteration is just to write final round key to ram
if (r_s /= X"2B") then
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
end if;
end if;
else
key_s(0) <= ram_data_out;
end if;
end if;
end process;
-- SIMON Core
pr_smn : process(clk, rst, enc, r_s, block_in, v_in_s, v_out_s, ram_rw)
begin
if rising_edge(clk) then
-- initalize
if rst = '1' then
if enc = '0' then
v_in_s <= block_in;
-- write every round key to RAM during encryption
-- so that encryption also functions as pre-expansion for decryption
ram_rw <= '1';
else
-- swap blocks for decryption
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
ram_rw <= '0';
end if;
-- run
else
if enc = '0' then
if (r_s /= X"2B") then
v_in_s <= v_out_s;
else
ram_rw <= '0';
end if;
else
v_in_s <= v_out_s;
end if;
end if;
end if;
end process;
-- v_in_s instead of v_out_s during decryption because of inner-round pipelining with negative-edge triggered registers
block_out <= v_out_s when (enc = '0') else v_in_s(31 downto 0) & v_in_s(63 downto 32);
end Behavioral; | gpl-2.0 |
samvartaka/simon_vhdl | INNER_ROUND_PIPELINING/K_1/round_f.vhd | 1 | 1657 |
-- SIMON 64/128
-- feistel round function
-- Inner-round pipelining using negative-edge triggered registers
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(clk : in std_logic;
rst : in std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end round_f;
architecture Behavioral of round_f is
signal op_0_s : std_logic_vector(31 downto 0);
signal stage_0_out_s : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
component phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0));
end component;
component neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
begin
PHI_0 : phi port map (v_in(63 downto 32), op_0_s);
GAMMA_0 : gamma port map (v_in(31 downto 0), v_k, op_1_s);
REG_STAGE_0 : neg_reg_32 port map (clk, rst, op_1_s, stage_0_out_s);
GAMMA_1 : gamma port map (op_0_s, stage_0_out_s, op_2_s);
v_out <= op_2_s & v_in(63 downto 32);
end Behavioral; | gpl-2.0 |
twasiluk/hdmilight | fpga/ambilight.vhd | 2 | 6909 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ambilight is
Port ( vidclk : in STD_LOGIC;
viddata_r : in STD_LOGIC_VECTOR (7 downto 0);
viddata_g : in STD_LOGIC_VECTOR (7 downto 0);
viddata_b : in STD_LOGIC_VECTOR (7 downto 0);
hblank : in STD_LOGIC;
vblank : in STD_LOGIC;
cfgclk : in STD_LOGIC;
cfgwe : in STD_LOGIC;
cfglight : in STD_LOGIC_VECTOR (7 downto 0);
cfgcomponent : in STD_LOGIC_VECTOR (3 downto 0);
cfgdatain : in STD_LOGIC_VECTOR (7 downto 0);
cfgdataout : out STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0));
end ambilight;
architecture Behavioral of ambilight is
COMPONENT configRam
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal ce2 : std_logic;
signal ce4 : std_logic;
signal hblank_delayed : std_logic;
signal vblank_delayed : std_logic;
signal ravg : std_logic_vector(7 downto 0);
signal gavg : std_logic_vector(7 downto 0);
signal bavg : std_logic_vector(7 downto 0);
signal lineBufferAddr : std_logic_vector(6 downto 0);
signal lineBufferData : std_logic_vector(23 downto 0);
signal yPos : std_logic_vector(5 downto 0);
signal lineReady : std_logic;
signal configAddrA : std_logic_vector(8 downto 0);
signal configDataA : std_logic_vector(31 downto 0);
signal configWeB : std_logic_vector(0 downto 0);
signal configAddrB : std_logic_vector(8 downto 0);
signal configDataOutB : std_logic_vector(31 downto 0);
signal configDataInB : std_logic_vector(31 downto 0);
signal configDataLatched : std_logic_vector(31 downto 0);
signal resultAddr : std_logic_vector(8 downto 0);
signal resultData : std_logic_vector(31 downto 0);
signal resultLatched : std_logic_vector(31 downto 0);
signal statusLatched : std_logic_vector(7 downto 0);
signal outputStart : std_logic;
signal outputBusy : std_logic;
signal outputAddr : std_logic_vector( 7 downto 0);
signal outputData : std_logic_vector(23 downto 0);
signal driverOutput : std_logic;
begin
conf : configRam
PORT MAP (
clka => vidclk,
wea => "0",
addra => configAddrA,
dina => (others => '0'),
douta => configDataA,
clkb => cfgclk,
web => configWeB,
addrb => configAddrB,
dinb => configDataInB,
doutb => configDataOutB
);
hscale4 : entity work.hscale4 port map(vidclk, hblank, vblank, viddata_r, viddata_g, viddata_b,
hblank_delayed, vblank_delayed, ce2, ce4, ravg, gavg, bavg);
scaler : entity work.scaler port map(vidclk, ce2, hblank_delayed, vblank_delayed, ravg, gavg, bavg,
vidclk, lineBufferAddr, lineBufferData, lineReady, yPos);
lightAverager : entity work.lightAverager port map(vidclk, ce2, lineReady, yPos,
lineBufferAddr, lineBufferData,
configAddrA, configDataA,
cfgclk, resultAddr, resultData);
resultDistributor : entity work.resultDistributor port map(cfgclk, vblank,
resultAddr, resultData,
outputBusy, outputStart,
outputAddr, outputData);
ws2811Driver : entity work.ws2811Driver port map(cfgclk, outputStart, outputData, outputBusy, driverOutput);
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
configDataLatched <= configDataOutB;
statusLatched <= "000000" & hblank & vblank;
if(resultAddr(7 downto 0) = cfglight) then
resultLatched <= resultData;
end if;
end if;
end process;
configWeB(0) <= cfgwe;
configAddrB <= "0" & cfglight;
--resultAddr <= "0" & cfglight;
with cfgcomponent select configDataInB <=
configDataLatched(31 downto 6) & cfgdatain(5 downto 0) when "0000",
configDataLatched(31 downto 12) & cfgdatain(5 downto 0) & configDataLatched(5 downto 0) when "0001",
configDataLatched(31 downto 18) & cfgdatain(5 downto 0) & configDataLatched(11 downto 0) when "0010",
configDataLatched(31 downto 24) & cfgdatain(5 downto 0) & configDataLatched(17 downto 0) when "0011",
configDataLatched(31 downto 28) & cfgdatain(3 downto 0) & configDataLatched(23 downto 0) when "0100",
configDataLatched(31 downto 31) & cfgdatain(2 downto 0) & configDataLatched(27 downto 0) when "0101",
configDataLatched when others;
with cfgcomponent select cfgdataout <=
"00" & configDataLatched( 5 downto 0) when "0000",
"00" & configDataLatched(11 downto 6) when "0001",
"00" & configDataLatched(17 downto 12) when "0010",
"00" & configDataLatched(23 downto 18) when "0011",
"0000" & configDataLatched(27 downto 24) when "0100",
"00000" & configDataLatched(30 downto 28) when "0101",
resultLatched( 7 downto 0) when "1000",
resultLatched(15 downto 8) when "1001",
resultLatched(23 downto 16) when "1010",
statusLatched when "1111",
(others => '0') when others;
with outputAddr select output <=
"0000000" & driverOutput when x"00",
"000000" & driverOutput & "0" when x"01",
"00000" & driverOutput & "00" when x"02",
"0000" & driverOutput & "000" when x"03",
"000" & driverOutput & "0000" when x"04",
"00" & driverOutput & "00000" when x"05",
"0" & driverOutput & "000000" when x"06",
driverOutput & "0000000" when x"07",
"00000000" when others;
end Behavioral;
| gpl-2.0 |
twasiluk/hdmilight | fpga/uart_rx.vhd | 1 | 3799 | library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART Receiver ------------------------------------------------------------
entity uart_rx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
dout : out std_logic_vector(7 downto 0);
avail : out std_logic;
error : out std_logic;
clear : in std_logic;
--
rxd : in std_logic );
end uart_rx;
-----------------------------------------------------------------------------
-- Implemenattion -----------------------------------------------------------
architecture rtl of uart_rx is
constant halfbit : integer := fullbit / 2;
-- Signals
signal bitcount : integer range 0 to 10;
signal count : integer range 0 to FULLBIT;
signal shiftreg : std_logic_vector(7 downto 0);
signal rxd2 : std_logic;
begin
proc: process(clk, reset) is
begin
if reset='1' then
bitcount <= 0;
count <= 0;
error <= '0';
avail <= '0';
elsif clk'event and clk='1' then
if clear='1' then
error <= '0';
avail <= '0';
end if;
if count/=0 then
count <= count - 1;
else
if bitcount=0 then -- wait for startbit
if rxd2='0' then -- FOUND
count <= HALFBIT;
bitcount <= bitcount + 1;
end if;
elsif bitcount=1 then -- sample mid of startbit
if rxd2='0' then -- OK
count <= FULLBIT;
bitcount <= bitcount + 1;
shiftreg <= "00000000";
else -- ERROR
error <= '1';
bitcount <= 0;
end if;
elsif bitcount=10 then -- stopbit
if rxd2='1' then -- OK
count <= 0;
bitcount <= 0;
dout <= shiftreg;
avail <= '1';
else -- ERROR
count <= FULLBIT;
bitcount <= 0;
error <= '1';
end if;
else
shiftreg(6 downto 0) <= shiftreg(7 downto 1);
shiftreg(7) <= rxd2;
count <= FULLBIT;
bitcount <= bitcount + 1;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sync incoming RXD (anti metastable) --------------------------------------
syncproc: process(reset, clk) is
begin
if reset='1' then
rxd2 <= '1';
elsif clk'event and clk='1' then
rxd2 <= rxd;
end if;
end process;
end rtl; | gpl-2.0 |
sksavant/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple_arc.vhdl | 15 | 1525 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE simple_arc OF BJT_transistor_simple IS
terminal unnamed_net8 : electrical;
terminal unnamed_net7 : electrical;
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
SP1 : ENTITY SP_DIODE(SPICE_Diode_Model)
GENERIC MAP (
VT => VT,
AF => AF,
KF => KF,
PT => PT,
EG => EG,
M => ME,
PB => PE,
TT => TF,
CJ0 => CJE,
ISS => ISS)
PORT MAP ( ANODE => unnamed_net8,
KATHODE => unnamed_net5);
CS2 : ENTITY SPICE_cs(current_controlled)
GENERIC MAP (
N => BF,
VT => VT,
ISS => ISS)
PORT MAP ( urt => unnamed_net4,
lrt => unnamed_net5,
ult => unnamed_net1,
llt => unnamed_net8);
CAP2 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net5,
RT => unnamed_net1);
CAP1 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net1,
RT => unnamed_net4);
GND1 : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net7);
CAP3 : ENTITY CAPACITOR
GENERIC MAP (
c => CCS)
PORT MAP ( LT => unnamed_net7,
RT => unnamed_net4);
RES_emitter : ENTITY RESISTOR
GENERIC MAP (
r => RE)
PORT MAP ( RT => unnamed_net5,
LT => emitter);
RES_collector : ENTITY RESISTOR
GENERIC MAP (
r => RC)
PORT MAP ( RT => collector,
LT => unnamed_net4);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => RB)
PORT MAP ( RT => unnamed_net1,
LT => base);
END ARCHITECTURE simple_arc;
| gpl-2.0 |
samvartaka/simon_vhdl | OUTER_ROUND_PIPELINING/reg_64.vhd | 2 | 832 | -- SIMON 64/128
-- outer-pipelining word (64-bit) registry
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- data_in: registry input
-- data_out: registry output
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0)
);
end reg_64;
architecture Behavioral of reg_64 is
signal reg_64_s : std_logic_vector(63 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_64_s <= (others => '0');
else
reg_64_s <= data_in;
end if;
end if;
end process;
data_out <= reg_64_s;
end Behavioral; | gpl-2.0 |
gigglesninja/digital-system-design | lab9_uart_rx/ipcore_dir/fifo_rx/simulation/fifo_rx_dverif.vhd | 1 | 5496 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fifo_rx_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_rx/simulation/fifo_rx_rng.vhd | 2 | 3884 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo_rx_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo_rx_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_rx/simulation/fifo_rx_synth.vhd | 1 | 10246 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_rx_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_rx_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_rx_dgen
GENERIC MAP (
C_DIN_WIDTH => 9,
C_DOUT_WIDTH => 9,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_rx_dverif
GENERIC MAP (
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_rx_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_rx_inst : fifo_rx_exdes
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
pragmaware/ctags | Units/parser-vhdl.r/vhdl-process.d/input-0.vhd | 2 | 1493 | --
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer0 is
generic (
abits0 : integer := 5;
dbits0 : integer := 64
);
port (
i_clk0 : in std_logic;
i_raddr0 : in std_logic_vector(abits0-1 downto 0);
o_rdata0 : out std_logic_vector(dbits0-1 downto 0);
i_we0 : in std_logic;
i_waddr0 : in std_logic_vector(abits0-1 downto 0);
i_wdata0 : in std_logic_vector(dbits0-1 downto 0)
);
end;
architecture arch_StackTraceBuffer0 of StackTraceBuffer0 is
type ram_type0 is array ((2**abits0)-1 downto 0) of std_logic_vector (dbits0-1 downto 0);
signal stackbuf0 : ram_type0;
signal raddr0 : std_logic_vector(abits0-1 downto 0);
begin
-- registers:
process(i_clk0) begin
if rising_edge(i_clk0) then
if i_we0 = '1' then
stackbuf0(conv_integer(i_waddr0)) <= i_wdata0;
end if;
raddr0 <= i_raddr0;
end if;
end process;
o_rdata0 <= stackbuf0(conv_integer(raddr0));
end;
| gpl-2.0 |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_rx/simulation/fifo_rx_pctrl.vhd | 1 | 15371 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_rx_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/control.vhd | 1 | 4651 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:18:39 12/23/2015
-- Design Name:
-- Module Name: module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( Clock : IN std_logic;
Initial : IN std_logic;
trafo : IN std_logic;
EN125 : out std_logic;
EN346 : out std_logic;
EN78 : out std_logic;
S : out std_logic_vector(1 downto 0);
S_t : out std_logic_vector(1 downto 0);
Result : out std_logic);
end control;
architecture Behavioral of control is
signal int_state_sig : std_logic_vector(2 downto 0) := "111" ;
signal S_sig :std_logic_vector(1 downto 0) := "00";
begin
S <= S_sig;
proc_counter: process (Clock, int_state_sig, Initial, trafo)
begin
if Clock = '1' and Clock'EVENT then
if trafo = '0' then
case int_state_sig is
when "000" => int_state_sig <= "001";
when "001" => int_state_sig <= "010";
when "010" => int_state_sig <= "011";
when "011" => int_state_sig <= "100";
when "100" => int_state_sig <= "101";
when "101" => int_state_sig <= "110";
when "110" => int_state_sig <= "111";
when "111" => if Initial = '1' then int_state_sig <= "000";
else int_state_sig <= "111";
end if;
when others => int_state_sig <= "111";
end case;
else
case int_state_sig is
when "000" => int_state_sig <= "001";
when "001" => int_state_sig <= "010";
when "010" => int_state_sig <= "011";
when "011" => int_state_sig <= "110";
when "110" => int_state_sig <= "111";
when "111" => if Initial = '1' then int_state_sig <= "000";
else int_state_sig <= "111";
end if;
when others => int_state_sig <= "111";
end case;
end if;
end if;
end process proc_counter;
register_enable_proc : process (int_state_sig, trafo)
begin
if trafo = '0' then
case int_state_sig is
when "000" => EN125 <= '1';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
when "010" => EN125 <= '0';
EN346 <= '1';
EN78 <= '0';
Result <= '0';
when "100" => EN125 <= '0';
EN346 <= '0';
EN78 <= '1';
Result <= '0';
when "110" => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '1';
when others => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
end case;
else
case int_state_sig is
when "000" => EN125 <= '1';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
when "010" => EN125 <= '0';
EN346 <= '1';
EN78 <= '0';
Result <= '0';
when "110" => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '1';
when others => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
end case;
end if;
end process register_enable_proc;
int_state_proc : process (int_state_sig, trafo)
begin
if trafo = '0' then
case int_state_sig is
when "000" => S_sig <= "00";
when "001" => S_sig <= "00";
when "010" => S_sig <= "01";
when "011" => S_sig <= "01";
when "100" => S_sig <= "10";
when "101" => S_sig <= "10";
when "110" => S_sig <= "11";
when "111" => S_sig <= "11";
when others => S_sig <= "00";
end case;
else
case int_state_sig is
when "000" => S_sig <= "00";
when "001" => S_sig <= "00";
when "010" => S_sig <= "01";
when "011" => S_sig <= "01";
when "110" => S_sig <= "11";
when "111" => S_sig <= "11";
when others => S_sig <= "00";
end case;
end if;
end process int_state_proc;
signal_S_t_proc : process (S_sig, trafo)
begin
if trafo = '0' then
S_t(1) <= S_sig(1);
S_t(0) <= S_sig(0);
else
S_t(1) <= S_sig(1);
S_t(0) <= not S_sig(0);
end if;
end process signal_S_t_proc;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/tb_trafo.vhd | 4 | 3581 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:21:42 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_trafo.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trafo
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_trafo IS
END tb_trafo;
ARCHITECTURE behavior OF tb_trafo IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trafo
PORT(
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X1 : std_logic_vector(15 downto 0) := (others => '0');
signal X2 : std_logic_vector(15 downto 0) := (others => '0');
signal X3 : std_logic_vector(15 downto 0) := (others => '0');
signal X4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z1 : std_logic_vector(15 downto 0) := (others => '0');
signal Z2 : std_logic_vector(15 downto 0) := (others => '0');
signal Z3 : std_logic_vector(15 downto 0) := (others => '0');
signal Z4 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Y1 : std_logic_vector(15 downto 0);
signal Y2 : std_logic_vector(15 downto 0);
signal Y3 : std_logic_vector(15 downto 0);
signal Y4 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trafo PORT MAP (
X1 => X1,
X2 => X2,
X3 => X3,
X4 => X4,
Z1 => Z1,
Z2 => Z2,
Z3 => Z3,
Z4 => Z4,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
X1 <= std_logic_vector(to_unsigned(2596, 16));
X2 <= std_logic_vector(to_unsigned(152, 16));
X3 <= std_logic_vector(to_unsigned(60523, 16));
X4 <= std_logic_vector(to_unsigned(18725, 16));
Z1 <= std_logic_vector(to_unsigned(128, 16));
Z2 <= std_logic_vector(to_unsigned(192, 16));
Z3 <= std_logic_vector(to_unsigned(256, 16));
Z4 <= std_logic_vector(to_unsigned(320, 16));
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/tb_multiplexer_4_to_1.vhd | 2 | 2887 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:42 12/23/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_multiplexer_4_to_1.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer_4_to_1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_multiplexer_4_to_1 IS
END tb_multiplexer_4_to_1;
ARCHITECTURE behavior OF tb_multiplexer_4_to_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer_4_to_1
PORT(
in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
s : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal in1 : std_logic_vector(15 downto 0) := (others => '0');
signal in2 : std_logic_vector(15 downto 0) := (others => '0');
signal in3 : std_logic_vector(15 downto 0) := (others => '0');
signal in4 : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer_4_to_1 PORT MAP (
in1 => in1,
in2 => in2,
in3 => in3,
in4 => in4,
s => s,
O => O
);
in1 <= "0000000000000000", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in2 <= "0000000000000001", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in3 <= "0000000000000010", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in4 <= "0000000000000100", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
s <= "00", "01" after 5 ns, "11" after 15 ns, "10" after 25 ns, "00" after 35 ns, "01" after 40 ns, "10" after 50 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/roundcounter.vhd | 2 | 2568 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:31:58 12/25/2015
-- Design Name:
-- Module Name: round_counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity roundcounter is
Port ( Start : in STD_LOGIC;
Clock : in STD_LOGIC;
Ready : out STD_LOGIC;
S_i : out STD_LOGIC;
Result: in STD_LOGIC;
Round : out STD_LOGIC_VECTOR(3 DOWNTO 0);
Init : out STD_LOGIC;
Trafo : out STD_LOGIC);
end roundcounter;
architecture Behavioral of roundcounter is
signal Round_Sig : STD_LOGIC_VECTOR(3 DOWNTO 0);
type States is (Sleep, Calc, Setup);
signal State, Next_State : States;
begin
Trafo <= Round_Sig(3);
Round <= Round_Sig;
trafo_proc : process(Round_Sig)
begin
if Round_Sig = "0000" then S_i <= '1';
else S_i <= '0';
end if;
end process trafo_proc;
State_Memory : process (Clock)
begin
if Clock = '1' and Clock'EVENT then
State <= Next_State;
end if;
end process State_Memory;
NextStateLogic: process(Clock, State)
begin
if Clock = '1' and Clock'EVENT then
case State is
when Sleep => If Start = '1' then
Next_State <= Setup;
Round_Sig <= "0000";
else
Round_Sig <= "1000";
end if;
when Setup => Next_State <= Calc;
when Calc => If Result = '0' then --Next_State <= Calc;
else
if Result = '1' and Round_Sig = "1000" then
Next_State <= Sleep;
else if Result = '1' and Round_Sig /= "1000" then
Next_State <= Setup;
Round_Sig <= Round_Sig + 1;
end if;
end if;
end if;
end case;
end if;
end process NextStateLogic;
OutputLogic: process(Clock, State)
begin
case State is
when Sleep => Init <= '0';
Ready <= '1';
when Calc => Ready <= '0';
Init <= '0';
when Setup => Init <= '1';
Ready <= '0';
end case;
end process OutputLogic;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/roundcounter.vhd | 2 | 2568 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:31:58 12/25/2015
-- Design Name:
-- Module Name: round_counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity roundcounter is
Port ( Start : in STD_LOGIC;
Clock : in STD_LOGIC;
Ready : out STD_LOGIC;
S_i : out STD_LOGIC;
Result: in STD_LOGIC;
Round : out STD_LOGIC_VECTOR(3 DOWNTO 0);
Init : out STD_LOGIC;
Trafo : out STD_LOGIC);
end roundcounter;
architecture Behavioral of roundcounter is
signal Round_Sig : STD_LOGIC_VECTOR(3 DOWNTO 0);
type States is (Sleep, Calc, Setup);
signal State, Next_State : States;
begin
Trafo <= Round_Sig(3);
Round <= Round_Sig;
trafo_proc : process(Round_Sig)
begin
if Round_Sig = "0000" then S_i <= '1';
else S_i <= '0';
end if;
end process trafo_proc;
State_Memory : process (Clock)
begin
if Clock = '1' and Clock'EVENT then
State <= Next_State;
end if;
end process State_Memory;
NextStateLogic: process(Clock, State)
begin
if Clock = '1' and Clock'EVENT then
case State is
when Sleep => If Start = '1' then
Next_State <= Setup;
Round_Sig <= "0000";
else
Round_Sig <= "1000";
end if;
when Setup => Next_State <= Calc;
when Calc => If Result = '0' then --Next_State <= Calc;
else
if Result = '1' and Round_Sig = "1000" then
Next_State <= Sleep;
else if Result = '1' and Round_Sig /= "1000" then
Next_State <= Setup;
Round_Sig <= Round_Sig + 1;
end if;
end if;
end if;
end case;
end if;
end process NextStateLogic;
OutputLogic: process(Clock, State)
begin
case State is
when Sleep => Init <= '0';
Ready <= '1';
when Calc => Ready <= '0';
Init <= '0';
when Setup => Init <= '1';
Ready <= '0';
end case;
end process OutputLogic;
end Behavioral;
| gpl-2.0 |
DesignChips/wp-p5js | assets/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/multiplexer.vhd | 4 | 1283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:06:16 11/14/2015
-- Design Name:
-- Module Name: multiplexer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplexer is
Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
O : out STD_LOGIC_VECTOR(15 downto 0);
s : in STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
multiplex_proc : process(A,B,s)
begin
case s is
when '0' => O <= A;
when '1' => O <= B;
when others => O <= "XXXXXXXXXXXXXXXX";
end case;
end process multiplex_proc;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/txmit.vhd | 4 | 5787 | -- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: txmit.vhd
--
-- Purpose: UART transmit description. Interprets
-- processor read/write parallel bus cycles
-- and converts to output serial data.
--
-- Created: VHDL code generated by Visual HDL 8-15-01
--
-- Revision 2.00 (Ning Chen): avoid latch
--
-- *******************************************************************
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- use work.pkg_util.all;
entity txmit is
port (
mclkx16 : in STD_LOGIC;
write : in STD_LOGIC;
reset : in STD_LOGIC;
sout : out STD_LOGIC;
txrdy : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0)
);
end txmit;
architecture behavior of txmit is
-- ********************** SIGNAL DECLARATIONS *************************
signal write1 : STD_LOGIC; -- Delayed write signals
signal write2 : STD_LOGIC;
signal txdone1 : STD_LOGIC; -- txdone delayed signal
-- Transmit shift register bits
signal thr : STD_LOGIC_VECTOR(7 downto 0 ); -- Transmit hold register
signal tsr : STD_LOGIC_VECTOR(7 downto 0 ); -- Transmit shift register, used for shifting out data to sout
signal tag1 : STD_LOGIC; -- Tag bits used for detecting, when the tsr is empty
signal tag2 : STD_LOGIC;
signal paritymode : STD_LOGIC := 'Z';
signal txparity : STD_LOGIC; -- Parity generation register
-- Transmit clock and other control signals
signal txclk : STD_LOGIC; -- Transmit clock, i.e. baudrate clock = mclkx16 / 16
signal txdone : STD_LOGIC; -- Set to high, when shifting of byte is done
signal paritycycle : STD_LOGIC; -- Set to high, one cycle next to last shift cycle
signal txdatardy : STD_LOGIC; -- Set to high, when data is ready in transmit hold register
signal cnt : STD_LOGIC_VECTOR(2 downto 0 ); -- Counter used for generating the internal baud rate clock
begin
-- *************************** SIGNAL DEFINITIONS ****************************
paritymode <= '1';
-- Paritycycle = 1 on next to last cycle, this means when tsr[1] gets tag2
paritycycle <= tsr(1) and not((tag2 or tag1 or tsr(7) or tsr(6) or tsr(5) or
tsr(4) or tsr(3) or tsr(2)));
-- txdone = 1 when done shifting, this means when sout gets tag2
txdone <= not(tag2 or tag1 or tsr(7) or tsr(6) or tsr(5) or tsr(4) or tsr(3)
or tsr(2) or tsr(1) or tsr(0));
-- Ready for new data to be written, when no data is in transmit hold register
txrdy <= not(txdatardy);
-- *************************** PROCESS DEFINITIONS ****************************
-- Latch data[7:0] into the transmit hold register at falling edge of write
process (write, data)
begin
if not((write) = '1' ) then
thr <= data;
else
thr <= data;
end if ;
end process ;
-- Toggle txclk every 8 counts, which divides the clock by 16, to generate the baud clock
process (mclkx16, reset)
begin
if (reset) = '1' then
txclk <= '0';
cnt <= "000";
elsif (mclkx16'event and mclkx16 = '1' ) then
if cnt = "000" then
txclk <= not(txclk);
end if ;
cnt <= ext(ext(cnt,32) + 1,abs(2-0)+1);
end if ;
end process ;
-- Shifting out data to sout
process (txclk, reset)
begin
if (reset) = '1' then
tsr <= "00000000"; -- Reset transmit shift register
tag2 <= '0'; -- Reset tag bit
tag1 <= '0'; -- Reset tag bit
txparity <= '0'; -- Reset txparty bit
sout <= '1'; -- Idle -> set start bit high
elsif (txclk'event and txclk = '1' ) then
if (txdone) = '1' and (txdatardy) = '1' then
tsr <= thr; -- Load thr to shift register
tag2 <= '1'; -- Set tag bits for detecting when shifting is done
tag1 <= '1'; -- Set tag bits for detecting when shifting is done
txparity <= paritymode; -- Set parity mode -> 0 = even parity, 1 = odd parity
sout <= '0'; -- Set start bit low
else
tsr <= std_logic_vector(SHR(unsigned(tsr) , unsigned'("00000000000000000000000000000001"
))); -- Send LSB first
tsr(7) <= tag1; -- Set tsr[7] = tag1
tag1 <= tag2; -- Set tag1 = tag2
tag2 <= '0'; -- Set tag2 = 0
txparity <= txparity xor tsr(0); -- Generate parity
-- Shift out data or parity bit or stop/idle bit.
if (txdone) = '1' then
sout <= '1'; -- Output stop/idle bit
else
if (paritycycle) = '1' then
sout <= txparity; -- Output parity bit
else
sout <= tsr(0);-- Shift out data bit
end if ;
end if ;
end if ;
end if ;
end process ;
process (mclkx16, reset)
begin
if (reset) = '1' then
txdatardy <= '0';
write2 <= '1';
write1 <= '1';
txdone1 <= '1';
elsif (mclkx16'event and mclkx16 = '1' ) then
if (write1) = '1' and (write2 = '0' ) then
txdatardy <= '1'; -- Set txdatardy on rising edge of write
else
if (txdone = '0' ) and (txdone1) = '1' then
txdatardy <= '0';-- Falling edge of txdone indicated the thr is loaded in the tsr
end if ;
end if ;
-- Generate delayed versions of write and txdone signals for edge detection.
write2 <= write1;
write1 <= write;
txdone1 <= txdone;
end if ;
end process ;
end ;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/keygen.vhd | 4 | 5950 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:10:30 11/15/2015
-- Design Name:
-- Module Name: keygen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keygen is
Port ( rc : in STD_LOGIC_VECTOR(3 downto 0); --rc:round_counter
key_in : in STD_LOGIC_VECTOR(127 downto 0);
z1 : out STD_LOGIC_VECTOR(15 downto 0);
z2 : out STD_LOGIC_VECTOR(15 downto 0);
z3 : out STD_LOGIC_VECTOR(15 downto 0);
z4 : out STD_LOGIC_VECTOR(15 downto 0);
z5 : out STD_LOGIC_VECTOR(15 downto 0);
z6 : out STD_LOGIC_VECTOR(15 downto 0));
end keygen;
architecture Behavioral of keygen is
signal skeyshift1 : std_logic_vector(127 downto 0);
signal skeyshift2 : std_logic_vector(127 downto 0);
signal skeyshift3 : std_logic_vector(127 downto 0);
signal skeyshift4 : std_logic_vector(127 downto 0);
signal skeyshift5 : std_logic_vector(127 downto 0);
signal skeyshift6 : std_logic_vector(127 downto 0);
signal skeyshift7 : std_logic_vector(127 downto 0);
begin
keygen_proc: process(rc,key_in)
variable skeyshift1 : std_logic_vector(127 downto 0);
variable skeyshift2 : std_logic_vector(127 downto 0);
variable skeyshift3 : std_logic_vector(127 downto 0);
variable skeyshift4 : std_logic_vector(127 downto 0);
variable skeyshift5 : std_logic_vector(127 downto 0);
variable skeyshift6 : std_logic_vector(127 downto 0);
variable skeyshift7 : std_logic_vector(127 downto 0);
begin
skeyshift1 := key_in;
skeyshift2 := skeyshift1(102 downto 0) & skeyshift1(127 downto 103);
skeyshift3 := skeyshift2(102 downto 0) & skeyshift2(127 downto 103);
skeyshift4 := skeyshift3(102 downto 0) & skeyshift3(127 downto 103);
skeyshift5 := skeyshift4(102 downto 0) & skeyshift4(127 downto 103);
skeyshift6 := skeyshift5(102 downto 0) & skeyshift5(127 downto 103);
skeyshift7 := skeyshift6(102 downto 0) & skeyshift6(127 downto 103);
case rc is
when "0000" => z1 <= skeyshift1(127 downto 112); --z1r1;
z2 <= skeyshift1(111 downto 96); --z2r1;
z3 <= skeyshift1(95 downto 80); --z3r1;
z4 <= skeyshift1(79 downto 64); --z4r1;
z5 <= skeyshift1(63 downto 48); --z5r1;
z6 <= skeyshift1(47 downto 32); --z6r1;
when "0001" =>
z1 <= skeyshift1(31 downto 16); --z1r2;
z2 <= skeyshift1(15 downto 0); --z2r2;
z3 <= skeyshift2(127 downto 112); --z3r2;
z4 <= skeyshift2(111 downto 96); --z4r2;
z5 <= skeyshift2(95 downto 80); --z5r2;
z6 <= skeyshift2(79 downto 64); --z6r2;
when "0010" => z1 <= skeyshift2(63 downto 48); --z1r3;
z2 <= skeyshift2(47 downto 32); --z3r2;
z3 <= skeyshift2(31 downto 16); --z3r3;
z4 <= skeyshift2(15 downto 0); --z4r3;
z5 <= skeyshift3(127 downto 112); --z5r3;
z6 <= skeyshift3(111 downto 96); --z6r3;
when "0011" =>
z1 <= skeyshift3(95 downto 80); --z1r4;
z2 <= skeyshift3(79 downto 64); --z2r4;
z3 <= skeyshift3(63 downto 48); --z3r4;
z4 <= skeyshift3(47 downto 32); --z4r4;
z5 <= skeyshift3(31 downto 16); --z5r4;
z6 <= skeyshift3(15 downto 0); --z6r4;
when "0100" => z1 <= skeyshift4(127 downto 112); --z1r5;
z2 <= skeyshift4(111 downto 96); --z2r5;
z3 <= skeyshift4(95 downto 80); --z3r5;
z4 <= skeyshift4(79 downto 64); --z4r5;
z5 <= skeyshift4(63 downto 48); --z5r5;
z6 <= skeyshift4(47 downto 32); --z6r5;
when "0101" =>
z1 <= skeyshift4(31 downto 16); --z1r6;
z2 <= skeyshift4(15 downto 0); --z2r6;
z3 <= skeyshift5(127 downto 112); --z3r6;
z4 <= skeyshift5(111 downto 96); --z4r6;
z5 <= skeyshift5(95 downto 80); --z5r6;
z6 <= skeyshift5(79 downto 64); --z6r6;
when "0110" =>
z1 <= skeyshift5(63 downto 48); --z1r7;
z2 <= skeyshift5(47 downto 32); --2r7;
z3 <= skeyshift5(31 downto 16); --z3r7;
z4 <= skeyshift5(15 downto 0); --z4r7;
z5 <= skeyshift6(127 downto 112); --z5r7;
z6 <= skeyshift6(111 downto 96); --z6r7;
when "0111" =>
z1 <= skeyshift6(95 downto 80); --z1r8;
z2 <= skeyshift6(79 downto 64); --z2r8;
z3 <= skeyshift6(63 downto 48); --z3r8;
z4 <= skeyshift6(47 downto 32); --z4r8;
z5 <= skeyshift6(31 downto 16); --z5r8;
z6 <= skeyshift6(15 downto 0); --z6r8;
when "1000" =>
z1 <= skeyshift7(127 downto 112); --z1r9;
z2 <= skeyshift7(111 downto 96); --z2r9;
z3 <= skeyshift7(95 downto 80); --z3r9;
z4 <= skeyshift7(79 downto 64); --z4r9;
z5 <= "0000000000000000"; --z5r8;
z6 <= "0000000000000000"; --z6r8;
when others =>
z1 <= "0000000000000000"; --z1r9;
z2 <= "0000000000000000"; --z2r9;
z3 <= "0000000000000000"; --z3r9;
z4 <= "0000000000000000"; --z4r9;
z5 <= "0000000000000000"; --z5r8;
z6 <= "0000000000000000"; --z6r8;
end case;
end process keygen_proc;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/idea_rcs2.vhd | 2 | 7150 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:24:26 12/25/2015
-- Design Name:
-- Module Name: idea_rcs2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_rcs2 is
Port ( X1 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
X2 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
X3 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
X4 : in STD_LOGIC_VECTOR(15 DOWNTO 0);
Y1 : out STD_LOGIC_VECTOR(15 DOWNTO 0);
Y2 : out STD_LOGIC_VECTOR(15 DOWNTO 0);
Y3 : out STD_LOGIC_VECTOR(15 DOWNTO 0);
Y4 : out STD_LOGIC_VECTOR(15 DOWNTO 0);
Clock : in STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
Start : IN STD_LOGIC;
Ready : OUT STD_LOGIC);
end idea_rcs2;
architecture Behavioral of idea_rcs2 is
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
COMPONENT roundcounter
PORT(
Start : IN std_logic;
Clock : IN std_logic;
Ready : OUT std_logic;
S_i : OUT std_logic;
Result : IN std_logic;
Round : OUT std_logic_vector(3 downto 0);
Init : OUT std_logic;
Trafo : OUT std_logic
);
END COMPONENT;
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT clockedround
PORT(
Clock : IN std_logic;
Init : IN Std_Logic;
Result : OUT Std_Logic;
Trafo : IN Std_Logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal EN125 : STD_LOGIC;
signal EN346 : STD_LOGIC;
signal EN78 : STD_LOGIC;
signal S : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_t : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_i : STD_LOGIC;
signal Trafo : STD_LOGIC;
signal Init : STD_LOGIC;
signal Result : STD_LOGIC;
signal Round : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal Y1_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Y2_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Y3_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Y4_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal MUX1_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal MUX2_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal MUX3_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal MUX4_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal R1_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal R2_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal R3_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal R4_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z1_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z2_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z3_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z4_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z5_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Z6_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
REG1: register_16bit PORT MAP (
D => Y1_OUT,
Q => R1_OUT,
en => Result,
clk => Clock
);
REG2: register_16bit PORT MAP (
D => Y2_OUT,
Q => R2_OUT,
en => Result,
clk => Clock
);
REG3: register_16bit PORT MAP (
D => Y3_OUT,
Q => R3_OUT,
en => Result,
clk => Clock
);
REG4: register_16bit PORT MAP (
D => Y4_OUT,
Q => R4_OUT,
en => Result,
clk => Clock
);
MUX1: multiplexer PORT MAP (
A => R1_OUT,
B => X1,
O => MUX1_OUT,
s => S_i
);
MUX2: multiplexer PORT MAP (
A => R2_OUT,
B => X2,
O => MUX2_OUT,
s => S_i
);
MUX3: multiplexer PORT MAP (
A => R3_OUT,
B => X3,
O => MUX3_OUT,
s => S_i
);
MUX4: multiplexer PORT MAP (
A => R4_OUT,
B => X4,
O => MUX4_OUT,
s => S_i
);
ROUND_COUNTER: roundcounter PORT MAP (
Start => Start,
Clock => Clock,
Ready => Ready,
S_i => S_i,
Result => Result,
Round => Round,
Init => Init,
Trafo => Trafo
);
KEY_GENERATOR: keygen PORT MAP (
rc => Round,
key_in => KEY,
z1 => Z1_OUT,
z2 => Z2_OUT,
z3 => Z3_OUT,
z4 => Z4_OUT,
z5 => Z5_OUT,
z6 => Z6_OUT
);
extended_round_module: clockedround PORT MAP (
Clock => Clock,
Init => Init,
Result => Result,
Trafo => Trafo,
X1 => MUX1_OUT,
X2 => MUX2_OUT,
X3 => MUX3_OUT,
X4 => MUX4_OUT,
Z1 => Z1_OUT,
Z2 => Z2_OUT,
Z3 => Z3_OUT,
Z4 => Z4_OUT,
Z5 => Z5_OUT,
Z6 => Z6_OUT,
Y1 => Y1_OUT,
Y2 => Y2_OUT,
Y3 => Y3_OUT,
Y4 => Y4_OUT,
Y1_trafo => Y1,
Y2_trafo => Y2,
Y3_trafo => Y3,
Y4_trafo => Y4
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_module.vhd | 2 | 2423 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:55:53 12/23/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_module.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: module
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_module IS
END tb_module;
ARCHITECTURE behavior OF tb_module IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT module
PORT(
Clock : IN std_logic;
Initial : IN std_logic;
EN125 : OUT std_logic;
EN346 : OUT std_logic;
EN78 : OUT std_logic;
S : OUT std_logic_vector(1 downto 0);
Result : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal Initial : std_logic := '0';
--Outputs
signal EN125 : std_logic;
signal EN346 : std_logic;
signal EN78 : std_logic;
signal S : std_logic_vector(1 downto 0);
signal Result : std_logic;
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: module PORT MAP (
Clock => Clock,
Initial => Initial,
EN125 => EN125,
EN346 => EN346,
EN78 => EN78,
S => S,
Result => Result
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
Initial <= '0', '1' after 40 ns, '0' after 70 ns, '1' after 170 ns, '0' after 200 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/idea_single.vhd | 4 | 8352 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:05:10 11/16/2015
-- Design Name:
-- Module Name: idea_single - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_single is
Port ( KEY : in std_logic_vector(127 downto 0);
clk_in : in std_logic;
ready_out : out std_logic;
start_in : in std_logic;
X1 : in std_logic_vector(15 downto 0);
X2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
X4 : in std_logic_vector(15 downto 0);
Y1 : out std_logic_vector(15 downto 0);
Y2 : out std_logic_vector(15 downto 0);
Y3 : out std_logic_vector(15 downto 0);
Y4 : out std_logic_vector(15 downto 0));
end idea_single;
architecture Behavioral of idea_single is
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0) ;
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
COMPONENT trafo
PORT(
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT round
PORT(
x1 : IN std_logic_vector(15 downto 0);
x2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
x4 : IN std_logic_vector(15 downto 0);
z1 : IN std_logic_vector(15 downto 0);
z2 : IN std_logic_vector(15 downto 0);
z3 : IN std_logic_vector(15 downto 0);
z4 : IN std_logic_vector(15 downto 0);
z5 : IN std_logic_vector(15 downto 0);
z6 : IN std_logic_vector(15 downto 0);
y1 : OUT std_logic_vector(15 downto 0);
y2 : OUT std_logic_vector(15 downto 0);
y3 : OUT std_logic_vector(15 downto 0);
y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
round : OUT std_logic_vector(3 downto 0);
ready : OUT std_logic;
en : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
signal round_out_y1 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y2 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y3 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y4 : std_logic_vector(15 downto 0) := (others => '0');
signal round_number : std_logic_vector(3 downto 0) := (others => '0');
signal enable_sig : std_logic := '0';
signal s_sig : std_logic := '0';
signal key_1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_4_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_5_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_6_sig : std_logic_vector(15 downto 0) := (others => '0');
signal reg_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal y1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y4_sig : std_logic_vector(15 downto 0) := (others => '0');
begin
Y1 <= y1_sig;
Y2 <= y2_sig;
Y3 <= y3_sig;
Y4 <= y4_sig;
register_1: register_16bit PORT MAP (
D => round_out_y1,
Q => reg_1_out,
en => enable_sig,
clk => clk_in
);
register_2: register_16bit PORT MAP (
D => round_out_y2,
Q => reg_2_out,
en => enable_sig,
clk => clk_in
);
register_3: register_16bit PORT MAP (
D => round_out_y3,
Q => reg_3_out,
en => enable_sig,
clk => clk_in
);
register_4: register_16bit PORT MAP (
D => round_out_y4,
Q => reg_4_out,
en => enable_sig,
clk => clk_in
);
control_1: control PORT MAP (
clk => clk_in,
start => start_in,
round => round_number,
ready => ready_out,
en => enable_sig,
s => s_sig
);
trafo_1: trafo PORT MAP (
X1 => reg_1_out,
X2 => reg_2_out,
X3 => reg_3_out,
X4 => reg_4_out,
Z1 => key_1_sig,
Z2 => key_2_sig,
Z3 => key_3_sig,
Z4 => key_4_sig,
Y1 => y1_sig,
Y2 => y2_sig,
Y3 => y3_sig,
Y4 => y4_sig
);
round_module: round PORT MAP (
x1 => mux_1_out,
x2 => mux_2_out,
X3 => mux_3_out,
x4 => mux_4_out,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig,
y1 => round_out_y1,
y2 => round_out_y2,
y3 => round_out_y3,
y4 => round_out_y4
);
mux_1: multiplexer PORT MAP (
A => X1,
B => reg_1_out,
O => mux_1_out,
s => s_sig
);
mux_2: multiplexer PORT MAP (
A => X2,
B => reg_2_out,
O => mux_2_out,
s => s_sig
);
mux_3: multiplexer PORT MAP (
A => X3,
B => reg_3_out,
O => mux_3_out,
s => s_sig
);
mux_4: multiplexer PORT MAP (
A => X4,
B => reg_4_out,
O => mux_4_out,
s => s_sig
);
keygen_module: keygen PORT MAP (
rc => round_number,
key_in => KEY,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/Exercise1/direct_implementation/round.vhd | 1 | 4531 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 10:57:18 11/03/2015
-- Design Name:
-- Module Name: round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity round is
Port ( x1 : in std_logic_vector(15 downto 0);
x2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
x4 : in std_logic_vector(15 downto 0);
z1 : in std_logic_vector(15 downto 0);
z2 : in std_logic_vector(15 downto 0);
z3 : in std_logic_vector(15 downto 0);
z4 : in std_logic_vector(15 downto 0);
z5 : in std_logic_vector(15 downto 0);
z6 : in std_logic_vector(15 downto 0);
y1 : out std_logic_vector(15 downto 0);
y2 : out std_logic_vector(15 downto 0);
y3 : out std_logic_vector(15 downto 0);
y4 : out std_logic_vector(15 downto 0));
end round;
architecture Behavioral of round is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal x1z1 : std_logic_vector(15 downto 0) := (others => '0');
signal x2z2 : std_logic_vector(15 downto 0) := (others => '0');
signal x3z3 : std_logic_vector(15 downto 0) := (others => '0');
signal x4z4 : std_logic_vector(15 downto 0) := (others => '0');
signal sm1 : std_logic_vector(15 downto 0) := (others => '0');
signal sm2 : std_logic_vector(15 downto 0) := (others => '0');
signal sm3 : std_logic_vector(15 downto 0) := (others => '0');
signal sm4 : std_logic_vector(15 downto 0) := (others => '0');
signal sa1 : std_logic_vector(15 downto 0) := (others => '0');
signal sa2 : std_logic_vector(15 downto 0) := (others => '0');
signal sa3 : std_logic_vector(15 downto 0) := (others => '0');
signal sa4 : std_logic_vector(15 downto 0) := (others => '0');
signal sx1 : std_logic_vector(15 downto 0) := (others => '0');
signal sx2 : std_logic_vector(15 downto 0) := (others => '0');
begin
mulop_1: mulop PORT MAP (
X => x1,
Y => z1,
O => x1z1
);
mulop_2: mulop PORT MAP (
X => x4,
Y => z4,
O => x4z4
);
mulop_3: mulop PORT MAP (
X => sx1,
Y => z5,
O => sm3
);
mulop_4: mulop PORT MAP (
X => sa3,
Y => z6,
O => sm4
);
addop_1: addop PORT MAP (
A => x2,
B => z2,
O => x2z2
);
addop_2: addop PORT MAP (
A => x3,
B => z3,
O => x3z3
);
addop_3: addop PORT MAP (
A => sx2,
B => sm3,
O => sa3
);
addop_4: addop PORT MAP (
A => sm4,
B => sm3,
O => sa4
);
xorop_1: xorop PORT MAP (
A => x1z1,
B => x3z3,
O => sx1
);
xorop_2: xorop PORT MAP (
A => x2z2,
B => x4z4,
O => sx2
);
xorop_3: xorop PORT MAP (
A => x1z1,
B => sm4,
O => y1
);
xorop_4: xorop PORT MAP (
A => x3z3,
B => sm4,
O => y2
);
xorop_5: xorop PORT MAP (
A => x2z2,
B => sa4,
O => y3
);
xorop_6: xorop PORT MAP (
A => x4z4,
B => sa4,
O => y4
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/tb_keygen.vhd | 4 | 3237 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/clk_div.vhd | 4 | 1285 | ----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 09:38:04 05/29/2008
-- Design Name:
-- Module Name: clk_div - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This is the clock generator.
-- It takes the 50MHz on-board clock and devides it
-- by a factor to get the frequency 16*19200 Hz,
-- which is needed for the UART.
--
-- Dependencies:
--
-- Revision 1.00 - File created and tested
-- Revision 2.00 - Changed baud rate to 19200
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk_div is
Port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk_div;
architecture Behavioral of clk_div is
signal counter : INTEGER := 0;
begin
process(CLK)
begin
if ( CLK'event and CLK = '1' ) then
counter<=counter+1;
if ( counter < 81 ) then
CLK_OUT <= '0';
elsif ( counter < 162 ) then
CLK_OUT <= '1';
else
counter <= 0;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/tb_reg_sync.vhd | 4 | 2269 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/round.vhd | 3 | 4882 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 10:57:18 11/03/2015
-- Design Name:
-- Module Name: round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity round is
Port ( x1 : in std_logic_vector(15 downto 0);
x2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
x4 : in std_logic_vector(15 downto 0);
z1 : in std_logic_vector(15 downto 0);
z2 : in std_logic_vector(15 downto 0);
z3 : in std_logic_vector(15 downto 0);
z4 : in std_logic_vector(15 downto 0);
z5 : in std_logic_vector(15 downto 0);
z6 : in std_logic_vector(15 downto 0);
y1 : out std_logic_vector(15 downto 0);
y2 : out std_logic_vector(15 downto 0);
y3 : out std_logic_vector(15 downto 0);
y4 : out std_logic_vector(15 downto 0));
end round;
architecture Behavioral of round is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal x1z1 : std_logic_vector(15 downto 0) := (others => '0');
signal x2z2 : std_logic_vector(15 downto 0) := (others => '0');
signal x3z3 : std_logic_vector(15 downto 0) := (others => '0');
signal x4z4 : std_logic_vector(15 downto 0) := (others => '0');
signal sm1 : std_logic_vector(15 downto 0) := (others => '0');
signal sm2 : std_logic_vector(15 downto 0) := (others => '0');
signal sm3 : std_logic_vector(15 downto 0) := (others => '0');
signal sm4 : std_logic_vector(15 downto 0) := (others => '0');
signal sa1 : std_logic_vector(15 downto 0) := (others => '0');
signal sa2 : std_logic_vector(15 downto 0) := (others => '0');
signal sa3 : std_logic_vector(15 downto 0) := (others => '0');
signal sa4 : std_logic_vector(15 downto 0) := (others => '0');
signal sx1 : std_logic_vector(15 downto 0) := (others => '0');
signal sx2 : std_logic_vector(15 downto 0) := (others => '0');
signal y1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y4_sig : std_logic_vector(15 downto 0) := (others => '0');
begin
y1 <= y1_sig;
y2 <= y2_sig;
y3 <= y3_sig;
y4 <= y4_sig;
mulop_1: mulop PORT MAP (
X => x1,
Y => z1,
O => x1z1
);
mulop_2: mulop PORT MAP (
X => x4,
Y => z4,
O => x4z4
);
mulop_3: mulop PORT MAP (
X => sx1,
Y => z5,
O => sm3
);
mulop_4: mulop PORT MAP (
X => sa3,
Y => z6,
O => sm4
);
addop_1: addop PORT MAP (
A => x2,
B => z2,
O => x2z2
);
addop_2: addop PORT MAP (
A => x3,
B => z3,
O => x3z3
);
addop_3: addop PORT MAP (
A => sx2,
B => sm3,
O => sa3
);
addop_4: addop PORT MAP (
A => sm4,
B => sm3,
O => sa4
);
xorop_1: xorop PORT MAP (
A => x1z1,
B => x3z3,
O => sx1
);
xorop_2: xorop PORT MAP (
A => x2z2,
B => x4z4,
O => sx2
);
xorop_3: xorop PORT MAP (
A => x1z1,
B => sm4,
O => y1_sig
);
xorop_4: xorop PORT MAP (
A => x3z3,
B => sm4,
O => y2_sig
);
xorop_5: xorop PORT MAP (
A => x2z2,
B => sa4,
O => y3_sig
);
xorop_6: xorop PORT MAP (
A => x4z4,
B => sa4,
O => y4_sig
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/round.vhd | 3 | 4882 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 10:57:18 11/03/2015
-- Design Name:
-- Module Name: round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity round is
Port ( x1 : in std_logic_vector(15 downto 0);
x2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
x4 : in std_logic_vector(15 downto 0);
z1 : in std_logic_vector(15 downto 0);
z2 : in std_logic_vector(15 downto 0);
z3 : in std_logic_vector(15 downto 0);
z4 : in std_logic_vector(15 downto 0);
z5 : in std_logic_vector(15 downto 0);
z6 : in std_logic_vector(15 downto 0);
y1 : out std_logic_vector(15 downto 0);
y2 : out std_logic_vector(15 downto 0);
y3 : out std_logic_vector(15 downto 0);
y4 : out std_logic_vector(15 downto 0));
end round;
architecture Behavioral of round is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal x1z1 : std_logic_vector(15 downto 0) := (others => '0');
signal x2z2 : std_logic_vector(15 downto 0) := (others => '0');
signal x3z3 : std_logic_vector(15 downto 0) := (others => '0');
signal x4z4 : std_logic_vector(15 downto 0) := (others => '0');
signal sm1 : std_logic_vector(15 downto 0) := (others => '0');
signal sm2 : std_logic_vector(15 downto 0) := (others => '0');
signal sm3 : std_logic_vector(15 downto 0) := (others => '0');
signal sm4 : std_logic_vector(15 downto 0) := (others => '0');
signal sa1 : std_logic_vector(15 downto 0) := (others => '0');
signal sa2 : std_logic_vector(15 downto 0) := (others => '0');
signal sa3 : std_logic_vector(15 downto 0) := (others => '0');
signal sa4 : std_logic_vector(15 downto 0) := (others => '0');
signal sx1 : std_logic_vector(15 downto 0) := (others => '0');
signal sx2 : std_logic_vector(15 downto 0) := (others => '0');
signal y1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y4_sig : std_logic_vector(15 downto 0) := (others => '0');
begin
y1 <= y1_sig;
y2 <= y2_sig;
y3 <= y3_sig;
y4 <= y4_sig;
mulop_1: mulop PORT MAP (
X => x1,
Y => z1,
O => x1z1
);
mulop_2: mulop PORT MAP (
X => x4,
Y => z4,
O => x4z4
);
mulop_3: mulop PORT MAP (
X => sx1,
Y => z5,
O => sm3
);
mulop_4: mulop PORT MAP (
X => sa3,
Y => z6,
O => sm4
);
addop_1: addop PORT MAP (
A => x2,
B => z2,
O => x2z2
);
addop_2: addop PORT MAP (
A => x3,
B => z3,
O => x3z3
);
addop_3: addop PORT MAP (
A => sx2,
B => sm3,
O => sa3
);
addop_4: addop PORT MAP (
A => sm4,
B => sm3,
O => sa4
);
xorop_1: xorop PORT MAP (
A => x1z1,
B => x3z3,
O => sx1
);
xorop_2: xorop PORT MAP (
A => x2z2,
B => x4z4,
O => sx2
);
xorop_3: xorop PORT MAP (
A => x1z1,
B => sm4,
O => y1_sig
);
xorop_4: xorop PORT MAP (
A => x3z3,
B => sm4,
O => y2_sig
);
xorop_5: xorop PORT MAP (
A => x2z2,
B => sa4,
O => y3_sig
);
xorop_6: xorop PORT MAP (
A => x4z4,
B => sa4,
O => y4_sig
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/mulop.vhd | 4 | 2399 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:33:45 11/02/2015
-- Design Name:
-- Module Name: mulop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mulop is
Port ( X : in STD_LOGIC_VECTOR(15 downto 0);
Y : in STD_LOGIC_VECTOR(15 downto 0);
O : out STD_LOGIC_VECTOR(15 downto 0));
end mulop;
architecture Behavioral of mulop is
begin
mul_process: process (X,Y)
variable a: std_logic_vector(16 downto 0) := "00000000000000000"; --X signed to a
variable b: std_logic_vector(16 downto 0) := "00000000000000000"; --Y signed to b
variable c: std_logic_vector(33 downto 0) := "0000000000000000000000000000000000"; -- result a*b
variable d: std_logic_vector(32 downto 0) := "000000000000000000000000000000000"; -- result d=c mod (2^16)
variable e: std_logic_vector(32 downto 0) := "000000000000000000000000000000000"; -- result d=c mod (2^16)
variable f: std_logic_vector(32 downto 0) := "000000000000000000000000000000000"; -- total result
begin
-- substitute
if X="0000000000000000" then a:="10000000000000000";
else a:='0' & X(15 downto 0);
end if;
if Y="0000000000000000" then b:="10000000000000000";
else b:='0' & Y(15 downto 0);
end if;
-- c=a*b
-- c is 33 downto 0 because 33th bit is vorzeichen
c := std_logic_vector(unsigned(a)*unsigned(b));
-- d= c mod (2^16)
d := "00000000000000000"&c(15 downto 0);
-- e=c div (2^16)
e := "0000000000000000"&c(32 downto 16);
if unsigned(d) >= unsigned(e) then f := std_logic_vector(unsigned(d)-unsigned(e));
else f := std_logic_vector(unsigned(d)-unsigned(e) + 65537);
end if;
O<=f(15 downto 0);
end process mul_process;
end Behavioral;
| gpl-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/ipcore_dir/ROM_4K_ste/example_design/ROM_4K_top.vhd | 1 | 4567 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ROM_4K_top IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ROM_4K_top;
ARCHITECTURE xilinx OF ROM_4K_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ROM_4K IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ROM_4K
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd | 1 | 4355 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v6_2_top IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v6_2_top;
ARCHITECTURE xilinx OF blk_mem_gen_v6_2_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v6_2 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v6_2
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 |
alyoshin/geda-gaf | gnetlist/examples/vams/vhdl/new-vhdl/bjt_transistor_simple_top.vhdl | 14 | 223 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY bjt_transistor_simple_top IS
END ENTITY bjt_transistor_simple_top;
| gpl-2.0 |
ashtonchase/logic_analyzer | test/sump_comms_tb.vhd | 1 | 5341 | -------------------------------------------------------------------------------
-- Title : UART testbench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : UART_tb.vhd
-- Created : 2016-02-22
-- Last update: 2016-04-06
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the UART testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-16 1.0 ian Created
-------------------------------------------------------------------------------
use WORK.all;
library ieee;
use IEEE.std_logic_1164.all;
entity UART_tb is
end entity;
library ieee;
use IEEE.std_logic_1164.all;
architecture test of sump_commsT_tb is
signal clk : std_logic; -- clock
signal rst : std_logic; -- reset
signal rx : std_logic; -- data line from top level
signal tx : std_logic;
signal tx_command : std_logic_vector(31 downto 0); -- data from storage
signal command_ready : std_logic; -- flags for data message collect
signal data_ready : std_logic; -- flag for transmit message
signal data_sent : std_logic; -- flag for transmit message
--
signal command : std_logic_vector(7 downto 0); -- commands for message handler
constant baud_rate : integer := 9600;
constant clock_freq : integer := 10_000_000;
signal recieve_data : std_logic_vector(7 downto 0);
begin
u1 : entity work.uart_comms
generic map (clock_freq => clock_freq,
baud_rate => baud_rate)
port map (clk => clk,
rst => rst,
tx => tx,
rx => rx,
tx_command => tx_command,
command_ready => command_ready,
data_ready => data_ready,
data_sent => data_sent,
command => command);
process (clk)
begin
clk <= not clk after 50 ns; -- 10 MHz clock
end process;
baud_clocking : process (clk)
begin
if(clk = '1' and clk'event) then
if (baud_counter < baud_total-1) then
baud_counter <= baud_counter + 1;
else
baud_counter <= 0;
baud_clock <= not baud_clock;
end if;
end if;
end process baud_clocking;
process
begin
rx <= '1';
rst <= '0';
wait for 10 ns;
receive_data <= "10011100";
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
rx <= '1'; -- nothing
wait until rising_edge(baud_clock);
rx <= '0'; -- stb
wait until rising_edge(baud_clock);
rx <= receive_data(0);
wait until rising_edge(baud_clock);
rx <= receive_data(1);
wait until rising_edge(baud_clock);
rx <= receive_data(2);
wait until rising_edge(baud_clock);
rx <= receive_data(3);
wait until rising_edge(baud_clock);
rx <= receive_data(4);
wait until rising_edge(baud_clock);
rx <= receive_data(5);
wait until rising_edge(baud_clock);
rx <= receive_data(6);
wait until rising_edge(baud_clock);
rx <= receive_data(7);
wait until rising_edge(baud_clock);
rx <= '1'; -- end
assert data_out = receive_data report "data out does not match UART data in" severity failure;
wait for 100 us;
wait until rising_edge(baud_clock);
rx_get_more_data <= '1';
end process;
process
begin
data_ready <= '0';
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
tx_command <= "10100111"&"00001111"&"10101010"&"01010101";
data_ready <= '1';
wait for 100 ms;
end process;
end test;
| gpl-2.0 |
alyoshin/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/resistor_arc.vhdl | 15 | 113 | ARCHITECTURE beh OF resistor IS
QUANTITY v ACROSS i THROUGH lt to rt;
BEGIN
v == r * i;
END ARCHITECTURE beh;
| gpl-2.0 |
ashtonchase/logic_analyzer | src/la_top.vhd | 1 | 8359 | ----------------------------------------------------------------------------
-- Title : Logic Analyzer Top Module
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : la_top.vhd
-- Created : 2016-02-22
-- Last update: 2016-04-09
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the top instatiting modue of the logic analyzer. This
-- will define the generic I/O interfaces to the system. Ideally, all modules
-- below this will be portable to whatever your target hardware will be.
--
-- Stucture: (incomplete)
-- -----------
-- RX | UART |
-- -----| |
-- | |
-- TX | |
-- -----| |
-- | |
-- | |
-- -----------
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-- 2016-03-09 1.1 ashton Added sample_storage_block and
-- DATA_WIDTH and SAMPLE_DEPTH generics.
-- 2016-04-?? 1.2 paul made integration updates.
-- 2016-04-09 1.3 ashton updated sample rate block instantiation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity la_top is
generic (
BAUD_RATE : positive := 115_200;
INPUT_CLK_RATE_HZ : positive range 10_000_000 to 200_000_000 := 100_000_000;
DATA_WIDTH : positive range 1 to 32 := 8;
SAMPLE_DEPTH : positive range 1 to 2**18 := 2**8);
port (
--COMMON INTERFACES
clk : in std_logic; --clock
rst : in std_logic := '0'; --reset, (async high/ sync low)
--data input. defaulte to zeroes so you don't have to hook all 32 lines up.
din : in std_logic_vector(31 downto 0) := (others => '0');
--UART INTERFACES
uart_rx : in std_logic; -- UART Receive Data
uart_tx : out std_logic; -- UART Transmit Data
armed : out std_logic;
triggered : out std_logic;
capture_rdy : out std_logic;
--data_sent : out std_logic;
command_ready : out std_logic;
debug : out std_logic_vector(7 downto 0));
begin
--entity-wide checks
assert IS_X(clk) = false report "clk is undefined" severity error;
assert IS_X(din) = false report "din is undefined" severity error;
assert IS_X(uart_rx) = false report "uart_rx is undefined" severity error;
end entity la_top;
architecture structural of la_top is
-- LA Control Signals
signal rst_cmd : std_logic := '0';
signal arm_cmd : std_logic;
signal id_cmd : std_logic;
signal debug_cmd : std_logic;
signal sample_enable : std_logic := '1';
signal sample_cnt_rst : std_logic;
signal delay_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '0');
signal read_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '1');
signal par_trig_msk : std_logic_vector(32-1 downto 0) := (others => '0');
signal par_trig_val : std_logic_vector(32-1 downto 0) := (others => '1');
-- Input to Storage Signals
signal in_fifo_tdata : std_logic_vector(31 downto 0);
signal in_fifo_tvalid : std_logic;
signal in_fifo_tlast : std_logic;
signal in_fifo_tready : std_logic;
signal in_fifo_tfull : std_logic;
signal in_fifo_tempty : std_logic;
signal in_fifo_tflush : std_logic;
-- Output from Storage Signals
signal out_fifo_tdata : std_logic_vector(7 downto 0);
signal out_fifo_tvalid : std_logic;
signal out_fifo_tlast : std_logic;
signal out_fifo_tready : std_logic;
-- Sump Comms Signals
signal sump_byte : std_logic_vector(7 downto 0);
signal command_ready_int : std_logic;
signal data_sent : std_logic;
-- Message Processing Signals
signal sample_f : std_logic_vector(23 downto 0);
signal armed_int : std_logic;
begin -- ARCHITECTURE structural
command_ready <= command_ready_int;
debug <= sump_byte;
capture_control_block : entity work.capture_ctrl
generic map (
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst => rst,
--
din => din(7 downto 0),
armed => armed_int,
triggered => triggered,
id_cmd => id_cmd,
rst_cmd => rst_cmd,
arm_cmd => arm_cmd,
debug_cmd => debug_cmd,
sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
delay_cnt_4x => delay_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => capture_rdy, -- FIX: NOT USED, don't need. message_processing will try. you determine if it will work
--
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : entity work.storage
generic map (
FIFO_SIZE => SAMPLE_DEPTH)
port map (
clk => clk,
reset => rst,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => data_sent); -- data_sent is named poorly, using it for ready signal
SUMP_UART_block : entity work.SUMPComms
generic map (clock_freq => INPUT_CLK_RATE_HZ, baud_rate => baud_rate)
port map (
clk => clk,
rst => rst,
rx => uart_rx,
tx => uart_tx,
tx_command => out_fifo_tdata,
command_ready => command_ready_int,
data_ready => out_fifo_tvalid,
data_sent => data_sent,
command => sump_byte);
Message_processing_block : entity work.msg_processor
port map (
clk => clk,
rst => rst,
--
byte_in => sump_byte,
byte_new => command_ready_int,
--
sample_f => sample_f,
--outputs
reset => rst_cmd,
armed => arm_cmd,
send_ID => id_cmd,
send_debug=> debug_cmd,
read_cnt => read_cnt_4x,
delay_cnt => delay_cnt_4x,
trig_msk => par_trig_msk,
trig_vals => par_trig_val);
sample_rate_block : entity work.sample_rate_ctrl -- not implemented yet
port map(
clk => clk,
rst => rst,
divider_rate => sample_f,
reset => sample_cnt_rst,
armed => armed_int,
sample_en => sample_enable);
armed <= armed_int;
end architecture structural;
| gpl-2.0 |
alyoshin/geda-gaf | gnetlist/tests/gnetlistrc.vhdl | 8 | 205 | ;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
| gpl-2.0 |
ashtonchase/logic_analyzer | target_hardware/ZedBoard/zed_top_capture_ctrl_test.vhd | 1 | 11863 | -------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY zybo_top IS
PORT (
--Clock Source
GCLK : IN STD_LOGIC; -- 100 MHz clock
--LED Outputs
LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 : OUT STD_LOGIC;
--Buttons
BTNC, BTND, BTNL, BTNR, BTNU : IN STD_LOGIC;
--Temporary Data Ouput (JA10-JA7, JA4-JA1)
JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1 : OUT STD_LOGIC;
--UART SIGNALS
JB4 : IN STD_LOGIC := 'H'; --RX
JB1 : OUT STD_LOGIC --TX
--Fixed Zync Signals
--DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
--DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
--DDR_cas_n : INOUT STD_LOGIC;
--DDR_ck_n : INOUT STD_LOGIC;
--DDR_ck_p : INOUT STD_LOGIC;
--DDR_cke : INOUT STD_LOGIC;
--DDR_cs_n : INOUT STD_LOGIC;
--DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
--DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_odt : INOUT STD_LOGIC;
--DDR_ras_n : INOUT STD_LOGIC;
--DDR_reset_n : INOUT STD_LOGIC;
--DDR_we_n : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
--FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
--FIXED_IO_ps_clk : INOUT STD_LOGIC;
--FIXED_IO_ps_porb : INOUT STD_LOGIC;
--FIXED_IO_ps_srstb : INOUT STD_LOGIC;
);
END ENTITY zybo_top;
ARCHITECTURE top OF zybo_top IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
COMPONENT Zynq_BD_wrapper IS
PORT (
DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
DDR_cas_n : INOUT STD_LOGIC;
DDR_ck_n : INOUT STD_LOGIC;
DDR_ck_p : INOUT STD_LOGIC;
DDR_cke : INOUT STD_LOGIC;
DDR_cs_n : INOUT STD_LOGIC;
DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_odt : INOUT STD_LOGIC;
DDR_ras_n : INOUT STD_LOGIC;
DDR_reset_n : INOUT STD_LOGIC;
DDR_we_n : INOUT STD_LOGIC;
FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
FIXED_IO_ps_clk : INOUT STD_LOGIC;
FIXED_IO_ps_porb : INOUT STD_LOGIC;
FIXED_IO_ps_srstb : INOUT STD_LOGIC;
UART_rxd : IN STD_LOGIC;
UART_txd : OUT STD_LOGIC
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT DATA_WIDTH : POSITIVE := 32;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
SIGNAL reset, reset_clk_gen : STD_LOGIC := '1'; -- reset (async high, sync low)
SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard
SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC;
SIGNAL sample_enable : STD_LOGIC := '1';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL delay_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1000, 16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"00_00_00_03";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
SIGNAL in_fifo_tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL in_fifo_tvalid : STD_LOGIC;
SIGNAL in_fifo_tlast : STD_LOGIC;
SIGNAL in_fifo_tready : STD_LOGIC;
SIGNAL in_fifo_tfull : STD_LOGIC;
SIGNAL in_fifo_tempty : STD_LOGIC;
SIGNAL in_fifo_tflush : STD_LOGIC;
--
SIGNAL out_fifo_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL out_fifo_tvalid : STD_LOGIC;
SIGNAL out_fifo_tlast : STD_LOGIC;
SIGNAL out_fifo_tready : STD_LOGIC;
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
ALIAS reset_btn : STD_LOGIC IS BTND;
ALIAS CLK : STD_LOGIC IS GCLK;
ALIAS UART_RX : STD_LOGIC IS JB4;
ALIAS UART_TX : STD_LOGIC IS JB1;
BEGIN -- ARCHITECTURE top
JA10 <= out_fifo_tdata(7);
JA9 <= out_fifo_tdata(6);
JA8 <= out_fifo_tdata(5);
JA7 <= out_fifo_tdata(4);
JA4 <= out_fifo_tdata(3);
JA3 <= out_fifo_tdata(2);
JA2 <= out_fifo_tdata(1);
JA1 <= out_fifo_tdata(0);
--LED to indicate that the clock is locked
LD1 <= clk_locked;
capture_control_block : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => run_clk,
rst => reset,
din => X"00_00_00" & "00000" & btnl & btnc & btnr,
armed => ld3,
triggered => ld2,
rst_cmd => btnd,
arm_cmd => btnu,
-- sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
-- delay_cnt_4x => delay_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => ld0,
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : ENTITY work.storage
GENERIC MAP (
FIFO_SIZE => 2**18)
PORT MAP (
clk => run_clk,
reset => reset,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => '1');
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : ENTITY work.clock_gen
PORT MAP (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_clk_gen,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
run_clk_reset_proc : PROCESS (reset_btn, run_clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset <= '1';
reset_dly_v := '1';
ELSIF rising_edge(run_clk) THEN
IF clk_locked = '1' THEN
reset <= reset_dly_v;
reset_dly_v := '0';
ELSE
reset <= '1';
reset_dly_v := '1';
END IF;
END IF;
END PROCESS run_clk_reset_proc;
reset_proc : PROCESS (reset_btn, clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset_clk_gen <= '1';
ELSIF rising_edge(clk) THEN
reset_clk_gen <= reset_dly_v;
reset_dly_v := '0';
END IF;
END PROCESS reset_proc;
--zynq : ENTITY work.Zynq_BD_wrapper
-- PORT MAP (
-- DDR_addr => DDR_addr,
-- DDR_ba => DDR_ba,
-- DDR_cas_n => DDR_cas_n,
-- DDR_ck_n => DDR_ck_n,
-- DDR_ck_p => DDR_ck_p,
-- DDR_cke => DDR_cke,
-- DDR_cs_n => DDR_cs_n,
-- DDR_dm => DDR_dm,
-- DDR_dq => DDR_dq,
-- DDR_dqs_n => DDR_dqs_n,
-- DDR_dqs_p => DDR_dqs_p,
-- DDR_odt => DDR_odt,
-- DDR_ras_n => DDR_ras_n,
-- DDR_reset_n => DDR_reset_n,
-- DDR_we_n => DDR_we_n,
-- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
-- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
-- FIXED_IO_mio => FIXED_IO_mio,
-- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
-- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
-- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
-- UART_rxd => UART_rxd,
-- UART_txd => UART_txd);
END ARCHITECTURE top;
| gpl-2.0 |
oridb/ctags | Units/review-needed.r/test.vhd.t/input.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
juvasquezg/geany-hacking | data/filetypes.vhdl | 5 | 2985 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10306 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library user_logic;
use user_logic.all;
entity dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
attribute secure_config : string;
attribute secure_config of dyplo_hdl_node : entity is "PROTECT";
attribute secure_netlist : string;
attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT";
attribute secure_net_editing : string;
attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT";
attribute secure_net_probing : string;
attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT";
end dyplo_hdl_node;
architecture rtl of dyplo_hdl_node is
component dyplo_user_logic_adder_2_to_1 is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component dyplo_user_logic_adder_2_to_1;
signal dab_sel_ul : std_logic;
signal dab_wvalid_ul : std_logic;
signal dab_rvalid_ul : std_logic;
signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal cin_tdata_i : cin_tdata_ul_type;
signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tlevel_i : cin_tlevel_ul_type;
signal cout_tdata_i : cout_tdata_ul_type;
signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0);
signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE --
-----------------------------------------------------------------------------
-- The available memory range for the CPU fifo control is limited to --
-- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the --
-- AXI bus is 256 words. The actual FIFO data memory range is also limited --
-- to 64Kbytes or 16Kwords. Also, the space is divided between reading and --
-- writing. This leaves 8Kwords per direction and with a burst length of --
-- 256 words, maximum 32 input streams and 32 output streams can be --
-- supported. --
-----------------------------------------------------------------------------
-- Each fifo has the following metrics: --
-- - FIFO full and FIFO empty flag --
-- - FIFO fill level compare register and compare flag --
-- - Actual FIFO fill level indicator --
-- - Under/overflow detection flag when operating FIFO out of range --
-- --
-- Per input FIFO (from FPGA fabric to the CPU) it is required to specify --
-- the stream source. Also, a maskable interrupt should be issued per --
-- input FIFO to signal the need to empty the FIFO by the CPU. --
-----------------------------------------------------------------------------
dyplo_hdl_node_logic_i : dyplo_hdl_node_logic
generic map (
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Miscellaneous
node_id => node_id,
-- DAB interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr,
dab_sel => dab_sel,
dab_wvalid => dab_wvalid,
dab_rvalid => dab_rvalid,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata,
b2f_tstream_id => b2f_tstream_id,
b2f_tvalid => b2f_tvalid,
b2f_tready => b2f_tready,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata,
f2b_tstream_id => f2b_tstream_id,
f2b_tvalid => f2b_tvalid,
f2b_tready => f2b_tready,
-- Serial fifo status info
fifo_status_sync => fifo_status_sync,
fifo_status_flag => fifo_status_flag,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0),
-- DAB interface to user logic
dab_sel_ul => dab_sel_ul,
dab_wvalid_ul => dab_wvalid_ul,
dab_rvalid_ul => dab_rvalid_ul,
dab_rdata_ul => dab_rdata_ul,
-- In streams to user logic
cin_tdata_ul => cin_tdata_i,
cin_tvalid_ul => cin_tvalid_i,
cin_tready_ul => cin_tready_i,
cin_tlevel_ul => cin_tlevel_i,
-- Out streams from user logic
cout_tdata_ul => cout_tdata_i,
cout_tvalid_ul => cout_tvalid_i,
cout_tready_ul => cout_tready_i
);
dyplo_user_logic_i : dyplo_user_logic_adder_2_to_1
generic map(
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Processor bus interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr(15 downto 0),
dab_sel => dab_sel_ul,
dab_wvalid => dab_wvalid_ul,
dab_rvalid => dab_rvalid_ul,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata_ul,
-- Streaming input interfaces
cin_tdata => cin_tdata_i,
cin_tvalid => cin_tvalid_i,
cin_tready => cin_tready_i,
cin_tlevel => cin_tlevel_i,
-- Streaming output interfaces
cout_tdata => cout_tdata_i,
cout_tvalid => cout_tvalid_i,
cout_tready => cout_tready_i,
-- Clock signals
user_clocks => user_clocks
);
end rtl;
| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10300 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library user_logic;
use user_logic.all;
entity dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
attribute secure_config : string;
attribute secure_config of dyplo_hdl_node : entity is "PROTECT";
attribute secure_netlist : string;
attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT";
attribute secure_net_editing : string;
attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT";
attribute secure_net_probing : string;
attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT";
end dyplo_hdl_node;
architecture rtl of dyplo_hdl_node is
component dyplo_user_logic_subtractor is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component dyplo_user_logic_subtractor;
signal dab_sel_ul : std_logic;
signal dab_wvalid_ul : std_logic;
signal dab_rvalid_ul : std_logic;
signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal cin_tdata_i : cin_tdata_ul_type;
signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tlevel_i : cin_tlevel_ul_type;
signal cout_tdata_i : cout_tdata_ul_type;
signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0);
signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE --
-----------------------------------------------------------------------------
-- The available memory range for the CPU fifo control is limited to --
-- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the --
-- AXI bus is 256 words. The actual FIFO data memory range is also limited --
-- to 64Kbytes or 16Kwords. Also, the space is divided between reading and --
-- writing. This leaves 8Kwords per direction and with a burst length of --
-- 256 words, maximum 32 input streams and 32 output streams can be --
-- supported. --
-----------------------------------------------------------------------------
-- Each fifo has the following metrics: --
-- - FIFO full and FIFO empty flag --
-- - FIFO fill level compare register and compare flag --
-- - Actual FIFO fill level indicator --
-- - Under/overflow detection flag when operating FIFO out of range --
-- --
-- Per input FIFO (from FPGA fabric to the CPU) it is required to specify --
-- the stream source. Also, a maskable interrupt should be issued per --
-- input FIFO to signal the need to empty the FIFO by the CPU. --
-----------------------------------------------------------------------------
dyplo_hdl_node_logic_i : dyplo_hdl_node_logic
generic map (
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Miscellaneous
node_id => node_id,
-- DAB interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr,
dab_sel => dab_sel,
dab_wvalid => dab_wvalid,
dab_rvalid => dab_rvalid,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata,
b2f_tstream_id => b2f_tstream_id,
b2f_tvalid => b2f_tvalid,
b2f_tready => b2f_tready,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata,
f2b_tstream_id => f2b_tstream_id,
f2b_tvalid => f2b_tvalid,
f2b_tready => f2b_tready,
-- Serial fifo status info
fifo_status_sync => fifo_status_sync,
fifo_status_flag => fifo_status_flag,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0),
-- DAB interface to user logic
dab_sel_ul => dab_sel_ul,
dab_wvalid_ul => dab_wvalid_ul,
dab_rvalid_ul => dab_rvalid_ul,
dab_rdata_ul => dab_rdata_ul,
-- In streams to user logic
cin_tdata_ul => cin_tdata_i,
cin_tvalid_ul => cin_tvalid_i,
cin_tready_ul => cin_tready_i,
cin_tlevel_ul => cin_tlevel_i,
-- Out streams from user logic
cout_tdata_ul => cout_tdata_i,
cout_tvalid_ul => cout_tvalid_i,
cout_tready_ul => cout_tready_i
);
dyplo_user_logic_i : dyplo_user_logic_subtractor
generic map(
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Processor bus interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr(15 downto 0),
dab_sel => dab_sel_ul,
dab_wvalid => dab_wvalid_ul,
dab_rvalid => dab_rvalid_ul,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata_ul,
-- Streaming input interfaces
cin_tdata => cin_tdata_i,
cin_tvalid => cin_tvalid_i,
cin_tready => cin_tready_i,
cin_tlevel => cin_tlevel_i,
-- Streaming output interfaces
cout_tdata => cout_tdata_i,
cout_tvalid => cout_tvalid_i,
cout_tready => cout_tready_i,
-- Clock signals
user_clocks => user_clocks
);
end rtl;
| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_hdl_node_user_params.vhd | 2 | 2533 | -- File: dyplo_hdl_node_user_params.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic�s maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hdl_node_user_params is
constant c_vendor_id : integer range 0 to 255 := 1;
constant c_product_id : integer range 0 to 255 := 4;
constant c_version_id : integer range 0 to 255 := 1;
constant c_revision_id : integer range 0 to 255 := 1;
constant c_input_streams : integer range 0 to 4 := 4;
constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096
constant c_hdl_in_fifo_type : string := "DISTRIBUTED";
constant c_output_streams : integer range 0 to 4 := 4;
end hdl_node_user_params;
| gpl-2.0 |
mbgh/aes128-hdl | src/vhdl/mixColumn.vhd | 1 | 4555 | -------------------------------------------------------------------------------
--! @file mixColumn.vhd
--! @brief AES MixColumn operation (single column)
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-06-05
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: mixColumn.vhd 6 2014-06-12 12:49:55Z u59323933 $
-- Revision : $Revision: 6 $
-- Local Date : $Date: 2014-06-12 14:49:55 +0200 (Thu, 12 Jun 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES MixColumn operation (single column)
--!
--! The present design implements the MixColumn operation of the Advanced
--! Encryption Standard (AES).
-------------------------------------------------------------------------------
entity mixColumn is
port (
--! @brief Input to the "MixColumn" function.
In_DI : in Word;
--! @brief Output of the "MixColumn" function.
Out_DO : out Word);
end entity mixColumn;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture of the "MixColumn" function.
-------------------------------------------------------------------------------
architecture Behavioral of mixColumn is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal Byte0_D, Byte0Doubled_D, Byte0Tripled_D : Byte;
signal Byte1_D, Byte1Doubled_D, Byte1Tripled_D : Byte;
signal Byte2_D, Byte2Doubled_D, Byte2Tripled_D : Byte;
signal Byte3_D, Byte3Doubled_D, Byte3Tripled_D : Byte;
begin -- architecture Behavioral
-----------------------------------------------------------------------------
-- First Byte
-----------------------------------------------------------------------------
Byte0_D <= In_DI(0);
Byte0Doubled_D <= ((In_DI(0)(6 downto 0) & '0') xor x"1B") when In_DI(0)(7) = '1'
else (In_DI(0)(6 downto 0) & '0');
Byte0Tripled_D <= Byte0Doubled_D xor Byte0_D;
-----------------------------------------------------------------------------
-- Second Byte
-----------------------------------------------------------------------------
Byte1_D <= In_DI(1);
Byte1Doubled_D <= ((In_DI(1)(6 downto 0) & '0') xor x"1B") when In_DI(1)(7) = '1'
else (In_DI(1)(6 downto 0) & '0');
Byte1Tripled_D <= Byte1Doubled_D xor Byte1_D;
-----------------------------------------------------------------------------
-- Third Byte
-----------------------------------------------------------------------------
Byte2_D <= In_DI(2);
Byte2Doubled_D <= ((In_DI(2)(6 downto 0) & '0') xor x"1B") when In_DI(2)(7) = '1'
else (In_DI(2)(6 downto 0) & '0');
Byte2Tripled_D <= Byte2Doubled_D xor Byte2_D;
-----------------------------------------------------------------------------
-- Fourth Byte
-----------------------------------------------------------------------------
Byte3_D <= In_DI(3);
Byte3Doubled_D <= ((In_DI(3)(6 downto 0) & '0') xor x"1B") when In_DI(3)(7) = '1'
else (In_DI(3)(6 downto 0) & '0');
Byte3Tripled_D <= Byte3Doubled_D xor Byte3_D;
-----------------------------------------------------------------------------
-- Output Assignment
-----------------------------------------------------------------------------
Out_DO(0) <= Byte0Doubled_D xor Byte1Tripled_D xor Byte2_D xor Byte3_D;
Out_DO(1) <= Byte0_D xor Byte1Doubled_D xor Byte2Tripled_D xor Byte3_D;
Out_DO(2) <= Byte0_D xor Byte1_D xor Byte2Doubled_D xor Byte3Tripled_D;
Out_DO(3) <= Byte0Tripled_D xor Byte1_D xor Byte2_D xor Byte3Doubled_D;
end architecture Behavioral;
| gpl-2.0 |
zefie/hackrf | firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_ecb_encryption_monte_carlo_testbench_192bits.vhd | 1 | 11509 | -- Twofish_ecb_encryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench192 is
end ecb_encryption_monte_carlo_testbench192;
architecture ecb_encryption192_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round192
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_encryption_circuit: twofish_encryption_round192
port map (
in1_ter192 => to_round(127 downto 96),
in2_ter192 => to_round(95 downto 64),
in3_ter192 => to_round(63 downto 32),
in4_ter192 => to_round(31 downto 0),
in_Sfirst_ter192 => Sfirst,
in_Ssecond_ter192 => Ssecond,
in_Sthird_ter192 => Sthird,
in_key_up_ter192 => key_up,
in_key_down_ter192 => key_down,
out1_ter192 => to_encr_reg128(127 downto 96),
out2_ter192 => to_encr_reg128(95 downto 64),
out3_ter192 => to_encr_reg128(63 downto 32),
out4_ter192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption192_monte_carlo_testbench_arch;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd | 1 | 11468 | -- Twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench192 is
end cbc_decryption_monte_carlo_testbench192;
architecture cbc_decryption192_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round192
port (
in1_tdr192,
in2_tdr192,
in3_tdr192,
in4_tdr192,
in_Sfirst_tdr192,
in_Ssecond_tdr192,
in_Sthird_tdr192,
in_key_up_tdr192,
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
out1_tdr192,
out2_tdr192,
out3_tdr192,
out4_tdr192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_192bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_decryption_circuit: twofish_decryption_round192
port map (
in1_tdr192 => to_round(127 downto 96),
in2_tdr192 => to_round(95 downto 64),
in3_tdr192 => to_round(63 downto 32),
in4_tdr192 => to_round(31 downto 0),
in_Sfirst_tdr192 => Sfirst,
in_Ssecond_tdr192 => Ssecond,
in_Sthird_tdr192 => Sthird,
in_key_up_tdr192 => key_up,
in_key_down_tdr192 => key_down,
out1_tdr192 => to_encr_reg128(127 downto 96),
out2_tdr192 => to_encr_reg128(95 downto 64),
out3_tdr192 => to_encr_reg128(63 downto 32),
out4_tdr192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption192_monte_carlo_testbench_arch;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd | 1 | 11309 | -- Twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench128 is
end ecb_encryption_monte_carlo_testbench128;
architecture ecb_encryption128_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption128_monte_carlo_testbench_arch;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/svgactrl.in.vhd | 4 | 80 | -- SVGA controller
constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/alltap.vhd | 1 | 12624 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: alltap
-- File: alltap.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Test Access Port (TAP) Controller component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package alltap is
component tap_gen
generic (
irlen : integer range 2 to 8 := 2;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1);
port (
trst : in std_ulogic;
tckp : in std_ulogic;
tckn : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic
);
end component;
component virtex_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex2_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex4_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex5_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan3_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component altera_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component fusion_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3e_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3l_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component virtex6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component kintex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component artix7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component zynq_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component igloo2_tap is
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0));
end component;
-------------------------------------------------------------------------------
component scanregi_inf
generic (
intesten : integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego_inf
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregio_inf -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
hzsup : integer range 0 to 1 := 1;
intesten: integer := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic
);
end component;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/leon3mp.vhd | 1 | 56220 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 - 2014 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.IBUFDS;
-- pragma translate_on
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY0
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- Ethernet PHY1 SGMII
sgmiiclk_qo_p : in std_logic;
sgmiiclk_qo_n : in std_logic;
phy1_reset : out std_logic;
phy1_mdio : inout std_logic;
phy1_mdc : out std_logic;
phy1_int : out std_logic;
phy1_sgmii_tx_p : out std_logic;
phy1_sgmii_tx_n : out std_logic;
phy1_sgmii_rx_p : in std_logic;
phy1_sgmii_rx_n : in std_logic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
-- Set this constant to 1 to include an APB bridge with the Logan logic
-- analyzer attached to the PCI signals
constant CFG_LOGAN : integer := 0;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apb1i : apb_slv_in_type;
signal apbo, apb1o : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal opb_bus_errorl, plb_bus_errorl : std_ulogic;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal sgmii_refclk, sgmii_rst: std_logic;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP+CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal pci_dirq : std_logic_vector(3 downto 0);
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
-- Logan signals
signal signals : std_logic_vector(63*CFG_LOGAN downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute syn_keep of pciclk : signal is true;
attribute syn_preserve of pciclk : signal is true;
attribute syn_keep of sgmii_refclk : signal is true;
attribute syn_preserve of sgmii_refclk : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of pciclk : signal is true;
attribute keep of sgmii_refclk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11 + CFG_LOGAN)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE,
CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
opb_bus_errorl <= not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#D00#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ,
bwidth => AHBDW, ahbpf => CFG_AHBPF)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= not gpioo.val(0); -- Position on on GPIO DIP switch
plb_bus_errorl <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; plb_bus_errorl <= '0';
end generate;
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, opb_bus_errorl);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, plb_bus_errorl);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if CFG_MCTRL_LEON2 = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0, ahbsi, ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(63 downto 32*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1, ahbsi, ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_pads : iopadvv generic map (tech => padtech, width => 3, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 0), gpioo.dout(2 downto 0), gpioo.oen(2 downto 0),
gpioi.din(2 downto 0));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 6, haddr => CFG_APBADDR + 1, nslaves => 3)
port map (rstn, clkm, ahbsi, ahbso(6), apb1i, apb1o);
-- log: if CFG_LOGAN = 1 generate -- Logan is enabled by constant
-- -- declared above
-- apb0 : apbctrl -- AHB/APB bridge
-- generic map (hindex => 11, haddr => 16#F00#, nslaves => 1)
-- port map (rstn, clkm, ahbsi, ahbso(11), apb1i, apb1o);
-- logan0 : logan -- Logic analyzer
-- generic map (dbits => 64, depth => 4096, trigl => 2, usereg => 1,
-- usequal => 0, pindex => 0, paddr => 0, pmask => 16#F00#,
-- memtech => memtech)
-- port map (rstn, clkm, pciclk, apb1i, apb1o(0), signals);
-- signals(0) <= pcii.rst;
-- signals(1) <= pcii.gnt;
-- signals(2) <= pcii.idsel;
-- signals(34 downto 3) <= pcii.ad;
-- signals(38 downto 35) <= pcii.cbe;
-- signals(39) <= pcii.frame;
-- signals(40) <= pcii.irdy;
-- signals(41) <= pcii.trdy;
-- signals(42) <= pcii.devsel;
-- signals(43) <= pcii.stop;
-- signals(44) <= pcii.lock;
-- signals(45) <= pcii.perr;
-- signals(46) <= pcii.serr;
-- signals(47) <= pcii.par;
-- signals(48) <= pcii.host;
-- signals(49) <= pcii.pci66;
-- signals(53 downto 50) <= pcii.int;
-- signals(58 downto 54) <= pci_arb_gnt(0 to 4);
-- signals(63 downto 59) <= pci_arb_req(0 to 4);
-- end generate log;
nolog: if CFG_LOGAN /= 1 generate
signals <= (others => '0');
apb1o(0) <= apb_none;
end generate nolog;
l3sgen : if CFG_L3S_ENABLE /= 0 generate
l3s : l3stat
generic map (pindex => 1, paddr => 1, pmask => 16#fff#,
ncnt => CFG_L3S_CNT, ncpu => CFG_NCPU,
nmax => CFG_L3S_NMAX, lahben => 1, dsuen => CFG_DSU)
port map (rstn => rstn, clk => clkm, apbi => apb1i, apbo => apb1o(1),
ahbsi => ahbsi, dbgo => dbgo);
end generate;
nol3s : if CFG_L3S_ENABLE = 0 generate
apb1o(1) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk);
e2 : greths generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
pindex => 2, paddr => 2, pirq => 10,
fabtech => fabtech, memtech => memtech, transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
apbi => apb1i,
apbo => apb1o(2),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => phy1_sgmii_rx_p,
eth_rx_n => phy1_sgmii_rx_n,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
e2mdio_pad : iopad generic map (tech => padtech)
port map (phy1_mdio, mdio_o, mdio_oe, mdio_i);
e2mdc_pad : outpad generic map (tech => padtech)
port map (phy1_mdc, mdc);
e2rst_pad : outpad generic map (tech => padtech)
port map (phy1_reset, mdio_reset);
e2int_pad : outpad generic map (tech => padtech)
port map (phy1_int, mdint);
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => 0,
hmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2,
hdmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1,
hsindex => 7,
haddr => 16#800#,
hmask => 16#c00#,
ioaddr => 16#400#,
pindex => 4,
paddr => 4,
irq => 5,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn,
clkm,
pciclk,
pci_dirq,
pcii,
pcio,
apbi,
apbo(4),
ahbsi,
ahbso(7),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1)
);
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_GRPCI2_MASTER = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/adqsin.vhd | 6 | 1455 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsin is
port(
dqs_pad : in std_logic; -- DQS pad
dqsn_pad : in std_logic; -- DQSN pad
dqs : out std_logic
);
end;
architecture rtl of adqsin is
component stratixiii_io_ibuf IS
generic (
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "z";
lpm_type : string := "stratixiii_io_ibuf"
);
port (
i : in std_logic := '0';
ibar : in std_logic := '0';
o : out std_logic
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_buf : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- In buffer (DQS, DQSN) ------------------------------------------------------------
dqs_buf0 : stratixiii_io_ibuf
generic map(
differential_mode => "true",
bus_hold => "false",
simulate_z_as => "z",
lpm_type => "stratixiii_io_ibuf"
)
port map(
i => dqs_pad,
ibar => dqsn_pad,
o => dqs_buf
);
dqs <= dqs_buf;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/ahbrom.vhd | 3 | 8961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/unisim/ddr_unisim.vhd | 1 | 12176 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: unisim_iddr_reg
-- File: unisim_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
entity unisim_iddr_reg is
generic (tech : integer := virtex4;arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of unisim_iddr_reg is
attribute BOX_TYPE : string;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preQ1, preQ2 : std_ulogic;
signal D_delay : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
Port map( Q1 => Q1, Q2 => Q2, C => C1, CE => CE,
D => D, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE")
Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
S6 : if (tech = spartan6) generate
noalign : if arch = 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "NONE")
Port map( Q0 => Q1, Q1 => preQ2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
align : if arch /= 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "C0")
Port map( Q0 => preQ1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q1 <= preQ1;
end if;
end process;
end generate;
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
-- CE and S inputs inactive for virtex 2
q1reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
Q1 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q1 <= D;
end if;
end process;
q2reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
preQ2 <= '0';
elsif C1'event and C1='0' then --Clock event - negedge
preQ2 <= D;
end if;
end process;
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
-- S6 : if tech = spartan6 generate
--
-- x0 : IFDDRRSE port map (
-- Q0 => Q1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
-- D => D, R => R, S => S);
--
-- end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.oddr2;
--use unisim.FDDRRSE;
--pragma translate_on
entity unisim_oddr_reg is
generic (tech : integer := virtex4; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR : component is "PRIMITIVE";
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "ASYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR2 : component is "PRIMITIVE";
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
FDDRRSE : component is "PRIMITIVE";
signal preD2 : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
port map(
Q => Q, C => C1, CE => CE, D1 => D1,
D2 => D2, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
, SRTYPE => "ASYNC")
port map(
Q => Q,
C => C1,
CE => CE,
D1 => D1,
D2 => preD2,
R => R,
S => S);
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component FDDRRSE
-- generic map( INIT => '0')
port map(
Q => Q,
D0 => D1,
D1 => preD2,
C0 => C1,
C1 => C2,
CE => CE,
R => R,
S => S);
end generate;
s6 : if tech = spartan6 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => Q,
C0 => C1,
C1 => C2,
CE => CE,
D0 => D1,
D1 => D2,
R => R,
S => S);
end generate;
end ;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
--use unisim.FDDRRSE;
--pragma translate_on
entity oddrv2 is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrv2 is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDDRRSE
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
entity oddrc3e is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrc3e is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/arith/mul32.vhd | 1 | 15127 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
library techmap;
use techmap.gencomp.all;
entity mul32 is
generic (
tech : integer := 0;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant MULRES : mul_regtype := (
acc => (others => '0'),
state => (others => '0'),
start => '0',
ready => '0',
nready => '0');
constant MACRES : mac_regtype := (
mmac => '0',
xmac => '0',
msigned => '0',
xsigned => '0');
signal arst : std_ulogic;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
signal vcc : std_logic;
begin
vcc <= '1';
arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else
rst when ASYNC_RESET else
'1';
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.nready := MULRES.nready; v.ready := MULRES.ready;
v.state := MULRES.state; v.start := MULRES.start;
end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m1616 : techmult generic map (tech, arch, 17, 17, pipe+1, pipe)
port map (ma(16 downto 0), mb(16 downto 0), clk, holdn, vcc, prod(33 downto 0));
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
if RESET_ALL and (rst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
elsif rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate asyncrregs;
mreg(49 downto 34) <= (others => '0');
prod(65 downto 34) <= (others => '0');
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m3208 : techmult generic map (tech, arch, 33, 8, 2, 1)
port map (ma(32 downto 0), mb(8 downto 0), clk, holdn, vcc, mreg(41 downto 0));
mm <= ('0', '0', '0', '0');
mreg(49 downto 42) <= (others => '0');
prod <= (others => '0');
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m3216 : techmult generic map (tech, arch, 33, 17, 2, 1)
port map (ma(32 downto 0), mb(16 downto 0), clk, holdn, vcc, mreg(49 downto 0));
mm <= ('0', '0', '0', '0');
prod <= (others => '0');
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m3232 : techmult generic map (tech, arch, 33, 33, pipe+1, pipe)
port map (ma(32 downto 0), mb(32 downto 0), clk, holdn, vcc, prod(65 downto 0));
mm <= ('0', '0', '0', '0');
mreg <= (others => '0');
end generate;
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then
if RESET_ALL then
rm <= MULRES;
else
rm.nready <= MULRES.nready; rm.ready <= MULRES.ready;
rm.state <= MULRES.state; rm.start <= MULRES.start;
end if;
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
rm <= MULRES;
elsif rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
end if;
end process;
end generate asyncrregs;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/adqsout.vhd | 3 | 5194 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad.vhd | 1 | 7616 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen) and slew = 0
else 'X' when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else 'Z';
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad port map (pad, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
x0 : dare_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en, o(j), cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en(j), o(j), cfgi);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/tech/simprim/vcomponents/vcomponents.vhd | 3 | 28 | package vcomponents is
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/boards/terasic-sockit/ddr3controller.vhd | 1 | 43576 | -- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v14.1%
-- GENERATION: XML
-- ddr3controller.vhd
-- Generated using ACDS version 14.1 186 at 2015.02.11.15:25:43
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3controller is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_reset_n : out std_logic; -- .mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- .readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(15 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rzqin : in std_logic := '0'; -- oct.rzqin
pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
pll_write_clk : out std_logic; -- .pll_write_clk
pll_locked : out std_logic; -- .pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- .pll_avl_clk
pll_config_clk : out std_logic; -- .pll_config_clk
pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
afi_phy_clk : out std_logic; -- .afi_phy_clk
pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
);
end entity ddr3controller;
architecture rtl of ddr3controller is
component ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3controller_0002;
begin
ddr3controller_inst : component ddr3controller_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_reset_n => mem_reset_n, -- .mem_reset_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
avl_ready => avl_ready, -- avl.waitrequest_n
avl_burstbegin => avl_burstbegin, -- .beginbursttransfer
avl_addr => avl_addr, -- .address
avl_rdata_valid => avl_rdata_valid, -- .readdatavalid
avl_rdata => avl_rdata, -- .readdata
avl_wdata => avl_wdata, -- .writedata
avl_be => avl_be, -- .byteenable
avl_read_req => avl_read_req, -- .read
avl_write_req => avl_write_req, -- .write
avl_size => avl_size, -- .burstcount
local_init_done => local_init_done, -- status.local_init_done
local_cal_success => local_cal_success, -- .local_cal_success
local_cal_fail => local_cal_fail, -- .local_cal_fail
oct_rzqin => oct_rzqin, -- oct.rzqin
pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk
pll_write_clk => pll_write_clk, -- .pll_write_clk
pll_locked => pll_locked, -- .pll_locked
pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk
pll_avl_clk => pll_avl_clk, -- .pll_avl_clk
pll_config_clk => pll_config_clk, -- .pll_config_clk
pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk
afi_phy_clk => afi_phy_clk, -- .afi_phy_clk
pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk
);
end architecture rtl; -- of ddr3controller
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr3_emif" version="14.1" >
-- Retrieval info: <generic name="MEM_VENDOR" value="JEDEC" />
-- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" />
-- Retrieval info: <generic name="RDIMM_CONFIG" value="0000000000000000" />
-- Retrieval info: <generic name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="15" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="32" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="DUPLICATE_AC" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="AP_MODE_EN" value="0" />
-- Retrieval info: <generic name="AP_MODE" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="OTF" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="Normal" />
-- Retrieval info: <generic name="MEM_PD" value="DLL off" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="RZQ/7" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="RZQ/6" />
-- Retrieval info: <generic name="MEM_RTT_WR" value="RZQ/4" />
-- Retrieval info: <generic name="MEM_WTCL" value="5" />
-- Retrieval info: <generic name="MEM_ATCL" value="Disabled" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="200" />
-- Retrieval info: <generic name="TIMING_TIH" value="275" />
-- Retrieval info: <generic name="TIMING_TDS" value="75" />
-- Retrieval info: <generic name="TIMING_TDH" value="150" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQH" value="0.38" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="400" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TQSH" value="0.38" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="500" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="4" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="300.0" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="4" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="50.0" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="13.2" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="13.2" />
-- Retrieval info: <generic name="RATE" value="Half" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="300.0" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="6" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="16" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="32" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-- Retrieval info: <generic name="TREFI" value="35100" />
-- Retrieval info: <generic name="REFRESH_INTERVAL" value="15000" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL_TEST" value="false" />
-- Retrieval info: <generic name="TRFC" value="350" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="false" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_VOLTAGE" value="1.5V DDR3" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: <generic name="AUTO_DEVICE_SPEEDGRADE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : ddr3controller.vho
-- RELATED_FILES: ddr3controller.vhd, ddr3controller_0002.v, ddr3controller_pll0.sv, ddr3controller_p0_clock_pair_generator.v, ddr3controller_p0_read_valid_selector.v, ddr3controller_p0_addr_cmd_datapath.v, ddr3controller_p0_reset.v, ddr3controller_p0_acv_ldc.v, ddr3controller_p0_memphy.sv, ddr3controller_p0_reset_sync.v, ddr3controller_p0_new_io_pads.v, ddr3controller_p0_fr_cycle_shifter.v, ddr3controller_p0_fr_cycle_extender.v, ddr3controller_p0_read_datapath.sv, ddr3controller_p0_write_datapath.v, ddr3controller_p0_core_shadow_registers.sv, ddr3controller_p0_simple_ddio_out.sv, ddr3controller_p0_phy_csr.sv, ddr3controller_p0_iss_probe.v, ddr3controller_p0_addr_cmd_pads.v, ddr3controller_p0_flop_mem.v, ddr3controller_p0.sv, ddr3controller_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev.sv, afi_mux_ddr3_ddrx.v, ddr3controller_s0.v, ddr3controller_s0_mm_interconnect_0_rsp_demux_003.sv, ddr3controller_s0_mm_interconnect_0_cmd_demux_001.sv, sequencer_phy_mgr.sv, ddr3controller_s0_mm_interconnect_0_router_001.sv, rw_manager_ram.v, rw_manager_inst_ROM_no_ifdef_params.v, ddr3controller_s0_mm_interconnect_0_rsp_mux_001.sv, rw_manager_inst_ROM_reg.v, ddr3controller_s0_mm_interconnect_0_router_005.sv, sequencer_scc_reg_file.v, altera_avalon_sc_fifo.v, rw_manager_bitcheck.v, rw_manager_lfsr36.v, sequencer_scc_sv_phase_decode.v, rw_manager_di_buffer_wrap.v, rw_manager_ac_ROM_reg.v, rw_manager_jumplogic.v, sequencer_reg_file.sv, rw_manager_ddr3.v, ddr3controller_s0_mm_interconnect_0.v, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, rw_manager_core.sv, rw_manager_di_buffer.v, rw_manager_dm_decoder.v, rw_manager_write_decoder.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, rw_manager_data_broadcast.v, sequencer_data_mgr.sv, altera_merlin_slave_translator.sv, ddr3controller_s0_mm_interconnect_0_rsp_mux.sv, ddr3controller_s0_mm_interconnect_0_cmd_mux_003.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, sequencer_scc_siii_phase_decode.v, ddr3controller_s0_irq_mapper.sv, rw_manager_pattern_fifo.v, ddr3controller_s0_mm_interconnect_0_router.sv, ddr3controller_s0_mm_interconnect_0_cmd_mux.sv, rw_manager_lfsr12.v, rw_manager_lfsr72.v, rw_manager_ram_csr.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_acv_phase_decode.v, sequencer_scc_siii_wrapper.sv, altera_merlin_master_translator.sv, rw_manager_read_datapath.v, sequencer_scc_sv_wrapper.sv, altera_mem_if_sequencer_rst.sv, ddr3controller_s0_mm_interconnect_0_cmd_demux.sv, rw_manager_generic.sv, ddr3controller_s0_mm_interconnect_0_router_002.sv, altera_merlin_slave_agent.sv, altera_merlin_master_agent.sv, rw_manager_datamux.v, rw_manager_ac_ROM_no_ifdef_params.v, sequencer_scc_mgr.sv, rw_manager_data_decoder.v, altera_merlin_arbitrator.sv, altera_merlin_burst_uncompressor.sv, ddr3controller_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_ddr3_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/ahbrom.vhd | 3 | 13745 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 976;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"821020C0";
when 16#00001# => romdata <= X"81884000";
when 16#00002# => romdata <= X"01000000";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"01000000";
when 16#00006# => romdata <= X"01000000";
when 16#00007# => romdata <= X"81980000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"01000000";
when 16#0000A# => romdata <= X"C0A00040";
when 16#0000B# => romdata <= X"01000000";
when 16#0000C# => romdata <= X"01000000";
when 16#0000D# => romdata <= X"11200000";
when 16#0000E# => romdata <= X"90122100";
when 16#0000F# => romdata <= X"821020A2";
when 16#00010# => romdata <= X"C222200C";
when 16#00011# => romdata <= X"82102003";
when 16#00012# => romdata <= X"C2222008";
when 16#00013# => romdata <= X"11000000";
when 16#00014# => romdata <= X"90122344";
when 16#00015# => romdata <= X"40000091";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"113FFC00";
when 16#00018# => romdata <= X"90122200";
when 16#00019# => romdata <= X"82102018";
when 16#0001A# => romdata <= X"C2222004";
when 16#0001B# => romdata <= X"9010202E";
when 16#0001C# => romdata <= X"40000080";
when 16#0001D# => romdata <= X"01000000";
when 16#0001E# => romdata <= X"113FFC00";
when 16#0001F# => romdata <= X"90122200";
when 16#00020# => romdata <= X"C2022008";
when 16#00021# => romdata <= X"80886004";
when 16#00022# => romdata <= X"02BFFFFC";
when 16#00023# => romdata <= X"01000000";
when 16#00024# => romdata <= X"9010202E";
when 16#00025# => romdata <= X"40000077";
when 16#00026# => romdata <= X"01000000";
when 16#00027# => romdata <= X"113FFC00";
when 16#00028# => romdata <= X"90122100";
when 16#00029# => romdata <= X"13208821";
when 16#0002A# => romdata <= X"92126091";
when 16#0002B# => romdata <= X"D2220000";
when 16#0002C# => romdata <= X"1300B140";
when 16#0002D# => romdata <= X"D2222008";
when 16#0002E# => romdata <= X"92102100";
when 16#0002F# => romdata <= X"D222200C";
when 16#00030# => romdata <= X"130011C0";
when 16#00031# => romdata <= X"92126004";
when 16#00032# => romdata <= X"D2222010";
when 16#00033# => romdata <= X"13208821";
when 16#00034# => romdata <= X"92126091";
when 16#00035# => romdata <= X"03000040";
when 16#00036# => romdata <= X"92124001";
when 16#00037# => romdata <= X"D2220000";
when 16#00038# => romdata <= X"9010202E";
when 16#00039# => romdata <= X"40000063";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"40000051";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"40000081";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"9010202E";
when 16#00040# => romdata <= X"4000005C";
when 16#00041# => romdata <= X"01000000";
when 16#00042# => romdata <= X"40000070";
when 16#00043# => romdata <= X"01000000";
when 16#00044# => romdata <= X"9010202E";
when 16#00045# => romdata <= X"40000057";
when 16#00046# => romdata <= X"01000000";
when 16#00047# => romdata <= X"A2100000";
when 16#00048# => romdata <= X"A4100000";
when 16#00049# => romdata <= X"A6103FFF";
when 16#0004A# => romdata <= X"40000074";
when 16#0004B# => romdata <= X"01000000";
when 16#0004C# => romdata <= X"80A460A0";
when 16#0004D# => romdata <= X"22800002";
when 16#0004E# => romdata <= X"90100000";
when 16#0004F# => romdata <= X"80A22000";
when 16#00050# => romdata <= X"1280000B";
when 16#00051# => romdata <= X"A404A001";
when 16#00052# => romdata <= X"80A4A010";
when 16#00053# => romdata <= X"24800008";
when 16#00054# => romdata <= X"A4100000";
when 16#00055# => romdata <= X"80A4FFFF";
when 16#00056# => romdata <= X"32800005";
when 16#00057# => romdata <= X"A4100000";
when 16#00058# => romdata <= X"A534A001";
when 16#00059# => romdata <= X"A6244012";
when 16#0005A# => romdata <= X"A4100000";
when 16#0005B# => romdata <= X"4000003D";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"80A460A0";
when 16#0005E# => romdata <= X"A2046001";
when 16#0005F# => romdata <= X"12BFFFEB";
when 16#00060# => romdata <= X"01000000";
when 16#00061# => romdata <= X"80A4FFFF";
when 16#00062# => romdata <= X"02800022";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"11000000";
when 16#00065# => romdata <= X"9012234F";
when 16#00066# => romdata <= X"40000040";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"9134E004";
when 16#00069# => romdata <= X"40000033";
when 16#0006A# => romdata <= X"90022030";
when 16#0006B# => romdata <= X"900CE00F";
when 16#0006C# => romdata <= X"80A2200A";
when 16#0006D# => romdata <= X"90022030";
when 16#0006E# => romdata <= X"36800002";
when 16#0006F# => romdata <= X"90022027";
when 16#00070# => romdata <= X"4000002C";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"4000001A";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"4000004A";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"80A4E000";
when 16#00077# => romdata <= X"02800006";
when 16#00078# => romdata <= X"01000000";
when 16#00079# => romdata <= X"4000001F";
when 16#0007A# => romdata <= X"01000000";
when 16#0007B# => romdata <= X"10BFFFF9";
when 16#0007C# => romdata <= X"A624E001";
when 16#0007D# => romdata <= X"11000000";
when 16#0007E# => romdata <= X"90122360";
when 16#0007F# => romdata <= X"40000027";
when 16#00080# => romdata <= X"01000000";
when 16#00081# => romdata <= X"03380800";
when 16#00082# => romdata <= X"81C04000";
when 16#00083# => romdata <= X"01000000";
when 16#00084# => romdata <= X"11000000";
when 16#00085# => romdata <= X"90122368";
when 16#00086# => romdata <= X"40000020";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"40000004";
when 16#00089# => romdata <= X"01000000";
when 16#0008A# => romdata <= X"10BFFFF7";
when 16#0008B# => romdata <= X"01000000";
when 16#0008C# => romdata <= X"03200000";
when 16#0008D# => romdata <= X"113FFC00";
when 16#0008E# => romdata <= X"90122100";
when 16#0008F# => romdata <= X"1300B140";
when 16#00090# => romdata <= X"92124001";
when 16#00091# => romdata <= X"D2222008";
when 16#00092# => romdata <= X"82102014";
when 16#00093# => romdata <= X"82A06001";
when 16#00094# => romdata <= X"12BFFFFF";
when 16#00095# => romdata <= X"01000000";
when 16#00096# => romdata <= X"81C3E008";
when 16#00097# => romdata <= X"01000000";
when 16#00098# => romdata <= X"0300003F";
when 16#00099# => romdata <= X"821063FF";
when 16#0009A# => romdata <= X"10BFFFF3";
when 16#0009B# => romdata <= X"01000000";
when 16#0009C# => romdata <= X"03200000";
when 16#0009D# => romdata <= X"82106100";
when 16#0009E# => romdata <= X"C2006004";
when 16#0009F# => romdata <= X"80886004";
when 16#000A0# => romdata <= X"02BFFFFC";
when 16#000A1# => romdata <= X"03200000";
when 16#000A2# => romdata <= X"82106100";
when 16#000A3# => romdata <= X"D0204000";
when 16#000A4# => romdata <= X"81C3E008";
when 16#000A5# => romdata <= X"01000000";
when 16#000A6# => romdata <= X"9A10000F";
when 16#000A7# => romdata <= X"92100008";
when 16#000A8# => romdata <= X"D00A4000";
when 16#000A9# => romdata <= X"80A20000";
when 16#000AA# => romdata <= X"02800006";
when 16#000AB# => romdata <= X"92026001";
when 16#000AC# => romdata <= X"7FFFFFF0";
when 16#000AD# => romdata <= X"01000000";
when 16#000AE# => romdata <= X"10BFFFFA";
when 16#000AF# => romdata <= X"01000000";
when 16#000B0# => romdata <= X"81C36008";
when 16#000B1# => romdata <= X"01000000";
when 16#000B2# => romdata <= X"11100000";
when 16#000B3# => romdata <= X"13000000";
when 16#000B4# => romdata <= X"92126374";
when 16#000B5# => romdata <= X"94102010";
when 16#000B6# => romdata <= X"C2024000";
when 16#000B7# => romdata <= X"92026004";
when 16#000B8# => romdata <= X"C2220000";
when 16#000B9# => romdata <= X"94A2A001";
when 16#000BA# => romdata <= X"12BFFFFC";
when 16#000BB# => romdata <= X"90022004";
when 16#000BC# => romdata <= X"81C3E008";
when 16#000BD# => romdata <= X"01000000";
when 16#000BE# => romdata <= X"11100000";
when 16#000BF# => romdata <= X"13000000";
when 16#000C0# => romdata <= X"92126374";
when 16#000C1# => romdata <= X"D41A0000";
when 16#000C2# => romdata <= X"90022008";
when 16#000C3# => romdata <= X"C2024000";
when 16#000C4# => romdata <= X"80A0400A";
when 16#000C5# => romdata <= X"1280000A";
when 16#000C6# => romdata <= X"C2026004";
when 16#000C7# => romdata <= X"80A0400B";
when 16#000C8# => romdata <= X"12800007";
when 16#000C9# => romdata <= X"92026008";
when 16#000CA# => romdata <= X"808A2040";
when 16#000CB# => romdata <= X"02BFFFF6";
when 16#000CC# => romdata <= X"01000000";
when 16#000CD# => romdata <= X"81C3E008";
when 16#000CE# => romdata <= X"90102001";
when 16#000CF# => romdata <= X"81C3E008";
when 16#000D0# => romdata <= X"90102000";
when 16#000D1# => romdata <= X"0D0A4148";
when 16#000D2# => romdata <= X"42524F4D";
when 16#000D3# => romdata <= X"3A200020";
when 16#000D4# => romdata <= X"64647232";
when 16#000D5# => romdata <= X"5F64656C";
when 16#000D6# => romdata <= X"6179203D";
when 16#000D7# => romdata <= X"20307800";
when 16#000D8# => romdata <= X"2C204F4B";
when 16#000D9# => romdata <= X"2E0D0A00";
when 16#000DA# => romdata <= X"4641494C";
when 16#000DB# => romdata <= X"45440D0A";
when 16#000DC# => romdata <= X"00000000";
when 16#000DD# => romdata <= X"12345678";
when 16#000DE# => romdata <= X"F0C3A596";
when 16#000DF# => romdata <= X"6789ABCD";
when 16#000E0# => romdata <= X"A6F1590E";
when 16#000E1# => romdata <= X"EDCBA987";
when 16#000E2# => romdata <= X"0F3C5A69";
when 16#000E3# => romdata <= X"98765432";
when 16#000E4# => romdata <= X"590EA6F1";
when 16#000E5# => romdata <= X"FFFF0000";
when 16#000E6# => romdata <= X"0000FFFF";
when 16#000E7# => romdata <= X"5AC3FFFF";
when 16#000E8# => romdata <= X"0000A53C";
when 16#000E9# => romdata <= X"01510882";
when 16#000EA# => romdata <= X"F4D908FD";
when 16#000EB# => romdata <= X"9B6F7A46";
when 16#000EC# => romdata <= X"C721271D";
when 16#000ED# => romdata <= X"00000000";
when 16#000EE# => romdata <= X"00000000";
when 16#000EF# => romdata <= X"00000000";
when 16#000F0# => romdata <= X"00000000";
when 16#000F1# => romdata <= X"00000000";
when 16#000F2# => romdata <= X"00000000";
when 16#000F3# => romdata <= X"00000000";
when 16#000F4# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/misc.vhd | 1 | 51907 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
latchv : std_logic_vector(NAHBIRQ-1 downto 0);
latchd : std_logic_vector(NAHBIRQ-1 downto 0);
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0', (others => '0'), (others => '0'));
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1);
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0;
iflagreg : integer range 0 to 1:= 0;
bpmode : integer range 0 to 1 := 0;
inpen : integer range 0 to 1 := 0;
doutresv : integer := 0;
dirresv : integer := 0;
bpresv : integer := 0;
inpresv : integer := 0;
pulse : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0;
extrst: integer := 0;
rdataen: integer := 0;
wproten: integer := 0;
partrstmsk: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0);
resval : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
rdata : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
wprot : in std_logic_vector(nregs-1 downto 0) := (others => '0');
partrst : in std_ulogic := '1'
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component grclkgatex
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
component ahbpl is
generic (
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#;
wrretry: integer range 0 to 2 := 2
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Bus-side slave inputs
bi_hready: in std_ulogic;
bi_hsel: in std_ulogic;
bi_htrans: in std_logic_vector(1 downto 0);
bi_hsize: in std_logic_vector(2 downto 0);
bi_hburst: in std_logic_vector(2 downto 0);
bi_hwrite: in std_ulogic;
bi_haddr: in std_logic_vector(31 downto 0);
bi_hwdata: in std_logic_vector(ahbbits-1 downto 0);
bi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
bi_hmaster: in std_logic_vector(3 downto 0);
bi_hprot: in std_logic_vector(3 downto 0);
bi_hmastlock: in std_ulogic;
-- Bus-side slave outputs
bo_hready: out std_ulogic;
bo_hresp : out std_logic_vector(1 downto 0);
bo_hrdata: out std_logic_vector(ahbbits-1 downto 0);
-- Slave-side slave inputs
si_hready: out std_ulogic;
si_htrans: out std_logic_vector(1 downto 0);
si_hsize: out std_logic_vector(2 downto 0);
si_hburst: out std_logic_vector(2 downto 0);
si_hwrite: out std_ulogic;
si_haddr: out std_logic_vector(31 downto 0);
si_hwdata: out std_logic_vector(ahbbits-1 downto 0);
si_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
si_hmaster: out std_logic_vector(3 downto 0);
si_hprot : out std_logic_vector(3 downto 0);
si_hmastlock: out std_ulogic;
-- Slave-side slave outputs
so_hready: in std_ulogic;
so_hresp: in std_logic_vector(1 downto 0);
so_hrdata: in std_logic_vector(ahbbits-1 downto 0);
-- For use in master mode
mi_hgrant: in std_ulogic;
mo_hbusreq: out std_ulogic
);
end component;
component ahbpls is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
bi: in ahb_slv_in_type;
bo: out ahb_slv_out_type;
si: out ahb_slv_in_type;
so: in ahb_slv_out_type
);
end component;
component ahbplm is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
mi: out ahb_mst_in_type;
mo: in ahb_mst_out_type;
bi: in ahb_mst_in_type;
bo: out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/examples/vams/vhdl/basic-vhdl/transitest_arc.vhdl | 15 | 1201 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
BJT1 : ENTITY BJT_transistor_simple(simple_arc)
GENERIC MAP (
NEL => 5.0)
PORT MAP ( Base => unnamed_net2,
Collector => unnamed_net5,
Emitter => unnamed_net1);
VS_base : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 1.0,
k => 150.0)
PORT MAP ( LT => unnamed_net3,
RT => unnamed_net1);
VS_collector : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 2.0,
offset => 10.2,
k => 100.0)
PORT MAP ( LT => unnamed_net4,
RT => unnamed_net1);
RES_collecter : ENTITY RESISTOR
GENERIC MAP (
r => 60.0)
PORT MAP ( RT => unnamed_net4,
LT => unnamed_net5);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => 10000.0)
PORT MAP ( RT => unnamed_net2,
LT => unnamed_net3);
GND : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net1);
END ARCHITECTURE transistor_test;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/svga2ch7301c.vhd | 3 | 10231 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/tech/virage/simprims/virage_simprims.vhd | 1 | 18571 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4/leon3mp.vhd | 1 | 26816 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
--RamWait : in std_ulogic;
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyClk50Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(1 downto 0);
PhyTxEn : out std_ulogic;
PhyRxd : in std_logic_vector(1 downto 0);
PhyRxEr : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 4) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 23)
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (RamWE, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#b00#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => 0, readcmd => 16#0B#, dummybyte => 1, dualoutput => 0,
scaler => 1, altscaler => 2)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--QspiDB(3) <= '1'; QspiDB(2) <= '1';
spi_QspiDB_2_pad : outpad generic map (tech => padtech)
port map (QspiDB(2), '1');
spi_QspiDB_3_pad : outpad generic map (tech => padtech)
port map (QspiDB(3), '1');
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (PhyClk50Mhz, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (PhyRxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (PhyTxd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/can/can_rd.vhd | 1 | 6744 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd | 2 | 23812 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml50x is
constant BANK_WIDTH : integer := 2; -- # of memory bank addr bits.
constant CKE_WIDTH : integer := 2; -- # of memory clock enable outputs.
constant CLK_WIDTH : integer := 2; -- # of clock outputs.
constant COL_WIDTH : integer := 10; -- # of memory column bits.
constant CS_NUM : integer := 1; --2; -- # of separate memory chip selects.
constant CS_WIDTH : integer := 1; --2; -- # of total memory chip selects.
constant CS_BITS : integer := 0; --1; -- set to log2(CS_NUM) (rounded up).
constant DM_WIDTH : integer := 8; -- # of data mask bits.
constant DQ_WIDTH : integer := 64; -- # of data width.
constant DQ_PER_DQS : integer := 8; -- # of DQ data bits per strobe.
constant DQS_WIDTH : integer := 8; -- # of DQS strobes.
constant DQ_BITS : integer := 6; -- set to log2(DQS_WIDTH*DQ_PER_DQS).
constant DQS_BITS : integer := 3; -- set to log2(DQS_WIDTH).
constant ODT_WIDTH : integer := 1; -- # of memory on-die term enables.
constant ROW_WIDTH : integer := 13; -- # of memory row and # of addr bits.
constant APPDATA_WIDTH : integer := 128; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 31; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#F00#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component mig_36_1
generic(
BANK_WIDTH : integer := 2;
-- # of memory bank addr bits.
CKE_WIDTH : integer := 1;
-- # of memory clock enable outputs.
CLK_WIDTH : integer := 2;
-- # of clock outputs.
COL_WIDTH : integer := 10;
-- # of memory column bits.
CS_NUM : integer := 1;
-- # of separate memory chip selects.
CS_WIDTH : integer := 1;
-- # of total memory chip selects.
CS_BITS : integer := 0;
-- set to log2(CS_NUM) (rounded up).
DM_WIDTH : integer := 8;
-- # of data mask bits.
DQ_WIDTH : integer := 64;
-- # of data width.
DQ_PER_DQS : integer := 8;
-- # of DQ data bits per strobe.
DQS_WIDTH : integer := 8;
-- # of DQS strobes.
DQ_BITS : integer := 6;
-- set to log2(DQS_WIDTH*DQ_PER_DQS).
DQS_BITS : integer := 3;
-- set to log2(DQS_WIDTH).
ODT_WIDTH : integer := 1;
-- # of memory on-die term enables.
ROW_WIDTH : integer := 13;
-- # of memory row and # of addr bits.
ADDITIVE_LAT : integer := 0;
-- additive write latency.
BURST_LEN : integer := 4;
-- burst length (in double words).
BURST_TYPE : integer := 0;
-- burst type (=0 seq; =1 interleaved).
CAS_LAT : integer := 3;
-- CAS latency.
ECC_ENABLE : integer := 0;
-- enable ECC (=1 enable).
APPDATA_WIDTH : integer := 128;
-- # of usr read/write data bus bits.
MULTI_BANK_EN : integer := 1;
-- Keeps multiple banks open. (= 1 enable).
TWO_T_TIME_EN : integer := 1;
-- 2t timing for unbuffered dimms.
ODT_TYPE : integer := 1;
-- ODT (=0(none),=1(75),=2(150),=3(50)).
REDUCE_DRV : integer := 0;
-- reduced strength mem I/O (=1 yes).
REG_ENABLE : integer := 0;
-- registered addr/ctrl (=1 yes).
TREFI_NS : integer := 7800;
-- auto refresh interval (ns).
TRAS : integer := 40000;
-- active->precharge delay.
TRCD : integer := 15000;
-- active->read/write delay.
TRFC : integer := 105000;
-- refresh->refresh, refresh->active delay.
TRP : integer := 15000;
-- precharge->command delay.
TRTP : integer := 7500;
-- read->precharge delay.
TWR : integer := 15000;
-- used to determine write->precharge.
TWTR : integer := 10000;
-- write->read delay.
HIGH_PERFORMANCE_MODE : boolean := TRUE;
-- # = TRUE, the IODELAY performance mode is set
-- to high.
-- # = FALSE, the IODELAY performance mode is set
-- to low.
SIM_ONLY : integer := 0;
-- = 1 to skip SDRAM power up delay.
DEBUG_EN : integer := 0;
-- Enable debug signals/controls.
-- When this parameter is changed from 0 to 1,
-- make sure to uncomment the coregen commands
-- in ise_flow.bat or create_ise.bat files in
-- par folder.
CLK_PERIOD : integer := 5000;
-- Core/Memory clock period (in ps).
DLL_FREQ_MODE : string := "HIGH";
-- DCM Frequency range.
CLK_TYPE : string := "SINGLE_ENDED";
-- # = "DIFFERENTIAL " ->; Differential input clocks ,
-- # = "SINGLE_ENDED" -> Single ended input clocks.
NOCLK200 : boolean := FALSE;
-- clk200 enable and disable
RST_ACT_LOW : integer := 1
-- =1 for active low reset, =0 for active high.
);
port(
ddr2_dq : inout std_logic_vector((DQ_WIDTH-1) downto 0);
ddr2_a : out std_logic_vector((ROW_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_WIDTH-1) downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector((CS_WIDTH-1) downto 0);
ddr2_odt : out std_logic_vector((ODT_WIDTH-1) downto 0);
ddr2_cke : out std_logic_vector((CKE_WIDTH-1) downto 0);
ddr2_dm : out std_logic_vector((DM_WIDTH-1) downto 0);
sys_clk : in std_logic;
idly_clk_200 : in std_logic;
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
rst0_tb : out std_logic;
clk0_tb : out std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_data : in std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_mask_data : in std_logic_vector((APPDATA_WIDTH/8-1) downto 0);
ddr2_dqs : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0)
);
end component ;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml50x.all;
entity ahb2mig_ml50x is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml50x is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(63 downto 0) & rdata(127 downto 64);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "01" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "10" => va.hrdata(31 downto 0) := rdata(127 downto 96);
when others => va.hrdata(31 downto 0) := rdata(95 downto 64);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
migi.app_addr <= "00000" & ra.acc.haddr(28 downto 5) & "00";
ddr_ctrl : process(rst_ddr, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask(15 downto 0) := ra.write(2) & ra.write(3) & ra.write(0) & ra.write(1);
app_wdf_data := (others => '0');
app_wdf_data(127 downto 0) := ra.hwdata(2) & ra.hwdata(3) & ra.hwdata(0) & ra.hwdata(1);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if (startsd = '1') and (migo.app_af_afull = '0') then
if ra.acc.hwrite = '0' then
v.dstate := dread; app_en := '1';
elsif migo.app_wdf_afull = '0' then
v.dstate := dwrite; app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 0) := migo.app_rd_data(127 downto 0);
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(255 downto 128) := migo.app_rd_data(127 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
app_wdf_mask(15 downto 0) := ra.write(6) & ra.write(7) & ra.write(4) & ra.write(5);
app_wdf_data(127 downto 0) := ra.hwdata(6) & ra.hwdata(7) & ra.hwdata(4) & ra.hwdata(5);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/syncrambw.vhd | 1 | 4735 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncrambw
-- File: syncrambw.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Synchronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncrambw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncrambw is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2*dbits/8;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
signal xenable, xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
sbw : if has_srambw(tech) = 1 generate
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_be generic map (abits, dbits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncrambw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nosbw : if has_srambw(tech) = 0 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
dataout <= dataoutx;
end generate;
custominx <= (others => '0');
nocust: if has_srambw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/work/debug/cpu_disas.vhd | 1 | 4256 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Module for disassembly
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity gaisler_cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of gaisler_cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
| gpl-2.0 |
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