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elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/clkinv.vhd | 1 | 2035 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
rhs : if (tech = rhs65) generate
x0 : clkinv_rhs65 port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-115/leon3mp.vhd | 1 | 16967 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/ahbrom.vhd | 3 | 7818 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 432;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18C000";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"87444000";
when 16#00049# => romdata <= X"8730E01C";
when 16#0004A# => romdata <= X"8688E00F";
when 16#0004B# => romdata <= X"1280000A";
when 16#0004C# => romdata <= X"03200000";
when 16#0004D# => romdata <= X"05040E00";
when 16#0004E# => romdata <= X"8410A033";
when 16#0004F# => romdata <= X"C4204000";
when 16#00050# => romdata <= X"0539AE1B";
when 16#00051# => romdata <= X"8410A220";
when 16#00052# => romdata <= X"C4206004";
when 16#00053# => romdata <= X"050003FC";
when 16#00054# => romdata <= X"C4206008";
when 16#00055# => romdata <= X"05000008";
when 16#00056# => romdata <= X"82100000";
when 16#00057# => romdata <= X"80A0E000";
when 16#00058# => romdata <= X"02800005";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"82004002";
when 16#0005B# => romdata <= X"10BFFFFC";
when 16#0005C# => romdata <= X"8620E001";
when 16#0005D# => romdata <= X"3D1003FF";
when 16#0005E# => romdata <= X"BC17A3E0";
when 16#0005F# => romdata <= X"BC278001";
when 16#00060# => romdata <= X"9C27A060";
when 16#00061# => romdata <= X"03100000";
when 16#00062# => romdata <= X"81C04000";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"01000000";
when 16#00065# => romdata <= X"01000000";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"00000000";
when 16#00069# => romdata <= X"00000000";
when 16#0006A# => romdata <= X"00000000";
when 16#0006B# => romdata <= X"00000000";
when 16#0006C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbrom.in.vhd | 6 | 316 | -- AHB ROM
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/ahbrom.vhd | 28 | 6162 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xup/ahbrom.vhd | 3 | 6755 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"05000008";
when 16#00049# => romdata <= X"82100000";
when 16#0004A# => romdata <= X"3D1003FF";
when 16#0004B# => romdata <= X"BC17A3E0";
when 16#0004C# => romdata <= X"BC278001";
when 16#0004D# => romdata <= X"9C27A060";
when 16#0004E# => romdata <= X"03100000";
when 16#0004F# => romdata <= X"81C04000";
when 16#00050# => romdata <= X"01000000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml40x/leon3mp.vhd | 1 | 28065 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
sysace_clk_in : in std_ulogic; -- System ACE clock
plb_error : out std_logic; -- IU error mode
opb_error : out std_logic; -- DSU active
flash_a23 : out std_ulogic;
sram_flash_addr : out std_logic_vector(22 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(26 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_int_n : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_preserve of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo2.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(21) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 2));
addr23_pad : outpad generic map (tech => padtech)
port map (flash_a23, gnd(0));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
-- phyiconf => 1 = no diff pads for DDR clock pairs
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 27)
port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
gpioi.din(26 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (phy_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbram.vhd | 1 | 9212 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-sdr/smc_mctrl.vhd | 11 | 33398 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity smc_mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_logic; -- for smsc eth
eth_readn : out std_logic; -- for smsc eth
eth_writen: out std_logic; -- for smsc eth
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc eth
);
end;
architecture rtl of smc_mctrl is
constant REVISION : integer := 0;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
eth_aen : std_logic; -- for smsc eth
eth_readn : std_logic; -- for smsc eth
eth_writen : std_logic; -- for smsc eth
eth_nbe : std_logic_vector(3 downto 0);-- for smsc eth
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1') or (((sdmo.aload and r.hsel) = '1') and SDRAMEN))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then v.writedata := writedata;
else
v.writedata(31 downto 16) := writedata(31 downto 16);
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or (r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 19) := sdmo.prdata(31 downto 19);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
v.hresp := sdmo.hresp;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- for smc lan chip ********************************************
if (r.iosn(0) = '1' and v.iosn(0) = '0') then
v.eth_aen := '0';
v.eth_nbe := v.wrn and not (r.read&r.read&r.read&r.read);
elsif (r.iosn(0) = '1' and r.eth_aen = '0') then
v.eth_aen := '1';
v.eth_nbe := v.wrn;
end if;
if (r.eth_aen = '0' and v.iosn(0) = '0' and r.read = '1') then
v.eth_readn := '0';
else
v.eth_readn := '1';
end if;
if (r.eth_aen = '0' and v.iosn(0) = '0' and r.writen = '0') then
v.eth_writen := '0';
else
v.eth_writen := '1';
end if;
-- *************************************************************
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
v.eth_aen := '1'; -- for smsc eth
v.eth_readn := '1'; -- for smsc eth
v.eth_writen := '1'; -- for smsc eth
v.eth_nbe := (others => '1'); -- for smsc eth
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.sa <= r.sa;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rsbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
-- for smsc eth
eth_aen <= r.eth_aen;
eth_readn <= r.eth_readn;
eth_writen <= r.eth_writen;
eth_nbe <= r.eth_nbe;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => sdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11"; sdmo.prdata <= (others => '0');
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd | 1 | 2038 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clk50;
when "10" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/tech/dware/simprims/DW_Foundation_comp_arith.vhd | 4 | 2072 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/pci/grpci2/grpci2_phy.vhd | 1 | 25488 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2_phy
-- File: grpci2_phy.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Logic controlled by the PCI control signals in the GRPCI2 core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config.all;
use grlib.config_types.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture rtl of grpci2_phy is
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
type phy_m_reg_type is record
state : pci_master_state_type;
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
last : std_logic_vector(1 downto 0);
hold : std_logic_vector(1 downto 0);
term : std_logic_vector(1 downto 0);
end record;
type phy_t_reg_type is record
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
hold : std_logic_vector(0 downto 0);
stop : std_logic;
abort : std_logic;
diswithout : std_logic;
addr_perr : std_logic;
end record;
type phy_reg_type is record
po : pci_reg_out_type;
m : phy_m_reg_type;
t : phy_t_reg_type;
end record;
signal pr, prin : phy_reg_type;
signal pi, piin, piin_buf : pci_in_type; -- Registered PCI signals.
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal xarst : std_ulogic;
signal pcisynrst : std_ulogic;
attribute sync_set_reset of pcisynrst : signal is "true";
attribute syn_keep : boolean;
attribute syn_keep of poin_keep : signal is true;
begin
phycomb : process(pcii, pr, pi, po, phyi, pcisynrst, rinaden)
variable pv : phy_reg_type;
variable pci : pci_in_type;
begin
-- defaults ---------------------------------------------------------------------
pv := pr;
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.lock := '1'; pv.po.devsel := '1';
pv.po.serr := '1';
pv.po.devselen := oeoff; pv.po.trdyen := oeoff; pv.po.stopen := oeoff;
pv.po.aden := (others => oeoff); pv.po.cbeen := (others => oeoff);
pv.po.frameen := oeoff; pv.po.irdyen := oeoff;
pv.po.perren := oeoff; pv.po.serren := oeoff;
pv.po.reqen := oeon; -- Always on (point-to-point signal, tri-state during reset)
-- PCI input mux ----------------------------------------------------------------
pci := pcii;
if bypass /= 0 then
if pr.po.aden(0) = oeon then pci.ad := pr.po.ad; end if;
if pr.po.cbeen(0) = oeon then pci.cbe := pr.po.cbe; end if;
if pr.po.frameen = oeon then pci.frame := pr.po.frame; end if;
if pr.po.irdyen = oeon then pci.irdy := pr.po.irdy; end if;
if pr.po.trdyen = oeon then pci.trdy := pr.po.trdy; end if;
if pr.po.stopen = oeon then pci.stop := pr.po.stop; end if;
if pr.po.paren = oeon then pci.par := pr.po.par; end if;
if pr.po.devselen = oeon then pci.devsel := pr.po.devsel; end if;
if pr.po.perren = oeon then pci.perr := pr.po.perr; end if;
if pr.po.serren = oeon then pci.serr := pr.po.serren; end if;
end if;
-- Master -----------------------------------------------------------------------
pv.m.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if ((not (pr.po.irdy or pci.trdy)) and pr.m.pi_irdy_or_trdy) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi + 1;
case pr.m.cfi is
when 0 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 2;
when others => pv.m.cfi := 0;
end case;
end if;
elsif ((pr.po.irdy or pci.trdy) and (not pr.m.pi_irdy_or_trdy)) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi - 1;
case pr.m.cfi is
when 2 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 0;
when others => pv.m.cfi := 0;
end case;
end if;
end if;
-- PCI state machine
case pr.m.state is
when pm_idle =>
if pci.gnt = '0' and (pci.frame and pci.irdy) = '1' then
if phyi.m_request = '1' then pv.m.state := pm_addr;
else pv.m.state := pm_dr_bus; end if;
end if;
pv.m.cfi := 0;
when pm_addr =>
pv.m.state := pm_m_data;
when pm_m_data =>
if pr.po.frame = '0' or (pr.po.frame and pci.trdy and pci.stop and not phyi.m_mabort) = '1' then
pv.m.state := pm_m_data;
elsif (pr.po.frame and (phyi.m_mabort or not pci.stop)) = '1' then
pv.m.state := pm_s_tar;
else
pv.m.state := pm_turn_ar;
end if;
when pm_turn_ar =>
if pci.gnt = '0' then
if phyi.m_request = '1' then pv.m.state := pm_addr; -- remove if no back-to-back
else pv.m.state := pm_dr_bus; end if;
else
pv.m.state := pm_idle;
end if;
when pm_s_tar =>
if pci.gnt = '0' then pv.m.state := pm_dr_bus;
else pv.m.state := pm_idle; end if;
when pm_dr_bus =>
if pci.gnt = '1' then pv.m.state := pm_idle;
elsif phyi.m_request = '1' then pv.m.state := pm_addr; end if;
pv.m.cfi := 0;
when others =>
end case;
if phyi.pr_m_fstate = pmf_fifo then
if (phyi.pv_m_cfifo(0).valid = '1' and phyi.pv_m_cfifo(1).valid = '1' and phyi.pv_m_cfifo(2).valid = '1')
or (phyi.pv_m_cfifo(0).valid = '1' and phyi.pr_m_done_fifo = '1' and not (phyi.pv_m_cfifo(1).valid = '0' and phyi.pv_m_cfifo(2).valid = '1')) then
pv.m.hold(0) := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar))
or (phyi.pr_m_abort(0)) = '1' then
if phyi.pr_m_cfifo(pv.m.cfi).last = '1' and pr.m.last(0) = '0' then pv.m.last(0) := '1'; end if; -- This is the last data phase
pv.m.last(1) := pr.m.last(0);
if phyi.pr_m_done_fifo = '1' and phyi.pr_m_cfifo(pv.m.cfi).valid = '0' then pv.m.last(1) := '1'; end if; -- This is the last data phase
pv.m.hold(1) := pr.m.hold(0);
end if;
if (pr.m.state = pm_m_data or pr.m.state = pm_addr) and phyi.pr_m_cfifo(pv.m.cfi).hold = '1' then pv.m.hold(0) := '1'; end if; -- Transfer not done but no avalible fifo => deassert IRDY#
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.last := (others => '0');
pv.m.hold(0) := '0';
end if;
if phyi.pr_m_cfifo(0).last = '1' and phyi.pr_m_first(0) = '1' and pr.m.state = pm_addr and (phyi.pr_m_cbe_cmd = MEM_WRITE or phyi.pr_m_cbe_cmd = CONF_WRITE or phyi.pr_m_cbe_cmd = IO_WRITE) then pv.m.last := "11"; end if; -- Single data phase
if phyi.pr_m_first(1) = '1' and pr.m.state = pm_m_data and phyi.pr_m_cfifo(pv.m.cfi).last = '1' then pv.m.last(0) := '1'; end if; -- This is the last data phase
end if;
if phyi.pr_m_fstate = pmf_idle then
pv.m.last := (others => '0');
pv.m.hold := (others => '0');
end if;
-- PCI master latency timer timeout
pv.m.term := phyi.pv_m_term;
if pci.gnt = '1' then
if phyi.pr_m_ltimer = x"00" and pr.m.state = pm_m_data and phyi.pr_m_burst = '1' and phyi.pr_m_fstate /= pmf_idle then
pv.m.term(0) := '1';
end if;
end if;
-- FRAME#
if (pci.frame and pci.irdy and not pci.gnt and phyi.m_request) = '1' -- Address phase
or (pr.po.frame = '0' and phyi.m_mabort = '0' -- Not Master abort
and (pr.po.irdy or pci.stop) = '1' -- Not Disconnect
and ((phyi.pr_m_first(0) or not (pr.po.irdy or pci.trdy)) and (phyi.pr_m_cfifo(pv.m.cfi).last or pv.m.term(0))) = '0') then -- Not last data phase
pv.po.frame := '0';
end if;
-- IRDY#
if (pr.po.frame = '0' and phyi.m_mabort = '0' and (pr.m.hold(0) = '0' or (not pr.po.irdy and (pci.trdy and pci.stop)) = '1')) -- Access ongoing, not Master abort, not hold (no data available)
or (pr.po.frame and not phyi.m_mabort and not pr.po.irdy and (pci.trdy and pci.stop)) = '1' then -- Last data phase, not Master abort (if first access, can get master abort)
pv.po.irdy := '0';
end if;
-- Output enable ctrl signals
if (pci.frame and pci.irdy and not pci.gnt) = '1' -- Address phase
or pr.po.frame = '0' -- Access ongoing
or (not pr.po.irdy and (pci.stop and pci.trdy)) = '1' then -- Last data phase
pv.po.frameen := oeon;
pv.po.cbeen := (others => oeon);
end if;
pv.po.irdyen := pr.po.frameen;
-- REQ#
if (phyi.m_request) = '1' and (phyi.m_mabort or phyi.pr_m_abort(0)) = '0' then
pv.po.req := '0';
end if;
-- Output enable req
--pv.po.reqen := oeon; -- always on if not in reset
-- CBE#
if pr.po.irdy = '0' or pr.po.req = '0' or phyi.m_request = '1' then
if pr.m.state /= pm_idle and (pr.m.state /= pm_dr_bus) then pv.po.cbe := phyi.pr_m_cbe_data;
else pv.po.cbe := phyi.pr_m_cbe_cmd; end if;
else
pv.po.cbe := (others => '0');
end if;
-- Target -----------------------------------------------------------------------
pv.t.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if (pr.t.pi_irdy_or_trdy and (not (pci.irdy or pr.po.trdy))) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi + 1;
case pr.t.cfi is
when 0 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 2;
when others => pv.t.cfi := 0;
end case;
end if;
elsif ((not pr.t.pi_irdy_or_trdy) and (pci.irdy or pr.po.trdy)) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi - 1;
case pr.t.cfi is
when 2 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 0;
when others => pv.t.cfi := 0;
end case;
end if;
end if;
pv.t.hold(0) := (phyi.pr_t_cfifo(pv.t.cfi).hold or pr.t.hold(0) or phyi.pv_t_hold_write) and phyi.pv_t_hold_reset;
pv.t.stop := (phyi.pr_t_cfifo(pv.t.cfi).stlast or pr.t.stop) and phyi.pv_t_hold_reset;
if phyi.pr_t_state = pt_s_data and phyi.pr_t_cfifo(pv.t.cfi).err = '1' and (phyi.pr_t_stoped = '0' or pr.t.abort = '1') and phyi.t_retry = '0' then pv.t.abort := '1';
else pv.t.abort := '0'; end if;
pv.t.diswithout := phyi.pv_t_diswithout;
-- Disconnect without data if CBE change in burst
if pci.cbe /= pi.cbe and (phyi.pr_t_state = pt_s_data and phyi.pr_t_fstate = ptf_write) then pv.t.diswithout := '1'; end if;
-- Parity error detected on address phase
if (phyi.pr_t_state = pt_idle or phyi.pr_t_state = pt_turn_ar) and pi.frame = '0' then
pv.t.addr_perr := (pci.par xor xorv(pi.ad & pi.cbe));
else
pv.t.addr_perr := '0';
end if;
-- TRDY#
if (phyi.pr_t_state = pt_s_data and ((phyi.t_ready and not phyi.t_retry) = '1' and pv.t.diswithout = '0' and
pv.t.abort = '0') and (pr.po.stop and not phyi.pr_t_stoped) = '1' and (phyi.pr_t_first_word or not pci.frame) = '1') -- Target accessed, data/fifo available, not stoped
or (not pr.po.trdy and pci.irdy) = '1' then -- During master waitstates
pv.po.trdy := '0';
end if;
-- STOP#
if
(pr.po.stop = '1' and phyi.pr_t_stoped = '0' and phyi.pr_t_lcount = "111" and pr.po.trdy = '1') -- latency timerout
or ((
((phyi.t_abort = '1' or pv.t.diswithout = '1') and (pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') -- transfer done or disconnect without data (when cbe has changed during write to target)
or (pv.t.abort = '1' and (((pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') or phyi.pr_t_first_word = '1')) -- To signal target abort
or ((phyi.pr_t_cfifo(0).valid and phyi.pr_t_cfifo(0).hold and phyi.pr_t_cfifo(0).stlast and phyi.pr_t_first_word) = '1') -- When first word in this access is the last word in the transfer
) and pr.po.stop = '1' and phyi.pr_t_stoped = '0') -- Only stop when master is ready (and target ready)
or (pr.po.stop = '0' and pci.frame = '0') -- When stop and frame are asserted
or (phyi.t_retry = '1' and pr.po.stop = '1' and phyi.pr_t_stoped = '0') then -- To signal retry
pv.po.stop := '0';
end if;
-- DEVSEL#
if (phyi.pr_t_state /= pt_s_data and phyi.pv_t_state = pt_s_data)
or (pr.po.devsel = '0' and (pci.frame and not pci.irdy and not (pr.po.trdy and pr.po.stop)) = '0'
and pv.t.abort = '0' -- To signal target abort
) then
pv.po.devsel := '0';
end if;
-- Output enable ctrl signals
if phyi.pv_t_state = pt_s_data or phyi.pv_t_state = pt_backoff then
pv.po.devselen := oeon; pv.po.trdyen := oeon; pv.po.stopen := oeon;
end if;
-- Master & Target --------------------------------------------------------------
-- AD
if (pr.m.state /= pm_idle and pr.m.state /= pm_dr_bus and phyi.pr_m_fstate = pmf_fifo) then
pv.po.ad := phyi.pr_m_cfifo(pv.m.cfi).data; -- PCI master data
elsif (phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar) then
pv.po.ad := phyi.pr_t_cfifo(pv.t.cfi).data; -- PCI target data
else
pv.po.ad := phyi.pr_m_addr; -- Address
end if;
-- Output enable AD [target]
if phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar and phyi.pr_t_cur_acc_0_read = '1'
and (pci.frame and (not pr.po.stop or not pr.po.trdy)) = '0' then
pv.po.aden := (others => oeon);
end if;
-- Output enable AD [master]
if (pcii.frame and pcii.irdy and not pcii.gnt) = '1'
or ((pr.m.state = pm_addr or pr.m.state = pm_m_data) and phyi.pr_m_fstate /= pmf_read and (pr.po.frame and (not pci.stop or not pci.trdy)) = '0') then
pv.po.aden := (others => oeon);
end if;
-- PAR
pv.po.par := xorv(pr.po.ad & pci.cbe);
-- Output enable PAR
pv.po.paren := pr.po.aden(15); -- AD[15] should be closest to PAR
-- PERR
pv.po.perr := pi.irdy or pi.trdy or not (pci.par xor xorv(pi.ad & pi.cbe)); -- Signal perr two cycles after data phase is completed
-- Output enable PERR
if phyi.pr_conf_comm_perren = '1' and -- Parity error response enable bit[6] = 1
(phyi.pr_m_perren(0) = '1' -- During master read
or (phyi.pr_t_state = pt_s_data and phyi.pr_t_cur_acc_0_read = '0') -- Write to target
or (pr.po.perr = '0' and pr.po.perren = oeon)) then -- Parity error on last phase
pv.po.perren := oeon;
end if;
-- SERR & Output enable for SERR
if phyi.pr_conf_comm_perren = '1' and phyi.pr_conf_comm_serren = '1' and pv.t.addr_perr = '1' then
pv.po.serren := oeon;
end if;
-- PCI reset --------------------------------------------------------------------
-- soft reset
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(1)) = '0' then -- Master reset
-- Master
pv.m.state := pm_idle;
pv.m.cfi := 0;
pv.m.hold := (others => '0');
pv.m.term := (others => '0');
end if;
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(0)) = '0' then -- Target reset
-- Target
pv.t.cfi := 0;
pv.t.hold := (others => '0');
pv.t.stop := '0';
pv.t.addr_perr := '0';
end if;
if (pcisynrst and not phyi.pcisoftrst(2)) = '0' then -- Hard reset
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
end if;
---------------------------------------------------------------------------------
piin <= pci;
prin <= pv;
poin <= pv.po;
phyo.pciv <= pci;
phyo.pr_m_state <= pr.m.state;
phyo.pr_m_last <= pr.m.last;
phyo.pr_m_hold <= pr.m.hold;
phyo.pr_m_term <= pr.m.term;
phyo.pr_t_hold <= pr.t.hold;
phyo.pr_t_stop <= pr.t.stop;
phyo.pr_t_abort <= pr.t.abort;
phyo.pr_t_diswithout <= pr.t.diswithout;
phyo.pr_t_addr_perr <= pr.t.addr_perr;
phyo.pcirsto(0) <= pcisynrst;
phyo.pr_po <= pr.po;
phyo.pio <= pi;
phyo.poo <= po;
-- PCI output signals
pcio.ad <= po.ad; pcio.vaden <= po.aden;
pcio.cbe <= po.cbe; pcio.cbeen <= po.cbeen;
pcio.frame <= po.frame; pcio.frameen <= po.frameen;
pcio.irdy <= po.irdy; pcio.irdyen <= po.irdyen;
pcio.trdy <= po.trdy; pcio.trdyen <= po.trdyen;
pcio.stop <= po.stop; pcio.stopen <= po.stopen;
pcio.devsel <= po.devsel; pcio.devselen <= po.devselen;
pcio.par <= po.par; pcio.paren <= po.paren;
pcio.perr <= po.perr; pcio.perren <= po.perren;
pcio.req <= po.req; pcio.reqen <= po.reqen;
pcio.int <= '0'; pcio.inten <= phyi.pciinten(0);
pcio.vinten <= phyi.pciinten;
pcio.rst <= phyi.pcirstout;
pcio.serr <= po.serr; pcio.serren <= po.serren;
if SCANTEST/=0 and GRLIB_CONFIG_ARRAY(GRLIB_EXTERNAL_TESTOEN)=0 then
if phyi.testen='1' then
pcio.vaden <= (others => phyi.testoen);
pcio.cbeen <= (others => phyi.testoen);
pcio.frameen <= phyi.testoen;
pcio.irdyen <= phyi.testoen;
pcio.trdyen <= phyi.testoen;
pcio.stopen <= phyi.testoen;
pcio.devselen <= phyi.testoen;
pcio.paren <= phyi.testoen;
pcio.perren <= phyi.testoen;
pcio.reqen <= phyi.testoen;
pcio.inten <= phyi.testoen;
pcio.vinten <= (others => phyi.testoen);
pcio.rst <= phyi.testoen xor oeon;
pcio.serren <= phyi.testoen;
end if;
end if;
-- Unused signals
pcio.lock <= oeoff; pcio.locken <= oeoff;
pcio.aden <= oeoff; pcio.ctrlen <= oeoff;
pcio.pme_enable <= oeoff; pcio.pme_clear <= oeoff;
pcio.power_state <= (others => oeoff);
end process;
-- po_keep <= poin_keep;
poin_keep(31 downto 0) <= poin.ad; po_keep.ad <= poin_keep(31 downto 0);
poin_keep(63 downto 32) <= poin.aden; po_keep.aden <= poin_keep(63 downto 32);
poin_keep(67 downto 64) <= poin.cbe; po_keep.cbe <= poin_keep(67 downto 64);
poin_keep(71 downto 68) <= poin.cbeen; po_keep.cbeen <= poin_keep(71 downto 68);
poin_keep( 72) <= poin.frame; po_keep.frame <= poin_keep( 72);
poin_keep( 73) <= poin.frameen; po_keep.frameen <= poin_keep( 73);
poin_keep( 74) <= poin.irdy; po_keep.irdy <= poin_keep( 74);
poin_keep( 75) <= poin.irdyen; po_keep.irdyen <= poin_keep( 75);
poin_keep( 76) <= poin.trdy; po_keep.trdy <= poin_keep( 76);
poin_keep( 77) <= poin.trdyen; po_keep.trdyen <= poin_keep( 77);
poin_keep( 78) <= poin.stop; po_keep.stop <= poin_keep( 78);
poin_keep( 79) <= poin.stopen; po_keep.stopen <= poin_keep( 79);
poin_keep( 80) <= poin.devsel; po_keep.devsel <= poin_keep( 80);
poin_keep( 81) <= poin.devselen; po_keep.devselen <= poin_keep( 81);
poin_keep( 82) <= poin.par; po_keep.par <= poin_keep( 82);
poin_keep( 83) <= poin.paren; po_keep.paren <= poin_keep( 83);
poin_keep( 84) <= poin.perr; po_keep.perr <= poin_keep( 84);
poin_keep( 85) <= poin.perren; po_keep.perren <= poin_keep( 85);
poin_keep( 86) <= poin.lock; po_keep.lock <= poin_keep( 86);
poin_keep( 87) <= poin.locken; po_keep.locken <= poin_keep( 87);
poin_keep( 88) <= poin.req; po_keep.req <= poin_keep( 88);
poin_keep( 89) <= poin.reqen; po_keep.reqen <= poin_keep( 89);
poin_keep( 90) <= poin.serren; po_keep.serren <= poin_keep( 90);
po_keep.inten <= phyi.pciinten(0);
po_keep.vinten <= phyi.pciinten;
xarst <= phyi.testrst when scantest/=0 and phyi.testen='1' else pcirst(0);
phyreg : process(pciclk, phyi.pciasyncrst, pcirst, xarst)
begin
if rising_edge(pciclk) then
pr <= prin;
pi <= piin;
po <= po_keep;
if iotmact /= '0' then
po.ad <= iotdout(31 downto 0);
po.cbe <= iotdout(35 downto 32);
po.frame <= iotdout(36);
po.irdy <= iotdout(37);
po.trdy <= iotdout(38);
po.par <= iotdout(39);
po.perr <= iotdout(40);
po.serr <= iotdout(41);
po.devsel <= iotdout(42);
po.stop <= iotdout(43);
po.req <= iotdout(44);
po.reqen <= oeon;
if iotmoe /= '0' then
po.aden <= (others => oeon); po.cbeen <= (others => oeon); po.frameen <= oeon;
po.devselen <= oeon; po.trdyen <= oeon; po.irdyen <= oeon; po.stopen <= oeon;
po.paren <= oeon; po.perren <= oeon; po.locken <= oeon;
po.inten <= oeon; po.vinten <= (others => oeon); po.serren <= oeon;
else
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end if;
pcisynrst <= pcirst(1) and pcirst(2);
pcirst(0) <= pcirst(1) and pcirst(2);
pcirst(1) <= pcirst(2); pcirst(2) <= '1';
end if;
if phyi.pciasyncrst = '0' then pcirst <= (others => '0'); end if;
if xarst = '0' then -- asynch reset required
po.ad <= (others => '1'); pi.ad <= (others => '1'); -- for virtex-4 all registers in IOB need to have same reset
po.trdy <= '1'; pi.trdy <= '1'; po.stop <= '1'; pi.stop <= '1';
po.irdy <= '1'; pi.irdy <= '1'; po.frame <= '1'; pi.frame <= '1';
po.cbe <= (others => '1'); pi.cbe <= (others => '1');
po.par <= '1'; pi.par <= '1';
po.perr <= '1'; pi.perr <= '1';
po.devsel <= '1'; pi.devsel <= '1';
pi.serr <= '1';
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff; po.reqen <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end process;
iotdin(45) <= pi.idsel;
iotdin(44) <= pi.gnt;
iotdin(43) <= pi.stop;
iotdin(42) <= pi.devsel;
iotdin(41) <= pi.serr;
iotdin(40) <= pi.perr;
iotdin(39) <= pi.par;
iotdin(38) <= pi.trdy;
iotdin(37) <= pi.irdy;
iotdin(36) <= pi.frame;
iotdin(35 downto 32) <= pi.cbe;
iotdin(31 downto 0) <= pi.ad;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/sim/ddr3ram.vhd | 1 | 30855 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr3ram
-- File: ddr3ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr3ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
colbits: integer range 9 to 12 := 10;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G
speedbin: integer range 0 to 12 := 0;
density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip
pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD)
changeendian: integer range 0 to 32 := 0
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(2 downto 0);
a: in std_logic_vector(abits-1 downto 0);
resetn: in std_ulogic;
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr3ram is
type moderegs is record
-- Mode register (0)
ppd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
rbt: std_ulogic;
caslat: std_logic_vector(3 downto 0);
blen: std_logic_vector(1 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
tdqsen: std_ulogic;
level: std_ulogic;
al: std_logic_vector(1 downto 0);
rtt_nom: std_logic_vector(2 downto 0);
dic: std_logic_vector(1 downto 0);
dlldis: std_ulogic;
-- Extended mode register 2
rtt_wr: std_logic_vector(1 downto 0);
srt: std_ulogic;
asr: std_ulogic;
cwl: std_logic_vector(2 downto 0);
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
mpr: std_ulogic;
mprloc: std_logic_vector(1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en, dqscal_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 4;
constant tRTP_ck: integer := 4;
constant tRTP_t: time := 7.5 ns;
function tRTP(tper: time) return time is
begin
if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if;
end tRTP;
constant tMOD_ck: integer := 12;
constant tMOD_t: time := 15 ns;
type timetab is array (0 to 12) of time;
-- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G
constant tRAS : timetab :=
(37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns);
constant tRP : timetab :=
(15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(2 to 6) of time;
constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns);
function tRRD(tper: time; speedbin: integer range 0 to 12) return time is
variable t: time;
begin
case speedbin is
when 0 to 1 => t:=10 ns;
when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if;
when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if;
end case;
if t < 4*tper then t:=4*tper; end if;
return t;
end tRRD;
function pick(t,f: integer; b: boolean) return integer is
begin
if b then return t; else return f; end if;
end pick;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(2 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="---" or cba=ba) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t,t2: time;
variable i: integer;
begin
initdone <= false;
-- Allow resetn to be X or U for a while during sim start
if resetn /= '0' then
wait until resetn='0' for 1 us;
end if;
assert resetn='0' report "RESETn not asserted on power-up" severity warning;
wait until resetn/='0' for 200 us;
assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning;
l0: loop
initdone <= false;
wait until resetn/='0';
assert cke='0' report "CKE not low when RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') for 500 us;
if resetn='0' then next; end if;
assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') and rising_edge(ck);
if resetn='0' then next; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
t2 := t+tRFC(density)+(10 ns);
i := 0;
while i<5 and now<t2 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
i := i+1;
end loop;
-- EMRS EMR2
checkcmd('0','0','0',"010","----------------");
if resetn='0' then next; end if;
-- EMRS EMR3
checkcmd('0','0','0',"011","----------------");
if resetn='0' then next; end if;
-- EMRS EMR1 enable DLL
checkcmd('0','0','0',"001","---------------0");
if resetn='0' then next; end if;
-- EMRS EMR0 reset DLL
checkcmd('0','0','0',"000","-------1--------");
if resetn='0' then next; end if;
-- ZQCL
checkcmd('1','1','0',"---","-----1----------");
if resetn='0' then next; end if;
for x in 1 to 512 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
end loop;
initdone <= true;
wait until resetn='0';
end loop;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
-- Data split by bank to avoid exceeding 4G
constant b0size: integer := (2**(colbits+rowbits)) * ((width+15)/16);
constant b1size: integer := pick(b0size, 1, implbanks>1);
constant b2size: integer := pick(b0size, 1, implbanks>2);
constant b3size: integer := pick(b0size, 1, implbanks>3);
constant b4size: integer := pick(b0size, 1, implbanks>4);
constant b5size: integer := pick(b0size, 1, implbanks>5);
constant b6size: integer := pick(b0size, 1, implbanks>6);
constant b7size: integer := pick(b0size, 1, implbanks>7);
subtype coldata is std_logic_vector(width-1 downto 0);
subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state
type idata_arr is array(natural range <>) of idata;
variable memdata0: idata_arr(0 to b0size-1);
variable memdata1: idata_arr(0 to b1size-1);
variable memdata2: idata_arr(0 to b2size-1);
variable memdata3: idata_arr(0 to b3size-1);
variable memdata4: idata_arr(0 to b4size-1);
variable memdata5: idata_arr(0 to b5size-1);
variable memdata6: idata_arr(0 to b6size-1);
variable memdata7: idata_arr(0 to b7size-1);
function reversedata(data : std_logic_vector; step : integer)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/step-1) loop
rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step);
end loop;
return rdata;
end function reversedata;
impure function memdata_get(bank,idx: integer) return coldata is
variable r: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
case bank is
when 0 => x := memdata0(iidx+q);
when 1 => x := memdata1(iidx+q);
when 2 => x := memdata2(iidx+q);
when 3 => x := memdata3(iidx+q);
when 4 => x := memdata4(iidx+q);
when 5 => x := memdata5(iidx+q);
when 6 => x := memdata6(iidx+q);
when others => x := memdata7(iidx+q);
end case;
p := std_logic_vector(to_unsigned(x,20));
if p(18)='0' then p(15 downto 8) := "UUUUUUUU";
elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if;
if p(16)='0' then p(7 downto 0) := "UUUUUUUU";
elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if;
if width < 16 then
r := p(7 downto 0);
else
r(width-16*q-1 downto width-16*q-16) := p(15 downto 0);
end if;
end loop;
if changeendian /= 0 then
r := reversedata(r, changeendian);
end if;
return r;
end memdata_get;
procedure memdata_set(bank,idx: integer; v: coldata) is
variable n: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
-- assert false
-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v))
-- severity note;
n := v;
if changeendian /= 0 then
n := reversedata(n, changeendian);
end if;
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
p := "0101" & x"0000";
if width < 16 then
p(7 downto 0) := n;
else
p(15 downto 0) := n(width-16*q-1 downto width-16*q-16);
end if;
if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00";
elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if;
if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00";
elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if;
x := to_integer(unsigned(p));
case bank is
when 0 => memdata0(iidx+q) := x;
when 1 => memdata1(iidx+q) := x;
when 2 => memdata2(iidx+q) := x;
when 3 => memdata3(iidx+q) := x;
when 4 => memdata4(iidx+q) := x;
when 5 => memdata5(iidx+q) := x;
when 6 => memdata6(iidx+q) := x;
when others => memdata7(iidx+q) := x;
end case;
end loop;
end memdata_set;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable idx, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if width < 16 then
idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0)));
while len > 1 loop
memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7)));
idx := idx+1;
len := len-1;
recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1);
end loop;
else
assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry
idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1)));
while len > 1 loop
memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15)));
idx := idx+1;
len := len-2;
recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1);
end loop;
if len > 0 then
memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15)));
end if;
end if;
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
first,wchop: boolean;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 25);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-2 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen, wblen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, cwl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 100;
variable mrstime: time;
variable loaded: boolean := false;
variable cold: coldata;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) and resetn='1' then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if;
if cl<5 or cl>11 then cl:=0; end if;
case vmr.al is
when "00" => al:=0;
when "01" => al:=cl-1;
when "10" => al:=cl-2;
when others => al:=-1;
end case;
if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if;
if cwl>8 then cwl:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if;
if wrap<5 or wrap>12 then wrap:=0; end if;
-- Checks for all-bank commands
mrscount := mrscount+1;
assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111"))
report "tMRD violation!" severity warning;
assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or
(cke='1' and (csn='1' or cmd="111" or cmd="000"))
report "tMOD violation!" severity warning;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
if vmr.mpr='1' then
assert cke='0' or csn='1' or cmd="111" or cmd="101"
report "Command other than read in MPR mode!" severity warning;
for x in 7 downto 0 loop
assert banks(x).openrow<0
report "Row opened in MPR mode!" severity warning;
end loop;
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0 or vmr.mpr='1'
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0)));
wblen := 8;
case vmr.blen is
when "00" => blen := 8;
when "01" => if a(12)='1' then blen:=8; else blen:=4; end if;
when "11" => blen := 4; wblen:=4;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
if cmd(0)='0' then
alow(1 downto 0) := "00";
if blen=8 then alow(2):='0'; end if;
end if;
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.rbt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
accpipe(3-x/2).wchop := (blen<wblen);
end loop;
accpipe(3).first := true;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+tRTP_ck;
else
banks(bank).autopch := al+cwl+wblen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- ZQInit
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
for x in 3+cl+al downto 0 loop
assert not accpipe(x).r severity warning;
end loop;
for x in 4+cwl+al downto 0 loop
assert not accpipe(x).w severity warning;
end loop;
-- Currently does not check TZQCoper/TZQCs
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 6+cwl+al downto 0 loop
assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or
(a(10)='0' and accpipe(x).bank/=bank) )
report "Precharging bank with access in progress" severity warning;
end loop;
for x in 0 to 7 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.ppd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4) & a(2);
vmr.rbt := a(3);
vmr.blen := a(1 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.tdqsen := a(11);
vmr.level := a(7);
vmr.al := a(4 downto 3);
vmr.rtt_nom := a(9) & a(6) & a(2);
vmr.dic := a(5) & a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.rtt_wr := a(10 downto 9);
vmr.srt := a(7);
vmr.asr := a(6);
vmr.cwl := a(5 downto 3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.mpr := a(2);
vmr.mprloc := a(1 downto 0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := 0;
mrstime := now;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and
((now-banks(x).readtime-deltat) < tRTP_t or
(now-banks(x).opentime-deltat) < tRAS(speedbin)) then
-- Auto delay auto-precharge to satisfy tRTP_t
-- NOTE: According to Micron's datasheets, their DDR3 memories
-- automatically hold off the auto precharge so that also tRAS is satisfied,
-- and the MIG controller seems to depend on this. It is not clear in the
-- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3
-- RAMs, but we emulate that behavior here.
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
if vmr.mpr='1' then
assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning;
read_data <= (others => '0');
for x in width/8-1 downto 0 loop
read_data(x*8) <= '1';
end loop;
else
read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) &
memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1));
end if;
else
read_en <= false;
end if;
if accpipe(3+al).r and accpipe(3+al).first then
banks(accpipe(3+al).bank).readtime := now;
end if;
write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w;
if accpipe(4+cwl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x));
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
cold(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold);
end loop;
banks(accpipe(4+cwl+al).bank).writetime := now;
end if;
if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then
banks(accpipe(6+cwl+al).bank).writetime := now;
end if;
dqscal_en <= (vmr.level='1');
elsif resetn='0' then
for x in banks'range loop
banks(x).openrow := -1;
end loop;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en or dqscal_en;
assert not (read_en and write_en);
if dqscal_en then
while dqscal_en loop
prevdqs := dqs;
wait on dqs,dqscal_en;
for x in dqs'range loop
if dqs(x)='1' and prevdqs(x)='0' then
dq(8*x+7 downto 8*x) <= "0000000" & ck;
end if;
end loop;
end loop;
elsif read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/inferred/ddrphy_datapath.vhd | 1 | 9277 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/esa/pci/pcicomp.vhd | 3 | 837 | library ieee;
library grlib;
library techmap;
use grlib.amba.all;
use techmap.gencomp.all;
use ieee.std_logic_1164.all;
package pcicomp is
component pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0;
tech : integer := axcel;
reg : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
end package;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/grgates.vhd | 1 | 6916 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: grgates.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Various gates with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.allclkgen.all;
entity grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end;
architecture rtl of grmux2 is
component ut130hbd_mux2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_rhs65
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
constant has_mux2 : tech_ability_type :=
( rhlib18t => 1, ut130 => 1, ut90 => 1, rhs65 => 1, others => 0);
begin
y0 : if has_mux2(tech) = 1 generate
rhlib : if tech = rhlib18t generate
x0 : clkmux_rhlib18t port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_mux2 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut90n : if tech = ut90 generate
x0 : mux2_ut90nhbd port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
rhs65n: if tech=rhs65 generate
x0 : mux2_rhs65 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
end generate;
y1 : if has_mux2(tech) = 0 generate
op <= ip0 when sel = '0' else ip1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grmux2v is generic( tech : integer := inferred;
bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic;
op : out std_logic_vector(bits-1 downto 0));
end;
architecture rtl of grmux2v is
begin
x0 : for i in bits-1 downto 0 generate
y0 : grmux2 generic map (tech, imp) port map (ip0(i), ip1(i), sel, op(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grdff is
component ut130hbd_dff
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
component dff_ut90nhbd
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
constant has_dff : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_dff(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_dff port map (clk => clk, d => d, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : dff_ut90nhbd port map (clk => clk, d => d, q => q);
end generate;
end generate;
y1 : if has_dff(tech) = 0 generate
x0 : process(clk)
begin if rising_edge(clk) then q <= d; end if; end process;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of gror2 is
component ut130hbd_or2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component or2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_or2 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_or2(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_or2 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : or2_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_or2(tech) = 0 generate
q <= i0 or i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grand12 is
component ut130hbd_and12
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component and12_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_and12 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_and12(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_and12 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : and12_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_and12(tech) = 0 generate
q <= i0 and not i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grnand2 is
generic (
tech: integer := 0;
imp: integer := 0
);
port (
i0: in std_ulogic;
i1: in std_ulogic;
q : out std_ulogic
);
end;
architecture rtl of grnand2 is
constant has_nand2: tech_ability_type := (others => 0);
begin
y0: if has_nand2(tech)=1 generate
end generate;
y1: if has_nand2(tech)=0 generate
q <= not (i0 and i1);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/leon3mp.vhd | 1 | 28150 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic; -- Driven const low by MAXV CPLD?
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : inout std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- This has been commented out as some pins have been placed in
-- violation with the Altera diff pad keep-out rules.
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic; -- changed due to placement rule
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic; -- in due to placement rule
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_greth1 : integer := hmi_cpu + CFG_NCPU;
constant hmi_greth2 : integer := hmi_greth1 + CFG_GRETH;
constant hmi_ahbuart : integer := hmi_greth2 + CFG_GRETH2;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant nahbm : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant hsi_ssrctrl : integer := 0;
constant hsi_apbctrl : integer := hsi_ssrctrl + (CFG_SSCTRL + CFG_AHBROMEN + 1)/2;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_lpddr2 : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_lpddr2 + 1;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_irqmp : integer := 0;
constant pi_apbuart : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_gpt : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant pi_ssrctrl : integer := pi_ahbuart + CFG_AHB_UART;
constant pi_greth1 : integer := pi_ssrctrl + CFG_SSCTRL;
constant pi_greth2 : integer := pi_greth1 + CFG_GRETH;
constant pi_i2cmst : integer := pi_greth2 + CFG_GRETH2;
constant napbs : integer := pi_i2cmst + CFG_I2C_ENABLE;
constant CPU_FREQ : integer := 75000;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal ui_serial, ui_usb, ui, dui: uart_in_type;
signal uo_serial, uo_usb, uo, duo: uart_out_type;
signal ethi1,ethi2: eth_in_type;
signal etho1,etho2: eth_out_type;
signal i2ci: i2c_in_type;
signal i2co: i2c_out_type;
signal vcc, gnd: std_ulogic;
-- signal logsig: std_logic_vector(31 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
user_led(0) <= not clklock;
clkgen0: entity work.clkgen_c5ekit
port map (clkin_50_fpga_right, clkm, open, clklock);
rstgen0: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (cpu_resetn, clkm, clklock, rstn);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU, timer and IRQ controller
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (user_led(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (user_pb(3), dsui.break);
user_led(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
irqi(i).rst <= '1';
irqi(i).run <= '1';
irqi(i).rstvec <= (others => '0');
irqi(i).iact <= '0';
irqi(i).index <= (others => '0');
irqi(i).hrdrst <= '1';
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; gpti.wdogen <= '0';
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-- EDCL included in Ethernet below
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
fm_a <= del_addr; -- sro.address(26 downto 1);
-- fm_d_pad: iopadvv
-- generic map (tech => padtech, width => 16)
-- port map (pad => fm_d, i => sro.data(31 downto 16),
-- en => sro.vbdrive(31 downto 16), o => sri.data(31 downto 16));
sri.data(31 downto 16) <= fm_d;
flash_clk <= '0';
flash_resetn <= '1';
flash_cen <= '0'; -- sro.romsn(0);
flash_advn <= '0';
flash_wen <= sro.writen or sro.romsn(0);
flash_oen <= sro.oen or sro.romsn(0);
ssram_clk <= clkm;
ssram_oen <= sro.oen;
sram_cen <= del_ce; -- sro.ramsn(0);
ssram_bwen <= del_bwe(1); -- sro.writen;
ssram_bwan <= del_bwa(1); -- sro.wrn(0);
ssram_bwbn <= del_bwb(1); -- sro.wrn(1);
ssram_adscn <= '1';
ssram_adspn <= '0';
ssram_zzn <= '0';
ssram_advn <= '1';
sri.data(15 downto 0) <= sri.data(31 downto 16);
sri.brdyn <= '1';
sri.bexcn <= '1';
sri.writen <= '1';
sri.wrn <= (others => '1');
sri.bwidth <= "01";
sri.sd <= (others => '0');
sri.cb <= (others => '0');
sri.scb <= (others => '0');
sri.edac <= '0';
delproc: process(clkm)
begin
if rising_edge(clkm) then
del_addr <= sro.address(26 downto 1);
del_ce <= sro.ramsn(0);
del_bwe <= del_bwe(0) & sro.writen;
del_bwa <= del_bwa(0) & sro.wrn(0);
del_bwb <= del_bwb(0) & sro.wrn(1);
end if;
end process;
ssrctrl: if CFG_SSCTRL = 1 generate
ssrctrl0: gaisler.memctrl.ssrctrl
generic map (hindex => hsi_ssrctrl, pindex => pi_ssrctrl,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
bus16 => CFG_SSCTRLP16
)
port map (rstn, clkm, ahbsi, ahbso(hsi_ssrctrl), apbi, apbo(pi_ssrctrl), sri, sro);
end generate;
nossrctrl: if CFG_SSCTRL = 0 generate
sro <= memory_out_none;
end generate;
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SSCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ssrctrl, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ssrctrl));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#E00#
) port map (
pll_ref_clk => diff_clkin_top_125_p,
global_reset_n => cpu_resetn,
mem_a => ddr3_a,
mem_ba => ddr3_ba,
mem_ck => ddr3_ck_p,
mem_ck_n => ddr3_ck_n,
mem_cke => ddr3_cke,
mem_reset_n => ddr3_rstn,
mem_cs_n => ddr3_csn,
mem_dm => ddr3_dm,
mem_ras_n => ddr3_rasn,
mem_cas_n => ddr3_casn,
mem_we_n => ddr3_wen,
mem_dq => ddr3_dq,
mem_dqs => ddr3_dqs_p,
mem_dqs_n => ddr3_dqs_n,
mem_odt => ddr3_odt,
oct_rzqin => ddr3_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
lpddr2if0: entity work.lpddr2if
generic map (
hindex => hsi_lpddr2,
haddr => 16#600#, hmask => 16#F00#
) port map (
pll_ref_clk => diff_clkin_bot_125_p,
global_reset_n => cpu_resetn,
mem_ca => lpddr2_a,
mem_ck => lpddr2_ck_p,
mem_ck_n => lpddr2_ck_n,
mem_cke => lpddr2_cke,
mem_cs_n => lpddr2_csn,
mem_dm => lpddr2_dm,
mem_dq => lpddr2_dq,
mem_dqs => lpddr2_dqs_p,
mem_dqs_n => lpddr2_dqs_n,
oct_rzqin => lpddr2_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_lpddr2)
);
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
srx_pad : inpad generic map (tech => padtech) port map (uart_rxd, ui_serial.rxd);
srts_pad : inpad generic map (tech => padtech) port map (uart_rts, ui_serial.ctsn);
stx_pad : outpad generic map (tech => padtech) port map (uart_txd, uo_serial.txd);
scts_pad : outpad generic map (tech => padtech) port map (uart_cts, uo_serial.rtsn);
urx_pad : inpad generic map (tech => padtech) port map (usb_uart_rxd, ui_usb.rxd);
urts_pad : inpad generic map (tech => padtech) port map (usb_uart_rts, ui_usb.ctsn);
utx_pad : outpad generic map (tech => padtech) port map (usb_uart_txd, uo_usb.txd);
ucts_pad : outpad generic map (tech => padtech) port map (usb_uart_cts, uo_usb.rtsn);
usb_uart_dtr <= '0';
ui_serial.extclk <= '0'; ui_usb.extclk <= '0';
-- UART switch
ui <= ui_serial when user_dipsw(0)='0' else ui_usb;
dui <= ui_usb when user_dipsw(0)='0' else ui_serial;
uo_serial <= uo when user_dipsw(0)='0' else duo;
uo_usb <= duo when user_dipsw(0)='0' else uo;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate
uo.rtsn <= '0'; uo.txd <= '0'; uo.scaler <= (others => '0');
uo.txen <= '0'; uo.flow <= '0'; uo.rxen <= '0';
end generate;
-- AHBUART, see under Debug links above
-----------------------------------------------------------------------------
-- Ethernet
-----------------------------------------------------------------------------
emdio_pad : iopad generic map (tech => padtech)
port map (eneta_mdio, etho1.mdio_o, etho1.mdio_oe, ethi1.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_tx_clk, ethi1.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_rx_clk, ethi1.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (eneta_rx_d, ethi1.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (eneta_rx_dv, ethi1.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (eneta_rx_er, ethi1.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eneta_rx_col, ethi1.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eneta_rx_crs, ethi1.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (eneta_intn, ethi1.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (eneta_tx_d, etho1.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eneta_tx_en, etho1.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (eneta_tx_er, etho1.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (eneta_mdc, etho1.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eneta_resetn, rstn);
ethi1.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi1.gtx_clk <= '0'; ethi1.rmii_clk <= '0';
emdio_pad2 : iopad generic map (tech => padtech)
port map (enetb_mdio, etho2.mdio_o, etho2.mdio_oe, ethi2.mdio_i);
etxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_tx_clk, ethi2.tx_clk);
erxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_rx_clk, ethi2.rx_clk);
erxd_pad2 : inpadv generic map (tech => padtech, width => 4)
port map (enetb_rx_d, ethi2.rxd(3 downto 0));
erxdv_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_dv, ethi2.rx_dv);
erxer_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_er, ethi2.rx_er);
erxco_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_col, ethi2.rx_col);
erxcr_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_crs, ethi2.rx_crs);
emdint_pad2 : inpad generic map (tech => padtech)
port map (enetb_intn, ethi2.mdint);
etxd_pad2 : outpadv generic map (tech => padtech, width => 4)
port map (enetb_tx_d, etho2.txd(3 downto 0));
etxen_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_en, etho2.tx_en);
etxer_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_er, etho2.tx_er);
emdc_pad2 : outpad generic map (tech => padtech)
port map (enetb_mdc, etho2.mdc);
erst_pad2 : outpad generic map (tech => padtech)
port map (enetb_resetn, rstn);
ethi2.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi2.gtx_clk <= '0'; ethi2.rmii_clk <= '0';
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => hmi_greth1,
pindex => pi_greth1, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 0,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth1),
apbi => apbi, apbo => apbo(pi_greth1), ethi => ethi1, etho => etho1);
end generate;
noeth1 : if CFG_GRETH = 0 generate
etho1 <= eth_out_none;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Secondary ethernet MAC
e2 : grethm generic map(hindex => hmi_greth2,
pindex => pi_greth2, paddr => 12, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth2),
apbi => apbi, apbo => apbo(pi_greth2), ethi => ethi2, etho => etho2);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
etho2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------------
-- GPIO
-----------------------------------------------------------------------------
-- TO DO
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
max5_csn <= '1';
sclpad: iopad generic map (tech => padtech) port map (eeprom_scl, i2co.scl, i2co.scloen, i2ci.scl);
sdapad: iopad generic map (tech => padtech) port map (eeprom_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
i2c: if CFG_I2C_ENABLE=1 generate
i2cmst0: i2cmst
generic map (pindex => pi_i2cmst, paddr => 4, pmask => 16#FFF#, pirq => 4)
port map (rstn,clkm,apbi,apbo(pi_i2cmst),i2ci,i2co);
end generate;
noi2c: if CFG_I2C_ENABLE=0 generate
i2co <= (others => '1');
end generate;
-- logan0: logan
-- generic map (pindex => napbs-1, paddr => 16#100#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(napbs-1), logsig);
--
-- logsig(31 downto 6) <= (others => '0');
-- logsig(5 downto 0) <= i2co.scl & i2co.scloen & i2ci.scl & i2co.sda & i2co.sdaoen & i2ci.sda;
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera CycloneV E Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/examples/vams/vhdl/basic-vhdl/voltage_dependend_capacitor.vhdl | 15 | 513 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_DEPENDEND_CAPACITOR IS
GENERIC ( PB : REAL := 1.0;
M : REAL := 0.5;
VT : REAL := 25.85e-6;
ISS : REAL := 1.0e-15;
TT : REAL := 4.0e-9;
CJ0 : REAL := 2.5e-12;
v_init : REAL := 0.0;
N :REAL := 1.0);
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY VOLTAGE_DEPENDEND_CAPACITOR;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/svga2ch7301c.vhd | 2 | 6828 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-111/ahbrom.vhd | 6 | 8224 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-de2-ep2c35/mypackage.vhd | 3 | 1630 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
--use grlib.devices.all;
--use grlib.stdlib.all;
--library techmap;
--use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
package mypackage is
type lcd_out_type is record
rs : std_ulogic;
rw : std_ulogic;
e : std_ulogic;
db : std_logic_vector(7 downto 0);
db_oe : std_ulogic;
end record;
type lcd_in_type is record
db : std_logic_vector(7 downto 0);
end record;
component sdctrl16
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 16;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component apblcd
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer range 0 to 1 := 0;
tas : integer range 0 to 15 := 1;
epw : integer range 0 to 127 := 12
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdo : out lcd_out_type;
lcdi : in lcd_in_type
);
end component;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de0-nano/leon3mp.vhd | 1 | 20952 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS;
dbguart : integer := CFG_DUART;
pclow : integer := CFG_PCLOW
);
port (
clock_50 : in std_logic;
led : inout std_logic_vector(7 downto 0);
key : in std_logic_vector(1 downto 0);
sw : in std_logic_vector(3 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dqm : out std_logic_vector(1 downto 0);
dram_ras_n : out std_ulogic;
dram_cas_n : out std_ulogic;
dram_cke : out std_ulogic;
dram_clk : out std_ulogic;
dram_we_n : out std_ulogic;
dram_cs_n : out std_ulogic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
epcs_data0 : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_ncso : out std_ulogic;
epcs_asdo : out std_ulogic;
i2c_sclk : inout std_logic;
i2c_sdat : inout std_logic;
g_sensor_cs_n : out std_ulogic;
g_sensor_int : in std_ulogic;
adc_cs_n : out std_ulogic;
adc_saddr : out std_ulogic;
adc_sclk : out std_ulogic;
adc_sdat : in std_ulogic;
gpio_2 : inout std_logic_vector(12 downto 0);
gpio_2_in : in std_logic_vector(2 downto 0);
gpio_1_in : in std_logic_vector(1 downto 0);
gpio_1 : inout std_logic_vector(33 downto 0);
gpio_0_in : in std_logic_vector(1 downto 0);
gpio_0 : inout std_logic_vector(33 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal gpio0i, gpio1i, gpio2i : gpio_in_type;
signal gpio0o, gpio1o, gpio2o : gpio_out_type;
signal dsubren : std_ulogic;
signal tck, tms, tdi, tdo : std_logic;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de0
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl,
locked => clklck);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, clklck, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0,
kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : entity work.sdctrl16
generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
sa_pad : outpadv generic map (width => 13, tech => padtech)
port map (dram_addr, sdo.address(14 downto 2));
ba0_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_ba, sdo.address(16 downto 15));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_dqm, sdo.dqm(1 downto 0));
end generate;
spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller
spimc : spimctrl
generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
end generate;
nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate;
miso_pad : inpad generic map (tech => padtech)
port map (epcs_data0, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdo, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_ncso, spmo.csn);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(0));
end generate;
noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals ------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
apbo(0) <= apb_none; -- Typically occupied by memory controller
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.rxd <= '1';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 4, paddr => 4, pmask => 16#FFF#,
pirq => 3, filter => 3, dynfilt => 1)
port map (rstn, clkm, apbi, apbo(4), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
spii.astart <= '0';
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, vcc(0));
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
grgpio2: grgpio -- GRGPIO2 port
generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31)
port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o);
gpio_2_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0),
gpio2i.din(12 downto 0));
gpio_2_inpads : inpadv generic map (tech => padtech, width => 3)
port map (gpio_2_in, gpio2i.din(15 downto 13));
gpio_0_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16),
gpio2i.din(17 downto 16));
gpio_0_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_0_in, gpio2i.din(19 downto 18));
gpio_1_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20),
gpio2i.din(21 downto 20));
gpio_1_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_1_in, gpio2i.din(23 downto 22));
led_pads : iopadvv generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24),
gpio2i.din(29 downto 24));
g_sensor_int_pad : inpad generic map (tech => padtech)
port map (g_sensor_int, gpio2i.din(30));
-- g_sensor_cs_n_pad : outpad generic map (tech => padtech)
-- port map (g_sensor_cs_n, gpio2o.dout(31));
g_sensor_cs_n <= '1';
-- gpio2i.din(31) <= gpio2o.dout(31);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(4));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/micron/sdram/components.vhd | 1 | 13878 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Micron SDRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component mt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component mt46v16m16
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
bbits : INTEGER := 16;
fdelay : INTEGER := 0;
chktiming : boolean := true
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
component ftmt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
err : INTEGER := 0
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component ddr2 is
generic(
DM_BITS : integer := 2;
ADDR_BITS : integer := 13;
ROW_BITS : integer := 13;
COL_BITS : integer := 9;
DQ_BITS : integer := 16;
DQS_BITS : integer := 2;
TRRD : integer := 10000;
TFAW : integer := 50000;
DEBUG : integer := 0
);
port (
ck : in std_ulogic;
ck_n : in std_ulogic;
cke : in std_ulogic;
cs_n : in std_ulogic;
ras_n : in std_ulogic;
cas_n : in std_ulogic;
we_n : in std_ulogic;
dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_BITS-1 downto 0);
dq : inout std_logic_vector(DQ_BITS-1 downto 0);
dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
odt : in std_ulogic
);
end component;
component mobile_ddr
--GENERIC ( -- Timing for -75Z CL2
-- tCK : TIME := 7.500 ns;
-- tCH : TIME := 3.375 ns; -- 0.45*tCK
-- tCL : TIME := 3.375 ns; -- 0.45*tCK
-- tDH : TIME := 0.500 ns;
-- tDS : TIME := 0.500 ns;
-- tIH : TIME := 0.900 ns;
-- tIS : TIME := 0.900 ns;
-- tMRD : TIME := 15.000 ns;
-- tRAS : TIME := 40.000 ns;
-- tRAP : TIME := 20.000 ns;
-- tRC : TIME := 65.000 ns;
-- tRFC : TIME := 75.000 ns;
-- tRCD : TIME := 20.000 ns;
-- tRP : TIME := 20.000 ns;
-- tRRD : TIME := 15.000 ns;
-- tWR : TIME := 15.000 ns;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16;
-- cols_bits : INTEGER := 9;
-- index : INTEGER := 0;
-- fname : string := "ram.srec"; -- File to read from
-- bbits : INTEGER := 32
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
----Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
----Dqs : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
----Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
----Dm : IN STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
);
END component;
component mobile_ddr_fe
generic (addr_swap : integer := 0);
port (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
BEaddr: out std_logic_vector (24 downto 0);
BEwr : out std_logic_vector(1 downto 0);
BEdin : out std_logic_vector(15 downto 0);
BEdout: in std_logic_vector(15 downto 0);
BEclear: out std_logic;
BEclrpart: out std_logic;
BEsynco: out std_logic;
BEsynci: in std_logic
);
end component;
component mobile_ddr_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#;
addr_swap : integer := 0;
offset_addr : std_logic_vector(31 downto 0) := x"00000000";
swap_halfw : integer := 0
);
port (
Dq : INOUT STD_LOGIC_VECTOR (dbits-1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0)
);
end component;
component mobile_ddr2_fe
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector( 1 downto 0);
dq : inout std_logic_vector(15 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
BEaddr : out std_logic_vector(27 downto 0);
BEwr_h : out std_logic_vector( 1 downto 0);
BEwr_l : out std_logic_vector( 1 downto 0);
BEdin_h : out std_logic_vector(15 downto 0);
BEdin_l : out std_logic_vector(15 downto 0);
BEdout_h: in std_logic_vector(15 downto 0);
BEdout_l: in std_logic_vector(15 downto 0);
BEclear : out std_logic;
BEreload: out std_logic;
BEsynco : out std_logic;
BEsynci : in std_logic
);
end component;
component mobile_ddr2_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#
);
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector(dbits/8-1 downto 0);
dq : inout std_logic_vector( dbits-1 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z')
);
end component;
component mobile_sdr
--GENERIC (
-- DEBUG : INTEGER := 1;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
end;
-- pragma translate_on
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-asic/pads.vhd | 1 | 26677 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity pads is
generic (
padtech : integer := 0;
padlevel : integer := 0;
padvoltage : integer := 0;
padfilter : integer := 0;
padstrength : integer := 0;
padslew : integer := 0;
padclkarch : integer := 0;
padhf : integer := 0;
spw_input_type : integer := 0;
jtag_padfilter : integer := 0;
testen_padfilter : integer := 0;
resetn_padfilter : integer := 0;
clk_padfilter : integer := 0;
spw_padstrength : integer := 0;
jtag_padstrength : integer := 0;
uart_padstrength : integer := 0;
dsu_padstrength : integer := 0;
oepol : integer := 0
);
port (
----------------------------------------------------------------------------
--to chip boundary
----------------------------------------------------------------------------
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : inout std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
---------------------------------------------------------------------------
--to core
---------------------------------------------------------------------------
lresetn : out std_ulogic;
lclksel : out std_logic_vector (1 downto 0);
lclk : out std_ulogic;
llock : in std_ulogic;
lerrorn : in std_ulogic;
laddress : in std_logic_vector(27 downto 0);
ldatain : out std_logic_vector(31 downto 0);
ldataout : in std_logic_vector(31 downto 0);
ldataen : in std_logic_vector(31 downto 0);
lcbin : out std_logic_vector(7 downto 0);
lcbout : in std_logic_vector(7 downto 0);
lcben : in std_logic_vector(7 downto 0);
lsdclk : in std_ulogic;
lsdcsn : in std_logic_vector (1 downto 0);
lsdwen : in std_ulogic;
lsdrasn : in std_ulogic;
lsdcasn : in std_ulogic;
lsddqm : in std_logic_vector (3 downto 0);
ldsutx : in std_ulogic;
ldsurx : out std_ulogic;
ldsuen : out std_ulogic;
ldsubre : out std_ulogic;
ldsuact : in std_ulogic;
ltxd1 : in std_ulogic;
lrxd1 : out std_ulogic;
ltxd2 : in std_ulogic;
lrxd2 : out std_ulogic;
lramsn : in std_logic_vector (4 downto 0);
lramoen : in std_logic_vector (4 downto 0);
lrwen : in std_logic_vector (3 downto 0);
loen : in std_ulogic;
lwriten : in std_ulogic;
lread : in std_ulogic;
liosn : in std_ulogic;
lromsn : in std_logic_vector (1 downto 0);
lbrdyn : out std_ulogic;
lbexcn : out std_ulogic;
lwdogn : in std_ulogic;
lgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
li2c_sclout : in std_ulogic;
li2c_sclen : in std_ulogic;
li2c_sclin : out std_ulogic;
li2c_sdaout : in std_ulogic;
li2c_sdaen : in std_ulogic;
li2c_sdain : out std_ulogic;
lspi_miso : out std_ulogic;
lspi_mosi : in std_ulogic;
lspi_sck : in std_ulogic;
lspi_slvsel : in std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
lprom32 : out std_ulogic;
lspw_clksel : out std_logic_vector (1 downto 0);
lspw_clk : out std_ulogic;
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
lgtx_clk : out std_ulogic;
lerx_clk : out std_ulogic;
lerxd : out std_logic_vector(7 downto 0);
lerx_dv : out std_ulogic;
letx_clk : out std_ulogic;
letxd : in std_logic_vector(7 downto 0);
letx_en : in std_ulogic;
letx_er : in std_ulogic;
lerx_er : out std_ulogic;
lerx_col : out std_ulogic;
lerx_crs : out std_ulogic;
lemdint : out std_ulogic;
lemdioin : out std_logic;
lemdioout : in std_logic;
lemdioen : in std_logic;
lemdc : in std_ulogic;
ltesten : out std_ulogic;
ltrst : out std_ulogic;
ltck : out std_ulogic;
ltms : out std_ulogic;
ltdi : out std_ulogic;
ltdo : in std_ulogic;
ltdoen : in std_ulogic
);
end;
architecture rtl of pads is
signal vcc,gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
------------------------------------------------------------------------------
-- Clocking and clock pads
------------------------------------------------------------------------------
reset_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => resetn_padfilter,
strength => padstrength)
port map (
pad => resetn,
o => lresetn);
clk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => clk,
o => lclk);
clksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => clksel,
o => lclksel);
spwclk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => spw_clk,
o => lspw_clk);
spwclksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => spw_clksel,
o => lspw_clksel);
------------------------------------------------------------------------------
-- Test / Misc pads
------------------------------------------------------------------------------
wdogn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => wdogn,
en => lwdogn,
i => gnd);
testen_pad : inpad
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => testen_padfilter,
strength => padstrength)
port map(
pad => testen,
o => ltesten);
lockpad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => lock,
i => llock);
errorn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => errorn,
en => lerrorn,
i => gnd);
------------------------------------------------------------------------------
-- JTAG pads
------------------------------------------------------------------------------
trst_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => trst,
o => ltrst);
tck_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tck,
o => ltck);
tms_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tms,
o => ltms);
tdi_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tdi,
o => ltdi);
tdo_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => jtag_padstrength)
port map (
pad => tdo,
i => ltdo);
------------------------------------------------------------------------------
-- DSU pads
------------------------------------------------------------------------------
dsuen_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsuen,
o => ldsuen);
dsubre_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsubre,
o => ldsubre);
dsuact_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsuact,
i => ldsuact);
dsurx_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsurx,
o => ldsurx);
dsutx_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsutx,
i => ldsutx);
------------------------------------------------------------------------------
-- UART pads
------------------------------------------------------------------------------
rxd1_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd1,
o => lrxd1);
txd1_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd1,
i => ltxd1);
rxd2_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd2,
o => lrxd2);
txd2_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd2,
i => ltxd2);
------------------------------------------------------------------------------
-- SPI pads
------------------------------------------------------------------------------
miso_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map(
pad => spi_miso,
o => lspi_miso);
mosi_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_mosi,
i => lspi_mosi);
sck_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_sck,
i => lspi_sck);
slvsel_pad : outpadv
generic map (
width => CFG_SPICTRL_SLVS,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => spi_slvsel,
i => lspi_slvsel);
------------------------------------------------------------------------------
-- I2C pads
------------------------------------------------------------------------------
scl_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_scl,
i => li2c_sclout,
en => li2c_sclen,
o => li2c_sclin);
sda_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_sda,
i => li2c_sdaout,
en => li2c_sdaen,
o => li2c_sdain);
------------------------------------------------------------------------------
-- Memory Interface pads
------------------------------------------------------------------------------
addr_pad : outpadv generic map (width => 28, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (address, laddress);
data_pad : iopadvv generic map (width => 32, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => data, i => ldataout, en => ldataen, o => ldatain);
rams_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramsn, lramsn);
roms_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (romsn, lromsn);
ramoen_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramoen, lramoen);
rwen_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (rwen, lrwen);
oen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (oen, loen);
wri_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (writen, lwriten);
read_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (read, lread);
iosn_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (iosn, liosn);
cb_pad : iopadvv generic map (width => 8, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => cb, i => lcbout, en => lcben, o => lcbin);
sdpads : if CFG_MCTRL_SDEN = 1 generate
sdclk_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdclk, lsdclk);
sdwen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdwen, lsdwen);
sdras_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdrasn, lsdrasn);
sdcas_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcasn, lsdcasn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sddqm, lsddqm);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcsn, lsdcsn);
end generate;
brdyn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => brdyn,
o => lbrdyn);
bexcn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => bexcn,
o => lbexcn);
prom32_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => prom32,
o => lprom32);
------------------------------------------------------------------------------
-- GPIO pads
------------------------------------------------------------------------------
gpio_pads : iopadvv
generic map (
width => CFG_GRGPIO_WIDTH,
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => gpio,
i => lgpioout,
en => lgpioen,
o => lgpioin);
------------------------------------------------------------------------------
-- SpW pads
------------------------------------------------------------------------------
spwpads0 : if CFG_SPW_EN > 0 generate
spwlvttl_pads : entity work.spw_lvttl_pads
generic map(
padtech => padtech,
strength => spw_padstrength,
input_type => spw_input_type,
voltage => padvoltage,
level => padlevel)
port map(
spw_rxd => spw_rxd,
spw_rxs => spw_rxs,
spw_txd => spw_txd,
spw_txs => spw_txs,
lspw_rxd => lspw_rxd,
lspw_rxs => lspw_rxs,
lspw_txd => lspw_txd,
lspw_txs => lspw_txs);
end generate;
nospwpads0 : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
lspw_rxd <= (others => '0');
lspw_rxs <= (others => '0');
end generate;
------------------------------------------------------------------------------
-- ETHERNET
------------------------------------------------------------------------------
greth1g: if CFG_GRETH1G = 1 generate
gtx_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => gtx_clk,
o => lgtx_clk);
end generate;
nogreth1g: if CFG_GRETH1G = 0 generate
lgtx_clk <= '0';
end generate;
ethpads : if (CFG_GRETH = 1) generate
etxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (etx_clk, letx_clk);
erxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (erx_clk, lerx_clk);
erxd_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 8)
port map (erxd, lerxd);
erxdv_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_dv, lerx_dv);
erxer_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_er, lerx_er);
erxco_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_col, lerx_col);
erxcr_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_crs, lerx_crs);
etxd_pad : outpadv
generic map(
width => 8,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (etxd, letxd);
etxen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_en, letx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_er, letx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdc, lemdc);
emdio_pad : iopad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdio, lemdioout, lemdioen, lemdioin);
emdint_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (emdint, lemdint);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi2ahb.in.vhd | 3 | 688 | -- SPI to AHB bridge
constant CFG_SPI2AHB : integer := CONFIG_SPI2AHB;
constant CFG_SPI2AHB_APB : integer := CONFIG_SPI2AHB_APB;
constant CFG_SPI2AHB_ADDRH : integer := 16#CONFIG_SPI2AHB_ADDRH#;
constant CFG_SPI2AHB_ADDRL : integer := 16#CONFIG_SPI2AHB_ADDRL#;
constant CFG_SPI2AHB_MASKH : integer := 16#CONFIG_SPI2AHB_MASKH#;
constant CFG_SPI2AHB_MASKL : integer := 16#CONFIG_SPI2AHB_MASKL#;
constant CFG_SPI2AHB_RESEN : integer := CONFIG_SPI2AHB_RESEN;
constant CFG_SPI2AHB_FILTER : integer := CONFIG_SPI2AHB_FILTER;
constant CFG_SPI2AHB_CPOL : integer := CONFIG_SPI2AHB_CPOL;
constant CFG_SPI2AHB_CPHA : integer := CONFIG_SPI2AHB_CPHA;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/gr1553b/gr1553b_pads.vhd | 1 | 5018 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_pads
-- File: gr1553b_pads.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Pad instantiations for GR1553B
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
library techmap;
use techmap.gencomp.all;
entity gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_pads is
begin
outin_gen: if outen_pol /= 0 generate
busa_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txin);
busb_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txin);
end generate;
outen_gen: if outen_pol = 0 generate
busa_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txen);
busb_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txen);
end generate;
busa_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busainen, txout.busA_rxen);
busa_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainp, rxin.busA_rxP);
busa_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainn, rxin.busA_rxN);
busa_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutp, txout.busA_txP);
busa_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutn, txout.busA_txN);
busb_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busbinen, txout.busB_rxen);
busb_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinp, rxin.busB_rxP);
busb_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinn, rxin.busB_rxN);
busb_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutp, txout.busB_txP);
busb_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutn, txout.busB_txN);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc6s/config.vhd | 1 | 9317 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-kc705/ahbrom.vhd | 18 | 8961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800015";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE1B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800005";
when 16#00074# => romdata <= X"03200000";
when 16#00075# => romdata <= X"0539A81B";
when 16#00076# => romdata <= X"8410A260";
when 16#00077# => romdata <= X"C4204000";
when 16#00078# => romdata <= X"05000080";
when 16#00079# => romdata <= X"82100000";
when 16#0007A# => romdata <= X"80A0E000";
when 16#0007B# => romdata <= X"02800005";
when 16#0007C# => romdata <= X"01000000";
when 16#0007D# => romdata <= X"82004002";
when 16#0007E# => romdata <= X"10BFFFFC";
when 16#0007F# => romdata <= X"8620E001";
when 16#00080# => romdata <= X"3D1003FF";
when 16#00081# => romdata <= X"BC17A3E0";
when 16#00082# => romdata <= X"BC278001";
when 16#00083# => romdata <= X"9C27A060";
when 16#00084# => romdata <= X"03100000";
when 16#00085# => romdata <= X"81C04000";
when 16#00086# => romdata <= X"01000000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/ddr2if.vhd | 1 | 9430 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
ahbbits: integer := ahbdw;
burstlen: integer := 8
);
port (
pll_ref_clk : in std_ulogic;
global_reset_n : in std_ulogic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(1 downto 0);
mem_ck_n : out std_logic_vector(1 downto 0);
mem_cke : out std_logic;
mem_cs_n : out std_logic;
mem_dm : out std_logic_vector(7 downto 0);
mem_ras_n : out std_logic;
mem_cas_n : out std_logic;
mem_we_n : out std_logic;
mem_dq : inout std_logic_vector(63 downto 0);
mem_dqs : inout std_logic_vector(7 downto 0);
mem_dqs_n : inout std_logic_vector(7 downto 0);
mem_odt : out std_logic;
ahb_clk : in std_ulogic;
ahb_rst : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
oct_rdn : in std_logic;
oct_rup : in std_logic
);
end;
architecture rtl of ddr2if is
component ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end component ddr2ctrl;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr : std_logic_vector(1 downto 0);
signal ras_n_arr, cas_n_arr, we_n_arr, odt_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
signal rdata, wdata : std_logic_vector(255 downto 0);
signal be: std_logic_vector(31 downto 0);
begin
vcc <= '1';
mem_ras_n <= ras_n_arr(0);
mem_cas_n <= cas_n_arr(0);
mem_we_n <= we_n_arr(0);
mem_ck <= ck_p_arr;
mem_ck_n <= ck_n_arr;
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_odt <= odt_arr(0);
avlso.rdata(255 downto 0) <= rdata(255 downto 0);
wdata <= avlsi.wdata(255 downto 0);
be <= avlsi.be(31 downto 0);
ctrl0: ddr2ctrl
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => ras_n_arr,
mem_cas_n => cas_n_arr,
mem_we_n => we_n_arr,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => rdata,
avl_wdata => wdata,
avl_be => be,
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size,
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rdn => oct_rdn,
oct_rup => oct_rup
);
avlso.rdata(avlso.rdata'high downto 256) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
ahbbits => ahbbits,
avldbits => 256,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-2.0 |
o11c/ctags | Test/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc7z020/ahbrom.vhd | 3 | 8224 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800018";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E148";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"10800004";
when 16#00051# => romdata <= X"FD18C000";
when 16#00052# => romdata <= X"00000000";
when 16#00053# => romdata <= X"00000000";
when 16#00054# => romdata <= X"87444000";
when 16#00055# => romdata <= X"8730E01C";
when 16#00056# => romdata <= X"8688E00F";
when 16#00057# => romdata <= X"1280000B";
when 16#00058# => romdata <= X"03200000";
when 16#00059# => romdata <= X"82106300";
when 16#0005A# => romdata <= X"84102052";
when 16#0005B# => romdata <= X"C4206004";
when 16#0005C# => romdata <= X"C4206000";
when 16#0005D# => romdata <= X"C0206008";
when 16#0005E# => romdata <= X"84103FFF";
when 16#0005F# => romdata <= X"C4206014";
when 16#00060# => romdata <= X"84102007";
when 16#00061# => romdata <= X"C4206008";
when 16#00062# => romdata <= X"05000080";
when 16#00063# => romdata <= X"82100000";
when 16#00064# => romdata <= X"80A0E000";
when 16#00065# => romdata <= X"02800005";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"82004002";
when 16#00068# => romdata <= X"10BFFFFC";
when 16#00069# => romdata <= X"8620E001";
when 16#0006A# => romdata <= X"3D1003FF";
when 16#0006B# => romdata <= X"BC17A3E0";
when 16#0006C# => romdata <= X"BC278001";
when 16#0006D# => romdata <= X"9C27A060";
when 16#0006E# => romdata <= X"03100000";
when 16#0006F# => romdata <= X"81C04000";
when 16#00070# => romdata <= X"01000000";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml403/config.vhd | 1 | 6455 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml403/leon3mp.vhd | 1 | 26058 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
--pragma translate_off
plb_error : out std_logic; -- ERRORn
--pragma translate_on
opb_error : out std_logic; -- DSU active
sram_flash_addr : out std_logic_vector(20 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 3);
vid_g : out std_logic_vector(7 downto 3);
vid_b : out std_logic_vector(7 downto 3);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
g1clk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
clklock <= lock and cgo2.clklock;
end generate;
nog1clk : if CFG_GRETH1G = 0 generate
clklock <= lock;
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
--pragma translate_off
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
--pragma translate_on
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(13) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(13) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (sram_flash_addr, memo.address(22 downto 2));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(13) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_r(7 downto 3), vgao.video_out_r(7 downto 3));
video_out_g_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_g(7 downto 3), vgao.video_out_g(7 downto 3));
video_out_b_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_b(7 downto 3), vgao.video_out_b(7 downto 3));
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/prgmem.vhd | 3 | 5738 | ------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-- ROM. The ROM is located in upper part of program memory
-- and is initialized by the given (intel-).hex-file.
-- If there's no such file, everything is filled up with
-- 'null'. Everything before the ROM is always nulled.
-- If you don't want a System-ROM, just set ROM_BITS to 0.
entity prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
reset : in std_logic;
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end entity;
architecture Behavioral of prgmem is
-- some constants
constant MEM_DEPTH : positive := 2**PRGM_MEM;
-- constant MEM_WIDTH : positive := ;
-- constant ROM_DEPTH : positive := 2**ROM_BITS ;
-- constant ROM_POS : integer := rom_start(PRGM_MEM, ROM_BITS);
-- declare memory type
type MEM_TYPE is array(0 to MEM_DEPTH - 1) of std_logic_vector(MEM_WIDTH-1 downto 0);
type BYTE_STRING is array(1 downto 0) of character;
type WORD_STRING is array(3 downto 0) of character;
function CHAR_TO_INT ( char : in character) return integer is
variable r : integer := 0;
begin
case char is
when 'A' => r := 10;
when 'B' => r := 11;
when 'C' => r := 12;
when 'D' => r := 13;
when 'E' => r := 14;
when 'F' => r := 15;
when 'a' => r := 10;
when 'b' => r := 11;
when 'c' => r := 12;
when 'd' => r := 13;
when 'e' => r := 14;
when 'f' => r := 15;
when '1' => r := 1;
when '2' => r := 2;
when '3' => r := 3;
when '4' => r := 4;
when '5' => r := 5;
when '6' => r := 6;
when '7' => r := 7;
when '8' => r := 8;
when '9' => r := 9;
when others => null;
end case;
return r;
end function;
function BYTE_TO_INT ( bytechars : in string(1 to 2)) return integer is
begin
return CHAR_TO_INT(bytechars(1))*16+CHAR_TO_INT(bytechars(2));
end function;
function WORD_TO_INT ( wordchars : in string(1 to 4)) return integer is
begin
return BYTE_TO_INT(wordchars(1) & wordchars(2))*256+BYTE_TO_INT(wordchars(3) & wordchars(4));
end function;
-- function for loading the init values
impure function InitRamFromFile (file_name : in string) return MEM_TYPE is
FILE init_file : text;-- is in file_name;
variable rline : line;
variable memory : MEM_TYPE;
-- variable offs : integer := 0;
variable count : integer;
variable linemode : integer;
variable addr : integer;
variable tmp_chr : character;
variable tmp_byte : string(1 to 2);--BYTE_STRING;
variable tmp_word : string(1 to 4);--WORD_STRING;
variable tmp_addr : integer;
variable tmp_v : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
-- first just null everything
for i in 0 to MEM_DEPTH-1 loop
memory(i) := (others => '0');
end loop;
file_open(init_file, file_name, READ_MODE);
-- read rom file
while (not endfile(init_file)) loop
readline (init_file, rline);
exit when endfile (init_file);
read (rline, tmp_chr);
if tmp_chr = ':' then --beginning of line is correct
--how much to read
read (rline, tmp_byte);
count := BYTE_TO_INT(tmp_byte);
--addr
read (rline, tmp_word);
addr := WORD_TO_INT(tmp_word);
--line mode
read (rline, tmp_byte);
linemode := BYTE_TO_INT(tmp_byte);
if linemode = 0 then
-- loop every PROGRAM-WORD
for i in 0 to (count/(MEM_WIDTH/8) - 1) loop
tmp_v := (others=>'0');
-- loop for every BYTE IN PROGRAM-WORD
for j in 0 to MEM_WIDTH/8-1 loop
read (rline, tmp_byte);
tmp_v((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned(BYTE_TO_INT(tmp_byte),8));
end loop;
-- store in memory
memory(addr/(MEM_WIDTH/8) + i) := tmp_v;
end loop;
end if;
end if;
end loop;
file_close(init_file);
return memory;
end function;
-- define memory and initialize it
signal memory : MEM_TYPE := InitRamFromFile(INIT_FILE_NAME);
signal mem_addr : std_logic_vector(PRGM_MEM-1 downto 0);
signal mem_doa : std_logic_vector(15 downto 0);
signal mem_we : std_logic;
-- output register
signal reg_cmd_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_const_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_lpmspm : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
mem_addr <= addr;
---------------------------------------------------
-- infering the block ram
process(clk)
begin
if clk'event and clk = '1' then
data <= memory(to_integer(unsigned(addr)));
end if;
end process;
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/leon3/l3stat.in.vhd | 1 | 203 | -- LEON3 Statistics Module
constant CFG_L3S_ENABLE : integer := CONFIG_L3S_ENABLE;
constant CFG_L3S_CNT : integer := CONFIG_L3S_CNT;
constant CFG_L3S_NMAX : integer := CONFIG_L3S_NMAX;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-kc705/ddr_dummy.vhd | 8 | 5346 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2012 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Package: ddr_dummy
-- File:ddr_dummy.vhd
-- Author:Fredrik Ringhage - Gaisler Research
-- Description: Xilinx MIG wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
library work;
entity ddr_dummy is
generic (
USE_MIG_INTERFACE_MODEL : boolean := false;
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
BANK_WIDTH : integer := 3; -- # of bank address
CKE_WIDTH : integer := 1; -- # of clock enable outputs
CS_WIDTH : integer := 1; -- # of chip select
DM_WIDTH : integer := 8; -- # of data mask
DQ_WIDTH : integer := 64; -- # of data bits
DQS_WIDTH : integer := 8; -- # of strobe pairs
ODT_WIDTH : integer := 1; -- # of ODT outputs
ROW_WIDTH : integer := 14 -- # of row/column address
);
port (
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0)
);
end;
architecture rtl of ddr_dummy is
component OBUF generic (IOSTANDARD : string := "SSTL15");
port (O : out std_ulogic; I : in std_ulogic);
end component;
component IOBUF generic (IOSTANDARD : string := "SSTL15_T_DCI");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
end component;
component OBUFDS generic(IOSTANDARD : string := "DIFF_SSTL15");
port(O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component IOBUFDS generic (IOSTANDARD : string := "DIFF_SSTL15");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic);
end component;
signal in_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal in_dqs : std_logic_vector(DQS_WIDTH-1 downto 0);
begin
io_cas : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cas_n, I => '0');
io_ras : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ras_n, I => '0');
io_we : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_we_n, I => '0');
io_ck : OBUFDS generic map (IOSTANDARD => "DIFF_SSTL15")
port map (O => ddr_ck_p(0), OB => ddr_ck_n(0), I => '0');
io_addr_gen : for i in 0 to ROW_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_addr(i), I => '0');
end generate io_addr_gen;
io_ba_gen : for i in 0 to BANK_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ba(i), I => '0');
end generate io_ba_gen;
io_cs_gen : for i in 0 to CS_WIDTH*nCS_PER_RANK-1 generate
begin
io_cs : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cs_n(i), I => '0');
end generate io_cs_gen;
io_odt_gen : for i in 0 to ODT_WIDTH-1 generate
begin
io_odt : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_odt(i), I => '0');
end generate io_odt_gen;
io_dm_gen : for i in 0 to DM_WIDTH-1 generate
begin
io_dm : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_dm(i), I => '0');
end generate io_dm_gen;
io_cke_gen : for i in 0 to CKE_WIDTH-1 generate
begin
io_cke : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cke(i), I => '0');
end generate io_cke_gen;
op_reset : OBUF generic map (IOSTANDARD => "LVCMOS15")
port map (O => ddr_reset_n, I => '1');
io_dq_gen : for i in 0 to DQ_WIDTH-1 generate
begin
io_dq : IOBUF generic map (IOSTANDARD => "SSTL15_T_DCI")
port map (O => in_dq(i), IO => ddr_dq(i), I => '0', T => '0');
end generate io_dq_gen;
io_dqs_gen : for i in 0 to DQS_WIDTH-1 generate
begin
io_dqs : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL15_T_DCI")
port map (O => in_dqs(i), IO => ddr_dqs(i), IOB => ddr_dqs_n(i), I => '0', T => '1');
end generate io_dqs_gen;
end architecture rtl; | gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xup/leon3mp.vhd | 1 | 23418 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/memctrl.vhd | 1 | 20513 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0;
brdynto : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component p8ctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 0;
iomask : integer := 16#ff0#;
ioaddr : integer := 0;
rammask : integer := 16#ff0#;
romws : integer := 15;
ramws : integer := 15;
prom8en : integer := 0;
rmw : integer := 0;
oepol : integer := 0;
romasel : integer range 0 to 28 := 23
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ambatest/ahbtbm.vhd | 1 | 14280 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbm
-- File: ahbtbm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.ahbtbp.all;
entity ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of ahbtbm is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
-- new /*
grant : std_logic;
grant2 : std_logic;
retry : std_logic_vector(1 downto 0);
read : std_logic; -- indicate
dbgl : integer;
use128 : integer;
hsize : std_logic_vector(2 downto 0);
ac : ahbtbm_access_array_type;
retryac : ahbtbm_access_type;
curac : ahbtbm_access_type;
haddr : std_logic_vector(31 downto 0); -- addr current access
hdata : std_logic_vector(31 downto 0); -- data currnet access
hdata128 : std_logic_vector(127 downto 0); -- data currnet access
hwrite : std_logic; -- write current access
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
dvalid : std_logic;
oldhtrans : std_logic_vector(1 downto 0);
-- new */
start : std_ulogic;
active : std_ulogic;
end record;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal r, rin : reg_type;
begin
ctrlo.rst <= rst;
ctrlo.clk <= clk;
comb : process(ahbmi, ctrli, rst, r)
-- new /*
variable v : reg_type;
variable update : std_logic;
variable hbusreq : std_ulogic; -- bus request
variable kblimit : std_logic; -- 1 kB limit indicator
-- new */
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- new /*
v := r; update := '0'; hbusreq := '0';--v.retry := '0';
v.dvalid := '0'; xhirq := (others => '0');
hprot := "1110";
--v.hrdata := ahbmi.hrdata;
--v.hrdata128 := ahbmi.hrdata128;
v.hrdata := ahbmi.hrdata(31 downto 0);
v.hrdata128 := ahbread4word(ahbmi.hrdata);
-- pragma translate_off
if ahbmi.hready = '1' and ahbmi.hresp = HRESP_ERROR then
v.hrdata := (others => 'X');
v.hrdata128 := (others => 'X');
end if;
-- pragma translate_on
v.status.err := '0';
--v.oldhtrans := r.ac(1).htrans;
kblimit := '0';
-- Sample grant when hready
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
v.grant2 := r.grant;
v.oldhtrans := r.ac(1).htrans;
end if;
-- 1k limit
if (r.ac(0).htrans = HTRANS_SEQ
and (r.ac(0).haddr(10) xor r.ac(1).haddr(10)) = '1')
or (r.retryac.htrans = HTRANS_SEQ
and (r.retryac.haddr(10) xor r.ac(1).haddr(10)) = '1' and r.retry = "10") then
kblimit := '1';
end if;
-- Read in new access
--if ((ahbmi.hready = '1' and ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = '0' then
--if ahbmi.hready = '1' and ((ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
if ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif ahbmi.hready = '1' and ( r.grant = '1'
or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
-- elsif ahbmi.hready = '1' and (( r.grant = '1' and
-- (ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR))
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
v.ac(1) := r.ac(0); v.ac(0) := ctrli.ac;
v.curac := r.ac(1);
v.hdata := r.ac(1).hdata; v.haddr := r.ac(1).haddr;
v.hwrite := r.ac(1).hwrite; v.dbgl := r.ac(1).ctrl.dbgl;
v.use128 := r.ac(1).ctrl.use128;
if v.use128 = 0 then
v.hdata128 := r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata;
else
v.hdata128 := r.ac(1).hdata128;
end if;
v.hsize := r.ac(1).hsize;
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
update := '1';
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
elsif ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif r.retry = "01" then
v.ac(1).htrans := HTRANS_NONSEQ;
v.ac(1).hburst := r.curac.hburst;
v.read := '0';
v.retry := "10";
elsif ahbmi.hready = '1' and r.grant = '1' and r.retry = "10" then
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
--if ahbmi.hresp = HRESP_OKAY then
--if ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
v.retry := "00";
--end if;
end if;
-- NONSEQ in retry
--if r.retry = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
-- NONSEQ if burst is interrupted
if r.grant = '0' and r.ac(1).htrans = HTRANS_SEQ then
v.ac(1).htrans := HTRANS_NONSEQ;
end if;
--if r.ac(1).htrans /= HTRANS_IDLE or r.ac(0).htrans /= HTRANS_IDLE then
-- hbusreq := '1';
--end if;
if r.ac(1).htrans = HTRANS_NONSEQ
or (r.ac(1).htrans = HTRANS_SEQ
and r.ac(0).htrans /= HTRANS_NONSEQ and kblimit = '0') then
hbusreq := '1';
end if;
--if r.grant = '0' then -- fix dvalid if grant deasserted *** ???
if r.grant = '0' and ahbmi.hready = '1' then
v.read := '0';
end if;
-- Check read data
if r.read = '1' and ahbmi.hresp = HRESP_OKAY and ahbmi.hready = '1' then
v.dvalid := '1';
if r.use128 = 0 then
--if r.hdata /= ahbmi.hrdata then
if r.hdata /= ahbmi.hrdata(31 downto 0) then
v.status.err := '1';
end if;
else
if r.hsize = "100" then
--if r.hdata128 /= ahbmi.hrdata128 then
if r.hdata128 /= ahbread4word(ahbmi.hrdata) then
v.status.err := '1';
end if;
else
--if r.hdata128(63 downto 0) /= ahbmi.hrdata128(63 downto 0) then
--if r.hdata128(63 downto 0) /= ahbmi.hrdata(63 downto 0) then
if r.hdata128(63 downto 0) /= ahbreaddword(ahbmi.hrdata) then
v.status.err := '1';
end if;
end if;
end if;
elsif r.read = '1' and ahbmi.hresp = HRESP_ERROR and ahbmi.hready = '1' then
v.status.err := '1';
end if;
-- new */
if rst = '0' then
v.ac(0).htrans := (others => '0');
v.ac(1).htrans := (others => '0');
v.retry := (others => '0');
v.read := '0';
v.ac(1).haddr := (others => '0');
v.ac(1).htrans := (others => '0');
v.ac(1).hwrite := '0';
v.ac(1).hsize := (others => '0');
v.ac(1).hburst := (others =>'0');
end if;
rin <= v;
ctrlo.update <= update;
ctrlo.status <= r.status;
ctrlo.hrdata <= r.hrdata;
ctrlo.hrdata128 <= r.hrdata128;
ctrlo.dvalid <= r.dvalid;
ahbmo.haddr <= r.ac(1).haddr;
ahbmo.htrans <= r.ac(1).htrans;
ahbmo.hbusreq <= hbusreq;
--ahbmo.hwdata <= r.hdata;
--ahbmo.hwdata128 <= r.hdata128;
ahbmo.hwdata <= ahbdrivedata(r.hdata128);
ahbmo.hconfig <= hconfig;
ahbmo.hlock <= '0';
ahbmo.hwrite <= r.ac(1).hwrite;
ahbmo.hsize <= r.ac(1).hsize;
ahbmo.hburst <= r.ac(1).hburst;
ahbmo.hprot <= r.ac(1).hprot;
ahbmo.hirq <= xhirq;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
-- pragma translate_off
if r.read = '1' and ahbmi.hready = '1' then --and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if rin.status.err = '0' then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0)));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))); end if;
end if;
end if;
else
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0))
& " != " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata)
& " != " & tost(r.hdata128));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))
& " != " & tost(r.hdata128(63 downto 0)));
end if;
end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [RETRY]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
print(ptime & "Read[" & tost(r.haddr) & "]: [ERROR]");
end if;
end if;
end if;
if r.hwrite = '1' and ahbmi.hready = '1' and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128));
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0))); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [RETRY]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [RETRY]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [RETRY]"); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [ERROR]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [ERROR]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [ERROR]"); end if;
end if;
end if;
end if;
end if;
-- pragma translate_on
end if;
end process;
end;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/examples/vams/vhdl/basic-vhdl/spice_cs.vhdl | 15 | 406 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY SPICE_cs IS
GENERIC ( N : REAL := 10.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal llt : electrical;
terminal ult : electrical;
terminal lrt : electrical;
terminal urt : electrical );
END ENTITY SPICE_cs;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/sim/ser_phy.vhd | 1 | 5782 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ser_phy
-- File: ser_phy.vhd
-- Description: Serial wrapper for simulation model of an Ethernet PHY
-- Author: Andrea Gianarro
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use gaisler.net.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
entity ser_phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0
);
port(
rstn : in std_logic;
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : out std_logic;
eth_rx_n : out std_logic;
eth_tx_p : in std_logic;
eth_tx_n : in std_logic := '0';
mdio : inout std_logic;
mdc : in std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end;
architecture behavioral of ser_phy is
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
signal phy_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal phy_etho : eth_out_type;
signal pcs_etho : eth_out_type;
begin
p0: phy
generic map(
address => address,
extended_regs => extended_regs,
aneg => aneg,
fd_10 => fd_10,
hd_10 => hd_10,
base100_t4 => base100_t4,
base100_x_fd => base100_x_fd,
base100_x_hd => base100_x_hd,
base100_t2_fd => base100_t2_fd,
base100_t2_hd => base100_t2_hd,
base1000_x_fd => base1000_x_fd,
base1000_x_hd => base1000_x_hd,
base1000_t_fd => base1000_t_fd,
base1000_t_hd => base1000_t_hd,
rmii => 0,
rgmii => 0
)
port map(
rstn => rstn,
mdio => mdio,
tx_clk => open,
rx_clk => open,
rxd => phy_etho.txd,
rx_dv => phy_etho.tx_en,
rx_er => phy_etho.tx_er,
rx_col => open,
rx_crs => open,
txd => phy_ethi.rxd,
tx_en => phy_ethi.rx_dv,
tx_er => phy_ethi.rx_er,
mdc => mdc,
gtx_clk => phy_ethi.gtx_clk
);
-- GMII to MII adapter fixed to Gigabit mode (disabled)
phy_etho.gbit <= '1';
phy_etho.speed <= '0';
adapt_10_100_0: gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => phy_ethi, -- OUT
gmiio => phy_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
pcs0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_tx_p,
ser_rx_n => eth_tx_n,
ser_tx_p => eth_rx_p,
ser_tx_n => eth_rx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
mdc => mdc,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
end architecture;
-- pragma translate_on | gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/lpddr2if.vhd | 1 | 8374 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys3/ahbrom.vhd | 6 | 3101 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp601/ahbrom.vhd | 6 | 3101 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/techmult.vhd | 1 | 7825 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: techmult
-- File: techmult.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.multlib.all;
library techmap;
use techmap.allmul.all;
use techmap.gencomp.all;
entity techmult is
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : natural := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of techmult is
signal gnd, vcc : std_ulogic;
-- pragma translate_off
signal pres : std_ulogic := '0';
signal sonly : std_ulogic := '0';
-- pragma translate_on
begin
gnd <= '0'; vcc <= '1';
np : if num_stages = 1 generate
arch0 : if (arch = 0) generate --inferred
product <= mixed_mul(a, b, sign);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch1 : if (arch = 1) generate -- modgen
m1717 : if (a_width = 17) and (b_width = 17) generate
m17 : mul_17_17 generic map (mulpipe => 0)
port map (clk, vcc, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3317 : if (a_width = 33) and (b_width = 17) generate
m33 : mul_33_17 port map (a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m339 : if (a_width = 33) and (b_width = 9) generate
m33 : mul_33_9 port map (a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3333 : if (a_width = 33) and (b_width = 33) generate
m33 : mul_33_33 generic map (mulpipe => 0)
port map (clk, vcc, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
mgen : if not(((a_width = 17) and (b_width = 17)) or
((a_width = 33) and (b_width = 33)) or
((a_width = 33) and (b_width = 17)) or
((a_width = 33) and (b_width = 9)))
generate
product <= mixed_mul(a, b, sign);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
arch2 : if (arch = 2) generate --techspec
axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate
m33 : axcel_mul_33x33_signed generic map (pipe => 0)
port map (a, b, vcc, clk, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => 1, stall_mode => 0)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
pipe2 : if num_stages = 2 generate
arch0 : if (arch = 0) generate -- inferred
dwm : gen_mult_pipe
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, tc => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch1 : if (arch = 1) generate -- modgen
m1717 : if (a_width = 17) and (b_width = 17) generate
m17 : mul_17_17 generic map (mulpipe => 1)
port map (clk, en, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
m3333 : if (a_width = 33) and (b_width = 33) generate
m33 : mul_33_33 generic map (mulpipe => 1)
port map (clk, en, a, b, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch2 : if (arch = 2) generate --techspec
axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate
m33 : axcel_mul_33x33_signed generic map (pipe => 1)
port map (a, b, en, clk, product);
-- pragma translate_off
pres <= '1'; sonly <= '1';
-- pragma translate_on
end generate;
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
pipe3 : if num_stages > 2 generate
arch0 : if (arch = 0) generate -- inferred
dwm : gen_mult_pipe
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, tc => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
arch3 : if (arch = 3) generate -- designware
dwm : mul_dw
generic map (a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode)
port map (a => a, b => b, clk => clk, en => en, sign => sign,
product => product);
-- pragma translate_off
pres <= '1';
-- pragma translate_on
end generate;
end generate;
-- pragma translate_off
process begin
wait for 5 ns;
assert pres = '1' report "techmult: configuration not supported. (width " &
tost(a_width) & "x" & tost(b_width) & ", tech " & tost(tech) & ", arch " &
tost(arch) & ")"
severity failure;
wait;
end process;
process begin
wait for 5 ns;
assert not ((sonly = '1') and (sign = '0')) report "techmult: unsinged multiplication for this configuration not supported"
severity failure;
if sonly = '1' then wait on sign; else wait; end if;
end process;
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/sim/sdrtestmod.vhd | 1 | 5688 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdrtestmod
-- File: sdrtestmod.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Test report module with SDRAM interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.sim.all;
entity sdrtestmod is
generic (
width: integer := 32; -- 32-bit or 64-bit supported
bank: integer range 0 to 3 := 0;
row: integer := 0;
halt: integer range 0 to 1 := 1;
swwidth: integer := 32 -- Internal reportdev size, can be 32/64
);
port (
clk: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
ba: in std_logic_vector(1 downto 0);
addr: in std_logic_vector(12 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqm: in std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of sdrtestmod is
begin
dq <= (others => 'Z');
p: process(clk)
variable modereg: std_logic_vector(12 downto 0);
variable myrow: boolean := false;
variable wrburst: integer := 0;
variable wrcol: integer;
variable i,j,k: integer;
variable d: std_logic_vector(31 downto 0);
variable errcnt, vendorid, deviceid : integer;
procedure write_main(addr: integer; d: std_logic_vector) is
variable errno, subtest : integer;
begin
case i is
when 0 =>
vendorid := conv_integer(d(31 downto 24));
deviceid := conv_integer(d(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when 1 =>
errno := conv_integer(d(15 downto 0));
if (halt = 1) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when 2 =>
subtest := conv_integer(d(7 downto 0));
call_subtest(vendorid, deviceid, subtest);
when 4 =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when 5 =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when 6 =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(d(15 downto 0))));
when 7 =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end write_main;
begin
if rising_edge(clk) then
if csn='0' then
if rasn='0' and casn='0' and wen='0' then
modereg := addr;
elsif rasn='0' and casn='1' and wen='1' then
if ba=conv_std_logic_vector(bank,2) and addr=conv_std_logic_vector(row,13) then
myrow := true;
else
myrow := false;
end if;
elsif rasn='1' and casn='0' and wen='0' then
if myrow then
if modereg(9)='0' and modereg(2 downto 0)="001" then
wrburst := 2;
elsif modereg(9)='0' and modereg(2 downto 0)="010" then
wrburst := 4;
elsif modereg(9)='0' and (modereg(2 downto 0)="011" or modereg(2)='1') then
wrburst := 8;
else
wrburst := 1;
end if;
wrcol := conv_integer(addr(7 downto 0));
end if;
elsif rasn='0' and casn='1' and wen='0' then
if ba=conv_std_logic_vector(bank,2) or addr(10)='1' then
myrow := false;
wrburst := 0;
end if;
end if;
end if;
if wrburst > 0 then
for x in 0 to (width/32)-1 loop
if width=32 and swwidth=64 and (wrcol mod 2 < 1) then next; end if;
if width=64 and swwidth=64 and x=0 then next; end if;
if dqm(width/8-1-x*4 downto width/8-4-x*4) = "0000" then
i := (wrcol*width)/swwidth + (x*32)/swwidth;
d := dq(width-1-x*32 downto width-32-x*32);
if d /= x"DEADBEEF" then
write_main(i,d);
end if;
end if;
end loop;
wrburst := wrburst-1;
wrcol := wrcol+1;
end if;
end if;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/adq_dqs/dq_dqs_inst.vhd | 3 | 37991 | --altdq_dqs CBX_SINGLE_OUTPUT_FILE="ON" DELAY_BUFFER_MODE="LOW" DELAY_DQS_ENABLE_BY_HALF_CYCLE="FALSE" device_family="stratixiii" DQ_HALF_RATE_USE_DATAOUTBYPASS="FALSE" DQ_INPUT_REG_ASYNC_MODE="NONE" DQ_INPUT_REG_CLK_SOURCE="CORE" DQ_INPUT_REG_MODE="DDIO" DQ_INPUT_REG_POWER_UP="HIGH" DQ_INPUT_REG_SYNC_MODE="NONE" DQ_INPUT_REG_USE_CLKN="FALSE" DQ_IPA_ADD_INPUT_CYCLE_DELAY="FALSE" DQ_IPA_ADD_PHASE_TRANSFER_REG="FALSE" DQ_IPA_BYPASS_OUTPUT_REGISTER="TRUE" DQ_IPA_INVERT_PHASE="FALSE" DQ_IPA_PHASE_SETTING=0 DQ_OE_REG_ASYNC_MODE="PRESET" DQ_OE_REG_MODE="FF" DQ_OE_REG_POWER_UP="HIGH" DQ_OE_REG_SYNC_MODE="NONE" DQ_OUTPUT_REG_ASYNC_MODE="NONE" DQ_OUTPUT_REG_MODE="DDIO" DQ_OUTPUT_REG_POWER_UP="HIGH" DQ_OUTPUT_REG_SYNC_MODE="NONE" DQS_CTRL_LATCHES_ENABLE="FALSE" DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE="CORE" DQS_DELAY_CHAIN_PHASE_SETTING=0 DQS_DQSN_MODE="DIFFERENTIAL" DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REG="FALSE" DQS_ENABLE_CTRL_INVERT_PHASE="FALSE" DQS_ENABLE_CTRL_PHASE_SETTING=0 DQS_OE_REG_ASYNC_MODE="PRESET" DQS_OE_REG_MODE="DDIO" DQS_OE_REG_POWER_UP="HIGH" DQS_OE_REG_SYNC_MODE="NONE" DQS_OFFSETCTRL_ENABLE="FALSE" DQS_OUTPUT_REG_ASYNC_MODE="NONE" DQS_OUTPUT_REG_MODE="DDIO" DQS_OUTPUT_REG_POWER_UP="LOW" DQS_OUTPUT_REG_SYNC_MODE="NONE" DQS_PHASE_SHIFT=0 IO_CLOCK_DIVIDER_CLK_SOURCE="CORE" IO_CLOCK_DIVIDER_INVERT_PHASE="FALSE" IO_CLOCK_DIVIDER_PHASE_SETTING=0 LEVEL_DQS_ENABLE="FALSE" NUMBER_OF_BIDIR_DQ=8 NUMBER_OF_CLK_DIVIDER=0 NUMBER_OF_INPUT_DQ=0 NUMBER_OF_OUTPUT_DQ=0 OCT_REG_MODE="FF" USE_DQ_INPUT_DELAY_CHAIN="TRUE" USE_DQ_IPA="FALSE" USE_DQ_IPA_PHASECTRLIN="FALSE" USE_DQ_OE_DELAY_CHAIN1="FALSE" USE_DQ_OE_DELAY_CHAIN2="FALSE" USE_DQ_OE_PATH="TRUE" USE_DQ_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQ_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS="TRUE" USE_DQS_DELAY_CHAIN="FALSE" USE_DQS_DELAY_CHAIN_PHASECTRLIN="FALSE" USE_DQS_ENABLE="FALSE" USE_DQS_ENABLE_CTRL="FALSE" USE_DQS_ENABLE_CTRL_PHASECTRLIN="FALSE" USE_DQS_INPUT_DELAY_CHAIN="FALSE" USE_DQS_INPUT_PATH="FALSE" USE_DQS_OE_DELAY_CHAIN1="FALSE" USE_DQS_OE_DELAY_CHAIN2="FALSE" USE_DQS_OE_PATH="TRUE" USE_DQS_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQS_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS_OUTPUT_PATH="TRUE" USE_DQSBUSOUT_DELAY_CHAIN="FALSE" USE_DQSENABLE_DELAY_CHAIN="FALSE" USE_DYNAMIC_OCT="TRUE" USE_HALF_RATE="FALSE" USE_IO_CLOCK_DIVIDER_MASTERIN="FALSE" USE_IO_CLOCK_DIVIDER_PHASECTRLIN="FALSE" USE_OCT_DELAY_CHAIN1="FALSE" USE_OCT_DELAY_CHAIN2="FALSE" bidir_dq_input_data_in bidir_dq_input_data_out_high bidir_dq_input_data_out_low bidir_dq_io_config_ena bidir_dq_oct_in bidir_dq_oct_out bidir_dq_oe_in bidir_dq_oe_out bidir_dq_output_data_in_high bidir_dq_output_data_in_low bidir_dq_output_data_out bidir_dq_sreset config_clk config_datain config_update dq_input_reg_clk dq_output_reg_clk dqs_areset dqs_oct_in dqs_oct_out dqs_oe_in dqs_oe_out dqs_output_data_in_high dqs_output_data_in_low dqs_output_data_out dqs_output_reg_clk dqsn_oct_in dqsn_oct_out dqsn_oe_in dqsn_oe_out oct_reg_clk
--VERSION_BEGIN 8.0SP1 cbx_altdq_dqs 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY altera;
USE altera.all;
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_ddio_in 8 stratixiii_ddio_oe 2 stratixiii_ddio_out 9 stratixiii_delay_chain 8 stratixiii_dqs_config 2 stratixiii_ff 18 stratixiii_io_clock_divider 2 stratixiii_io_config 10
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dq_dqs_inst IS
PORT
(
bidir_dq_input_data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
bidir_dq_input_data_out_high : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bidir_dq_input_data_out_low : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bidir_dq_io_config_ena : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '1');
bidir_dq_oct_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
bidir_dq_oct_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bidir_dq_oe_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
bidir_dq_oe_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bidir_dq_output_data_in_high : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
bidir_dq_output_data_in_low : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
bidir_dq_output_data_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bidir_dq_sreset : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
config_clk : IN STD_LOGIC := '0';
config_datain : IN STD_LOGIC := '0';
config_update : IN STD_LOGIC := '0';
dq_input_reg_clk : IN STD_LOGIC := '0';
dq_output_reg_clk : IN STD_LOGIC := '0';
dqs_areset : IN STD_LOGIC := '0';
dqs_oct_in : IN STD_LOGIC := '0';
dqs_oct_out : OUT STD_LOGIC;
dqs_oe_in : IN STD_LOGIC := '0';
dqs_oe_out : OUT STD_LOGIC;
dqs_output_data_in_high : IN STD_LOGIC := '0';
dqs_output_data_in_low : IN STD_LOGIC := '0';
dqs_output_data_out : OUT STD_LOGIC;
dqs_output_reg_clk : IN STD_LOGIC := '0';
dqsn_oct_in : IN STD_LOGIC := '0';
dqsn_oct_out : OUT STD_LOGIC;
dqsn_oe_in : IN STD_LOGIC := '0';
dqsn_oe_out : OUT STD_LOGIC;
oct_reg_clk : IN STD_LOGIC := '0'
);
END dq_dqs_inst;
ARCHITECTURE RTL OF dq_dqs_inst IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_0_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_1_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_2_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_3_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_4_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_5_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_6_output_ddio_out_inst"" }DQ_GROUP=9;{ -from ""dqs_output_ddio_out_inst"" -to ""bidir_dq_7_output_ddio_out_inst"" }DQ_GROUP=9";
SIGNAL wire_bidir_dq_0_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_0_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_1_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_1_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_2_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_2_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_3_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_3_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_4_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_4_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_5_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_5_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_6_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_6_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_bidir_dq_7_ddio_in_inst_regouthi : STD_LOGIC;
SIGNAL wire_bidir_dq_7_ddio_in_inst_regoutlo : STD_LOGIC;
SIGNAL wire_dqs_oe_ddio_oe_inst_w_lg_dataout1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dqs_oe_ddio_oe_inst_dataout : STD_LOGIC;
SIGNAL wire_dqsn_oe_ddio_oe_inst_w_lg_dataout2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dqsn_oe_ddio_oe_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_0_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_1_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_2_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_3_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_4_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_5_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_6_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_7_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_dqs_output_ddio_out_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_0_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_1_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_2_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_3_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_4_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_5_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_6_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_bidir_dq_7_input_delay_chain_inst_dataout : STD_LOGIC;
SIGNAL wire_dqs_config_0_inst_dividerphasesetting : STD_LOGIC;
SIGNAL wire_dqs_config_1_inst_dividerphasesetting : STD_LOGIC;
SIGNAL wire_bidir_dq_0_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_0_oe_ff_inst_w_lg_q11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_0_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_1_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_1_oe_ff_inst_w_lg_q28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_1_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_2_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_2_oe_ff_inst_w_lg_q41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_2_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_3_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_3_oe_ff_inst_w_lg_q54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_3_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_4_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_4_oe_ff_inst_w_lg_q67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_4_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_5_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_5_oe_ff_inst_w_lg_q80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_5_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_6_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_6_oe_ff_inst_w_lg_q93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_6_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_7_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_bidir_dq_7_oe_ff_inst_w_lg_q106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_bidir_dq_7_oe_ff_inst_q : STD_LOGIC;
SIGNAL wire_dqs_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_dqsn_oct_ff_inst_q : STD_LOGIC;
SIGNAL wire_io_clock_divider_0_inst_slaveout : STD_LOGIC;
SIGNAL wire_bidir_dq_0_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_1_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_2_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_3_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_4_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_5_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_6_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_bidir_dq_7_io_config_inst_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL dqs_config_ena : STD_LOGIC;
SIGNAL dqs_io_config_ena : STD_LOGIC;
SIGNAL dqsn_io_config_ena : STD_LOGIC;
SIGNAL io_clock_divider_clk : STD_LOGIC;
COMPONENT stratixiii_ddio_in
GENERIC
(
async_mode : STRING := "none";
power_up : STRING := "low";
sync_mode : STRING := "none";
use_clkn : STRING := "false";
lpm_type : STRING := "stratixiii_ddio_in"
);
PORT
(
areset : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '0';
clkn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regouthi : OUT STD_LOGIC;
regoutlo : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT stratixiii_ddio_oe
GENERIC
(
async_mode : STRING := "none";
power_up : STRING := "low";
sync_mode : STRING := "none";
lpm_type : STRING := "stratixiii_ddio_oe"
);
PORT
(
areset : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '0';
dataout : OUT STD_LOGIC;
ena : IN STD_LOGIC := '1';
oe : IN STD_LOGIC := '1';
sreset : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT stratixiii_ddio_out
GENERIC
(
async_mode : STRING := "none";
half_rate_mode : STRING := "false";
power_up : STRING := "low";
sync_mode : STRING := "none";
use_new_clocking_model : STRING := "false";
lpm_type : STRING := "stratixiii_ddio_out"
);
PORT
(
areset : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '0';
clkhi : IN STD_LOGIC := '0';
clklo : IN STD_LOGIC := '0';
datainhi : IN STD_LOGIC := '0';
datainlo : IN STD_LOGIC := '0';
dataout : OUT STD_LOGIC;
ena : IN STD_LOGIC := '1';
muxsel : IN STD_LOGIC := '0';
sreset : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT stratixiii_delay_chain
PORT
(
datain : IN STD_LOGIC := '0';
dataout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_dqs_config
PORT
(
clk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dataout : OUT STD_LOGIC;
dividerphasesetting : OUT STD_LOGIC;
dqoutputphaseinvert : OUT STD_LOGIC;
dqoutputphasesetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dqsbusoutdelaysetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dqsenablectrlphaseinvert : OUT STD_LOGIC;
dqsenablectrlphasesetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dqsenabledelaysetting : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
dqsinputphasesetting : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
dqsoutputphaseinvert : OUT STD_LOGIC;
dqsoutputphasesetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ena : IN STD_LOGIC := '1';
enadataoutbypass : OUT STD_LOGIC;
enadqsenablephasetransferreg : OUT STD_LOGIC;
enainputcycledelaysetting : OUT STD_LOGIC;
enainputphasetransferreg : OUT STD_LOGIC;
enaoctcycledelaysetting : OUT STD_LOGIC;
enaoctphasetransferreg : OUT STD_LOGIC;
enaoutputcycledelaysetting : OUT STD_LOGIC;
enaoutputphasetransferreg : OUT STD_LOGIC;
octdelaysetting1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
octdelaysetting2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
resyncinputphaseinvert : OUT STD_LOGIC;
resyncinputphasesetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
update : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT stratixiii_ff
GENERIC
(
--POWER_UP : STRING := "DONT_CARE"; -- *** ???
POWER_UP : STRING := "low";
lpm_type : STRING := "stratixiii_ff"
);
PORT
(
aload : IN STD_LOGIC := '0';
asdata : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '0';
clrn : IN STD_LOGIC := '1';
d : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
q : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT stratixiii_io_clock_divider
GENERIC
(
delay_buffer_mode : STRING := "high";
invert_phase : STRING := "false";
phase_setting : NATURAL := 0;
sim_buffer_delay_increment : NATURAL := 10;
sim_high_buffer_intrinsic_delay : NATURAL := 175;
sim_low_buffer_intrinsic_delay : NATURAL := 350;
use_masterin : STRING := "false";
use_phasectrlin : STRING := "true";
lpm_type : STRING := "stratixiii_io_clock_divider"
);
PORT
(
clk : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
masterin : IN STD_LOGIC := '0';
phasectrlin : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
phaseinvertctrl : IN STD_LOGIC := '0';
phaseselect : IN STD_LOGIC := '0';
slaveout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_io_config
PORT
(
clk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dataout : OUT STD_LOGIC;
ena : IN STD_LOGIC := '1';
outputdelaysetting1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outputdelaysetting2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
padtoinputregisterdelaysetting : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
update : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
bidir_dq_input_data_out_high <= ( wire_bidir_dq_7_ddio_in_inst_regouthi & wire_bidir_dq_6_ddio_in_inst_regouthi & wire_bidir_dq_5_ddio_in_inst_regouthi & wire_bidir_dq_4_ddio_in_inst_regouthi & wire_bidir_dq_3_ddio_in_inst_regouthi & wire_bidir_dq_2_ddio_in_inst_regouthi & wire_bidir_dq_1_ddio_in_inst_regouthi & wire_bidir_dq_0_ddio_in_inst_regouthi);
bidir_dq_input_data_out_low <= ( wire_bidir_dq_7_ddio_in_inst_regoutlo & wire_bidir_dq_6_ddio_in_inst_regoutlo & wire_bidir_dq_5_ddio_in_inst_regoutlo & wire_bidir_dq_4_ddio_in_inst_regoutlo & wire_bidir_dq_3_ddio_in_inst_regoutlo & wire_bidir_dq_2_ddio_in_inst_regoutlo & wire_bidir_dq_1_ddio_in_inst_regoutlo & wire_bidir_dq_0_ddio_in_inst_regoutlo);
bidir_dq_oct_out <= ( wire_bidir_dq_7_oct_ff_inst_q & wire_bidir_dq_6_oct_ff_inst_q & wire_bidir_dq_5_oct_ff_inst_q & wire_bidir_dq_4_oct_ff_inst_q & wire_bidir_dq_3_oct_ff_inst_q & wire_bidir_dq_2_oct_ff_inst_q & wire_bidir_dq_1_oct_ff_inst_q & wire_bidir_dq_0_oct_ff_inst_q);
bidir_dq_oe_out <= ( wire_bidir_dq_7_oe_ff_inst_w_lg_q106w & wire_bidir_dq_6_oe_ff_inst_w_lg_q93w & wire_bidir_dq_5_oe_ff_inst_w_lg_q80w & wire_bidir_dq_4_oe_ff_inst_w_lg_q67w & wire_bidir_dq_3_oe_ff_inst_w_lg_q54w & wire_bidir_dq_2_oe_ff_inst_w_lg_q41w & wire_bidir_dq_1_oe_ff_inst_w_lg_q28w & wire_bidir_dq_0_oe_ff_inst_w_lg_q11w);
bidir_dq_output_data_out <= ( wire_bidir_dq_7_output_ddio_out_inst_dataout & wire_bidir_dq_6_output_ddio_out_inst_dataout & wire_bidir_dq_5_output_ddio_out_inst_dataout & wire_bidir_dq_4_output_ddio_out_inst_dataout & wire_bidir_dq_3_output_ddio_out_inst_dataout & wire_bidir_dq_2_output_ddio_out_inst_dataout & wire_bidir_dq_1_output_ddio_out_inst_dataout & wire_bidir_dq_0_output_ddio_out_inst_dataout);
dqs_config_ena <= '1';
dqs_io_config_ena <= '1';
dqs_oct_out <= wire_dqs_oct_ff_inst_q;
dqs_oe_out <= wire_dqs_oe_ddio_oe_inst_w_lg_dataout1w(0);
dqs_output_data_out <= wire_dqs_output_ddio_out_inst_dataout;
dqsn_io_config_ena <= '1';
dqsn_oct_out <= wire_dqsn_oct_ff_inst_q;
dqsn_oe_out <= wire_dqsn_oe_ddio_oe_inst_w_lg_dataout2w(0);
io_clock_divider_clk <= '0';
bidir_dq_0_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_0_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_0_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_0_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(0)
);
bidir_dq_1_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_1_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_1_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_1_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(1)
);
bidir_dq_2_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_2_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_2_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_2_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(2)
);
bidir_dq_3_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_3_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_3_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_3_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(3)
);
bidir_dq_4_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_4_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_4_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_4_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(4)
);
bidir_dq_5_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_5_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_5_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_5_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(5)
);
bidir_dq_6_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_6_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_6_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_6_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(6)
);
bidir_dq_7_ddio_in_inst : stratixiii_ddio_in
GENERIC MAP (
async_mode => "none",
power_up => "high",
sync_mode => "none",
use_clkn => "false"
)
PORT MAP (
clk => dq_input_reg_clk,
datain => wire_bidir_dq_7_input_delay_chain_inst_dataout,
regouthi => wire_bidir_dq_7_ddio_in_inst_regouthi,
regoutlo => wire_bidir_dq_7_ddio_in_inst_regoutlo,
sreset => bidir_dq_sreset(7)
);
wire_dqs_oe_ddio_oe_inst_w_lg_dataout1w(0) <= NOT wire_dqs_oe_ddio_oe_inst_dataout;
dqs_oe_ddio_oe_inst : stratixiii_ddio_oe
GENERIC MAP (
async_mode => "preset",
power_up => "high",
sync_mode => "none"
)
PORT MAP (
areset => dqs_areset,
clk => dqs_output_reg_clk,
dataout => wire_dqs_oe_ddio_oe_inst_dataout,
oe => dqs_oe_in
);
wire_dqsn_oe_ddio_oe_inst_w_lg_dataout2w(0) <= NOT wire_dqsn_oe_ddio_oe_inst_dataout;
dqsn_oe_ddio_oe_inst : stratixiii_ddio_oe
GENERIC MAP (
async_mode => "preset",
power_up => "high",
sync_mode => "none"
)
PORT MAP (
clk => dqs_output_reg_clk,
dataout => wire_dqsn_oe_ddio_oe_inst_dataout,
oe => dqsn_oe_in
);
bidir_dq_0_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(0),
datainlo => bidir_dq_output_data_in_low(0),
dataout => wire_bidir_dq_0_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(0)
);
bidir_dq_1_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(1),
datainlo => bidir_dq_output_data_in_low(1),
dataout => wire_bidir_dq_1_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(1)
);
bidir_dq_2_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(2),
datainlo => bidir_dq_output_data_in_low(2),
dataout => wire_bidir_dq_2_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(2)
);
bidir_dq_3_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(3),
datainlo => bidir_dq_output_data_in_low(3),
dataout => wire_bidir_dq_3_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(3)
);
bidir_dq_4_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(4),
datainlo => bidir_dq_output_data_in_low(4),
dataout => wire_bidir_dq_4_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(4)
);
bidir_dq_5_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(5),
datainlo => bidir_dq_output_data_in_low(5),
dataout => wire_bidir_dq_5_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(5)
);
bidir_dq_6_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(6),
datainlo => bidir_dq_output_data_in_low(6),
dataout => wire_bidir_dq_6_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(6)
);
bidir_dq_7_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "high",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
clkhi => dq_output_reg_clk,
clklo => dq_output_reg_clk,
datainhi => bidir_dq_output_data_in_high(7),
datainlo => bidir_dq_output_data_in_low(7),
dataout => wire_bidir_dq_7_output_ddio_out_inst_dataout,
muxsel => dq_output_reg_clk,
sreset => bidir_dq_sreset(7)
);
dqs_output_ddio_out_inst : stratixiii_ddio_out
GENERIC MAP (
async_mode => "none",
half_rate_mode => "false",
power_up => "low",
sync_mode => "none",
use_new_clocking_model => "true"
)
PORT MAP (
areset => dqs_areset,
clkhi => dqs_output_reg_clk,
clklo => dqs_output_reg_clk,
datainhi => dqs_output_data_in_high,
datainlo => dqs_output_data_in_low,
dataout => wire_dqs_output_ddio_out_inst_dataout,
muxsel => dqs_output_reg_clk
);
bidir_dq_0_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(0),
dataout => wire_bidir_dq_0_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_0_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_1_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(1),
dataout => wire_bidir_dq_1_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_1_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_2_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(2),
dataout => wire_bidir_dq_2_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_2_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_3_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(3),
dataout => wire_bidir_dq_3_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_3_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_4_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(4),
dataout => wire_bidir_dq_4_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_4_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_5_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(5),
dataout => wire_bidir_dq_5_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_5_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_6_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(6),
dataout => wire_bidir_dq_6_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_6_io_config_inst_padtoinputregisterdelaysetting
);
bidir_dq_7_input_delay_chain_inst : stratixiii_delay_chain
PORT MAP (
datain => bidir_dq_input_data_in(7),
dataout => wire_bidir_dq_7_input_delay_chain_inst_dataout,
delayctrlin => wire_bidir_dq_7_io_config_inst_padtoinputregisterdelaysetting
);
dqs_config_0_inst : stratixiii_dqs_config
PORT MAP (
clk => config_clk,
datain => config_datain,
dividerphasesetting => wire_dqs_config_0_inst_dividerphasesetting,
ena => dqs_config_ena,
update => config_update
);
dqs_config_1_inst : stratixiii_dqs_config
PORT MAP (
clk => config_clk,
datain => config_datain,
dividerphasesetting => wire_dqs_config_1_inst_dividerphasesetting,
ena => dqs_config_ena,
update => config_update
);
bidir_dq_0_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(0),
q => wire_bidir_dq_0_oct_ff_inst_q
);
wire_bidir_dq_0_oe_ff_inst_w_lg_q11w(0) <= NOT wire_bidir_dq_0_oe_ff_inst_q;
bidir_dq_0_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(0),
q => wire_bidir_dq_0_oe_ff_inst_q,
sclr => bidir_dq_sreset(0)
);
bidir_dq_1_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(1),
q => wire_bidir_dq_1_oct_ff_inst_q
);
wire_bidir_dq_1_oe_ff_inst_w_lg_q28w(0) <= NOT wire_bidir_dq_1_oe_ff_inst_q;
bidir_dq_1_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(1),
q => wire_bidir_dq_1_oe_ff_inst_q,
sclr => bidir_dq_sreset(1)
);
bidir_dq_2_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(2),
q => wire_bidir_dq_2_oct_ff_inst_q
);
wire_bidir_dq_2_oe_ff_inst_w_lg_q41w(0) <= NOT wire_bidir_dq_2_oe_ff_inst_q;
bidir_dq_2_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(2),
q => wire_bidir_dq_2_oe_ff_inst_q,
sclr => bidir_dq_sreset(2)
);
bidir_dq_3_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(3),
q => wire_bidir_dq_3_oct_ff_inst_q
);
wire_bidir_dq_3_oe_ff_inst_w_lg_q54w(0) <= NOT wire_bidir_dq_3_oe_ff_inst_q;
bidir_dq_3_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(3),
q => wire_bidir_dq_3_oe_ff_inst_q,
sclr => bidir_dq_sreset(3)
);
bidir_dq_4_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(4),
q => wire_bidir_dq_4_oct_ff_inst_q
);
wire_bidir_dq_4_oe_ff_inst_w_lg_q67w(0) <= NOT wire_bidir_dq_4_oe_ff_inst_q;
bidir_dq_4_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(4),
q => wire_bidir_dq_4_oe_ff_inst_q,
sclr => bidir_dq_sreset(4)
);
bidir_dq_5_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(5),
q => wire_bidir_dq_5_oct_ff_inst_q
);
wire_bidir_dq_5_oe_ff_inst_w_lg_q80w(0) <= NOT wire_bidir_dq_5_oe_ff_inst_q;
bidir_dq_5_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(5),
q => wire_bidir_dq_5_oe_ff_inst_q,
sclr => bidir_dq_sreset(5)
);
bidir_dq_6_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(6),
q => wire_bidir_dq_6_oct_ff_inst_q
);
wire_bidir_dq_6_oe_ff_inst_w_lg_q93w(0) <= NOT wire_bidir_dq_6_oe_ff_inst_q;
bidir_dq_6_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(6),
q => wire_bidir_dq_6_oe_ff_inst_q,
sclr => bidir_dq_sreset(6)
);
bidir_dq_7_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => bidir_dq_oct_in(7),
q => wire_bidir_dq_7_oct_ff_inst_q
);
wire_bidir_dq_7_oe_ff_inst_w_lg_q106w(0) <= NOT wire_bidir_dq_7_oe_ff_inst_q;
bidir_dq_7_oe_ff_inst : stratixiii_ff
GENERIC MAP (
POWER_UP => "HIGH"
)
PORT MAP (
clk => dq_output_reg_clk,
d => bidir_dq_oe_in(7),
q => wire_bidir_dq_7_oe_ff_inst_q,
sclr => bidir_dq_sreset(7)
);
dqs_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => dqs_oct_in,
q => wire_dqs_oct_ff_inst_q
);
dqsn_oct_ff_inst : stratixiii_ff
PORT MAP (
clk => oct_reg_clk,
d => dqsn_oct_in,
q => wire_dqsn_oct_ff_inst_q
);
io_clock_divider_0_inst : stratixiii_io_clock_divider
GENERIC MAP (
invert_phase => "false",
phase_setting => 0,
use_masterin => "false",
use_phasectrlin => "false"
)
PORT MAP (
clk => io_clock_divider_clk,
phaseselect => wire_dqs_config_0_inst_dividerphasesetting,
slaveout => wire_io_clock_divider_0_inst_slaveout
);
io_clock_divider_1_inst : stratixiii_io_clock_divider
GENERIC MAP (
invert_phase => "false",
phase_setting => 0,
use_masterin => "true",
use_phasectrlin => "false"
)
PORT MAP (
clk => io_clock_divider_clk,
masterin => wire_io_clock_divider_0_inst_slaveout,
phaseselect => wire_dqs_config_1_inst_dividerphasesetting
);
bidir_dq_0_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(0),
padtoinputregisterdelaysetting => wire_bidir_dq_0_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_1_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(1),
padtoinputregisterdelaysetting => wire_bidir_dq_1_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_2_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(2),
padtoinputregisterdelaysetting => wire_bidir_dq_2_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_3_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(3),
padtoinputregisterdelaysetting => wire_bidir_dq_3_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_4_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(4),
padtoinputregisterdelaysetting => wire_bidir_dq_4_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_5_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(5),
padtoinputregisterdelaysetting => wire_bidir_dq_5_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_6_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(6),
padtoinputregisterdelaysetting => wire_bidir_dq_6_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
bidir_dq_7_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => bidir_dq_io_config_ena(7),
padtoinputregisterdelaysetting => wire_bidir_dq_7_io_config_inst_padtoinputregisterdelaysetting,
update => config_update
);
dqs_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => dqs_io_config_ena,
update => config_update
);
dqsn_io_config_inst : stratixiii_io_config
PORT MAP (
clk => config_clk,
datain => config_datain,
ena => dqsn_io_config_ena,
update => config_update
);
END RTL; --dq_dqs_inst
--VALID FILE
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/ringosc.vhd | 1 | 2525 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_ut130hbd
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_rhs65
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
ut130r : if tech = ut130 generate
ut130rx : ringosc_ut130hbd port map (roen, roout);
end generate;
rhs65r : if tech = rhs65 generate
rhs65rx : ringosc_rhs65 port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc and tech /= ut130 and tech /= rhs65 generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-asic/testbench_netlist.vhd | 1 | 13207 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
library dare;
use work.config.all; -- configuration
entity testbench_netlist is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 1000; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench_netlist is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal promwidth: std_logic_vector(1 downto 0);
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1';
dsubre <= '1' when (testen = 1) and (scanen = 1) else
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "HHL";
-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
gpio(15 downto 11) <= "HLLHH"; --19
gpio(10 downto 8) <= "HLL"; --4
gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxdp <= spw_txdp; spw_rxsp <= spw_txsp;
spw_rxdn <= spw_txdn; spw_rxsn <= spw_txsn;
roen <= '0';
promedac <= '0';
promwidth <= "10";
rxd2 <= txd2;
d3 : entity dare.leon3mp
port map (rst, clksel, clk, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
promwidth, promedac,
spw_clksel, spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp, spw_txdn,
spw_txsp, spw_txsn, gnd(0), roen, roout, nandout, test);
-- optional sdram
sd0 : if (CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
promcb0 : sramft generic map (index => 7, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), cb(7 downto 0), romsn(0), writen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
iuerr : process
begin
wait for (100*clkperiod) * 1 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
cb <= buskeep(cb), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/testbench.vhd | 1 | 13550 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 21; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 4 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal dsuen, dsutx, dsurx, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal debugout : std_logic_vector(31 downto 0);
-- External Adress/data bus, flash+ssram
signal fs_addr : std_logic_vector(24 downto 0);
signal fs_data : std_logic_vector(31 downto 0);
signal io_cen : std_logic;
signal flash_cen : std_ulogic;
signal flash_oen : std_ulogic;
signal flash_wen : std_ulogic;
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adspn : std_ulogic;
signal ssram_advn : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
signal flash_addr : std_logic_vector(romdepth downto 0);
-- muxed data bus
signal prd : std_logic_vector(31 downto 0);
signal ssd : std_logic_vector(31 downto 0);
-- ddr memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal phy_gtx_clk : std_logic;
signal phy_mii_data : std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal ft245_data : std_logic_vector (7 downto 0);
signal ft245_rdn : std_logic;
signal ft245_wr : std_logic;
signal ft245_rxfn : std_logic;
signal ft245_txen : std_logic;
signal ft245_pwrenn : std_logic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
component sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end component;
begin
-- clock and reset
-- 100 MHz
clk <= not clk after 5 ns;
-- ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
rxd1 <= '1';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech,
ncpu, disas, dbguart, pclow )
port map (
resetn => rst,
clk => clk,
errorn => error,
fs_addr => fs_addr,
fs_data => fs_data,
io_cen => io_cen,
flash_cen => flash_cen,
flash_oen => flash_oen,
flash_wen => flash_wen,
ssram_cen => ssram_cen,
ssram_wen => ssram_wen,
ssram_bw => ssram_bw,
ssram_oen => ssram_oen,
ssram_clk => ssram_clk,
ssram_adscn => ssram_adscn,
ssram_adspn => ssram_adspn,
ssram_advn => ssram_advn,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_odt => ddr_odt,
ddr_web => ddr_web, -- ddr write enable
ddr_rasb => ddr_rasb, -- ddr ras
ddr_casb => ddr_casb, -- ddr cas
ddr_dm => ddr_dm, -- ddr dm
ddr_dqs => ddr_dqs, -- ddr dqs
ddr_ad => ddr_ad, -- ddr address
ddr_ba => ddr_ba, -- ddr bank address
ddr_dq => ddr_dq, -- ddr data
phy_gtx_clk => phy_gtx_clk,
phy_mii_data => phy_mii_data,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_rx_data => phy_rx_data,
phy_dv => phy_dv,
phy_rx_er => phy_rx_er,
phy_col => phy_col,
phy_crs => phy_crs,
phy_tx_data => phy_tx_data,
phy_tx_en => phy_tx_en,
phy_tx_er => phy_tx_er,
phy_mii_clk => phy_mii_clk,
dsuact => dsuact,
rxd1 => rxd1,
txd1 => txd1,
gpio => gpio,
ft245_data => ft245_data,
ft245_rdn => ft245_rdn,
ft245_wr => ft245_wr,
ft245_rxfn => ft245_rxfn,
ft245_txen => ft245_txen,
ft245_pwrenn => ft245_pwrenn
);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => fs_data,
iAddr => fs_addr(19 downto 1), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_advn,
inADSP => ssram_adspn, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
flash_addr <= '0'&fs_addr(romdepth-1 downto 0);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (a => flash_addr(romdepth-1 downto 0), d => fs_data(31 downto 16), lb => '0', ub => '0',
ce => flash_cen, we => flash_wen, oe => flash_oen);
-- prd(23 downto 0) <= (others => '0');
-- data mux
-- fs_data <= ssd when ssram_oen='0' and ssram_cen='0' else
-- prd when flash_oen='0' and flash_cen='0' else
-- (others => 'Z');
-- data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, fs_addr(20 downto 1), fs_data,
io_cen, flash_oen, flash_wen, open);
error <= 'H'; -- ERROR pull-up
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => ddr_dq, b => ddr_dq2);
--DDR2
ddr2mem0: ddr2ram
generic map (
width => 64, abits => 14, babits => 2,
colbits => 10, implbanks => 1, fname => sdramfile
)
port map (
ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn
);
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
ddr_dqsn <= (others => 'U');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad_ds.vhd | 1 | 5112 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad_ds port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml40x/testbench.vhd | 1 | 10420 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc4v/dprc_fir_demo/fir_ahb_dma_apb.vhd | 4 | 13836 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/cypress/ssram/cy7c1380d.vhd | 4 | 26441 | --***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2spax_ahb.vhd | 1 | 16843 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa_ahb
-- File: ddr2spa_ahb.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynch AHB interface for DDR memory controller
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog: out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end ddr2spax_ahb;
architecture rtl of ddr2spax_ahb is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant ramwt: integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, DEVID, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ahbw: integer := log2(ahbbits);
constant l2ddrw: integer := log2(2*ddrbits);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_wabits: integer := 1+l2blen-5; -- log2(burstlen);
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw; -- log2(burstlen*32/ahbbits);
constant rbuf_rdbits: integer := ahbbits;
type ahbstate is (asnormal,asw1,asw2,asww1,asww2,aswr,aswwx);
type ahb_reg_type is record
s : ahbstate;
start_tog : std_logic;
ramaddr : std_logic_vector(l2blen-4 downto 2);
-- These are sent to the DDR layer
req : ddr_request_type;
-- Posted write following current request
nreq : ddr_request_type;
-- Read flow control
rctr_lin : std_logic_vector(3 downto 0);
endpos : std_logic_vector(7 downto log2(ddrbits/4));
block_read: std_logic_vector(1 downto 0);
-- Current AHB control signals
haddr : std_logic_vector(31 downto 0);
haddr_nonseq: std_logic_vector(9 downto 0);
hio : std_logic;
hsize : std_logic_vector(2 downto 0);
hwrite : std_logic;
hburst0 : std_logic;
-- AHB slave outputs
so_hready : std_logic;
-- From DDR layer
resp1,resp2: ddr_response_type;
end record;
signal ar,nar : ahb_reg_type;
begin
ahbcomb : process(ahbsi,rst,ar,response,rbrdata,hwidth,beid)
variable av: ahb_reg_type;
variable va2d: ddr_request_type;
variable so: ahb_slv_out_type;
variable vdone: std_logic;
variable vresp: ddr_response_type;
variable bigsize,midsize,canburst: std_logic;
variable inc_ramaddr: std_logic;
variable row: std_logic_vector(14 downto 0);
variable wbwa: std_logic_vector(wbuf_wabits-1 downto 0);
variable wbwd: std_logic_vector(wbuf_wdbits-1 downto 0);
variable wbw,wbwb: std_logic;
variable rbra: std_logic_vector(rbuf_rabits-1 downto 0);
variable ha0: std_logic_vector(31 downto 0);
variable rend,nrend: std_logic_vector(7 downto log2(ddrbits/4));
variable datavalid, writedone: std_logic;
variable rctr_gray: std_logic_vector(3 downto 0);
variable tog_start: std_logic;
variable regdata: std_logic_vector(31 downto 0);
begin
ha0 := ahbsi.haddr;
ha0(31 downto 20) := ha0(31 downto 20) and not std_logic_vector(to_unsigned(hmask,12));
av := ar;
so := (hready => ar.so_hready, hresp => HRESP_OKAY, hrdata => (others => '0'),
hsplit => (others => '0'), hirq => (others => '0'),
hconfig => hconfig, hindex => hindex);
wbw := '0';
wbwb := '0';
wbwa := ar.start_tog & ar.ramaddr;
wbwd := ahbreaddata(ahbsi.hwdata,ar.haddr(4 downto 2),
std_logic_vector(to_unsigned(log2(ahbbits/8),3)));
rbra := ar.ramaddr(l2blen-4 downto l2ahbw-3);
-- Determine whether the current hsize is a big (ahbbits-width) access
bigsize := '0';
if (ahbbits = 256 and ar.hsize(2)='1' and ar.hsize(0)='1') or
(ahbbits = 128 and ar.hsize(2)='1') or
(ahbbits = 64 and ar.hsize="011") then
bigsize := '1';
end if;
midsize := '0';
if ( (ahbbits = 256 and ((ar.hsize(2)='1' and ar.hsize(0)='0') or (ar.hsize(1 downto 0)="11"))) or
(ahbbits = 128 and ar.hsize="011") ) then
midsize := '1';
end if;
-- Determine whether sequential burst is allowed after current access
canburst := '0';
if (bigsize='1' and ar.haddr(l2blen-4 downto l2ahbw-3)/=(not zerov(l2blen-l2ahbw))) or
(ar.hsize="010" and ar.haddr(l2blen-4 downto 2)/=(not zerov(l2blen-5))) then
canburst := '1';
end if;
-- if canburst='1' then
-- print("ar.hsize=" & tost(ar.hsize) & "ar.haddr: " & tost(ar.haddr(l2blen-4 downto 2)) & " /= " & tost(not zerov(l2blen-5)));
-- end if;
if ar.hio='1' then
canburst := '0';
end if;
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.haddr := ha0;
av.ramaddr := ha0(log2(4*burstlen)-1 downto 2);
av.hio := ahbsi.hmbsel(1);
av.hsize := ahbsi.hsize;
av.hwrite := ahbsi.hwrite;
av.hburst0 := ahbsi.hburst(0);
if ahbsi.htrans(0)='0' or canburst='0' then
av.haddr_nonseq := ha0(9 downto 0);
end if;
end if;
-- Synchronize from DDR domain
av.resp1:=response; av.resp2:=ar.resp1;
vresp := ar.resp2;
if nosync /= 0 then vresp := response; end if;
vdone := vresp.done_tog;
-- Determine whether we can read more data in burst
datavalid := '0';
writedone := '0';
if ar.start_tog=vdone then
datavalid := '1';
writedone := '1';
end if;
if ar.rctr_lin="0000" then rend:=ar.haddr(7 downto l2ddrw-3); else rend:=ar.endpos; end if;
nrend := std_logic_vector(unsigned(rend)+1);
rctr_gray := lin2gray(ar.rctr_lin);
if ar.start_tog/=vdone and rctr_gray /= vresp.rctr_gray and ar.block_read(0)='0' then
av.rctr_lin := std_logic_vector(unsigned(ar.rctr_lin)+1);
av.endpos := nrend;
rend := nrend;
end if;
if 2*ddrbits > ahbbits then
if rend /= ar.haddr(7 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
else
if rend(7 downto log2(ahbbits/8)) /= ar.haddr(7 downto log2(ahbbits/8)) then
datavalid := '1';
end if;
if 2*ddrbits < ahbbits and ahbbits > 32 then
if ar.hsize="010" or ar.hsize="001" or ar.hsize="000" then
if rend(log2(ahbbits/8)-1 downto log2(ddrbits/4)) /=
ar.haddr(log2(ahbbits/8)-1 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
end if;
end if;
end if;
if ar.block_read(1)='1' or (ar.start_tog/=vdone and ar.block_read(0)='1') then
datavalid := '0';
writedone := '0';
end if;
if ar.block_read(1)='1' and ar.start_tog/=vdone then
av.block_read(1) := '0';
end if;
if ar.block_read(1)='0' and vresp.rctr_gray="0000" then
av.block_read(0) := '0';
end if;
-- FSM
inc_ramaddr := '0';
tog_start := '0';
case ar.s is
when asnormal =>
-- Idle and memory read state
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
-- Pass on address immediately to request for read case
av.req := (startaddr => ha0,
endaddr => ha0(9 downto 0),
hsize => ahbsi.hsize,
hwrite => ahbsi.hwrite,
hio => ahbsi.hmbsel(1),
burst => ahbsi.hburst(0),
maskdata => '0', maskcb => '0');
if ahbsi.hwrite='0' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
tog_start := '1';
elsif datavalid='1' then
inc_ramaddr := '1';
else
av.so_hready := '0';
-- grlib.testlib.print("Going to waitstate!");
end if;
else
av.s := asw1;
end if;
end if;
if ar.so_hready='0' and datavalid='1' then
av.so_hready := '1';
inc_ramaddr := '1';
end if;
when asw1 =>
-- Transfer data for write request
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.req.endaddr := ar.haddr(9 downto 0);
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
tog_start := '1';
end if;
else
av.s := asw2;
tog_start := '1';
end if;
when asw2 =>
-- Write request ongoing
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
elsif writedone='1' then
av.s := asnormal;
end if;
when asww1 =>
-- Transfer data for second write while write request ongoing
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
av.s := aswwx;
end if;
else
av.s := asww2;
end if;
when asww2 =>
-- Second write enqueued, wait for first write to finish
-- Any new request here will cause HREADY to go low
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.so_hready := '0';
av.s := aswwx;
elsif writedone='1' then
av.req := ar.nreq;
tog_start := '1';
av.s := asw2;
end if;
when aswr =>
-- Read request following ongoing write request
-- HREADY is low in this state
av.so_hready := '0';
if writedone='1' then
av.req := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.hwrite := '0';
tog_start := '1';
av.s := asnormal;
end if;
when aswwx =>
-- Write ongoing + write posted + another AHB request (read or write)
-- Keep HREADY low
av.so_hready := '0';
if writedone='1' then
tog_start := '1';
av.req := ar.nreq;
if ar.hwrite='1' then
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.so_hready := '1';
av.s := asww1;
else
av.s := aswr;
end if;
end if;
end case;
if tog_start='1' and (regarea=0 or av.req.hio='0' or av.req.startaddr(5)='0') then
av.start_tog := not ar.start_tog;
av.rctr_lin := "0000";
if ar.start_tog /= vdone then
av.block_read(1) := '1';
end if;
av.block_read(0) := '1';
end if;
if inc_ramaddr='1' then
if bigsize='1' then
av.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)))+1);
else
av.ramaddr(log2(4*burstlen)-1 downto 2) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto 2))+1);
end if;
end if;
-- Used only if regarea /= 0
regdata := (others => '0');
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/8),3));
if hwidth/='0' then
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/16),3));
end if;
regdata(15 downto 12) := beid;
-- If we are using AMBA-compliant data muxing, nothing needs to be done to
-- the hrdata vector. Otherwise, we need to duplicate 32-bit lanes
if regarea/=0 and ar.req.hio='1' and ar.req.startaddr(5)='1' then
so.hrdata := ahbdrivedata(regdata);
elsif CORE_ACDM /= 0 then
so.hrdata := ahbdrivedata(rbrdata);
else
so.hrdata := ahbselectdata(ahbdrivedata(rbrdata),ar.haddr(4 downto 2),ar.hsize);
end if;
if rst='0' then
av.s := asnormal;
av.block_read := "00";
av.start_tog := '0';
av.so_hready := '1';
so.hready := '1';
so.hresp := HRESP_OKAY;
end if;
if l2blen-l2ddrw < 4 then
av.rctr_lin(3 downto l2blen-l2ddrw) := (others => '0');
end if;
nar <= av;
request <= ar.req;
start_tog <= ar.start_tog;
ahbso <= so;
wbwrite <= wbw;
wbwritebig <= wbwb;
wbwaddr <= wbwa;
wbwdata <= wbwd;
rbraddr <= rbra;
end process;
ahbregs : process(clk_ahb)
begin
if rising_edge(clk_ahb) then
ar <= nar;
end if;
end process;
end;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682/tb/wrapreconfmodule-c.vhd | 1 | 998 | ------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of MAX6682_tb is
for behavior
for DUT : MAX6682
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/reconfmodule/chll/out/parent-module.vhd | 1 | 47395 | -- Automatically generated: write_netlist -parent -vhdl -module parent-module.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
LFXT_Clk_i : in std_logic;
Dbg_En_i : in std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0)
);
attribute src of Core : entity is "../../../core/verilog/core.v:22";
attribute src of Reset_n_i : signal is "../../../core/verilog/core.v:24";
attribute src of Clk_i : signal is "../../../core/verilog/core.v:25";
attribute src of Cpu_En_i : signal is "../../../core/verilog/core.v:28";
attribute src of LFXT_Clk_i : signal is "../../../core/verilog/core.v:30";
attribute src of Dbg_En_i : signal is "../../../core/verilog/core.v:32";
attribute src of Dbg_SCL_i : signal is "../../../core/verilog/core.v:38";
attribute src of Dbg_SDA_Out_o : signal is "../../../core/verilog/core.v:39";
attribute src of Dbg_SDA_In_i : signal is "../../../core/verilog/core.v:40";
attribute src of P1_DOut_o : signal is "../../../core/verilog/core.v:43";
attribute src of P1_En_o : signal is "../../../core/verilog/core.v:44";
attribute src of P1_DIn_i : signal is "../../../core/verilog/core.v:45";
attribute src of P2_DOut_o : signal is "../../../core/verilog/core.v:46";
attribute src of P2_En_o : signal is "../../../core/verilog/core.v:47";
attribute src of P2_DIn_i : signal is "../../../core/verilog/core.v:48";
attribute src of UartRxD_i : signal is "../../../core/verilog/core.v:50";
attribute src of UartTxD_o : signal is "../../../core/verilog/core.v:51";
attribute src of SCK_o : signal is "../../../core/verilog/core.v:53";
attribute src of MOSI_o : signal is "../../../core/verilog/core.v:54";
attribute src of MISO_i : signal is "../../../core/verilog/core.v:55";
attribute src of Inputs_i : signal is "../../../core/verilog/core.v:58";
attribute src of Outputs_o : signal is "../../../core/verilog/core.v:59";
attribute src of SPIMISO_i : signal is "../../../core/verilog/core.v:61";
attribute src of SPIMOSI_o : signal is "../../../core/verilog/core.v:62";
attribute src of SPISCK_o : signal is "../../../core/verilog/core.v:63";
attribute src of I2CSCL_o : signal is "../../../core/verilog/core.v:65";
attribute src of I2CSDA_i : signal is "../../../core/verilog/core.v:66";
attribute src of I2CSDA_o : signal is "../../../core/verilog/core.v:67";
attribute src of AdcConvComplete_i : signal is "../../../core/verilog/core.v:87";
attribute src of AdcDoConvert_o : signal is "../../../core/verilog/core.v:88";
attribute src of AdcValue_i : signal is "../../../core/verilog/core.v:89";
end Core;
architecture struct of Core is
component $not
generic (
A_SIGNED : integer := 0;
A_WIDTH : integer := 1;
Y_WIDTH : integer := 1
);
port (
A : in std_logic;
Y : out std_logic
);
end component;
component $logic_and
generic (
A_SIGNED : integer := 0;
B_SIGNED : integer := 0;
A_WIDTH : integer := 1;
B_WIDTH : integer := 1;
Y_WIDTH : integer := 1
);
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end component;
component $or
generic (
A_SIGNED : integer := 0;
B_SIGNED : integer := 0;
A_WIDTH : integer := 1;
B_WIDTH : integer := 1;
Y_WIDTH : integer := 1
);
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end component;
component $adff
generic (
WIDTH : integer := 0;
CLK_POLARITY : std_logic := '1';
ARST_POLARITY : std_logic := '1';
ARST_VALUE : integer := 0
);
port (
CLK : in std_logic;
ARST : in std_logic;
D : in std_logic;
Q : out std_logic
);
end component;
component $mux
generic (
WIDTH : integer := 0
);
port (
A : in std_logic;
B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end component;
component $reduce_or
generic (
A_SIGNED : integer := 0;
A_WIDTH : integer := 0;
Y_WIDTH : integer := 0
);
port (
A : in std_logic;
Y : out std_logic
);
end component;
component ram
port (
ram_dout : out std_logic_vector(15 downto 0);
ram_addr : in std_logic_vector(6 downto 0);
ram_cen : in std_logic;
ram_clk : in std_logic;
ram_din : in std_logic_vector(15 downto 0);
ram_wen : in std_logic_vector(1 downto 0)
);
end component;
component omsp_gpio
port (
irq_port1 : out std_logic;
irq_port2 : out std_logic;
p1_dout : out std_logic_vector(7 downto 0);
p1_dout_en : out std_logic_vector(7 downto 0);
p1_sel : out std_logic_vector(7 downto 0);
p2_dout : out std_logic_vector(7 downto 0);
p2_dout_en : out std_logic_vector(7 downto 0);
p2_sel : out std_logic_vector(7 downto 0);
p3_dout : out std_logic_vector(7 downto 0);
p3_dout_en : out std_logic_vector(7 downto 0);
p3_sel : out std_logic_vector(7 downto 0);
p4_dout : out std_logic_vector(7 downto 0);
p4_dout_en : out std_logic_vector(7 downto 0);
p4_sel : out std_logic_vector(7 downto 0);
p5_dout : out std_logic_vector(7 downto 0);
p5_dout_en : out std_logic_vector(7 downto 0);
p5_sel : out std_logic_vector(7 downto 0);
p6_dout : out std_logic_vector(7 downto 0);
p6_dout_en : out std_logic_vector(7 downto 0);
p6_sel : out std_logic_vector(7 downto 0);
per_dout : out std_logic_vector(15 downto 0);
mclk : in std_logic;
p1_din : in std_logic_vector(7 downto 0);
p2_din : in std_logic_vector(7 downto 0);
p3_din : in std_logic_vector(7 downto 0);
p4_din : in std_logic_vector(7 downto 0);
p5_din : in std_logic_vector(7 downto 0);
p6_din : in std_logic_vector(7 downto 0);
per_addr : in std_logic_vector(13 downto 0);
per_din : in std_logic_vector(15 downto 0);
per_en : in std_logic;
per_we : in std_logic_vector(1 downto 0);
puc_rst : in std_logic
);
end component;
component i2c_master
port (
Reset_i : in std_logic;
Clk_i : in std_logic;
F100_400_n_i : in std_logic;
Divider800_i : in std_logic_vector(15 downto 0);
StartProcess_i : in std_logic;
ReceiveSend_n_i : in std_logic;
Busy_o : out std_logic;
ReadCount_i : in std_logic_vector(3 downto 0);
FIFOReadNext_i : in std_logic;
FIFOWrite_i : in std_logic;
FIFOEmpty_o : out std_logic;
FIFOFull_o : out std_logic;
Data_i : in std_logic_vector(7 downto 0);
Data_o : out std_logic_vector(7 downto 0);
ErrAck_i : in std_logic;
ErrBusColl_o : out std_logic;
ErrFIFOFull_o : out std_logic;
ErrGotNAck_o : out std_logic;
ErrCoreBusy_o : out std_logic;
ErrFIFOEmpty_o : out std_logic;
ErrCoreStopped_o : out std_logic;
ErrDevNotPresent_o : out std_logic;
ErrReadCountZero_o : out std_logic;
SDA_i : in std_logic;
SDA_o : out std_logic;
SCL_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
component openMSP430
port (
aclk : out std_logic;
aclk_en : out std_logic;
dbg_freeze : out std_logic;
dbg_i2c_sda_out : out std_logic;
dbg_uart_txd : out std_logic;
dco_enable : out std_logic;
dco_wkup : out std_logic;
dmem_addr : out std_logic_vector(6 downto 0);
dmem_cen : out std_logic;
dmem_din : out std_logic_vector(15 downto 0);
dmem_wen : out std_logic_vector(1 downto 0);
irq_acc : out std_logic_vector(13 downto 0);
lfxt_enable : out std_logic;
lfxt_wkup : out std_logic;
mclk : out std_logic;
per_addr : out std_logic_vector(13 downto 0);
per_din : out std_logic_vector(15 downto 0);
per_we : out std_logic_vector(1 downto 0);
per_en : out std_logic;
pmem_addr : out std_logic_vector(11 downto 0);
pmem_cen : out std_logic;
pmem_din : out std_logic_vector(15 downto 0);
pmem_wen : out std_logic_vector(1 downto 0);
puc_rst : out std_logic;
smclk : out std_logic;
smclk_en : out std_logic;
cpu_en : in std_logic;
dbg_en : in std_logic;
dbg_i2c_addr : in std_logic_vector(6 downto 0);
dbg_i2c_broadcast : in std_logic_vector(6 downto 0);
dbg_i2c_scl : in std_logic;
dbg_i2c_sda_in : in std_logic;
dbg_uart_rxd : in std_logic;
dco_clk : in std_logic;
dmem_dout : in std_logic_vector(15 downto 0);
irq : in std_logic_vector(13 downto 0);
lfxt_clk : in std_logic;
nmi : in std_logic;
per_dout : in std_logic_vector(15 downto 0);
pmem_dout : in std_logic_vector(15 downto 0);
reset_n : in std_logic;
scan_enable : in std_logic;
scan_mode : in std_logic;
wkup : in std_logic
);
end component;
component SimpleSPI
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
Intr_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic
);
end component;
component SPI_Master
port (
Reset_n : in std_logic;
Clk : in std_logic;
CPOL_i : in std_logic;
CPHA_i : in std_logic;
LSBFE_i : in std_logic;
SPPR_i : in std_logic_vector(2 downto 0);
SPR_i : in std_logic_vector(2 downto 0);
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Transmission_o : out std_logic;
Write_i : in std_logic;
ReadNext_i : in std_logic;
Data_i : in std_logic_vector(7 downto 0);
Data_o : out std_logic_vector(7 downto 0);
FIFOFull_o : out std_logic;
FIFOEmpty_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
component omsp_timerA
port (
irq_ta0 : out std_logic;
irq_ta1 : out std_logic;
per_dout : out std_logic_vector(15 downto 0);
ta_out0 : out std_logic;
ta_out0_en : out std_logic;
ta_out1 : out std_logic;
ta_out1_en : out std_logic;
ta_out2 : out std_logic;
ta_out2_en : out std_logic;
aclk_en : in std_logic;
dbg_freeze : in std_logic;
inclk : in std_logic;
irq_ta0_acc : in std_logic;
mclk : in std_logic;
per_addr : in std_logic_vector(13 downto 0);
per_din : in std_logic_vector(15 downto 0);
per_en : in std_logic;
per_we : in std_logic_vector(1 downto 0);
puc_rst : in std_logic;
smclk_en : in std_logic;
ta_cci0a : in std_logic;
ta_cci0b : in std_logic;
ta_cci1a : in std_logic;
ta_cci1b : in std_logic;
ta_cci2a : in std_logic;
ta_cci2b : in std_logic;
taclk : in std_logic
);
end component;
component omsp_uart
port (
irq_uart_rx : out std_logic;
irq_uart_tx : out std_logic;
per_dout : out std_logic_vector(15 downto 0);
uart_txd : out std_logic;
mclk : in std_logic;
per_addr : in std_logic_vector(13 downto 0);
per_din : in std_logic_vector(15 downto 0);
per_en : in std_logic;
per_we : in std_logic_vector(1 downto 0);
puc_rst : in std_logic;
smclk_en : in std_logic;
uart_rxd : in std_logic
);
end component;
signal $0\I2C_ErrAck[0:0] : std_logic;
attribute src of $0\I2C_ErrAck[0:0] : signal is "../../../core/verilog/core.v:904";
signal $eq$../../../core/verilog/core.v:914$45_Y : std_logic;
attribute src of $eq$../../../core/verilog/core.v:914$45_Y : signal is "../../../core/verilog/core.v:914";
signal $logic_and$../../../core/verilog/core.v:914$46_Y : std_logic;
attribute src of $logic_and$../../../core/verilog/core.v:914$46_Y : signal is "../../../core/verilog/core.v:914";
signal $or$../../../core/verilog/core.v:656$10_Y : std_logic_vector(15 downto 0);
attribute src of $or$../../../core/verilog/core.v:656$10_Y : signal is "../../../core/verilog/core.v:656";
signal $or$../../../core/verilog/core.v:656$11_Y : std_logic_vector(15 downto 0);
attribute src of $or$../../../core/verilog/core.v:656$11_Y : signal is "../../../core/verilog/core.v:656";
signal $or$../../../core/verilog/core.v:656$12_Y : std_logic_vector(15 downto 0);
attribute src of $or$../../../core/verilog/core.v:656$12_Y : signal is "../../../core/verilog/core.v:656";
signal $or$../../../core/verilog/core.v:656$13_Y : std_logic_vector(15 downto 0);
attribute src of $or$../../../core/verilog/core.v:656$13_Y : signal is "../../../core/verilog/core.v:656";
signal $or$../../../core/verilog/core.v:656$9_Y : std_logic_vector(15 downto 0);
attribute src of $or$../../../core/verilog/core.v:656$9_Y : signal is "../../../core/verilog/core.v:656";
signal AClk_En_s : std_logic;
attribute src of AClk_En_s : signal is "../../../core/verilog/core.v:256";
signal AClk_s : std_logic;
attribute src of AClk_s : signal is "../../../core/verilog/core.v:255";
signal CPU_Enable_s : std_logic;
attribute src of CPU_Enable_s : signal is "../../../core/verilog/core.v:247";
signal CfgIntf_DOut_s : std_logic_vector(15 downto 0);
attribute src of CfgIntf_DOut_s : signal is "../../../core/verilog/core.v:616";
signal DCO_Enable_s : std_logic;
attribute src of DCO_Enable_s : signal is "../../../core/verilog/core.v:250";
signal DCO_Wakeup_s : std_logic;
attribute src of DCO_Wakeup_s : signal is "../../../core/verilog/core.v:251";
signal DMem_Addr_s : std_logic_vector(6 downto 0);
attribute src of DMem_Addr_s : signal is "../../../core/verilog/core.v:268";
signal DMem_DIn_s : std_logic_vector(15 downto 0);
attribute src of DMem_DIn_s : signal is "../../../core/verilog/core.v:270";
signal DMem_DOut_s : std_logic_vector(15 downto 0);
attribute src of DMem_DOut_s : signal is "../../../core/verilog/core.v:272";
signal DMem_En_n_s : std_logic;
attribute src of DMem_En_n_s : signal is "../../../core/verilog/core.v:269";
signal DMem_Wr_n_s : std_logic_vector(1 downto 0);
attribute src of DMem_Wr_n_s : signal is "../../../core/verilog/core.v:271";
signal Dbg_Freeze_s : std_logic;
attribute src of Dbg_Freeze_s : signal is "../../../core/verilog/core.v:286";
signal Dbg_UART_TxD_s : std_logic;
attribute src of Dbg_UART_TxD_s : signal is "../../../core/verilog/core.v:298";
signal Gpio_DOut_s : std_logic_vector(15 downto 0);
attribute src of Gpio_DOut_s : signal is "../../../core/verilog/core.v:440";
signal Gpio_IRQ1_s : std_logic;
attribute src of Gpio_IRQ1_s : signal is "../../../core/verilog/core.v:441";
signal Gpio_IRQ2_s : std_logic;
attribute src of Gpio_IRQ2_s : signal is "../../../core/verilog/core.v:442";
signal I2C_Busy : std_logic;
attribute src of I2C_Busy : signal is "../../../core/verilog/core.v:838";
signal I2C_DataIn : std_logic_vector(7 downto 0);
attribute src of I2C_DataIn : signal is "../../../core/verilog/core.v:844";
signal I2C_DataOut : std_logic_vector(7 downto 0);
attribute src of I2C_DataOut : signal is "../../../core/verilog/core.v:845";
signal I2C_Divider800 : std_logic_vector(15 downto 0);
attribute src of I2C_Divider800 : signal is "../../../core/verilog/core.v:835";
signal I2C_ErrAck : std_logic;
attribute src of I2C_ErrAck : signal is "../../../core/verilog/core.v:846";
signal I2C_ErrAckParam : std_logic;
attribute src of I2C_ErrAckParam : signal is "../../../core/verilog/core.v:902";
signal I2C_ErrAckParamOld : std_logic;
attribute src of I2C_ErrAckParamOld : signal is "../../../core/verilog/core.v:903";
signal I2C_ErrBusColl : std_logic;
attribute src of I2C_ErrBusColl : signal is "../../../core/verilog/core.v:847";
signal I2C_ErrCoreBusy : std_logic;
attribute src of I2C_ErrCoreBusy : signal is "../../../core/verilog/core.v:850";
signal I2C_ErrCoreStopped : std_logic;
attribute src of I2C_ErrCoreStopped : signal is "../../../core/verilog/core.v:852";
signal I2C_ErrDevNotPresent : std_logic;
attribute src of I2C_ErrDevNotPresent : signal is "../../../core/verilog/core.v:853";
signal I2C_ErrFIFOEmpty : std_logic;
attribute src of I2C_ErrFIFOEmpty : signal is "../../../core/verilog/core.v:851";
signal I2C_ErrFIFOFull : std_logic;
attribute src of I2C_ErrFIFOFull : signal is "../../../core/verilog/core.v:848";
signal I2C_ErrGotNAck : std_logic;
attribute src of I2C_ErrGotNAck : signal is "../../../core/verilog/core.v:849";
signal I2C_ErrReadCountZero : std_logic;
attribute src of I2C_ErrReadCountZero : signal is "../../../core/verilog/core.v:854";
signal I2C_Error : std_logic;
attribute keep of I2C_Error : signal is 1;
attribute src of I2C_Error : signal is "../../../core/verilog/core.v:857";
attribute unused_bits of I2C_Error : signal is "0";
signal I2C_Errors : std_logic_vector(7 downto 0);
attribute keep of I2C_Errors : signal is 1;
attribute src of I2C_Errors : signal is "../../../core/verilog/core.v:855";
signal I2C_F100_400_n : std_logic;
attribute src of I2C_F100_400_n : signal is "../../../core/verilog/core.v:834";
signal I2C_FIFOEmpty : std_logic;
attribute src of I2C_FIFOEmpty : signal is "../../../core/verilog/core.v:842";
signal I2C_FIFOFull : std_logic;
attribute src of I2C_FIFOFull : signal is "../../../core/verilog/core.v:843";
signal I2C_FIFOReadNext : std_logic;
attribute src of I2C_FIFOReadNext : signal is "../../../core/verilog/core.v:840";
signal I2C_FIFOWrite : std_logic;
attribute src of I2C_FIFOWrite : signal is "../../../core/verilog/core.v:841";
signal I2C_ReadCount : std_logic_vector(3 downto 0);
attribute src of I2C_ReadCount : signal is "../../../core/verilog/core.v:839";
signal I2C_ReceiveSend_n : std_logic;
attribute src of I2C_ReceiveSend_n : signal is "../../../core/verilog/core.v:837";
signal I2C_ScanDataOut : std_logic;
attribute src of I2C_ScanDataOut : signal is "../../../core/verilog/core.v:862";
signal I2C_StartProcess : std_logic;
attribute src of I2C_StartProcess : signal is "../../../core/verilog/core.v:836";
signal INClk_s : std_logic;
attribute src of INClk_s : signal is "../../../core/verilog/core.v:522";
signal IRQ_Ack_s : std_logic_vector(13 downto 0);
attribute src of IRQ_Ack_s : signal is "../../../core/verilog/core.v:281";
signal IRQ_s : std_logic_vector(13 downto 0);
attribute src of IRQ_s : signal is "../../../core/verilog/core.v:280";
signal LFXT_Enable_s : std_logic;
attribute src of LFXT_Enable_s : signal is "../../../core/verilog/core.v:252";
signal LFXT_Wakeup_s : std_logic;
attribute src of LFXT_Wakeup_s : signal is "../../../core/verilog/core.v:253";
signal MClk_s : std_logic;
attribute src of MClk_s : signal is "../../../core/verilog/core.v:254";
signal P1_DIn_s : std_logic_vector(7 downto 0);
attribute src of P1_DIn_s : signal is "../../../core/verilog/core.v:446";
signal P1_DOut_s : std_logic_vector(7 downto 0);
attribute src of P1_DOut_s : signal is "../../../core/verilog/core.v:443";
signal P1_En_s : std_logic_vector(7 downto 0);
attribute src of P1_En_s : signal is "../../../core/verilog/core.v:444";
signal P1_Sel_s : std_logic_vector(7 downto 0);
attribute src of P1_Sel_s : signal is "../../../core/verilog/core.v:445";
signal P2_DIn_s : std_logic_vector(7 downto 0);
attribute src of P2_DIn_s : signal is "../../../core/verilog/core.v:450";
signal P2_DOut_s : std_logic_vector(7 downto 0);
attribute src of P2_DOut_s : signal is "../../../core/verilog/core.v:447";
signal P2_En_s : std_logic_vector(7 downto 0);
attribute src of P2_En_s : signal is "../../../core/verilog/core.v:448";
signal P2_Sel_s : std_logic_vector(7 downto 0);
attribute src of P2_Sel_s : signal is "../../../core/verilog/core.v:449";
signal P3_DIn_s : std_logic_vector(7 downto 0);
attribute src of P3_DIn_s : signal is "../../../core/verilog/core.v:454";
signal P3_DOut_s : std_logic_vector(7 downto 0);
attribute src of P3_DOut_s : signal is "../../../core/verilog/core.v:451";
signal P3_En_s : std_logic_vector(7 downto 0);
attribute src of P3_En_s : signal is "../../../core/verilog/core.v:452";
signal P3_Sel_s : std_logic_vector(7 downto 0);
attribute src of P3_Sel_s : signal is "../../../core/verilog/core.v:453";
signal P4_DOut_s : std_logic_vector(7 downto 0);
attribute src of P4_DOut_s : signal is "../../../core/verilog/core.v:455";
signal P4_En_s : std_logic_vector(7 downto 0);
attribute src of P4_En_s : signal is "../../../core/verilog/core.v:456";
signal P4_Sel_s : std_logic_vector(7 downto 0);
attribute src of P4_Sel_s : signal is "../../../core/verilog/core.v:457";
signal P5_DOut_s : std_logic_vector(7 downto 0);
attribute src of P5_DOut_s : signal is "../../../core/verilog/core.v:459";
signal P5_En_s : std_logic_vector(7 downto 0);
attribute src of P5_En_s : signal is "../../../core/verilog/core.v:460";
signal P5_Sel_s : std_logic_vector(7 downto 0);
attribute src of P5_Sel_s : signal is "../../../core/verilog/core.v:461";
signal P6_DOut_s : std_logic_vector(7 downto 0);
attribute src of P6_DOut_s : signal is "../../../core/verilog/core.v:463";
signal P6_En_s : std_logic_vector(7 downto 0);
attribute src of P6_En_s : signal is "../../../core/verilog/core.v:464";
signal P6_Sel_s : std_logic_vector(7 downto 0);
attribute src of P6_Sel_s : signal is "../../../core/verilog/core.v:465";
signal PMem_Addr_s : std_logic_vector(11 downto 0);
attribute src of PMem_Addr_s : signal is "../../../core/verilog/core.v:262";
signal PMem_DIn_s : std_logic_vector(15 downto 0);
attribute src of PMem_DIn_s : signal is "../../../core/verilog/core.v:264";
signal PMem_DOut_s : std_logic_vector(15 downto 0);
attribute src of PMem_DOut_s : signal is "../../../core/verilog/core.v:266";
signal PMem_En_n_s : std_logic;
attribute src of PMem_En_n_s : signal is "../../../core/verilog/core.v:263";
signal PMem_Wr_n_s : std_logic_vector(1 downto 0);
attribute src of PMem_Wr_n_s : signal is "../../../core/verilog/core.v:265";
signal PUC_Reset_s : std_logic;
attribute src of PUC_Reset_s : signal is "../../../core/verilog/core.v:246";
signal ParamIntf_DOut_s : std_logic_vector(15 downto 0);
attribute src of ParamIntf_DOut_s : signal is "../../../core/verilog/core.v:618";
signal Per_Addr_s : std_logic_vector(13 downto 0);
attribute src of Per_Addr_s : signal is "../../../core/verilog/core.v:274";
signal Per_DIn_s : std_logic_vector(15 downto 0);
attribute src of Per_DIn_s : signal is "../../../core/verilog/core.v:275";
signal Per_DOut_s : std_logic_vector(15 downto 0);
attribute src of Per_DOut_s : signal is "../../../core/verilog/core.v:276";
signal Per_En_s : std_logic;
attribute src of Per_En_s : signal is "../../../core/verilog/core.v:278";
signal Per_Wr_s : std_logic_vector(1 downto 0);
attribute src of Per_Wr_s : signal is "../../../core/verilog/core.v:277";
signal ReconfModuleIRQs_s : std_logic_vector(4 downto 0);
attribute keep of ReconfModuleIRQs_s : signal is 1;
attribute src of ReconfModuleIRQs_s : signal is "../../../core/verilog/core.v:622";
signal ReconfModuleIn_s : std_logic_vector(7 downto 0);
attribute keep of ReconfModuleIn_s : signal is 1;
attribute src of ReconfModuleIn_s : signal is "../../../core/verilog/core.v:623";
signal ReconfModuleOut_s : std_logic_vector(7 downto 0);
attribute keep of ReconfModuleOut_s : signal is 1;
attribute src of ReconfModuleOut_s : signal is "../../../core/verilog/core.v:624";
signal ResetSync : std_logic_vector(1 downto 0);
attribute src of ResetSync : signal is "../../../core/verilog/core.v:113";
signal Reset_n_s : std_logic;
attribute src of Reset_n_s : signal is "../../../core/verilog/core.v:123";
signal Reset_s : std_logic;
attribute src of Reset_s : signal is "../../../core/verilog/core.v:125";
signal SMClk_En_s : std_logic;
attribute src of SMClk_En_s : signal is "../../../core/verilog/core.v:258";
signal SMClk_s : std_logic;
attribute src of SMClk_s : signal is "../../../core/verilog/core.v:257";
signal SPI_CPHA : std_logic;
attribute src of SPI_CPHA : signal is "../../../core/verilog/core.v:779";
signal SPI_CPOL : std_logic;
attribute src of SPI_CPOL : signal is "../../../core/verilog/core.v:778";
signal SPI_DOut_s : std_logic_vector(15 downto 0);
attribute src of SPI_DOut_s : signal is "../../../core/verilog/core.v:595";
signal SPI_DataIn : std_logic_vector(7 downto 0);
attribute src of SPI_DataIn : signal is "../../../core/verilog/core.v:787";
signal SPI_DataOut : std_logic_vector(7 downto 0);
attribute src of SPI_DataOut : signal is "../../../core/verilog/core.v:788";
signal SPI_FIFOEmpty : std_logic;
attribute src of SPI_FIFOEmpty : signal is "../../../core/verilog/core.v:790";
signal SPI_FIFOFull : std_logic;
attribute src of SPI_FIFOFull : signal is "../../../core/verilog/core.v:789";
signal SPI_IRQ_s : std_logic;
attribute src of SPI_IRQ_s : signal is "../../../core/verilog/core.v:596";
signal SPI_LSBFE : std_logic;
attribute src of SPI_LSBFE : signal is "../../../core/verilog/core.v:780";
signal SPI_ReadNext : std_logic;
attribute src of SPI_ReadNext : signal is "../../../core/verilog/core.v:786";
signal SPI_SPPR_SPR : std_logic_vector(7 downto 0);
attribute src of SPI_SPPR_SPR : signal is "../../../core/verilog/core.v:783";
signal SPI_ScanDataOut : std_logic;
attribute src of SPI_ScanDataOut : signal is "../../../core/verilog/core.v:794";
signal SPI_Transmission : std_logic;
attribute src of SPI_Transmission : signal is "../../../core/verilog/core.v:784";
signal SPI_Write : std_logic;
attribute src of SPI_Write : signal is "../../../core/verilog/core.v:785";
signal TAClk_s : std_logic;
attribute src of TAClk_s : signal is "../../../core/verilog/core.v:523";
signal TimerA_CCI0A_s : std_logic;
attribute src of TimerA_CCI0A_s : signal is "../../../core/verilog/core.v:524";
signal TimerA_CCI0B_s : std_logic;
attribute src of TimerA_CCI0B_s : signal is "../../../core/verilog/core.v:525";
signal TimerA_CCI1A_s : std_logic;
attribute src of TimerA_CCI1A_s : signal is "../../../core/verilog/core.v:528";
signal TimerA_CCI1B_s : std_logic;
attribute src of TimerA_CCI1B_s : signal is "../../../core/verilog/core.v:529";
signal TimerA_CCI2A_s : std_logic;
attribute src of TimerA_CCI2A_s : signal is "../../../core/verilog/core.v:532";
signal TimerA_CCI2B_s : std_logic;
attribute src of TimerA_CCI2B_s : signal is "../../../core/verilog/core.v:533";
signal TimerA_DOut_s : std_logic_vector(15 downto 0);
attribute src of TimerA_DOut_s : signal is "../../../core/verilog/core.v:519";
signal TimerA_IRQ1_s : std_logic;
attribute src of TimerA_IRQ1_s : signal is "../../../core/verilog/core.v:520";
signal TimerA_IRQ2_s : std_logic;
attribute src of TimerA_IRQ2_s : signal is "../../../core/verilog/core.v:521";
signal TimerA_Out0_En_s : std_logic;
attribute src of TimerA_Out0_En_s : signal is "../../../core/verilog/core.v:527";
signal TimerA_Out0_s : std_logic;
attribute src of TimerA_Out0_s : signal is "../../../core/verilog/core.v:526";
signal TimerA_Out1_En_s : std_logic;
attribute src of TimerA_Out1_En_s : signal is "../../../core/verilog/core.v:531";
signal TimerA_Out1_s : std_logic;
attribute src of TimerA_Out1_s : signal is "../../../core/verilog/core.v:530";
signal TimerA_Out2_En_s : std_logic;
attribute src of TimerA_Out2_En_s : signal is "../../../core/verilog/core.v:535";
signal TimerA_Out2_s : std_logic;
attribute src of TimerA_Out2_s : signal is "../../../core/verilog/core.v:534";
signal UART_DOut_s : std_logic_vector(15 downto 0);
attribute src of UART_DOut_s : signal is "../../../core/verilog/core.v:573";
signal UART_IRQ_Rx_s : std_logic;
attribute src of UART_IRQ_Rx_s : signal is "../../../core/verilog/core.v:574";
signal UART_IRQ_Tx_s : std_logic;
attribute src of UART_IRQ_Tx_s : signal is "../../../core/verilog/core.v:575";
signal Wakeup_s : std_logic;
attribute src of Wakeup_s : signal is "../../../core/verilog/core.v:260";
begin
$eq$../../../core/verilog/core.v:914$45: $not
generic map (
A_SIGNED => 0,
A_WIDTH => 1,
Y_WIDTH => 1
)
port map (
A => I2C_ErrAckParamOld,
Y => $eq$../../../core/verilog/core.v:914$45_Y
);
$logic_and$../../../core/verilog/core.v:914$46: $logic_and
generic map (
A_SIGNED => 0,
A_WIDTH => 1,
B_SIGNED => 0,
B_WIDTH => 1,
Y_WIDTH => 1
)
port map (
A => I2C_ErrAckParam,
B => $eq$../../../core/verilog/core.v:914$45_Y,
Y => $logic_and$../../../core/verilog/core.v:914$46_Y
);
$not$../../../core/verilog/core.v:126$6: $not
generic map (
A_SIGNED => 0,
A_WIDTH => 1,
Y_WIDTH => 1
)
port map (
A => ResetSync(1),
Y => Reset_s
);
$or$../../../core/verilog/core.v:656$10: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => $or$../../../core/verilog/core.v:656$9_Y,
B => UART_DOut_s,
Y => $or$../../../core/verilog/core.v:656$10_Y
);
$or$../../../core/verilog/core.v:656$11: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => $or$../../../core/verilog/core.v:656$10_Y,
B => SPI_DOut_s,
Y => $or$../../../core/verilog/core.v:656$11_Y
);
$or$../../../core/verilog/core.v:656$12: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => $or$../../../core/verilog/core.v:656$11_Y,
B => CfgIntf_DOut_s,
Y => $or$../../../core/verilog/core.v:656$12_Y
);
$or$../../../core/verilog/core.v:656$13: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => $or$../../../core/verilog/core.v:656$12_Y,
B => ParamIntf_DOut_s,
Y => $or$../../../core/verilog/core.v:656$13_Y
);
$or$../../../core/verilog/core.v:656$14: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => $or$../../../core/verilog/core.v:656$13_Y,
B => "0000000000000000",
Y => Per_DOut_s
);
$or$../../../core/verilog/core.v:656$9: $or
generic map (
A_SIGNED => 0,
A_WIDTH => 16,
B_SIGNED => 0,
B_WIDTH => 16,
Y_WIDTH => 16
)
port map (
A => Gpio_DOut_s,
B => TimerA_DOut_s,
Y => $or$../../../core/verilog/core.v:656$9_Y
);
$procdff$52: $adff
generic map (
ARST_POLARITY => '0',
ARST_VALUE => "00",
CLK_POLARITY => '1',
WIDTH => 2
)
port map (
ARST => Reset_n_i,
CLK => Clk_i,
D => ResetSync(0) & '1',
Q => ResetSync
);
$procdff$53: $adff
generic map (
ARST_POLARITY => '0',
ARST_VALUE => '0',
CLK_POLARITY => '1',
WIDTH => 1
)
port map (
ARST => ResetSync(1),
CLK => Clk_i,
D => $0\I2C_ErrAck[0:0],
Q => I2C_ErrAck
);
$procdff$54: $adff
generic map (
ARST_POLARITY => '0',
ARST_VALUE => '0',
CLK_POLARITY => '1',
WIDTH => 1
)
port map (
ARST => ResetSync(1),
CLK => Clk_i,
D => I2C_ErrAckParam,
Q => I2C_ErrAckParamOld
);
$procmux$48: $mux
generic map (
WIDTH => 1
)
port map (
A => '0',
B => '1',
S => $logic_and$../../../core/verilog/core.v:914$46_Y,
Y => $0\I2C_ErrAck[0:0]
);
$reduce_or$../../../core/verilog/core.v:282$7: $reduce_or
generic map (
A_SIGNED => 0,
A_WIDTH => 12,
Y_WIDTH => 1
)
port map (
A => IRQ_s(6) & IRQ_s(7) & IRQ_s(8) & IRQ_s(9) & IRQ_s(4) & ReconfModuleIRQs_s & Gpio_IRQ2_s & Gpio_IRQ1_s,
Y => Wakeup_s
);
$reduce_or$../../../core/verilog/core.v:858$41: $reduce_or
generic map (
A_SIGNED => 0,
A_WIDTH => 8,
Y_WIDTH => 1
)
port map (
A => I2C_ErrReadCountZero & I2C_ErrGotNAck & I2C_ErrFIFOFull & I2C_ErrFIFOEmpty & I2C_ErrDevNotPresent & I2C_ErrCoreStopped & I2C_ErrCoreBusy & I2C_ErrBusColl,
Y => I2C_Error
);
$ternary$../../../core/verilog/core.v:673$15: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(0),
B => '0',
S => P1_Sel_s(0),
Y => P1_DOut_o(0)
);
$ternary$../../../core/verilog/core.v:674$16: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(1),
B => TimerA_Out0_s,
S => P1_Sel_s(1),
Y => P1_DOut_o(1)
);
$ternary$../../../core/verilog/core.v:675$17: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(2),
B => TimerA_Out1_s,
S => P1_Sel_s(2),
Y => P1_DOut_o(2)
);
$ternary$../../../core/verilog/core.v:676$18: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(3),
B => TimerA_Out2_s,
S => P1_Sel_s(3),
Y => P1_DOut_o(3)
);
$ternary$../../../core/verilog/core.v:677$19: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(4),
B => SMClk_s,
S => P1_Sel_s(4),
Y => P1_DOut_o(4)
);
$ternary$../../../core/verilog/core.v:678$20: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(5),
B => TimerA_Out0_s,
S => P1_Sel_s(5),
Y => P1_DOut_o(5)
);
$ternary$../../../core/verilog/core.v:679$21: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(6),
B => TimerA_Out1_s,
S => P1_Sel_s(6),
Y => P1_DOut_o(6)
);
$ternary$../../../core/verilog/core.v:680$22: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_DOut_s(7),
B => TimerA_Out2_s,
S => P1_Sel_s(7),
Y => P1_DOut_o(7)
);
$ternary$../../../core/verilog/core.v:681$23: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(0),
B => '0',
S => P1_Sel_s(0),
Y => P1_En_o(0)
);
$ternary$../../../core/verilog/core.v:682$24: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(1),
B => TimerA_Out0_En_s,
S => P1_Sel_s(1),
Y => P1_En_o(1)
);
$ternary$../../../core/verilog/core.v:683$25: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(2),
B => TimerA_Out1_En_s,
S => P1_Sel_s(2),
Y => P1_En_o(2)
);
$ternary$../../../core/verilog/core.v:684$26: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(3),
B => TimerA_Out2_En_s,
S => P1_Sel_s(3),
Y => P1_En_o(3)
);
$ternary$../../../core/verilog/core.v:685$27: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(4),
B => '1',
S => P1_Sel_s(4),
Y => P1_En_o(4)
);
$ternary$../../../core/verilog/core.v:686$28: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(5),
B => TimerA_Out0_En_s,
S => P1_Sel_s(5),
Y => P1_En_o(5)
);
$ternary$../../../core/verilog/core.v:687$29: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(6),
B => TimerA_Out1_En_s,
S => P1_Sel_s(6),
Y => P1_En_o(6)
);
$ternary$../../../core/verilog/core.v:688$30: $mux
generic map (
WIDTH => 1
)
port map (
A => P1_En_s(7),
B => TimerA_Out2_En_s,
S => P1_Sel_s(7),
Y => P1_En_o(7)
);
$ternary$../../../core/verilog/core.v:695$31: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_DOut_s(0),
B => AClk_En_s,
S => P2_Sel_s(0),
Y => P2_DOut_o(0)
);
$ternary$../../../core/verilog/core.v:696$32: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_DOut_s(1),
B => '0',
S => P2_Sel_s(1),
Y => P2_DOut_o(1)
);
$ternary$../../../core/verilog/core.v:697$33: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_DOut_s(2),
B => TimerA_Out0_s,
S => P2_Sel_s(2),
Y => P2_DOut_o(2)
);
$ternary$../../../core/verilog/core.v:698$34: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_DOut_s(3),
B => TimerA_Out1_s,
S => P2_Sel_s(3),
Y => P2_DOut_o(3)
);
$ternary$../../../core/verilog/core.v:699$35: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_DOut_s(4),
B => TimerA_Out2_s,
S => P2_Sel_s(4),
Y => P2_DOut_o(4)
);
$ternary$../../../core/verilog/core.v:703$36: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_En_s(0),
B => '1',
S => P2_Sel_s(0),
Y => P2_En_o(0)
);
$ternary$../../../core/verilog/core.v:704$37: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_En_s(1),
B => '0',
S => P2_Sel_s(1),
Y => P2_En_o(1)
);
$ternary$../../../core/verilog/core.v:705$38: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_En_s(2),
B => TimerA_Out0_En_s,
S => P2_Sel_s(2),
Y => P2_En_o(2)
);
$ternary$../../../core/verilog/core.v:706$39: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_En_s(3),
B => TimerA_Out1_En_s,
S => P2_Sel_s(3),
Y => P2_En_o(3)
);
$ternary$../../../core/verilog/core.v:707$40: $mux
generic map (
WIDTH => 1
)
port map (
A => P2_En_s(4),
B => TimerA_Out2_En_s,
S => P2_Sel_s(4),
Y => P2_En_o(4)
);
DMem_0: ram
generic map (
$1 => 6,
$2 => 256
)
port map (
ram_addr => DMem_Addr_s,
ram_cen => DMem_En_n_s,
ram_clk => MClk_s,
ram_din => DMem_DIn_s,
ram_dout => DMem_DOut_s,
ram_wen => DMem_Wr_n_s
);
PMem_0: ram
generic map (
$1 => 11,
$2 => 8192
)
port map (
ram_addr => PMem_Addr_s,
ram_cen => PMem_En_n_s,
ram_clk => MClk_s,
ram_din => PMem_DIn_s,
ram_dout => PMem_DOut_s,
ram_wen => PMem_Wr_n_s
);
gpio_0: omsp_gpio
generic map (
P1_EN => '1',
P2_EN => '1',
P3_EN => '1',
P4_EN => '0',
P5_EN => '0',
P6_EN => '0'
)
port map (
irq_port1 => Gpio_IRQ1_s,
irq_port2 => Gpio_IRQ2_s,
mclk => SMClk_s,
p1_din => P1_DIn_i,
p1_dout => P1_DOut_s,
p1_dout_en => P1_En_s,
p1_sel => P1_Sel_s,
p2_din => P2_DIn_i,
p2_dout => P2_DOut_s,
p2_dout_en => P2_En_s,
p2_sel => P2_Sel_s,
p3_din => P3_DIn_s,
p3_dout => P3_DOut_s,
p3_dout_en => P3_En_s,
p3_sel => P3_Sel_s,
p4_din => "00000000",
p4_dout => P4_DOut_s,
p4_dout_en => P4_En_s,
p4_sel => P4_Sel_s,
p5_din => "00000000",
p5_dout => P5_DOut_s,
p5_dout_en => P5_En_s,
p5_sel => P5_Sel_s,
p6_din => "00000000",
p6_dout => P6_DOut_s,
p6_dout_en => P6_En_s,
p6_sel => P6_Sel_s,
per_addr => Per_Addr_s,
per_din => Per_DIn_s,
per_dout => Gpio_DOut_s,
per_en => Per_En_s,
per_we => Per_Wr_s,
puc_rst => PUC_Reset_s
);
i2c_master_1: i2c_master
generic map (
DividerWidth_g => 16,
FIFOAddressWidth_g => 2,
ReadCountWidth_g => 4
)
port map (
Busy_o => I2C_Busy,
Clk_i => Clk_i,
Data_i => I2C_DataIn,
Data_o => I2C_DataOut,
Divider800_i => I2C_Divider800,
ErrAck_i => I2C_ErrAck,
ErrBusColl_o => I2C_ErrBusColl,
ErrCoreBusy_o => I2C_ErrCoreBusy,
ErrCoreStopped_o => I2C_ErrCoreStopped,
ErrDevNotPresent_o => I2C_ErrDevNotPresent,
ErrFIFOEmpty_o => I2C_ErrFIFOEmpty,
ErrFIFOFull_o => I2C_ErrFIFOFull,
ErrGotNAck_o => I2C_ErrGotNAck,
ErrReadCountZero_o => I2C_ErrReadCountZero,
F100_400_n_i => I2C_F100_400_n,
FIFOEmpty_o => I2C_FIFOEmpty,
FIFOFull_o => I2C_FIFOFull,
FIFOReadNext_i => I2C_FIFOReadNext,
FIFOWrite_i => I2C_FIFOWrite,
ReadCount_i => I2C_ReadCount,
ReceiveSend_n_i => I2C_ReceiveSend_n,
Reset_i => Reset_s,
SCL_o => I2CSCL_o,
SDA_i => I2CSDA_i,
SDA_o => I2CSDA_o,
ScanClk_i => '0',
ScanDataIn_i => '0',
ScanDataOut_o => I2C_ScanDataOut,
ScanEnable_i => '0',
StartProcess_i => I2C_StartProcess
);
openMSP430_0: openMSP430
port map (
aclk => AClk_s,
aclk_en => AClk_En_s,
cpu_en => Cpu_En_i,
dbg_en => Dbg_En_i,
dbg_freeze => Dbg_Freeze_s,
dbg_i2c_addr => "0101010",
dbg_i2c_broadcast => "1111111",
dbg_i2c_scl => Dbg_SCL_i,
dbg_i2c_sda_in => Dbg_SDA_In_i,
dbg_i2c_sda_out => Dbg_SDA_Out_o,
dbg_uart_rxd => '0',
dbg_uart_txd => Dbg_UART_TxD_s,
dco_clk => Clk_i,
dco_enable => DCO_Enable_s,
dco_wkup => DCO_Wakeup_s,
dmem_addr => DMem_Addr_s,
dmem_cen => DMem_En_n_s,
dmem_din => DMem_DIn_s,
dmem_dout => DMem_DOut_s,
dmem_wen => DMem_Wr_n_s,
irq => ReconfModuleIRQs_s(4 downto 2) & '0' & IRQ_s(9 downto 6) & '0' & IRQ_s(4) & Gpio_IRQ2_s & Gpio_IRQ1_s & ReconfModuleIRQs_s(1 downto 0),
irq_acc => IRQ_Ack_s,
lfxt_clk => LFXT_Clk_i,
lfxt_enable => LFXT_Enable_s,
lfxt_wkup => LFXT_Wakeup_s,
mclk => MClk_s,
nmi => '0',
per_addr => Per_Addr_s,
per_din => Per_DIn_s,
per_dout => Per_DOut_s,
per_en => Per_En_s,
per_we => Per_Wr_s,
pmem_addr => PMem_Addr_s,
pmem_cen => PMem_En_n_s,
pmem_din => PMem_DIn_s,
pmem_dout => PMem_DOut_s,
pmem_wen => PMem_Wr_n_s,
puc_rst => PUC_Reset_s,
reset_n => Reset_n_i,
scan_enable => '0',
scan_mode => '0',
smclk => SMClk_s,
smclk_en => SMClk_En_s,
wkup => Wakeup_s
);
spi_0: SimpleSPI
generic map (
BaseAddr => "000000010000000"
)
port map (
Clk_i => SMClk_s,
Intr_o => IRQ_s(4),
MISO_i => MISO_i,
MOSI_o => MOSI_o,
PerAddr_i => Per_Addr_s,
PerDIn_i => Per_DIn_s,
PerDOut_o => SPI_DOut_s,
PerEn_i => Per_En_s,
PerWr_i => Per_Wr_s,
Reset_n_i => ResetSync(1),
SCK_o => SCK_o
);
spi_master_1: SPI_Master
generic map (
DataWidth => 8,
FIFOReadWidth => 2,
FIFOWriteWidth => 2,
SPPRWidth => 4,
SPRWidth => 4
)
port map (
CPHA_i => SPI_CPHA,
CPOL_i => SPI_CPOL,
Clk => Clk_i,
Data_i => SPI_DataIn,
Data_o => SPI_DataOut,
FIFOEmpty_o => SPI_FIFOEmpty,
FIFOFull_o => SPI_FIFOFull,
LSBFE_i => SPI_LSBFE,
MISO_i => SPIMISO_i,
MOSI_o => SPIMOSI_o,
ReadNext_i => SPI_ReadNext,
Reset_n => ResetSync(1),
SCK_o => SPISCK_o,
SPPR_i => SPI_SPPR_SPR(7 downto 4),
SPR_i => SPI_SPPR_SPR(3 downto 0),
ScanClk_i => '0',
ScanDataIn_i => '0',
ScanDataOut_o => SPI_ScanDataOut,
ScanEnable_i => '0',
Transmission_o => SPI_Transmission,
Write_i => SPI_Write
);
timerA_0: omsp_timerA
port map (
aclk_en => AClk_En_s,
dbg_freeze => Dbg_Freeze_s,
inclk => P2_DIn_i(1),
irq_ta0 => IRQ_s(9),
irq_ta0_acc => IRQ_Ack_s(9),
irq_ta1 => IRQ_s(8),
mclk => SMClk_s,
per_addr => Per_Addr_s,
per_din => Per_DIn_s,
per_dout => TimerA_DOut_s,
per_en => Per_En_s,
per_we => Per_Wr_s,
puc_rst => PUC_Reset_s,
smclk_en => SMClk_En_s,
ta_cci0a => P1_DIn_i(1),
ta_cci0b => P2_DIn_i(2),
ta_cci1a => P1_DIn_i(2),
ta_cci1b => P2_DIn_i(3),
ta_cci2a => P1_DIn_i(3),
ta_cci2b => P1_DIn_i(0),
ta_out0 => TimerA_Out0_s,
ta_out0_en => TimerA_Out0_En_s,
ta_out1 => TimerA_Out1_s,
ta_out1_en => TimerA_Out1_En_s,
ta_out2 => TimerA_Out2_s,
ta_out2_en => TimerA_Out2_En_s,
taclk => P1_DIn_i(0)
);
uart_0: omsp_uart
generic map (
BASE_ADDR => "000000001110000"
)
port map (
irq_uart_rx => IRQ_s(7),
irq_uart_tx => IRQ_s(6),
mclk => SMClk_s,
per_addr => Per_Addr_s,
per_din => Per_DIn_s,
per_dout => UART_DOut_s,
per_en => Per_En_s,
per_we => Per_Wr_s,
puc_rst => PUC_Reset_s,
smclk_en => SMClk_En_s,
uart_rxd => UartRxD_i,
uart_txd => UartTxD_o
);
CPU_Enable_s <= Cpu_En_i;
I2C_Errors <= I2C_ErrReadCountZero & I2C_ErrDevNotPresent & I2C_ErrCoreStopped & I2C_ErrFIFOEmpty & I2C_ErrCoreBusy & I2C_ErrGotNAck & I2C_ErrFIFOFull & I2C_ErrBusColl;
INClk_s <= P2_DIn_i(1);
IRQ_s(13 downto 10) & IRQ_s(5) & IRQ_s(3 downto 0) <= ReconfModuleIRQs_s(4 downto 2) & "00" & Gpio_IRQ2_s & Gpio_IRQ1_s & ReconfModuleIRQs_s(1 downto 0);
P1_DIn_s <= P1_DIn_i;
P2_DIn_s <= P2_DIn_i;
P2_DOut_o(7 downto 5) <= P2_DOut_s(7 downto 5);
P2_En_o(7 downto 5) <= P2_En_s(7 downto 5);
P3_DOut_s <= ReconfModuleIn_s;
P3_DIn_s <= ReconfModuleOut_s;
Reset_n_s <= ResetSync(1);
SPI_IRQ_s <= IRQ_s(4);
TAClk_s <= P1_DIn_i(0);
TimerA_CCI0A_s <= P1_DIn_i(1);
TimerA_CCI0B_s <= P2_DIn_i(2);
TimerA_CCI1A_s <= P1_DIn_i(2);
TimerA_CCI1B_s <= P2_DIn_i(3);
TimerA_CCI2A_s <= P1_DIn_i(3);
TimerA_CCI2B_s <= P1_DIn_i(0);
TimerA_IRQ1_s <= IRQ_s(9);
TimerA_IRQ2_s <= IRQ_s(8);
UART_IRQ_Rx_s <= IRQ_s(7);
UART_IRQ_Tx_s <= IRQ_s(6);
end struct;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/uart/rxmodule-e.vhd | 1 | 2569 | ----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Armin Faltinger
--
-- Create Date: 09:35:01 11/19/2009
-- Module Name: RxModule - structure
-- Project Name: Uart
-- Description: RxModule binds all receive modules
--
-- Dependencies: pure structure
-- RxModule
-- |- BaudGenerator: RXBAUD
-- |- RxDataStateMachine: RXSM
-- |- ErrorIndicator: RXERRORIND
-- |- ErrorBit: PARITYERR, STOPERR, RXBUFFERR
-- |- FIFOSyncTop: RXFIFO
-- |- FIFODualPortRam: DualPortRam
-- |- FIFOBinaryCounter: WriteCounter, ReadCounter
-- |- FIFOSyncCmp: SyncCmp
-- package: UartPkg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.UartPkg.all;
entity RxModule is
generic ( MaxDataWidth : integer range 2 to 64 := 9;
MaxSpeedDividerWidth : integer := 16;
RxFifoAdressWidth : integer range 2 to 10 := 4; -- 16 entries
Oversampling : integer range 2 to 2 := 2); -- only 2 allowed due to majority decision logic
Port ( -- Parallel data inputs; CPU sided
RxData_o : out STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
RxRd_i : in STD_LOGIC;
RxFull_o : out STD_LOGIC;
RxEmpty_o : out STD_LOGIC;
-- Configuration bits
BitsSelect_i : in BitSelectionType;
ParityOn_i : in STD_LOGIC;
ParityEvenOdd_i : in ParityType;
SpeedDivider_i : in STD_LOGIC_VECTOR((MaxSpeedDividerWidth-1) downto 0);
-- Global Signals
Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
-- Error Signals
RxParityErrorIndicator_o : out STD_LOGIC;
RxStopBitErrorIndicator_o : out STD_LOGIC;
RxBufferFullErrorIndicator_o : out STD_LOGIC;
-- Seriell input port
RxD_i : in STD_LOGIC);
end RxModule;
| gpl-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/ipcore_dir/Data_Mem/simulation/bmg_stim_gen.vhd | 2 | 7813 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadc/chll/out/extadc-fsm-fsm-wrapper.vhd | 2 | 3479 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
Out10_o : out std_logic;
Out11_o : out std_logic;
Out12_o : out std_logic;
Out13_o : out std_logic;
Out14_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end FSM;
architecture struct of FSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(7 downto 0);
signal Output_s : std_logic_vector(14 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 8,
OutputWidth => 15,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 10,
NumRows2 => 10,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
Out10_o <= Output_s(10);
Out11_o <= Output_s(11);
Out12_o <= Output_s(12);
Out13_o <= Output_s(13);
Out14_o <= Output_s(14);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadc/chll/out/extadc-extract-fsm-wrapper.vhd | 2 | 3479 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
Out10_o : out std_logic;
Out11_o : out std_logic;
Out12_o : out std_logic;
Out13_o : out std_logic;
Out14_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end FSM;
architecture struct of FSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(7 downto 0);
signal Output_s : std_logic_vector(14 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 8,
OutputWidth => 15,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 10,
NumRows2 => 10,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
Out10_o <= Output_s(10);
Out11_o <= Output_s(11);
Out12_o <= Output_s(12);
Out13_o <= Output_s(13);
Out14_o <= Output_s(14);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
hansiglaser/chll | tools/flowcmd/templates/chip/celllib/trfsm/vhdl/LargeMux-rtl-a.vhd | 2 | 891 | architecture rtl of LargeMux is
type Input_t is array (0 to NumTransitionRows-1) of std_logic_vector(Width-1 downto 0);
signal Inputs : Input_t;
signal InputAnd_s : Input_t;
begin -- rtl
TypeCast: for InputNum in 0 to NumTransitionRows-1 generate
Inputs(InputNum) <= Inputs_i((InputNum+1)*Width-1 downto InputNum*Width);
end generate TypeCast;
AndStruct: for i in 0 to NumTransitionRows-1 generate
InputAnd_s(i) <= Inputs(i) when Select_i(i) = '1' else (others => '0');
end generate AndStruct;
OrStruct: process (InputAnd_s)
variable result : std_logic;
begin -- process OrStruct
for i in Width-1 downto 0 loop
result := '0';
for TR in 0 to NumTransitionRows-1 loop
result := result or InputAnd_s(TR)(i);
end loop; -- TR
Output_o(i) <= result;
end loop; -- i
end process OrStruct;
end rtl; -- of LargeMux
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/tb/chip_max6682mean_tb.vhd | 2 | 11150 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Chip_tb is
end Chip_tb;
architecture behavior of Chip_tb is
component Chip
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
-- OneWire_b : inout std_logic;
-- PWM_i : in std_logic;
-- SENT_i : in std_logic;
-- SPC_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0)
);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0);
Enable : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_b : std_logic;
signal P1_b : std_logic_vector(7 downto 0);
signal P2_b : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_b : std_logic;
signal I2CSDA_b : std_logic;
-- signal OneWire_b : std_logic;
-- signal PWM_i : std_logic;
-- signal SENT_i : std_logic;
-- signal SPC_b : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
signal Enable_e : std_logic; -- directly from inside
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal Enable_i : std_logic; -- directly from inside
-- MAX6682 component ports
signal MAX6682CS_n_o : std_logic;
constant ClkPeriode : time := 10 ns;
-- MAX6682 simulation
signal MAX6682Value : unsigned(10 downto 0);
begin
DUT: Chip
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_b => Dbg_SDA_b,
P1_b => P1_b,
P2_b => P2_b,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_b => I2CSCL_b,
I2CSDA_b => I2CSDA_b,
-- OneWire_b => OneWire_b,
-- PWM_i => PWM_i,
-- SENT_i => SENT_i,
-- SPC_b => SPC_b,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
MAX6682CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
Cpu_En_i <= '1';
Dbg_En_i <= '0';
-- Dbg_UART_RxD_i <= '1';
Dbg_SCL_i <= 'H';
Dbg_SDA_b <= 'H';
P1_b <= (others => 'H');
P2_b <= (others => 'H');
UartRxD_i <= '1';
MISO_i <= '0';
I2CSCL_b <= 'H';
I2CSDA_b <= 'H';
-- OneWire_b <= 'H';
-- PWM_i <= 'H';
-- SENT_i <= 'H';
-- SPC_b <= 'H';
AdcConvComplete_i <= '0';
AdcValue_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e,
Enable => Enable_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
Enable_i <= Enable_e after 1.0 ns;
SPIMISO_i <= 'H';
MAX6682_1: MAX6682_Model
port map (
ChipSelect_n_i => MAX6682CS_n_o,
SCLK_i => SPISCK_o,
SO_o => SPIMISO_i,
Value_i => std_logic_vector(MAX6682Value));
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
MAX6682Value <= (others => '0');
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
wait until Enable_i = '1';
wait for 9*ClkPeriode; -- 9 cycles
assert MAX6682CS_n_o = '1' report "CS_n should be '1'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '0' report "CS_n should be '0' after 10 cycles" severity error;
wait for 35*ClkPeriode; -- 35 cycles
assert MAX6682CS_n_o = '0' report "CS_n should still be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
-- new sensor value: 38 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(38,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
-- new sensor value: 30 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(30,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 28 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(28,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 27 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(27,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 27" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7410/tb/core_adt7410_tb.vhd | 1 | 12803 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7410_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
i2c_addr_i : in std_logic_vector(1 downto 0);
int_o : out std_logic;
ct_o : out std_logic;
temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic := '0';
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic := 'H';
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic := 'H';
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic := '1';
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic := '0';
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic := '0';
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0) := (others => '0');
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_e : std_logic; -- directly from inside I2C_FSM
signal CpuIntr_e : std_logic; -- directly from inside I2C_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- ADT7410 component ports
signal I2C_SDA_s : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
signal TempBin_s : std_logic_vector(15 downto 0);
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
I2CFSM_Done_d <= I2CFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
TempBin_s <= std_logic_vector(to_unsigned(integer(Temp_s*128.0),16));
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
I2C_SDA_s <= 'H'; -- weak 1 -> simulate pull-up
I2C_SDA_s <= '0' when I2CSDA_o = '0' else 'Z';
I2CSDA_i <= to_X01(I2C_SDA_s) after 0.2 us;
adt7410_1: adt7410_model
port map (
scl_i => I2CSCL_o,
sda_io => I2C_SDA_s,
i2c_addr_i => "00",
INT_o => INT_n_s,
CT_o => CT_n_s,
temp_i => TempBin_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
wait until I2CFSM_Done_d = '1';
report "Starting with test pattern" severity note;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/tb/max6682-model_tb.vhd | 2 | 4119 | -------------------------------------------------------------------------------
-- Title : Testbench for design "MAX6682_Model"
-- Project :
-------------------------------------------------------------------------------
-- File : max6682_tb.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2011-04-14
-- Last update: 2011-04-14
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-14 1.0 hansi Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity MAX6682_Model_tb is
end MAX6682_Model_tb;
-------------------------------------------------------------------------------
architecture behavior of MAX6682_Model_tb is
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0));
end component;
-- component ports
signal ChipSelect_n_i : std_logic;
signal SCLK_i : std_logic;
signal SO_o : std_logic;
signal Value_i : std_logic_vector(10 downto 0);
-- clock
signal Clk : std_logic := '0';
begin -- behavior
-- component instantiation
DUT: MAX6682_Model
port map (
ChipSelect_n_i => ChipSelect_n_i,
SCLK_i => SCLK_i,
SO_o => SO_o,
Value_i => Value_i);
-- waveform generation
WaveGen_Proc: process
begin
ChipSelect_n_i <= '1';
SCLK_i <= '0';
Value_i <= "10110011101";
-- 1st round
wait for 1 us;
ChipSelect_n_i <= '0';
wait for 200 ns;
for i in 0 to 14 loop
SCLK_i <= '1';
wait for 100 ns;
SCLK_i <= '0';
wait for 100 ns;
end loop; -- i
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
ChipSelect_n_i <= '1';
wait for 100 ns;
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
-- 2nd round
Value_i <= "11010011010";
wait for 1 us;
ChipSelect_n_i <= '0';
wait for 200 ns;
for i in 0 to 14 loop
SCLK_i <= '1';
wait for 100 ns;
if i = 5 then
Value_i <= (others => '0');
end if;
SCLK_i <= '0';
wait for 100 ns;
end loop; -- i
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
ChipSelect_n_i <= '1';
wait for 200 ns;
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
wait for 200 ns;
-- 3rd round
Value_i <= "00011010011";
wait for 1 us;
ChipSelect_n_i <= '0';
wait for 200 ns;
for i in 0 to 8 loop
SCLK_i <= '1';
wait for 100 ns;
SCLK_i <= '0';
wait for 100 ns;
end loop; -- i
ChipSelect_n_i <= '1';
wait for 200 ns;
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
wait for 200 ns;
-- 4th round
Value_i <= "11100101000";
wait for 1 us;
ChipSelect_n_i <= '0';
wait for 200 ns;
for i in 0 to 10 loop
SCLK_i <= '1';
wait for 100 ns;
SCLK_i <= '0';
wait for 100 ns;
end loop; -- i
ChipSelect_n_i <= '1';
wait for 200 ns;
assert SO_o = 'Z' report "SO_o should be 'Z'" severity error;
wait for 200 ns;
assert false report "*** Simulation Finished ***" severity failure;
end process WaveGen_Proc;
end behavior;
-------------------------------------------------------------------------------
configuration MAX6682_Model_tb_behavior_cfg of MAX6682_Model_tb is
for behavior
end for;
end MAX6682_Model_tb_behavior_cfg;
-------------------------------------------------------------------------------
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310/tb/chip_adt7310_tb.vhd | 9 | 13315 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Chip_tb is
generic (
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
ClkPeriode : time := 10 us
);
--ClkPeriode : time := 100 ns;
end Chip_tb;
architecture behavior of Chip_tb is
component Chip
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
-- OneWire_b : inout std_logic;
-- PWM_i : in std_logic;
-- SENT_i : in std_logic;
-- SPC_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_b : std_logic;
signal P1_b : std_logic_vector(7 downto 0);
signal P2_b : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_b : std_logic;
signal I2CSDA_b : std_logic;
-- signal OneWire_b : std_logic;
-- signal PWM_i : std_logic;
-- signal SENT_i : std_logic;
-- signal SPC_b : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_e : std_logic; -- directly from inside SPI_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- ADT7310 component ports
signal ADT7310CS_n_o : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
begin
DUT: Chip
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_b => Dbg_SDA_b,
P1_b => P1_b,
P2_b => P2_b,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_b => I2CSCL_b,
I2CSDA_b => I2CSDA_b,
-- OneWire_b => OneWire_b,
-- PWM_i => PWM_i,
-- SENT_i => SENT_i,
-- SPC_b => SPC_b,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
ADT7310CS_n_o <= Outputs_o(0);
Inputs_i <= (others => '0');
Cpu_En_i <= '1';
Dbg_En_i <= '0';
-- Dbg_UART_RxD_i <= '1';
Dbg_SCL_i <= 'H';
Dbg_SDA_b <= 'H';
P1_b <= (others => 'H');
P2_b <= (others => 'H');
UartRxD_i <= '1';
MISO_i <= '0';
I2CSCL_b <= 'H';
I2CSDA_b <= 'H';
-- OneWire_b <= 'H';
-- PWM_i <= 'H';
-- SENT_i <= 'H';
-- SPC_b <= 'H';
AdcConvComplete_i <= '0';
AdcValue_i <= (others => '0');
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
SPIFSM_Done_d <= SPIFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
adt7310_1: adt7310_model
port map (
SCLK_i => SPISCK_o,
DOUT_o => SPIMISO_i,
DIN_i => SPIMOSI_o,
CS_n_i => ADT7310CS_n_o,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- In WrapADT7310, i.e. in the original ADT7310 Verilog source, SPIFSM_Done
-- is '1' directly after reset (combinational!). When using the
-- ReconfModule with the included TR-FSMs, the signal starts at '0' and is
-- set to '1' as soon as the config bitstream gets activated, i.e. when the
-- configuration is done and CfgMode_i goes to '0'.
--
-- Here we wait for the _second_ rising edge of SPIFSM_Done, because at the
-- first time, the sensor is queried, but the result can only be read back
-- after 240ms, i.e. at the second SPI transmission.
if SPIFSM_Done_d = '0' then
-- SPIFSM_Done starts at '0', so this simulation uses the TR-FSMs
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(10 ns);
report "Configuration done, ADT7310 App. starts working" severity note;
end if;
wait until SPIFSM_Done_d = '0' and SPIFSM_Done_d'quiet(10 ns);
-- There is a short "notch" in ADT7310CS_n_o of approx. 3ns approx. 10ns
-- after it went high. Wait for 12ns instead of only 10ns to get behind
-- this glich.
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(12 ns);
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(12 ns);
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(12 ns);
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(12 ns);
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until SPIFSM_Done_d = '1' and SPIFSM_Done_d'quiet(12 ns);
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/slowadt7410/chll/out/slowadt7410-extract-intersynth-trfsm3-bitstream.vhd | 6 | 2053 | constant TRFSM3Length : integer := 1935;
constant TRFSM3Cfg : std_logic_vector(TRFSM3Length-1 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/spi_master/vhdl/spicontrol-e.vhd | 1 | 1306 | ----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 21:57:29 01/28/2010
-- Design Name: SPI
-- Module Name: SPIControl - RTL
-- Description: Control module for SPI
--
-- Revision:
-- Revision 0.01 - File Created
--
-- Associated Testbench:
-- tb_SPIControl.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.Utils.all;
entity SPIControl is
Generic (
DataWidth : integer range 2 to 64 := 8);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
-- SPI config param
CPOL_i : in STD_LOGIC;
CPHA_i : in STD_LOGIC;
-- SPI clock output
SCK_o : out STD_LOGIC;
-- SPI control signals
Transmission_o : out STD_LOGIC;
EnFrqDivider_o : out STD_LOGIC;
NextStep_i : in STD_LOGIC;
LdShifter_o : out STD_LOGIC;
EnShift_o : out STD_LOGIC;
EnSample_o : out STD_LOGIC;
WrFIFOEmpty_i : in STD_LOGIC;
RdWriteFIFO_o : out STD_LOGIC;
RdFIFOFull_i : in STD_LOGIC;
LdReadFIFO_o : out STD_LOGIC);
end SPIControl;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/extadcsimple/tb/extadcsimple_tb.vhd | 1 | 15065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ExtADCSimple_tb is
end ExtADCSimple_tb;
architecture behavior of ExtADCSimple_tb is
component ExtADCSimple
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
SensorPower_o : out std_logic;
SensorStart_o : out std_logic;
SensorReady_i : in std_logic;
AdcStart_o : out std_logic;
AdcDone_i : in std_logic;
AdcValue_i : in std_logic_vector(15 downto 0);
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal SensorPower_o : std_logic;
signal SensorStart_o : std_logic;
signal SensorReady_i : std_logic;
signal AdcStart_o : std_logic;
signal AdcDone_i : std_logic;
constant AdcValueWidth : integer := 16;
signal AdcValue_i : std_logic_vector(AdcValueWidth-1 downto 0);
signal PeriodCounterPreset_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
constant ClkPeriode : time := 100 ns;
begin
DUT: ExtADCSimple
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
SensorPower_o => SensorPower_o,
SensorStart_o => SensorStart_o,
SensorReady_i => SensorReady_i,
AdcStart_o => AdcStart_o,
AdcDone_i => AdcDone_i,
AdcValue_i => AdcValue_i,
PeriodCounterPreset_i => PeriodCounterPreset_i,
SensorValue_o => SensorValue_o
);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
SensorReady_i <= '0';
AdcDone_i <= '0';
AdcValue_i <= (others => '0');
PeriodCounterPreset_i <= "0000000000001010";
-- Check constant values of dynamic signals coming out of the application modules
wait for 0.1*ClkPeriode;
-- none to check
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
report "Enable, first cycle at value 0" severity note;
Enable_i <= '1';
wait for 9*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 0.1*ClkPeriode;
assert AdcStart_o = '1' report "AdcStart_o should be '1'" severity error;
wait for 0.9*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 38
report "2nd cycle, new sensor value: 38" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(38,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 30
report "3rd cycle, new sensor value: 30" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(30,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 28
report "4th cycle, new sensor value: 28" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(28,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 27
report "5th cycle, new sensor value: 27" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(27,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
report "done testing" severity note;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682/chll/out/max6682-extract-sensorfsm-wrapper.vhd | 8 | 3283 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
| gpl-2.0 |
hansiglaser/chll | tools/flowcmd/templates/chip/vhdl_packs/config-p.vhd | 2 | 112 | package Config is
constant CfgClkGating : boolean := true;
end Config;
package body Config is
end Config;
| gpl-2.0 |
hansiglaser/chll | tools/flowcmd/templates/chip/celllib/trfsm/vhdl/ConfigRegister-e.vhd | 2 | 537 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Config.all;
-- used as Next State Register and as Output Pattern Register
entity ConfigRegister is
generic (
Width : integer range 1 to 65536
);
port (
Reset_n_i : in std_logic;
Output_o : out std_logic_vector(Width-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end ConfigRegister;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/core_tb-behavior-cfg-c.vhd | 1 | 171 | configuration Core_tb_behavior_cfg of Core_tb is
for behavior
for DUT : Core
use entity work.Core(verilog);
end for;
end for;
end Core_tb_behavior_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/reconfmodule/chll/out/chip-fpga_top-a.vhd | 1 | 3884 | -- Automatically generated: write_netlist -chip -vhdl -architecture chip-fpga_top-a.vhd
architecture fpga_top of chip is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
LFXT_Clk_i : in std_logic;
Dbg_En_i : in std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0)
);
end component;
signal Dbg_SDA_In_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
begin
core_1: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Cpu_En_i => Cpu_En_i,
LFXT_Clk_i => '0',
Dbg_En_i => Dbg_En_i,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_In_i => Dbg_SDA_In_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
P1_DIn_i => P1_DIn_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P2_DIn_i => P2_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
MISO_i => MISO_i,
MOSI_o => MOSI_o,
SCK_o => SCK_o,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
Dbg_SDA_In_i <= To_X01(Dbg_SDA_b);
OD_Dbg_SDA_b_Proc: process (Dbg_SDA_Out_o)
begin
if Dbg_SDA_Out_o = '1' then
Dbg_SDA_b <= 'Z';
else
Dbg_SDA_b <= '0';
end if;
end process OD_Dbg_SDA_b_Proc;
P1_DIn_i <= To_X01(P1_b);
InOut_P1_b_Proc: process (P1_DOut_o,P1_En_o)
begin
for I in P1_DOut_o'range loop
if P1_En_o(I) = '1' then
P1_b(I) <= P1_DOut_o(I);
else
P1_b(I) <= 'Z';
end if;
end loop;
end process InOut_P1_b_Proc;
P2_DIn_i <= To_X01(P2_b);
InOut_P2_b_Proc: process (P2_DOut_o,P2_En_o)
begin
for I in P2_DOut_o'range loop
if P2_En_o(I) = '1' then
P2_b(I) <= P2_DOut_o(I);
else
P2_b(I) <= 'Z';
end if;
end loop;
end process InOut_P2_b_Proc;
OD_I2CSCL_b_Proc: process (I2CSCL_o)
begin
if I2CSCL_o = '1' then
I2CSCL_b <= 'Z';
else
I2CSCL_b <= '0';
end if;
end process OD_I2CSCL_b_Proc;
I2CSDA_i <= To_X01(I2CSDA_b);
OD_I2CSDA_b_Proc: process (I2CSDA_o)
begin
if I2CSDA_o = '1' then
I2CSDA_b <= 'Z';
else
I2CSDA_b <= '0';
end if;
end process OD_I2CSDA_b_Proc;
end fpga_top;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/uart/uart-e.vhd | 1 | 3923 | ----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Armin Faltinger
--
-- Create Date: 09:35:01 11/19/2009
-- Module Name: Uart - structure
-- Project Name: Uart
-- Description: Uart binds all modules
--
-- Dependencies: pure structure
-- TxModule
-- |- BaudGenerator: TXBAUD
-- |- TxDataStateMachine: TXSM
-- |- FIFOSyncTop: TXFIFO,
-- |- FIFODualPortRam: DualPortRam
-- |- FIFOBinaryCounter: WriteCounter, ReadCounter
-- |- FIFOSyncCmp: SyncCmp
-- RxModule
-- |- BaudGenerator: RXBAUD
-- |- RxDataStateMachine: RXSM
-- |- ErrorIndicator: RXERRORIND
-- |- ErrorBit: PARITYERR, STOPERR, RXBUFFERR
-- |- FIFOSyncTop: RXFIFO
-- |- FIFODualPortRam: DualPortRam
-- |- FIFOBinaryCounter: WriteCounter, ReadCounter
-- |- FIFOSyncCmp: SyncCmp
-- package: UartPkg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.UartPkg.all;
-- Uart is the implementation of the UART core
-- MaxDataWith is in the range of 5-9 bits
-- The Fifo Size of Rx and Tx - module is independent
-- The 16550 Standard is determined by a 16 entries sized FIFO
-- (2^Oversampling)-1 = number of samplings for every bit; used in RXSM
-- coding of PartiyOn: parity is on at '1', off at '0'
entity Uart is
generic ( MaxDataWidth : integer range 5 to 9 := 9; -- 9
MaxSpeedDividerWidth : integer range 2 to 32 := 16; -- 16 bits
TxFifoAdressWidth : integer range 2 to 10 := 4; -- 16 entries
RxFifoAdressWidth : integer range 2 to 10 := 4; -- 16 entries
Oversampling : integer range 2 to 2 := 2); -- only 2 allowed due to majority decision logic
Port ( -- Parallel data inputs; CPU sided
TxData_i : in STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
TxWr_i : in STD_LOGIC;
TxEmpty_o : out STD_LOGIC;
TxFull_o : out STD_LOGIC;
RxData_o : out STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
RxRd_i : in STD_LOGIC;
RxFull_o : out STD_LOGIC;
RxEmpty_o : out STD_LOGIC;
-- Configuration bits
BitsSelect_i : in BitSelectionType;
ParityOn_i : in STD_LOGIC;
ParityEvenOdd_i : in ParityType;
SpeedDivider_i : in STD_LOGIC_VECTOR((MaxSpeedDividerWidth-1) downto 0);
-- Global Signals
Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
-- Error Signals
RxParityErrorIndicator_o : out STD_LOGIC;
RxStopBitErrorIndicator_o : out STD_LOGIC;
RxBufferFullErrorIndicator_o : out STD_LOGIC;
-- Seriell in/output ports
TxD_o : out STD_LOGIC;
RxD_i : in STD_LOGIC;
--------------------------------------------------------------------------
-- Scan Chain
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end Uart;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/simplespi/tb/simplespi_tb.vhd | 1 | 10966 | -------------------------------------------------------------------------------
-- Title : Testbench for design "SimpleSPI"
-- Project :
-------------------------------------------------------------------------------
-- File : simplespi_tb.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2014-08-25
-- Last update: 2014-08-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-08-25 1.0 hansi Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity SimpleSPI_tb is
end SimpleSPI_tb;
-------------------------------------------------------------------------------
architecture behavior of SimpleSPI_tb is
component SimpleSPI
generic (
BaseAddr : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
Intr_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic
);
end component;
-- component generics
constant BaseAddr : integer := 16#0188#;
-- component ports
signal Reset_n_i : std_logic := '0';
signal Clk_i : std_logic := '1';
signal PerAddr_i : std_logic_vector(13 downto 0);
signal PerDIn_i : std_logic_vector(15 downto 0);
signal PerDOut_o : std_logic_vector(15 downto 0);
signal PerWr_i : std_logic_vector(1 downto 0);
signal PerEn_i : std_logic;
signal Intr_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
-- clock
constant ClkPeriode : time := 100 ns;
begin -- behavior
-- component instantiation
DUT: SimpleSPI
generic map (
BaseAddr => BaseAddr
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => PerDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
Intr_o => Intr_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i
);
-- clock generation
Clk_i <= not Clk_i after ClkPeriode/2.0;
-- waveform generation
WaveGen_Proc: process
variable Result : std_logic_vector(15 downto 0);
procedure ClkCycle (
constant Count : in integer) is
begin -- ClkCycle
for i in 0 to Count-1 loop
wait until rising_edge(Clk_i);
wait for 0.2*ClkPeriode;
end loop; -- i
end ClkCycle;
procedure WriteWord (
constant Addr : in integer;
constant Value : in std_logic_vector) is
begin -- WriteWord
assert Addr mod 2 = 0 report "Only word-aligned access possible" severity failure;
PerAddr_i <= std_logic_vector(to_unsigned(Addr, 15)(14 downto 1));
PerDIn_i <= Value;
PerWr_i <= "11";
PerEn_i <= '1';
ClkCycle(1);
PerWr_i <= "00";
PerEn_i <= '0';
end WriteWord;
procedure WriteWord (
constant Addr : in integer;
constant Value : in integer) is
begin -- WriteWord
WriteWord(Addr,std_logic_vector(to_unsigned(Value,16)));
end WriteWord;
procedure ReadWord (
constant Addr : integer) is
begin -- ReadWord
assert Addr mod 2 = 0 report "Only word-aligned access possible" severity failure;
PerAddr_i <= std_logic_vector(to_unsigned(Addr, 15)(14 downto 1));
PerEn_i <= '1';
wait for 0.1*ClkPeriode; -- give simulator time to update signals
Result := PerDOut_o;
ClkCycle(1);
PerEn_i <= '0';
end ReadWord;
procedure CheckWord (
constant Addr : in integer;
constant Value : in std_logic_vector) is
begin -- CheckWord
assert Addr mod 2 = 0 report "Only word-aligned access possible" severity failure;
PerAddr_i <= std_logic_vector(to_unsigned(Addr, 15)(14 downto 1));
PerEn_i <= '1';
wait for 0.1*ClkPeriode; -- give simulator time to update signals
assert PerDOut_o = Value
report "Read resulted in wrong value" severity error;
Result := PerDOut_o;
ClkCycle(1);
PerEn_i <= '0';
end CheckWord;
procedure CheckWord (
constant Addr : in integer;
constant Value : in integer) is
begin -- CheckWord
CheckWord(Addr,std_logic_vector(to_unsigned(Value,16)));
end CheckWord;
procedure CheckTransfer (
constant IntEn : in std_logic;
constant BRDE : in std_logic_vector(3 downto 0);
constant BRDM : in std_logic_vector(3 downto 0);
constant CPHA : in std_logic;
constant CPOL : in std_logic;
constant MOSI_Byte : in std_logic_vector(7 downto 0);
constant MISO_Byte : in std_logic_vector(7 downto 0)
) is
variable NumCycles : integer; -- number of cycles per half-periode
begin
NumCycles := (to_integer(unsigned(BRDM))+1)*2**(to_integer(unsigned(BRDE)));
-- Busy res.
WriteWord(BaseAddr+0,"0" & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL);
ClkCycle(1);
WriteWord(BaseAddr+2,"00000000" & MOSI_Byte);
-- 1st cycle after write: Busy, Xfer and XferPhase were set at
-- rising_edge(Clk_i), PrescaleSet = '1' because PrescalePrev was held to
-- all '1', but nothing to see at the outputs
assert MOSI_o = '0' report "MOSI_o should still be '0'" severity error;
assert SCK_o = CPOL report "SCK_o should still be '" & std_logic'image(CPOL) & "'" severity error;
CheckWord(BaseAddr+0,"1" & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL); -- Busy bit is set
-- now the real transfer starts
for BitIdx in 7 downto 0 loop
-- first half-periode
MISO_i <= MISO_Byte(BitIdx);
for i in 1 to NumCycles loop
assert MOSI_o = MOSI_Byte(BitIdx) report "MOSI_o should be bit " & integer'image(BitIdx) & " = '" & std_logic'image(MOSI_Byte(BitIdx)) & "'" severity error;
assert SCK_o = (CPHA xor CPOL) report "SCK_o should be '" & std_logic'image(CPHA xor CPOL) & "' in first half" severity error;
CheckWord(BaseAddr+0,"1" & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL); -- Busy bit is set
end loop;
for i in 1 to NumCycles loop
assert MOSI_o = MOSI_Byte(BitIdx) report "MOSI_o should be bit " & integer'image(BitIdx) & " = '" & std_logic'image(MOSI_Byte(BitIdx)) & "'" severity error;
assert SCK_o = not (CPHA xor CPOL) report "SCK_o should be '" & std_logic'image(not (CPHA xor CPOL)) & "' in second half" severity error;
CheckWord(BaseAddr+0,"1" & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL); -- Busy bit is set
end loop;
end loop;
-- first cycle after last bit
assert MOSI_o = '0' report "MOSI_o should agaion be '0'" severity error;
assert SCK_o = CPOL report "SCK_o should still be '" & std_logic'image(CPOL) & "'" severity error;
assert Intr_o = IntEn report "Intr_o should be '" & std_logic'image(IntEn) & "'" severity error;
CheckWord(BaseAddr+0,"0" & "0000" & IntEn & BRDE & BRDM & CPHA & CPOL); -- Busy bit is set
-- check received value
CheckWord(BaseAddr+2,"00000000" & MISO_Byte);
ClkCycle(4);
end CheckTransfer;
begin
Reset_n_i <= '0';
wait for 5.2*ClkPeriode;
Reset_n_i <= '1';
---------------------------------------------------------------------------
-- silly write cycles to CSR
WriteWord(BaseAddr+0,16#5555#);
ClkCycle(3);
CheckWord(BaseAddr+0,16#0555#);
ClkCycle(3);
WriteWord(BaseAddr+0,16#AAAA#);
ClkCycle(3);
CheckWord(BaseAddr+0,16#02AA#);
ClkCycle(3);
---------------------------------------------------------------------------
-- Transfer bytes
CheckTransfer('0', "0000", "0001", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- CPHA=0, CPOL=0
CheckTransfer('1', "0000", "0001", '1', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- CPHA=1, CPOL=0
CheckTransfer('1', "0000", "0001", '0', '1', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- CPHA=0, CPOL=1
CheckTransfer('1', "0000", "0001", '1', '1', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- CPHA=1, CPOL=1
CheckTransfer('1', "0000", "0000", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 0, BRDM = 0 --> ClkPeriod/2
CheckTransfer('1', "0000", "0001", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 0, BRDM = 1 --> ClkPeriod/4
CheckTransfer('1', "0000", "0010", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 0, BRDM = 2 --> ClkPeriod/6
CheckTransfer('1', "0000", "0011", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 0, BRDM = 3 --> ClkPeriod/8
CheckTransfer('1', "0001", "0000", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 1, BRDM = 0 --> ClkPeriod/4
CheckTransfer('1', "0001", "0001", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 1, BRDM = 1 --> ClkPeriod/8
CheckTransfer('1', "0001", "0010", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 1, BRDM = 2 --> ClkPeriod/12
CheckTransfer('1', "0001", "0011", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 1, BRDM = 3 --> ClkPeriod/16
CheckTransfer('1', "0101", "0000", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 5, BRDM = 0 --> ClkPeriod/64
CheckTransfer('1', "0101", "0001", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 5, BRDM = 1 --> ClkPeriod/128
CheckTransfer('1', "0101", "0010", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 5, BRDM = 2 --> ClkPeriod/192
CheckTransfer('1', "0101", "0011", '0', '0', std_logic_vector(to_unsigned(16#00C9#,8)), "10100110"); -- BRDE = 5, BRDM = 3 --> ClkPeriod/256
---------------------------------------------------------------------------
ClkCycle(3);
report "### Simulation Finished ###" severity failure;
wait;
end process WaveGen_Proc;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/spi_master/vhdl/spishifter-rtl-a.vhd | 1 | 2093 |
architecture RTL of SPIShifter is
signal EnableShiftReg : STD_LOGIC;
signal ShiftRegister : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal NextShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal LoadShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal DataInRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal DataOut : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal DataOutRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal SampleRegister : STD_LOGIC;
begin
-- calculate DataInRev
DataInputReversion: process (Data_i)
begin
for BitNumber in DataWidth-1 downto 0 loop
DataInRev(BitNumber) <= Data_i((DataWidth-1) - BitNumber);
end loop;
end process DataInputReversion;
-- combinational inputs
EnableShiftReg <= LdShifter_i or EnShift_i;
LoadShiftReg <= Data_i when LSBFE_i = '0' else
DataInRev;
NextShiftReg <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister when LdShifter_i = '0' else
LoadShiftReg;
-- sequential statements
SPIShiftRegister: process (Reset_n, Clk)
begin
if Reset_n = '0' then
ShiftRegister <= (others => '0');
elsif Clk'event and Clk = '1' then
if EnableShiftReg = '1' then
ShiftRegister <= NextShiftReg;
end if;
end if;
end process SPIShiftRegister;
SPISampleRegister: process (Reset_n, Clk)
begin
if Reset_n = '0' then
SampleRegister <= '0';
elsif Clk'event and Clk = '1' then
if EnSample_i = '1' then
SampleRegister <= To_X01(MISO_i);
end if;
end if;
end process SPISampleRegister;
-- calculate DataOut
DataOut <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister;
-- calculate DataOutRev
DataOutputReversion: process (DataOut)
begin
for BitNumber in DataWidth-1 downto 0 loop
DataOutRev(BitNumber) <= DataOut((DataWidth-1) - BitNumber);
end loop;
end process DataOutputReversion;
-- combinational outputs
MOSI_o <= ShiftRegister(DataWidth-1);
Data_o <= DataOut when LSBFE_i = '0' else
DataOutRev;
end RTL;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/trfsm/vhdl/TransitionRow-e.vhd | 2 | 845 | library ieee;
use ieee.std_logic_1164.all;
use work.TRFSMParts.all;
entity TransitionRow is
generic (
TotalInputWidth : integer range 1 to 256;
MyInputWidth : integer range 0 to 10;
StateWidth : integer range 1 to 10;
OutputWidth : integer range 1 to 256
);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(TotalInputWidth-1 downto 0);
State_i : in std_logic_vector(StateWidth-1 downto 0);
Match_o : out std_logic;
NextState_o : out std_logic_vector(StateWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end TransitionRow;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/core/tb/core_tb-amsram-cfg-c.vhd | 1 | 354 | configuration Core_tb_amsram_cfg of Core_tb is
for behavior
for DUT : Core
use configuration work.CoreAMSRAM;
-- use entity work.Core(verilog);
-- for verilog
-- for DMem_0 : DMem
-- use configuration work.DMem_TimingChecksOFF_cfg;
-- end for;
-- end for;
end for;
end for;
end Core_tb_amsram_cfg;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/max6682mean/chll/out/reconflogic-wrapmax6682mean-a.vhd | 1 | 10328 | -- Automatically generated: write_netlist -wrapapp -vhdl -architecture reconflogic-wrapmax6682mean-a.vhd
architecture WrapMAX6682Mean of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgMode_o : out std_logic;
CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgDataOut_o : out std_logic;
CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0)
);
end component;
component MAX6682Mean
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PauseCounterPreset_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component ParamIntf
generic (
WrAddrWidth : integer range 1 to 15 := 4;
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end component;
component ParamOutReg
generic (
Width : integer := 16
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
ParamWrData_i : in std_logic_vector(Width-1 downto 0);
Param_o : out std_logic_vector(Width-1 downto 0)
);
end component;
signal PauseCounterPreset_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetH_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_s : std_logic_vector(15 downto 0);
signal SensorValue_s : std_logic_vector(15 downto 0);
signal Threshold_s : std_logic_vector(15 downto 0);
signal CfgClk_s : std_logic_vector(0 downto 0);
signal CfgMode_s : std_logic;
signal CfgShift_s : std_logic_vector(0 downto 0);
signal CfgDataOut_s : std_logic;
signal CfgDataIn_s : std_logic_vector(0 downto 0);
signal ParamWrAddr_s : std_logic_vector(2 downto 0);
signal ParamWrData_s : std_logic_vector(15 downto 0);
signal ParamWr_s : std_logic;
signal ParamRdAddr_s : std_logic_vector(0 downto 0);
signal ParamRdData_s : std_logic_vector(15 downto 0);
type Params_t is array(0 to 1) of std_logic_vector(15 downto 0);
signal Params_s : Params_t;
signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0);
signal ParamI2C_Divider800Enable_s : std_logic;
signal ParamI2C_ErrAckParamEnable_s : std_logic;
signal ParamPauseCounterPresetEnable_s : std_logic;
signal ParamPeriodCounterPresetHEnable_s : std_logic;
signal ParamPeriodCounterPresetLEnable_s : std_logic;
signal ParamThresholdEnable_s : std_logic;
begin
-- Configuration Interface
CfgIntf_0: CfgIntf
generic map (
BaseAddr => 16#0180#,
NumCfgs => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => CfgIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
CfgClk_o => CfgClk_s,
CfgMode_o => CfgMode_s,
CfgShift_o => CfgShift_s,
CfgDataOut_o => CfgDataOut_s,
CfgDataIn_i => CfgDataIn_s
);
-- Parameterization Interface: 6 write addresses, 2 read addresses
ParamIntf_0: ParamIntf
generic map (
BaseAddr => 16#0188#,
WrAddrWidth => 3,
RdAddrWidth => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => ParamIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
ParamWrAddr_o => ParamWrAddr_s,
ParamWrData_o => ParamWrData_s,
ParamWr_o => ParamWr_s,
ParamRdAddr_o => ParamRdAddr_s,
ParamRdData_i => ParamRdData_s
);
MAX6682Mean_0: MAX6682Mean
port map (
MAX6682CS_n_o => Outputs_o(0),
CpuIntr_o => ReconfModuleIRQs_o(0),
SPI_Data_o => SPI_DataIn_o,
SPI_Data_i => SPI_DataOut_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Transmission_i => SPI_Transmission_i,
SPI_Write_o => SPI_Write_o,
Enable_i => ReconfModuleIn_i(0),
Clk_i => Clk_i,
Reset_n_i => Reset_n_i,
PauseCounterPreset_i => PauseCounterPreset_s,
PeriodCounterPresetH_i => PeriodCounterPresetH_s,
PeriodCounterPresetL_i => PeriodCounterPresetL_s,
SensorValue_o => SensorValue_s,
Threshold_i => Threshold_s
);
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReadCount_o <= "0000";
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
Outputs_o(1) <= '0';
Outputs_o(2) <= '0';
Outputs_o(3) <= '0';
Outputs_o(4) <= '0';
Outputs_o(5) <= '0';
Outputs_o(6) <= '0';
Outputs_o(7) <= '0';
ReconfModuleIRQs_o(1) <= '0';
ReconfModuleIRQs_o(2) <= '0';
ReconfModuleIRQs_o(3) <= '0';
ReconfModuleIRQs_o(4) <= '0';
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_LSBFE_o <= '0';
SPI_SPPR_SPR_o <= "00000000";
ReconfModuleOut_o(0) <= '0';
ReconfModuleOut_o(1) <= '0';
ReconfModuleOut_o(2) <= '0';
ReconfModuleOut_o(3) <= '0';
ReconfModuleOut_o(4) <= '0';
ReconfModuleOut_o(5) <= '0';
ReconfModuleOut_o(6) <= '0';
ReconfModuleOut_o(7) <= '0';
-- just a fixed value for the config interface
CfgDataIn_s <= "0";
-- Param read address decoder
-- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
-- hope that the synthesis optimizes the MUX
-- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
-- 0 to n.", even during param write cycles, because ParamRdAddr has the
-- source as ParamWrAddr. Use the parameter "-noindexcheck" during
-- compilation ("vcom"). Simulation works fine then, but ModelSim generates
-- numerous "INTERNAL ERROR"s to stdout, which seem harmless.
ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s)));
ParamOutReg_I2C_Divider800: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_Divider800_o,
Enable_i => ParamI2C_Divider800Enable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_I2C_ErrAckParam: ParamOutReg
generic map (
Width => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_ErrAckParam_s,
Enable_i => ParamI2C_ErrAckParamEnable_s,
ParamWrData_i => ParamWrData_s(0 downto 0)
);
ParamOutReg_PauseCounterPreset: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PauseCounterPreset_s,
Enable_i => ParamPauseCounterPresetEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetH_s,
Enable_i => ParamPeriodCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetL_s,
Enable_i => ParamPeriodCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_Threshold: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => Threshold_s,
Enable_i => ParamThresholdEnable_s,
ParamWrData_i => ParamWrData_s
);
I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0);
-- Address $00
Params_s(0) <= "00000000" & I2C_Errors_i;
-- Address $01
Params_s(1) <= SensorValue_s;
-- Address $00
ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else
'0';
-- Address $01
ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else
'0';
-- Address $02
ParamPauseCounterPresetEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else
'0';
-- Address $03
ParamPeriodCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else
'0';
-- Address $04
ParamPeriodCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else
'0';
-- Address $05
ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "101" else
'0';
end WrapMAX6682Mean;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7410/chll/out/adt7410-fsm-i2cfsm-bitstream.vhd | 2 | 1413 | constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "00011000000001000000000000010001010000000100000000001100110000000000001000000111001000000010000000000100000101000000000000010000000000100001000000000100000000000000000001000100011100001000000000000001000000011000001000000000000100000010000000101010000000000000001000001000000010100000000000000100000000101000000011000101000000000000001001010000000101010110000000000000010100100000100100011000000000010000001001000001000101001000000000100000010100000000011000100000000100000000001000000011001000010000000001000000000100000001100010100100000000100000001011000000001111000110010000000000000110000000000111100001000000000001000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310/chll/out/adt7310-extract-intersynth-trfsm1-bitstream.vhd | 1 | 1896 | constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00000100011100001001100100000010000000000000011100000000010100101000000100101000000011000001100000100100001000011100010000001001100010000100000010100000100101000000100100001000001000010000011111100000000000000000000011111100000000000000000000011111100000000000000000000000000000000001000100000000000011100000000000000000001001000011000000100100000000001000000000010100001000000001010000100001000000000011000100000000100100000100001100000000101000001100000000100000000001100000000100100100100001000100000000101000000000100100000100001000100000000101000000000101000101000000000100000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000111111000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000";
| gpl-2.0 |
hansiglaser/chll | tools/flowcmd/templates/chip/celllib/trfsm/tb/tb_trfsm-behavior.vhd | 1 | 19568 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.trfsmpkg.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_trfsm is
end tb_trfsm;
architecture behavior of tb_trfsm is
constant InputWidth : integer range 1 to 256 := 10;
constant OutputWidth : integer range 1 to 256 := 7;
constant StateWidth : integer range 1 to 8 := 5;
constant UseResetRow : integer range 0 to 1 := 1;
constant UseCurrentState : integer range 0 to 1 := 1;
constant NumRows0 : integer := 3;
constant NumRows1 : integer := 2;
constant NumRows2 : integer := 6;
constant NumRows3 : integer := 6;
constant NumRows4 : integer := 9;
constant NumRows5 : integer := 0;
constant NumRows6 : integer := 0;
constant NumRows7 : integer := 0;
constant NumRows8 : integer := 0;
constant NumRows9 : integer := 0;
constant ConfigLength : integer := CalcTRFSMConfigLength(InputWidth,OutputWidth,StateWidth,UseResetRow,UseCurrentState,NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
-- Attention: don't make symmetric values because otherwise we can't find
-- problems with the order
constant CBS_S0_S1: std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1010xxxxxx","00000","00001","1100110");
constant CBS_S0_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1111xxxxxx","00000","00010","0011001");
constant CBS_S0_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0000xxxxxx","00000","00011","0110011");
constant CBS_S0_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1010xxxxxx,1111xxxxxx,0000xxxxxx","00000","00000","1111111");
constant CBS_S1_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1100xxxxxx","00001","00110","1111111");
constant CBS_S1_S7 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0011xxxxxx","00001","00111","1011101");
constant CBS_S1_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1100xxxxxx,0011xxxxxx","00001","00001","0111110");
constant CBS_S2_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xxxx1xxxxx","00010","00011","1111000");
constant CBS_S2_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxx0xxxxx","00010","00101","0001111");
constant CBS_S3_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx1","00011","00100","1110001");
constant CBS_S3_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx0","00011","00101","1100011");
constant CBS_S4_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx01xxxxxx","00100","00001","0111000");
constant CBS_S4_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx10xxxxxx","00100","00101","1000111");
constant CBS_S4_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!xx01xxxxxx,xx10xxxxxx","00100","00100","1111100");
constant CBS_S5_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx111","00101","00110","1100010");
constant CBS_S5_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx000","00101","00000","1100111");
constant CBS_S5_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx111,xxxxxxx000","00101","00101","0000000");
constant CBS_S6_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"xxxxxxx110","00110","00000","1010101");
constant CBS_S6_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx010","00110","00101","0101010");
constant CBS_S6_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx110,xxxxxxx010","00110","00110","1101111");
constant CBS_S7_S8 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","00111","01000","1011110");
constant CBS_S8_S9 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","01000","01001","1011111");
constant CBS_S9_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","01001","00010","1011100");
-- use an unused state to disable this TR
constant CBS_0_unused : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","11111","00000","1010101");
-- use a used state but set the IPG to "0000" to disable this TR
constant CBS_2_unused_noinput : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"","00001","00000","1010110");
-- use an unused state to disable this TR but set the IPG to "1111"
constant CBS_2_unused_nostate : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","11110","00000","1010111");
-- important: the LSBs of this vector are assiciated with the low-input TRs
constant ConfigBitStream : std_logic_vector(ConfigLength-1 downto 0) :=
-- Width = 0
CBS_S7_S8 &
CBS_S8_S9 &
CBS_0_unused &
-- Width = 1
CBS_S3_S4 &
CBS_S3_S5 &
-- Width = 2
CBS_S2_S3 &
CBS_S4_S1 &
CBS_S4_S5 &
CBS_S9_S2 &
CBS_2_unused_noinput &
CBS_2_unused_nostate &
-- Width = 3
CBS_S2_S5 &
CBS_S5_S6 &
CBS_S5_S0 &
CBS_S5_S5 &
CBS_S6_S5 &
CBS_S6_S6 &
-- Width = 4
CBS_S0_S1 &
CBS_S0_S2 &
CBS_S0_S3 &
CBS_S0_S0 &
CBS_S1_S6 &
CBS_S1_S7 &
CBS_S1_S1 &
CBS_S4_S4 &
CBS_S6_S0;
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n_i : std_logic;
signal Clk_i : std_logic;
signal Input_i : std_logic_vector(InputWidth-1 downto 0);
signal Output_o : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
signal ScanEnable_i : std_logic;
signal ScanClk_i : std_logic;
signal ScanDataIn_i : std_logic;
signal ScanDataOut_o : std_logic;
procedure CheckTRFSM (
constant Input : in std_logic_vector(InputWidth-1 downto 0);
constant Output : in std_logic_vector(OutputWidth-1 downto 0);
signal Input_i : out std_logic_vector(InputWidth-1 downto 0);
signal Output_o : in std_logic_vector(OutputWidth-1 downto 0)
) is
variable l : line;
begin
Input_i <= Input;
write(l,string'("Input = "));
write(l,Input);
wait for CheckOutputDelay;
write(l,string'(" => Output = "));
write(l,Output_o);
if Output_o = Output then
write(l,string'(" OK "));
else
write(l,string'(" ERROR: should be "));
write(l,Output);
end if;
writeline(std.textio.output,l);
wait for SetupNextInputDelay;
end CheckTRFSM;
procedure ClkCycle (
signal Clk_i : out std_logic
) is
begin
Clk_i <= '1';
wait for CfgClkHalfPeriode;
Clk_i <= '0';
wait for CfgClkHalfPeriode;
end ClkCycle;
begin -- behavior
TRFSM_1: TRFSM
generic map (
InputWidth => InputWidth,
OutputWidth => OutputWidth,
StateWidth => StateWidth,
UseResetRow => UseResetRow,
NumRows0 => NumRows0,
NumRows1 => NumRows1,
NumRows2 => NumRows2,
NumRows3 => NumRows3,
NumRows4 => NumRows4,
NumRows5 => NumRows5,
NumRows6 => NumRows6,
NumRows7 => NumRows7,
NumRows8 => NumRows8,
NumRows9 => NumRows9)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_i,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_i,
ScanClk_i => ScanClk_i,
ScanDataIn_i => ScanDataIn_i,
ScanDataOut_o => ScanDataOut_o);
Check: process
begin -- process Check
-- set all inputs
Clk_i <= '0';
Input_i <= (others => '0');
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
ScanEnable_i <= '0';
ScanClk_i <= '0';
ScanDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
-- assert false report "ConfigBitStream = " & Vector2String(ConfigBitStream) severity note;
CfgMode_i <= '1';
CfgShift_i <= '1';
wait for CfgClkHalfPeriode; -- strange, ModelSim needs this :-(
for i in 0 to ConfigLength-1 loop
CfgDataIn_i <= ConfigBitStream(i);
wait for 1 ns; -- strange, ModelSim needs this :-(
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CfgClk_i <= '0';
wait for CfgClkHalfPeriode;
end loop; -- i
CfgMode_i <= '0';
CfgShift_i <= '0';
wait for 1 ns; -- strange, ModelSim needs this :-(
assert false report "### Configuration done" severity note;
-- 127129ns
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- State 0, test all transitions
CheckTRFSM("1010000000","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010111111","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010110011","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010010101","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010101010","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1111000000","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111001100","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111101010","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111010111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("0000000000","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000111111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000101010","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000010101","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000110111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("1110000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("1110111011","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0010000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0101000000","1111111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 0 again
CheckTRFSM("1010110111","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("1100110111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100111111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100000000","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011111111","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011010101","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("1111110111","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0000000000","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0010010101","0111110",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1100011001","1111111",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
CheckTRFSM("0000000010","0101010",Input_i,Output_o); -- to S5
CheckTRFSM("0000000111","1101111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1111111010","0101010",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0000000111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("0000100000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("0001110000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("1111011111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("0001110011","1111000",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("0000000001","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("1010101011","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("0000000000","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0101010100","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0011100111","1110001",Input_i,Output_o); -- to S4
ClkCycle(Clk_i);
-- State 4
CheckTRFSM("0001000000","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("1101111111","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("0010000000","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1110111111","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1111111111","1111100",Input_i,Output_o); -- stay
CheckTRFSM("1100111111","1111100",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1010101010","1000111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1111111111","1100010",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("0000011010","0110011",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("1111111110","1100011",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0010011111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("0101010000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1010011010","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
ClkCycle(Clk_i);
-- State 7
CheckTRFSM("0000000000","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1111111111","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1010101010","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0101010101","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1100110011","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0011001100","1011110",Input_i,Output_o); -- to S8
ClkCycle(Clk_i);
-- State 8
CheckTRFSM("0000000000","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1111111111","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1010101010","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0101010101","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1100110011","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0011001100","1011111",Input_i,Output_o); -- to S9
ClkCycle(Clk_i);
-- State 9
CheckTRFSM("0000000000","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1010101010","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0101010101","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1100110011","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0011001100","1011100",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process Check;
end behavior;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7410/chll/out/adt7410-wrapreconfmodule-vhdl2008.vhd | 1 | 8808 | -- Automatically generated: write_netlist -wraprm_vhdl2008 -vhdl -module adt7410-wrapreconfmodule-vhdl2008.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADT7410 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
WaitCounterPreset_i : in std_logic_vector(15 downto 0)
);
attribute intersynth_port : string;
attribute intersynth_conntype : string;
attribute intersynth_param : string;
attribute intersynth_port of Reset_n_i : signal is "Reset_n_i";
attribute intersynth_port of Clk_i : signal is "Clk_i";
attribute intersynth_port of Enable_i : signal is "ReconfModuleIn_s";
attribute intersynth_conntype of Enable_i : signal is "Bit";
attribute intersynth_port of CpuIntr_o : signal is "ReconfModuleIRQs_s";
attribute intersynth_conntype of CpuIntr_o : signal is "Bit";
attribute intersynth_port of I2C_ReceiveSend_n_o : signal is "I2C_ReceiveSend_n";
attribute intersynth_conntype of I2C_ReceiveSend_n_o : signal is "Bit";
attribute intersynth_port of I2C_ReadCount_o : signal is "I2C_ReadCount";
attribute intersynth_conntype of I2C_ReadCount_o : signal is "Byte";
attribute intersynth_port of I2C_StartProcess_o : signal is "I2C_StartProcess";
attribute intersynth_conntype of I2C_StartProcess_o : signal is "Bit";
attribute intersynth_port of I2C_Busy_i : signal is "I2C_Busy";
attribute intersynth_conntype of I2C_Busy_i : signal is "Bit";
attribute intersynth_port of I2C_FIFOReadNext_o : signal is "I2C_FIFOReadNext";
attribute intersynth_conntype of I2C_FIFOReadNext_o : signal is "Bit";
attribute intersynth_port of I2C_FIFOWrite_o : signal is "I2C_FIFOWrite";
attribute intersynth_conntype of I2C_FIFOWrite_o : signal is "Bit";
attribute intersynth_port of I2C_Data_o : signal is "I2C_DataIn";
attribute intersynth_conntype of I2C_Data_o : signal is "Byte";
attribute intersynth_port of I2C_Data_i : signal is "I2C_DataOut";
attribute intersynth_conntype of I2C_Data_i : signal is "Byte";
attribute intersynth_port of I2C_Error_i : signal is "I2C_Error";
attribute intersynth_conntype of I2C_Error_i : signal is "Bit";
attribute intersynth_param of PeriodCounterPreset_i : signal is "PeriodCounterPreset_i";
attribute intersynth_conntype of PeriodCounterPreset_i : signal is "Word";
attribute intersynth_param of SensorValue_o : signal is "SensorValue_o";
attribute intersynth_conntype of SensorValue_o : signal is "Word";
attribute intersynth_param of Threshold_i : signal is "Threshold_i";
attribute intersynth_conntype of Threshold_i : signal is "Word";
attribute intersynth_param of WaitCounterPreset_i : signal is "WaitCounterPreset_i";
attribute intersynth_conntype of WaitCounterPreset_i : signal is "Word";
end ADT7410;
architecture WrapReconfModule of ADT7410 is
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
signal ReconfModuleIn_s : std_logic_vector(7 downto 0);
signal ReconfModuleIRQs_s : std_logic_vector(4 downto 0);
signal I2C_ReadCount_s : std_logic_vector(3 downto 0);
signal AdcDoConvert_s : std_logic;
signal CfgIntfDOut_s : std_logic_vector(15 downto 0);
signal I2C_Divider800_s : std_logic_vector(15 downto 0);
signal I2C_ErrAckParam_s : std_logic;
signal I2C_F100_400_n_s : std_logic;
signal Outputs_s : std_logic_vector(7 downto 0);
signal ParamIntfDOut_s : std_logic_vector(15 downto 0);
signal ReconfModuleOut_s : std_logic_vector(7 downto 0);
signal SPI_CPHA_s : std_logic;
signal SPI_CPOL_s : std_logic;
signal SPI_DataIn_s : std_logic_vector(7 downto 0);
signal SPI_LSBFE_s : std_logic;
signal SPI_ReadNext_s : std_logic;
signal SPI_SPPR_SPR_s : std_logic_vector(7 downto 0);
signal SPI_Write_s : std_logic;
begin
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_ReadCount_o => I2C_ReadCount_s,
I2C_StartProcess_o => I2C_StartProcess_o,
I2C_Busy_i => I2C_Busy_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_DataIn_o => I2C_Data_o,
I2C_DataOut_i => I2C_Data_i,
I2C_Error_i => I2C_Error_i,
AdcConvComplete_i => '0',
AdcDoConvert_o => AdcDoConvert_s,
AdcValue_i => "0000000000",
CfgIntfDOut_o => CfgIntfDOut_s,
I2C_Divider800_o => I2C_Divider800_s,
I2C_ErrAckParam_o => I2C_ErrAckParam_s,
I2C_Errors_i => "00000000",
I2C_F100_400_n_o => I2C_F100_400_n_s,
I2C_FIFOEmpty_i => '0',
I2C_FIFOFull_i => '0',
Inputs_i => "00000000",
Outputs_o => Outputs_s,
ParamIntfDOut_o => ParamIntfDOut_s,
PerAddr_i => "00000000000000",
PerDIn_i => "0000000000000000",
PerEn_i => '0',
PerWr_i => "00",
ReconfModuleOut_o => ReconfModuleOut_s,
SPI_CPHA_o => SPI_CPHA_s,
SPI_CPOL_o => SPI_CPOL_s,
SPI_DataIn_o => SPI_DataIn_s,
SPI_DataOut_i => "00000000",
SPI_FIFOEmpty_i => '0',
SPI_FIFOFull_i => '0',
SPI_LSBFE_o => SPI_LSBFE_s,
SPI_ReadNext_o => SPI_ReadNext_s,
SPI_SPPR_SPR_o => SPI_SPPR_SPR_s,
SPI_Transmission_i => '0',
SPI_Write_o => SPI_Write_s
);
CpuIntr_o <= ReconfModuleIRQs_s(0);
I2C_ReadCount_o <= "0000" & I2C_ReadCount_s;
<< signal MyReconfigLogic_0.ParamIn_Word_0_s : std_logic_vector(15 downto 0) >> <= PeriodCounterPreset_i;
SensorValue_o <= << signal MyReconfigLogic_0.ParamOut_Word_0_s : std_logic_vector(15 downto 0) >>;
<< signal MyReconfigLogic_0.ParamIn_Word_1_s : std_logic_vector(15 downto 0) >> <= Threshold_i;
<< signal MyReconfigLogic_0.ParamIn_Word_2_s : std_logic_vector(15 downto 0) >> <= WaitCounterPreset_i;
<< signal MyReconfigLogic_0.ParamIn_Word_3_s : std_logic_vector(15 downto 0) >> <= "0000000000000000";
<< signal MyReconfigLogic_0.ParamIn_Word_4_s : std_logic_vector(15 downto 0) >> <= "0000000000000000";
<< signal MyReconfigLogic_0.I2C_Divider800_o : std_logic_vector(15 downto 0) >> <= "0000000001111100";
<< signal MyReconfigLogic_0.I2C_ErrAckParam_o : std_logic >> <= '0';
ReconfModuleIn_s <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & Enable_i;
end WrapReconfModule;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/units/i2c_master/vhdl/i2ccore-e.vhd | 1 | 2574 | --------------------------------------------------------------------------------
-- Company: vienna university of technology
-- Engineer: mario faschang
-- Create Date: 14:24:06 11/30/2009
-- Module Name: i2ccore - rtl
-- Project Name: i2c master controller
-- Description: * the core controller (which basically is a mealy-state-
-- machine) is able to communicate with 7-bit-i2c-slaves as a
-- single master on the i2c bus
-- * as long as DoTransfer_i is '1' the core-controller sends
-- bytes (from Data_i) to a slave on the bus or reads bytes
-- from the slave (to Data_o) depending on the value of
-- ReadWrite_n_i
-- * every transfer starts with an addressing-procedure and then
-- continues with reading or writing bytes. the slave's
-- address has to be available at data_i from the beginning
-- of the procedure till first rising edge of ByteReady_o
-- * the i2c-core does not read SCL-Line so clock-
-- synchronization, arbitration, multi-master and clock-
-- stretching is not supported.
-- * if the data at SDA does not match the i2c-core's SDA_o,
-- communication will stop and BusErr_o will be set to '1'
-- till DoTransfer_i is '0' again.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i2ccore is
Generic ( DividerWidth_g : integer range 4 to 32);
Port ( Reset_i : in STD_LOGIC;
Clk_i : in STD_LOGIC;
Data_i : in STD_LOGIC_VECTOR (7 downto 0);
Data_o : out STD_LOGIC_VECTOR (7 downto 0);
DoTransfer_i : in STD_LOGIC;
ReadWrite_n_i : in STD_LOGIC;
AckTx_i : in STD_LOGIC;
AckRx_o : out STD_LOGIC;
AckValid_o : out STD_LOGIC;
Busy_o : out STD_LOGIC;
ByteReady_o : out STD_LOGIC;
BusErr_o : out STD_LOGIC;
SDA_o : out STD_LOGIC;
SDA_i : in STD_LOGIC;
SCL_o : out STD_LOGIC;
F100_400_n_i : in STD_LOGIC;
Divider800_i : in std_logic_vector(DividerWidth_g-1 downto 0));
end i2ccore;
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/celllib/trfsm/vhdl/InputPatternGate-rtl-a.vhd | 2 | 535 |
architecture rtl of InputPatternGate is
signal CfgValue : std_logic_vector(2**InputWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => 2**InputWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
Match_o <= Enable_i and CfgValue(conv_integer(Input_i));
end rtl; -- of InputPatternGate
| gpl-2.0 |
hansiglaser/chll | examples/wsn-soc/apps/adt7310p32s32/tb/wrapreconfmodule-c.vhd | 9 | 998 | ------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of ADT7310_tb is
for behavior
for DUT : ADT7310
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
| gpl-2.0 |
dtysky/Led_Array | VHDL_TEST/IMG3.vhd | 1 | 6147 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG3.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY IMG3 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END IMG3;
ARCHITECTURE SYN OF img3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/IMG3.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 40,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/IMG3.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "40"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/IMG3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 |
freecores/lzrw1-compressor-core | hw/testbench/LZRWcompressorTb.vhd | 1 | 6816 | --/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/9/16 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* This is a file based testbench for the LZRW1 compressor core. It reads data
--* binary from a configured file, and feeds it int the core. The compressed data
--* is stored in a second file for verifycation. (Use the two java programs
--* provided with this project to create and verify test vectors)
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use std.textio.all;
-------------------------------------------------------------------------------
entity LZRWcompressor_tb is
end LZRWcompressor_tb;
-------------------------------------------------------------------------------
architecture tb of LZRWcompressor_tb is
component LZRWcompressor
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DataInxDI : in std_logic_vector(7 downto 0);
StrobexSI : in std_logic;
FlushBufxSI : in std_logic;
BusyxSO : out std_logic;
DonexSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal DInxDI : std_logic_vector(7 downto 0) := (others => '0');
signal StrobexSI : std_logic := '0';
signal FlushBufxSI : std_logic := '0';
signal BusyxSO : std_logic;
signal DonexSO : std_logic;
signal BufOutxDO : std_logic_vector(7 downto 0);
signal OutputValidxSO : std_logic;
signal RdStrobexSI : std_logic := '0';
signal LengthxDO : integer range 0 to 1024;
-- clock
signal Clk : std_logic := '1';
signal TbDone : std_logic := '0';
-- configuration
constant DATA_IN_FILE_NAME : string := "../../test files/TVect1.bin"; -- file with stimuli which will be compressed (relative to XST directroy)
constant DATA_OUT_FILE_NAME : string := "../../test files/TVect1.cmp"; -- filename for compressed data
constant PERIOD : time := 20 ns;
type binFileType is file of character;
begin -- tb
-- component instantiation
DUT : LZRWcompressor
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
DataInxDI => DInxDI,
StrobexSI => StrobexSI,
FlushBufxSI => FlushBufxSI,
BusyxSO => BusyxSO,
DonexSO => DonexSO,
BufOutxDO => BufOutxDO,
OutputValidxSO => OutputValidxSO,
RdStrobexSI => RdStrobexSI,
LengthxDO => LengthxDO
);
-- clock generation
Clk <= not Clk after (PERIOD / 2);
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
file srcFile : binFileType is in DATA_IN_FILE_NAME; -- uncompressed data input in file
variable srcChar : character;
variable l : line;
begin
wait for PERIOD;
wait until Clk'event and Clk = '1';
RstxRI <= '0';
while not endfile(srcFile) loop
read(srcFile, srcChar);
-- write(l, "found char ");
-- write(l, character'image(srcChar));
-- write(l, " ");
-- write(l, character'pos(srcChar));
-- writeline(OUTPUT, l);
wait until Clk'event and Clk = '1';
if BusyxSO = '0' then
DInxDI <= std_logic_vector(to_unsigned(character'pos(srcChar), 8));
StrobexSI <= '1';
end if;
wait until Clk'event and Clk = '1';
StrobexSI <= '0';
DInxDI <= "--------";
end loop;
StrobexSI <= '0';
for i in 0 to 10 loop
wait until Clk'event and Clk = '1';
end loop;
--wait until Clk'event and Clk = '1';
FlushBufxSI <= '1';
wait until Clk'event and Clk = '1';
FlushBufxSI <= '0';
file_close(srcFile);
for i in 0 to 10 loop
wait until Clk'event and Clk = '1';
end loop;
TbDone <= '1';
wait;
end process WaveGen_Proc;
-- process to receive compressed data from the core and store it in a file
pickupPrcs : process
file destFile : binFileType is out DATA_OUT_FILE_NAME; -- receives compressed data
variable destChar : character;
variable l : line;
begin
while true loop
wait until Clk'event and Clk = '1';
if LengthxDO > 0 then
RdStrobexSI <= '1';
else
RdStrobexSI <= '0';
end if;
if OutputValidxSO = '1' then
-- wait until Clk'event and Clk = '1';
destChar := character'val(to_integer(unsigned(BufOutxDO)));
write(destFile, destChar);
end if;
end loop;
file_close(destFile);
wait;
end process;
end tb;
-------------------------------------------------------------------------------
configuration LZRWcompressor_tb_tb_cfg of LZRWcompressor_tb is
for tb
end for;
end LZRWcompressor_tb_tb_cfg;
-------------------------------------------------------------------------------
| gpl-2.0 |
spiersad/ECGR4146-FIFO | FIFO_TB.vhd | 1 | 1826 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity FIFO_TB is
end FIFO_TB;
architecture behavior of FIFO_TB is
constant N: integer := 8;
constant M: integer := 64;
constant clk_period : time := 1 ns;
component FIFO
port(CLK, PUSH, POP, INIT: in std_logic;
DIN: in std_logic_vector(M-1 downto 0);
DOUT: out std_logic_vector(M-1 downto 0);
FULL, EMPTY, NOPUSH, NOPOP: out std_logic);
end component;
signal CLK, PUSH, POP, INIT: std_logic := '0';
signal DIN: std_logic_vector(M-1 downto 0) := std_logic_vector(to_unsigned(5, M));
signal DOUT: std_logic_vector(M-1 downto 0);
signal FULL, EMPTY, NOPUSH, NOPOP: std_logic;
begin
uut: FIFO port map(CLK => CLK, PUSH => PUSH, POP => POP,
INIT => INIT, DIN => DIN, DOUT => DOUT,
FULL => FULL, EMPTY => EMPTY,
NOPUSH => NOPUSH, NOPOP => NOPOP);
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
init <= '1';
wait for 1 ns;
init <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(5, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(30, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(255, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
pop <= '1';
wait for 1 ns;
pop <= '0';
wait for 1 ns;
pop <= '1';
wait for 1 ns;
pop <= '0';
wait;
end process;
end behavior; | gpl-2.0 |
jslhs/hackrf | firmware/cpld/sgpio_if/top.vhd | 12 | 5535 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/divider_r2.vhd | 1 | 9498 | ------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_SIGNED.ALL;
------------------------------------------------------------------------------
entity divider is
generic (
tag_width : integer := 6
);
port (
clk : IN std_logic;
Resetb : IN std_logic;
PhyReg_DivRsData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit
PhyReg_DivRtData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit --
Iss_RobTag : IN std_logic_vector( 4 downto 0); -- from divider issue queue unit
Iss_Div : IN std_logic; -- from issue unit
-------------------------------- Logic for the pics ( added by Atif) --------------------------------
Div_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Div_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionDiv : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Div_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 ) ;
Div_Done : out std_logic ;
Div_RobTag : OUT std_logic_vector(4 downto 0);
Div_Rddata : OUT std_logic_vector(31 downto 0);
Div_ExeRdy : OUT std_logic -- divider is read for division ==> drives "div_exec_ready" in the TOP
);
end divider;
architecture behv of divider is
component divider_core is
Port ( Dividend : in std_logic_vector (31 downto 0 );
Divisor : in std_logic_vector ( 31 downto 0);
Rem_n_Quo : out std_logic_vector ( 31 downto 0)
);
end component divider_core;
-- component divider_core is
-- port ( DATA_A : in std_logic_vector (31 downto 0 );
-- DATA_B : in std_logic_vector (31 downto 0);
-- DIV_OUT : out std_logic_vector ( 31 downto 0)
-- );
-- end component divider_core;
subtype tag_type is std_logic_vector(4 downto 0);
type tag is array (0 to 5) of tag_type; -- changed from (0 to 4)
-- tag_valid: 0 through 5 for the 6 pipeline registers forming a 6-clock long combinational division
-- note: Since 1 clock is lost in holding the incoming operands in a register before starting the division
-- we can only take 6 clocks (including a clock long combinational logic upstream of the CDB mux)
signal tag_valid,rdwrite : std_logic_vector(5 downto 0); -- changed from (4 downto 0)
signal tag_div : tag;
subtype PhyAddr_Type is std_logic_vector(5 downto 0);
type PhyAddr is array (0 to 5) of PhyAddr_Type;
signal RdPhyAddr : PhyAddr;
-- signal div_rem_quo : std_logic_vector(31 downto 0);
-- signal result : std_logic_vector(31 downto 0);
signal divisor, dividend: std_logic_vector(31 downto 0);
signal rfd : std_logic; -- rfd = ready for division
signal BufferDepth :std_logic_vector ( 4 downto 0 ) ; -- for the instruction coming from the division issue queue
signal Buffer0Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer1Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer2Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer3Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer4Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer5Depth :std_logic_vector ( 4 downto 0 ) ;
begin
div : divider_core
port map (
Dividend => dividend,
Divisor => divisor,
Rem_n_Quo => Div_Rddata
);
-- port map (
-- DATA_A => divisor,
-- DATA_B => dividend,
-- DIV_OUT => result
-- );
Div_ExeRdy <= rfd;
-- Div_Rddata <= div_rem_quo;
-- translate_off
Div_instruction <= Iss_instructionDiv ;
-- translate_on
Div_Done <= tag_valid(5) ; -- previously 3? -- are you doing only 0 to 3? -- let us do 0 to 5 as our diagrams show 0 to 5
Div_RobTag <= tag_div(5);
Div_RdPhyAddr <= RdPhyAddr(5);
Div_RdWrite <= rdwrite(5);
BufferDepth <= unsigned(Iss_RobTag) - unsigned(Rob_TopPtr) ;
Buffer0Depth <= unsigned(tag_div(0)) - unsigned(Rob_TopPtr) ;
Buffer1Depth <= unsigned(tag_div(1)) - unsigned(Rob_TopPtr) ;
Buffer2Depth <= unsigned(tag_div(2)) - unsigned(Rob_TopPtr) ;
Buffer3Depth <= unsigned(tag_div(3)) - unsigned(Rob_TopPtr) ;
Buffer4Depth <= unsigned(tag_div(4)) - unsigned(Rob_TopPtr) ;
-- Note: On the tick of the clock, the six pipeline registers (0 to 5) will move one step down.
-- The top-most register 0 will receive a tag from divider issue unit.
-- When Cdb_Flush is activated, we are responsible to invalidate appropriate Flip-Flops
-- by the end of the clock. So we take care of the six valid-bit FFs, tag_valid(0 to 5) by looking at the 5 depths.
-- The CDB shall take care of invalidiating the outgoing div instruction
-- (going out of multiplier and entering the CDB register). So CDB will worry about Buf5Depth!
-- Hence the following line is not needed here
-- Buffer5Depth <= unsigned(tag_div(5)) - unsigned(Rob_TopPtr) ;
tag_carry : process (clk, Resetb)
begin
if (Resetb = '0') then
for i in 0 to 5 loop -- 0 to 5
tag_div(i) <= (others => '0'); -- Though we could have these as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others=>'0');
end loop;
tag_valid <= (others => '0');
rdwrite <= (others => '0');
rfd <= '1';
divisor <= (others => '-');
dividend <= (others => '-');
elsif(clk'event and clk = '1') then
-- if an instruction is coming in from divide issue queue
if(Iss_Div = '1' and rfd = '1' and ( (Cdb_Flush = '0') or ( Cdb_Flush = '1' and BufferDepth < Cdb_RobDepth ) ) ) then
-- (Iss_Div = '1' and rfd = '1' ) ? it is enough to say (Iss_Div = '1') as Iss_Div can not be made '1' by the issue unit unless rfd was '1'
divisor <= PhyReg_DivRtData;
dividend <= PhyReg_DivRsData;
tag_div(0) <= Iss_RobTag;
RdPhyAddr(0)<= Iss_RdPhyAddr;
rdwrite(0) <= Iss_RdWrite;
tag_valid(0)<= '1';
rfd <= '0';
else
tag_div(0) <= (others => '0'); -- though it is not necessary, we wish to clear to make debugging easy
RdPhyAddr(0) <= (others => '0');
tag_valid(0)<= '0';
rdwrite(0)<='0';
end if;
if ( Cdb_Flush = '1' and
( -- if there is an ongoing div operation which does not leave the divisor by the end of the clock
( Buffer0Depth > Cdb_RobDepth and tag_valid(0) = '1' ) or
( Buffer1Depth > Cdb_RobDepth and tag_valid(1) = '1' ) or
( Buffer2Depth > Cdb_RobDepth and tag_valid(2) = '1' ) or
( Buffer3Depth > Cdb_RobDepth and tag_valid(3) = '1' ) or
( Buffer4Depth > Cdb_RobDepth and tag_valid(4) = '1' )
-- ( Buffer5Depth > Cdb_RobDepth and tag_valid(5) = '1' ) -- see the above note regarding Buffer5Depth
) ) then
rfd <= '1' ;
for i in 1 to 5 loop -- note: it's 1 to 5, not 0 to 4 as these items are on move!
tag_valid(i) <= '0' ;
rdwrite(i)<='0';
tag_div(i) <= (others => '0'); -- Though we could have these tags as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others => '0');
end loop;
else
for i in 1 to 5 loop
tag_valid(i) <= tag_valid(i-1); -- tag_valid(0) receives a 1 or 0 depending on whether a new div instruction is issued or not.
tag_div(i) <= tag_div(i-1);
rdwrite(i) <= rdwrite(i-1);
RdPhyAddr(i) <= RdPhyAddr(i-1) ;
end loop;
if (rfd = '0' and
( (tag_valid(5) = '1') or -- it is unnecessary to qaulify with (rfd = '0' ) as (tag_valid(5) = '1') is enough for this part of the clause
( (tag_valid(0) = '0') and (tag_valid(1) = '0') and (tag_valid(2) = '0') and (tag_valid(3) = '0') and (tag_valid(4) = '0') ) ) )
-- if all the upper 5 tag valid bits (bits 0 to 4) are zeros -- this is perhaps redundant
-- However, if you do keep this piece of the clause, you do need the(rfd = '0' ) as a qualifier.
-- This is not apparent at first sight. This is an artifact of HDL coding!
-- Notice that, if we are initiating a division, we are assigning a '0' to the rfd signal (with delta-T delay) on line 125 above.
-- Then we come down here and override that assignment with '1' in line 162, resulting rfd continuing to be 1 for 1 extra clock.
-- To avoid this problem, you need to have (rfd = '0' ) as a qualifier for this part of the clause.
-- In fact, if the tag_valid[0:4] = 00000 and (rfd = '0' ) , then (tag_valid(5) = '1') is true and hence this clause is redundant as stated before.
then
rfd <= '1';
end if;
-- if (rfd = '1')then
-- div_rem_quo <= result; -- another clock? Result shall go directly to the CDB mux
-- end if;
-- Div_RobTag <= tag_div(4);
end if;
end if ;
end process tag_carry;
end architecture behv; | gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/simulation/fg_tb_dverif.vhd | 8 | 6078 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0');
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_d_sel_d1 <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN
rd_d_sel_d1 <= rd_d_sel_d1+"1";
END IF;
END IF;
END PROCESS;
pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY;
expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTH*conv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH*(conv_integer(rd_d_sel_d1)+1));
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/example_design/RD_DATA_FIFO_top_wrapper.vhd | 1 | 19269 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RD_DATA_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RD_DATA_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(256-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(256-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RD_DATA_FIFO_top_wrapper;
architecture xilinx of RD_DATA_FIFO_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component RD_DATA_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : RD_DATA_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Move_FIFO_4KB/simulation/fg_tb_dgen.vhd | 36 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_add.vhd | 3 | 7087 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are add $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421020_00421020_00421020_00421020", -- Loc 0C, 08, 04, 00
X"00421020_00421020_00421020_00421020", -- Loc 1C, 18, 14, 10
X"00421020_00421020_00421020_00421020", -- Loc 2C, 28, 24, 20
X"00421020_00421020_00421020_00421020", -- Loc 3C, 38, 34, 30
X"00421020_00421020_00421020_00421020", -- Loc 4C, 48, 44, 40
X"00421020_00421020_00421020_00421020", -- Loc 5C, 58, 54, 50
X"00421020_00421020_00421020_00421020", -- Loc 6C, 68, 64, 60
X"00421020_00421020_00421020_00421020", -- Loc 7C, 78, 74, 70
X"00421020_00421020_00421020_00421020", -- Loc 8C, 88, 84, 80
X"00421020_00421020_00421020_00421020", -- Loc 9C, 98, 94, 90
X"00421020_00421020_00421020_00421020", -- Loc AC, A8, A4, A0
X"00421020_00421020_00421020_00421020", -- Loc BC, B8, B4, B0
X"00421020_00421020_00421020_00421020", -- Loc CC, C8, C4, C0
X"00421020_00421020_00421020_00421020", -- Loc DC, D8, D4, D0
X"00421020_00421020_00421020_00421020", -- Loc EC, E8, E4, E0
X"00421020_00421020_00421020_00421020", -- Loc FC, F8, F4, F0
X"00421020_00421020_00421020_00421020", -- Loc 10C, 108, 104, 100
X"00421020_00421020_00421020_00421020", -- Loc 11C, 118, 114, 110
X"00421020_00421020_00421020_00421020", -- Loc 12C, 128, 124, 120
X"00421020_00421020_00421020_00421020", -- Loc 13C, 138, 134, 130
X"00421020_00421020_00421020_00421020", -- Loc 14C, 148, 144, 140
X"00421020_00421020_00421020_00421020", -- Loc 15C, 158, 154, 150
X"00421020_00421020_00421020_00421020", -- Loc 16C, 168, 164, 160
X"00421020_00421020_00421020_00421020", -- Loc 17C, 178, 174, 170
X"00421020_00421020_00421020_00421020", -- Loc 18C, 188, 184, 180
X"00421020_00421020_00421020_00421020", -- Loc 19C, 198, 194, 190
X"00421020_00421020_00421020_00421020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421020_00421020_00421020_00421020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421020_00421020_00421020_00421020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421020_00421020_00421020_00421020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421020_00421020_00421020_00421020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421020_00421020_00421020_00421020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421020_00421020_00421020_00421020", -- Loc 20C, 208, 204, 200
X"00421020_00421020_00421020_00421020", -- Loc 21C, 218, 214, 221
X"00421020_00421020_00421020_00421020", -- Loc 22C, 228, 224, 220
X"00421020_00421020_00421020_00421020", -- Loc 23C, 238, 234, 230
X"00421020_00421020_00421020_00421020", -- Loc 24C, 248, 244, 240
X"00421020_00421020_00421020_00421020", -- Loc 25C, 258, 254, 250
X"00421020_00421020_00421020_00421020", -- Loc 26C, 268, 264, 260
X"00421020_00421020_00421020_00421020", -- Loc 27C, 278, 274, 270
X"00421020_00421020_00421020_00421020", -- Loc 28C, 288, 284, 280
X"00421020_00421020_00421020_00421020", -- Loc 29C, 298, 294, 290
X"00421020_00421020_00421020_00421020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421020_00421020_00421020_00421020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421020_00421020_00421020_00421020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421020_00421020_00421020_00421020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421020_00421020_00421020_00421020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421020_00421020_00421020_00421020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421020_00421020_00421020_00421020", -- Loc 30C, 308, 304, 300
X"00421020_00421020_00421020_00421020", -- Loc 31C, 318, 314, 331
X"00421020_00421020_00421020_00421020", -- Loc 32C, 328, 324, 320
X"00421020_00421020_00421020_00421020", -- Loc 33C, 338, 334, 330
X"00421020_00421020_00421020_00421020", -- Loc 34C, 348, 344, 340
X"00421020_00421020_00421020_00421020", -- Loc 35C, 358, 354, 350
X"00421020_00421020_00421020_00421020", -- Loc 36C, 368, 364, 360
X"00421020_00421020_00421020_00421020", -- Loc 37C, 378, 374, 370
X"00421020_00421020_00421020_00421020", -- Loc 38C, 388, 384, 380
X"00421020_00421020_00421020_00421020", -- Loc 39C, 398, 394, 390
X"00421020_00421020_00421020_00421020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421020_00421020_00421020_00421020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/issueque.vhd | 1 | 52726 | -------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= OutSelecttemp(0) or OutSelecttemp(1) or OutSelecttemp (2) or OutSelecttemp(3) or
OutSelecttemp(4) or OutSelecttemp(5) or OutSelecttemp (6) or OutSelecttemp(7);
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= '0' ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower; --Complete the right hand side of the expression
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or
(not (IssuequefullTemp_Upper) and not (IssuequefullTemp_Lower)) ;
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag(0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag(1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag(2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag(3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag(4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag(5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag(6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag(7)) - unsigned(Rob_TopPtr);
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= IssuequeInstrValReg(1); --Hint: Take into account the shift mechanism so is it i or i+1 or i - 1?
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= IssuequeInstrValReg(2);
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= IssuequeInstrValReg(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= IssuequeInstrValReg(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= IssuequeInstrValReg(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= IssuequeInstrValReg(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= IssuequeInstrValReg(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_send_fifo/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/bpb_NEW.vhd | 2 | 7498 | ------------------------------------------------------------------------------
--
-- Design : Branch Predicton Buffer
-- Project : Tomasulo Processor
-- Entity : bpb
-- Author : kapil
-- Company : University of Southern California
-- Last Updated : June 24, 2010
-- Last Updated by : Waleed Dweik
-- Modification : 1. Modify the branch prediction to use the most well-known state machine of the 2-bit saturating counter
-- 2. Update old comments
-------------------------------------------------------------------------------
--
-- Description : 2 - bit wide / 8 deep
-- each 2 bit locn is a state machine
-- 2 bit saturating counter
-- 00 strongly nottaken
-- 01 mildly nottaken
-- 10 mildly taken
-- 11 strongly taken
--
-------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------------------------------------
entity bpb is
port (
Clk : in std_logic;
Resetb : in std_logic;
---- Interaction with Cdb -------------------
Dis_CdbUpdBranch : in std_logic; -- indicates that a branch appears on Cdb(wen to bpb)
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch on the Cdb
Dis_CdbBranchOutcome : in std_logic; -- indiacates the outocome of the branch to the bpb: 0 means nottaken and 1 means taken
---- Interaction with dispatch --------------
Bpb_BranchPrediction : out std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;--indiaces the 3 least sig bits of the current instr being dispatched
Dis_BpbBranch : in std_logic -- indiactes that there is a branch instr in the dispatch (ren to the bpb)
);
end bpb;
architecture behv of bpb is
subtype sat_counters is std_logic_vector(1 downto 0);
type bpb_array is array (0 to 7) of sat_counters ;
signal bpb_array_r: bpb_array ; -- An array of 8 2-bit saturating counters represents 8 location bpb.
signal Bpb_read_status,Bpb_write_status : std_logic_vector(1 downto 0);
begin
---------------------------------------------------------------------------
-- Task1: Complete the following 2 concurrent statements for Bpb read and write status:
-- Hint: You may want to use CONV_INTEGER function to convert from std_logic_vector to an integer
-- Bpb_read_status represets the 2-bit counter value in the Bpb entry addressed by the branch instruction in dispatch.
-- Bpb_read_status tells whether branch should predicted Taken (11,10) or not Taken (00,01)
Bpb_read_status <= bpb_array_r(0) when Dis_BpbBranchPCBits = "000" else
bpb_array_r(1) when Dis_BpbBranchPCBits = "001" else
bpb_array_r(2) when Dis_BpbBranchPCBits = "010" else
bpb_array_r(3) when Dis_BpbBranchPCBits = "011" else
bpb_array_r(4) when Dis_BpbBranchPCBits = "100" else
bpb_array_r(5) when Dis_BpbBranchPCBits = "101" else
bpb_array_r(6) when Dis_BpbBranchPCBits = "110" else
bpb_array_r(7) when Dis_BpbBranchPCBits = "111";
-- Bpb_write_status represents the 2-bit counter value in the Bpb entry addressed by the branch instruction on the Cdb.
-- Bpb_write_status is used along with the actual outcome of the branch on Cdb to update the corresponding Bpb entry.
--Bpb_write_status <= --
---------------------------------------------------------------------------
-- Update Process
-- This prcoess is used to update the Bpb entry indexed by the PC[4:2] of the branch instruction which appears on Cdb.
-- The update process is based on the State machine for a 2-bit saturating counter which is given in the slide set.
bpb_write: process (Clk,Resetb)
variable write_data_bpb: std_logic_vector(1 downto 0);
variable bpb_waddr_mask ,bpb_index_addr,raw_bpb_addr: std_logic_vector(7 downto 0);
begin
if (Resetb = '0') then
-------------------------------Initialize register file contents(!! weakly taken, weakly not taken alternatvely!!) here----------------------------------
bpb_array_r <= (
"01", -- $0
"10", -- $1
"01", -- $2
"10", -- $3
"01", -- $4
"10", -- $5
"01", -- $6
"10" -- $7
);
elsif(Clk'event and Clk='1') then
if (Dis_CdbUpdBranch = '1')then
bpb_waddr_mask := X"FF";
else
bpb_waddr_mask := X"00";
end if ;
case Dis_CdbUpdBranchAddr is
when "000" => raw_bpb_addr := ("00000001");
when "001" => raw_bpb_addr := ("00000010");
when "010" => raw_bpb_addr := ("00000100");
when "011" => raw_bpb_addr := ("00001000");
when "100" => raw_bpb_addr := ("00010000");
when "101" => raw_bpb_addr := ("00100000");
when "110" => raw_bpb_addr := ("01000000");
when others => raw_bpb_addr := ("10000000");
end case ;
bpb_index_addr := raw_bpb_addr and bpb_waddr_mask ;
---------------------------------------------------------------------------
-- Task2: Add the Code inside the for loop to modify Bpb entries:
-- Hint: According to the current counter value of the corresponding entry and the actual outcome of the branch on Cdb you can
-- decide what is the new prediction value should be based on the state machine given in the slides.
---------------------------------------------------------------------------
for i in 0 to 7 loop
if (bpb_index_addr(i) = '1') then
case (bpb_array_r(i)) is
when "00" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "01";
end if;
when "01" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "10";
else
bpb_array_r(i) <= "00";
end if;
when "10" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "11";
else
bpb_array_r(i) <= "01";
end if;
when others =>
if (Dis_CdbBranchOutcome = '0') then
bpb_array_r(i) <= "10";
end if;
end case;
end if;
end loop;
end if;
end process bpb_write;
-- Prediction Process
-- This prcoess generates Bpb_BranchPrediction signal which indicates the prediction for branch instruction
-- The signal is always set to '0' except when there is a branch instruction in dispatch and the prediction is either Strongly Taken or Taken.
bpb_predict : process(Bpb_read_status ,Dis_BpbBranch)
begin
Bpb_BranchPrediction<= '0';
if (Bpb_read_status(1) = '0' ) then
Bpb_BranchPrediction<= '0';
else
Bpb_BranchPrediction<= '1' and Dis_BpbBranch;
end if ;
end process;
end behv;
| gpl-2.0 |
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