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peteut/ghdl | libraries/synopsys/std_logic_misc.vhdl | 4 | 5966 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2068.vhd | 4 | 2534 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2068.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02068ent IS
END c07s02b04x00p01n02i02068ent;
ARCHITECTURE c07s02b04x00p01n02i02068arch OF c07s02b04x00p01n02i02068ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
POSV := POSV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02068 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02068arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd | 4 | 1964 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc934.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p04n01i00934pkg is
Type Weekdays is (Monday, Tuesday, Wednesday, Thursday, Friday);
end c10s04b00x00p04n01i00934pkg;
ENTITY c10s04b00x00p04n01i00934ent IS
END c10s04b00x00p04n01i00934ent;
use WORK.c10s04b00x00p04n01i00934pkg.all;
ARCHITECTURE c10s04b00x00p04n01i00934arch OF c10s04b00x00p04n01i00934ent IS
signal done : bit;
signal wkday :Weekdays; -- No_failure_here
BEGIN
TESTING : PROCESS
BEGIN
assert NOT(wkday = Monday)
report "***PASSED TEST: c10s04b00x00p04n01i00934"
severity NOTE;
assert (wkday = Monday)
report "***FAILED TEST: c10s04b00x00p04n01i00934 - Items declared via a use clause are visible in the declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p04n01i00934arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2024.vhd | 4 | 1815 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2024.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02024ent IS
END c07s02b04x00p01n01i02024ent;
ARCHITECTURE c07s02b04x00p01n01i02024arch OF c07s02b04x00p01n01i02024ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02024 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02024arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2793.vhd | 4 | 1854 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2793.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ELSE is
end ELSE;
ENTITY c13s09b00x00p99n01i02793ent IS
END c13s09b00x00p99n01i02793ent;
ARCHITECTURE c13s09b00x00p99n01i02793arch OF c13s09b00x00p99n01i02793ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02793 - Reserved word ELSE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02793arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1094.vhd | 4 | 1876 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1094.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01094ent IS
END c06s05b00x00p03n01i01094ent;
ARCHITECTURE c06s05b00x00p03n01i01094arch OF c06s05b00x00p03n01i01094ent IS
BEGIN
TESTING: PROCESS
type sting is array (1 to 5, 1 to 5) of character;
variable str : sting;
BEGIN
str(1 to 3, 1 to 3) := str(3 to 5, 3 to 5); -- slice of a two
-- dimensional array is
-- illegal.
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01094 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01094arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1789.vhd | 4 | 1781 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1789.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p02n01i01789ent IS
END c09s07b00x00p02n01i01789ent;
ARCHITECTURE c09s07b00x00p02n01i01789arch OF c09s07b00x00p02n01i01789ent IS
BEGIN
BL: block
begin
L1: for i in 1 to 3 generate
if i = 5 then
null;
end if;
end generate L1;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p02n01i01789 - In the generate statement, the reserved word generate must be followed by zero or more concurrent statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s07b00x00p02n01i01789arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd | 4 | 1736 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal positive_supply, negative_supply : electrical;
terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture saturating of opamp is
constant gain : real := 50.0;
quantity v_pos across positive_supply;
quantity v_neg across negative_supply;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
if v_in'above(v_pos / gain) use
v_amplified == v_pos;
elsif not v_in'above(v_neg / gain) use
v_amplified == v_neg;
else
v_amplified == gain * v_in;
end use;
break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture saturating;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2891.vhd | 4 | 2023 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2891.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n01i02891ent IS
PORT ( d : IN bit;
q : OUT bit);
END c02s01b01x00p05n01i02891ent;
ARCHITECTURE c02s01b01x00p05n01i02891arch OF c02s01b01x00p05n01i02891ent IS
function func1 (signal p1 : in bit) return bit;
function func2 (signal p1 : buffer bit) return bit;
function func1 (signal p1 : in bit) return bit is
variable v1 : bit;
begin
v1 := p1;
return (v1);
end;
function func2 (signal p1 : buffer bit) return bit is
variable v1 : bit;
begin
v1 := p1;
return (v1);
end;
BEGIN
func1 (d);
func2 (d);
q <= d;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n01i02891 - Buffer is not an allowed mode for formal parameters of a function."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n01i02891arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc721.vhd | 4 | 1691 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc721.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p02n01i00721ent IS
port (B:BIT);
generic (N:natural:= 2); -- Failure_here
-- Generic clause must precede the port clause
END c01s01b01x00p02n01i00721ent;
ARCHITECTURE c01s01b01x00p02n01i00721arch OF c01s01b01x00p02n01i00721ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p02n01i00721 - Generic declarations should come before port declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p02n01i00721arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd | 4 | 1878 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p22n01i00925ent IS
END c10s03b00x00p22n01i00925ent;
ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
constant x : integer := 3;
procedure xxx is
constant x : integer := 5;
variable y : bit;
begin
if x > 3 then
y := '1';
else
y := '0';
end if;
assert NOT( y='1' )
report "***PASSED TEST: c10s03b00x00p22n01i00925"
severity NOTE;
assert ( y='1' )
report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p22n01i00925arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd | 4 | 3130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:41 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00701ent IS
END c03s04b01x00p23n01i00701ent;
ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : NATURAL := 1;
variable VAR : NATURAL;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00701"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00701arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket55/bug3.vhdl | 3 | 189 | package pkg is
type e is (identifier, i2);
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2911.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2911.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02911ent IS
END c02s01b01x02p03n01i02911ent;
ARCHITECTURE c02s01b01x02p03n01i02911arch OF c02s01b01x02p03n01i02911ent IS
procedure proc1 (signal S1: inout bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02911 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02911arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2742.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p04n01i02742ent IS
END c13s06b00x00p04n01i02742ent;
ARCHITECTURE c13s06b00x00p04n01i02742arch OF c13s06b00x00p04n01i02742ent IS
constant mystring : string := "123456789";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( mystring'length = 9 )
report "***PASSED TEST: c13s06b00x00p04n01i02742"
severity NOTE;
assert ( mystring'length = 9 )
report "***FAILED TEST: c13s06b00x00p04n01i02742 - The length of a digit string is the number of character values in the sequence represented."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p04n01i02742arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd | 4 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n01i01908ent IS
END c07s02b00x00p09n01i01908ent;
ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***PASSED TEST: c07s02b00x00p09n01i01908"
severity NOTE;
assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n01i01908arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd | 4 | 1945 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2428.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02428ent IS
END c07s03b02x01p01n03i02428ent;
ARCHITECTURE c07s03b02x01p01n03i02428arch OF c07s03b02x01p01n03i02428ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : real;
ele_2 : real;
end record;
constant p :rec := (ele_1 | ele_2 => 4.5); -- No_failure_here
BEGIN
assert NOT(p.ele_1=4.5 and p.ele_2=4.5)
report "***PASSED TEST: c07s03b02x01p01n03i02428"
severity NOTE;
assert (p.ele_1=4.5 and p.ele_2=4.5)
report "***FAILED TEST: c07s03b02x01p01n03i02428 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02428arch;
| gpl-2.0 |
123gmax/Digital-Lab | Lab1/Ganesh/counter/tb_counter.vhd | 2 | 2008 | library ieee;
use ieee.std_logic_1164.all;
entity tb_counter is
end tb_counter;
architecture beh of tb_counter is
component counter
Port (
UP: in std_logic;
AUTO: in std_logic;
LOAD: in std_logic;
VALUE: in std_logic_vector(3 downto 0);
TICK: in std_logic;
COUNT: out std_logic_vector(3 downto 0);
RESET: in std_logic;
clk: in std_logic
);
end component;
signal up_in,auto_in,load_in,tick_in,reset_in,clk_in : std_logic;
signal value_in,count_out : std_logic_vector(3 downto 0);
constant clock_period : time:= 10 ns;
constant period_1sec : time:= 50 ns;
begin
uut:counter
port map(UP=>up_in,AUTO=>auto_in,LOAD=>load_in,VALUE=>value_in,TICK=>tick_in,COUNT=>count_out,RESET=>reset_in,clk=>clk_in);
clock_process:process
begin
clk_in <= '0';
wait for clock_period/2;
clk_in <= not clk_in;
wait for clock_period/2;
end process;
test_bench:process
begin
reset_in <= '1';
up_in <= '0';
auto_in <='0';
load_in <='0';
value_in <="0000";
tick_in <= '0';
wait for 10*clock_period;
reset_in <= '0';
wait for period_1sec;
value_in <= "1010";
load_in <= '1';
up_in <= '1'; --Up counter
auto_in <='1'; --Auto count
wait for period_1sec + 5 ns;
load_in <='0';
wait for 10*period_1sec;
up_in <= '0';--Down count
wait for 10*period_1sec;
auto_in <='0';--Manual mode
wait for period_1sec;
tick_in <= not tick_in;--1
wait for 2*period_1sec;
tick_in <= not tick_in;--0
wait for period_1sec*3;
tick_in <= not tick_in;--1
wait for period_1sec;
auto_in <= '1';--Auto mode
up_in <= '1'; -- Up count
wait;
end process;
end beh;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket19/psl_test_cover2.vhd | 1 | 1260 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover always (s_write -> not(s_read));
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1155.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01155ent IS
END c06s06b00x00p02n01i01155ent;
ARCHITECTURE c06s06b00x00p02n01i01155arch OF c06s06b00x00p02n01i01155ent IS
BEGIN
TESTING: PROCESS
type ABASE is array (INTEGER range <>) of BOOLEAN;
subtype A1 is ABASE(1 to 5);
variable V : A1;
variable k : integer := 0;
BEGIN
if V(2 to 4)'LOW = 2 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01155"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01155 - The prefix of an attribute name may be a slice name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01155arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd | 4 | 1598 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc719.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p04n01i00719ent IS
BEGIN
END; -- No_Failure_Here
ENTITY c01s01b00x00p04n01i00719ent IS
END c01s01b00x00p04n01i00719ent;
ARCHITECTURE c01s01b00x00p04n01i00719arch OF c01s01b00x00p04n01i00719ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b00x00p04n01i00719"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b00x00p04n01i00719arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd | 4 | 1972 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc365.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n01i00365ent IS
END c03s02b01x01p03n01i00365ent;
ARCHITECTURE c03s02b01x01p03n01i00365arch OF c03s02b01x01p03n01i00365ent IS
subtype decade is integer;
type MVL_vector is array (decade range 1 to 50) of integer;
BEGIN
TESTING: PROCESS
variable k : MVL_vector;
BEGIN
k(1) := 2;
k(50) := 5;
assert NOT (k(1)=2 and k(50)=5)
report "***PASSED TEST: c03s02b01x01p03n01i00365"
severity NOTE;
assert (k(1)=2 and k(50)=5)
report "***FAILED TEST: c03s02b01x01p03n01i00365 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n01i00365arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket52/file.vhdl | 3 | 160 | entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd | 4 | 3438 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1523.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s09b00x00p07n01i01523pkg is
-- Global procedure.
procedure proc1;
-- Global function.
function func1 return INTEGER;
end c08s09b00x00p07n01i01523pkg;
package body c08s09b00x00p07n01i01523pkg is
procedure proc1 is
-- Local variables
variable INTV : INTEGER := 0;
begin
-- Check initialization.
assert (INTV = 0);
-- Loop until the indicated condition has been met.
loop
-- Execute some meaningful function.
null;
-- Increment the counter.
INTV := INTV + 1;
-- If the condition has been met, terminate the loop.
if (INTV = 10) then
return;
end if;
-- Verify that we have not exceeded the limits of the loop.
assert (INTV < 10);
end loop;
-- Should NEVER get to this step.
assert (FALSE)
report "Return has not exited the procedure.";
end proc1;
function func1 return INTEGER is
-- Local variables
variable INTV : INTEGER := 0;
begin
-- Check initialization.
assert (INTV = 0);
-- Loop until the indicated condition has been met.
loop
-- Execute some meaningful function.
null;
-- Increment the counter.
INTV := INTV + 1;
-- If the condition has been met, terminate the loop.
if (INTV = 10) then
return( INTV );
end if;
-- Verify that we have not exceeded the limits of the loop.
assert (INTV < 10);
end loop;
-- Should NEVER get to this step.
assert (FALSE)
report "Return has not exited the procedure.";
end func1;
end c08s09b00x00p07n01i01523pkg;
use work.c08s09b00x00p07n01i01523pkg.all;
ENTITY c08s09b00x00p07n01i01523ent IS
END c08s09b00x00p07n01i01523ent;
ARCHITECTURE c08s09b00x00p07n01i01523arch OF c08s09b00x00p07n01i01523ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
-- Call procedure to loop/return.
proc1;
assert NOT(func1=10)
report "***PASSED TEST: c08s09b00x00p07n01i01523"
severity NOTE;
assert (func1=10)
report "***PASSED TEST: c08s09b00x00p07n01i01523 - Function did not return proper value."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s09b00x00p07n01i01523arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd | 4 | 2272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1030.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01030ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01030ent;
ARCHITECTURE c06s04b00x00p02n01i01030arch OF c06s04b00x00p02n01i01030ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V3.RE3(1)(3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01030"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01030 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01030arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd | 4 | 1943 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00581ent IS
END c03s04b01x00p01n01i00581ent;
ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
type string_file is file of string;
BEGIN
TESTING: PROCESS
file filein : string_file open write_mode is "iofile.21";
BEGIN
for i in 1 to 100 loop
write(filein,"shishir");
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00581arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd | 4 | 2461 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_16_07 is
end entity fg_16_07;
architecture test of fg_16_07 is
constant reg0 : std_logic_vector(7 downto 0) := "00000000";
constant reg1 : std_logic_vector(7 downto 0) := "11111111";
signal dbus : std_logic_vector(7 downto 0);
signal reg_sel, read, reg_addr : X01 := '0';
begin
-- code from book
reg_read_selector : block (reg_sel = '1' and read = '1') is
begin
dbus <= reg0 when guard and reg_addr = '0' else
reg1 when guard and reg_addr = '1' else
"ZZZZZZZZ";
end block reg_read_selector;
-- end code from book
stimulus : process is
begin
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_sel <= '0'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_addr <= '1'; wait for 10 ns;
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc720.vhd | 3 | 1568 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc720.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p04n01i00720ent IS
END c01s01b00x00p04n01i00720ent;
ARCHITECTURE c01s01b00x00p04n01i00720arch OF c01s01b00x00p04n01i00720ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p04n01i00720 - Entity_simple_name differs from identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p04n01i00720arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd | 4 | 2518 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p10n01i00778ent_a IS
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
END c01s01b01x02p10n01i00778ent_a;
ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
BEGIN
test : process
begin
wait;
end process test;
END c01s01b01x02p10n01i00778arch_a;
ENTITY c01s01b01x02p10n01i00778ent IS
port (p1 : in integer;
p2 : out integer;
p3 : inout integer;
p4 : buffer integer;
p5 : linkage integer);
END c01s01b01x02p10n01i00778ent;
ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
component c01s01b01x02p10n01i00778ent_b
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
end component;
for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
BEGIN
L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p10n01i00778"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p10n01i00778arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl | 4 | 347 | entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : bit_vector( 3 downto 0 );
begin -- only
p: process
begin -- process p
sig <= "1001";
wait for 1 fs;
assert sig = "1001" report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket9/index_range_test_A.vhd | 3 | 650 | --
-- indexing testcase "A" derived from gna bug16782
--
-- ghdl-0.31-mcode on win32 : indexing off the end of an unconstrained port results in an unhandled exception
--
entity comp2 is
port(a :in bit_vector);
end entity;
architecture arch of comp2 is
constant DATAPATH : natural := a'length;
signal tmp : bit;
begin
tmp <= a(DATAPATH+3);
end architecture;
entity index_range_test_A is end entity;
architecture arch of index_range_test_A is
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: entity work.comp2 port map(a);
end architecture; | gpl-2.0 |
peteut/ghdl | testsuite/gna/bug18351/18351.vhd | 3 | 1419 | entity PROBLEM is
end PROBLEM;
architecture BUG of PROBLEM is
-- original testcase used std_logic_vector but other types suffer too
type t_int_ptr is access integer;
function ISSUE_HERE return t_int_ptr is
begin
return new integer;
end ISSUE_HERE;
-- do functions with parameters work?
function ISSUE_2(I : Integer) return t_int_ptr is
variable Temp : t_int_ptr;
begin
Temp := new integer;
Temp.all := I;
return Temp;
end ISSUE_2;
function ISSUE_3 return t_int_ptr is
variable Temp : t_int_ptr;
begin
Temp := new integer;
Temp.all := 33;
return Temp;
end ISSUE_3;
-- original testcase passed the result as param to a procedure
-- so test passing parameters too
procedure ANY_STUFF(param: in integer) is
begin
report "Integer value " & integer'image(param) severity note;
end procedure;
begin
eval : process is
variable X : t_int_ptr;
variable Y : integer;
begin
X := ISSUE_HERE;
ANY_STUFF(X.all); -- Test case (1) : works
--Y := ISSUE_2(55).all; -- Test case (2) : used to fail; works with first patch
--ANY_STUFF(Y);
Y := ISSUE_HERE.all; -- Test case (3) : fails
ANY_STUFF(Y);
ANY_STUFF(ISSUE_HERE.all); -- Test case (4) : fails
Y := ISSUE_3.all; -- Test case (5) : fails
ANY_STUFF(Y);
ANY_STUFF(ISSUE_3.all); -- Test case (6) : fails
wait;
end process;
end BUG;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2929.vhd | 4 | 1844 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2929.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02929ent IS
END c02s02b00x00p04n01i02929ent;
ARCHITECTURE c02s02b00x00p04n01i02929arch OF c02s02b00x00p04n01i02929ent IS
function Q return BIT;
function Q return BIT is
for all : COMP_NAME use entity (open) architecture(open);
end for; -- Failure_here
-- ERROR : configuration specification not allowed in subprogram declarations
begin
return '0';
end Q;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02929 - Configuration declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02929arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2582.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2582.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02582ent IS
END c13s03b01x00p02n01i02582ent;
ARCHITECTURE c13s03b01x00p02n01i02582arch OF c13s03b01x00p02n01i02582ent IS
BEGIN
TESTING: PROCESS
variable k# : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02582 - Identifier can not end with '#'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02582arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1253.vhd | 4 | 1672 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1253.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01253ent IS
END c08s02b00x00p04n02i01253ent;
ARCHITECTURE c08s02b00x00p04n02i01253arch OF c08s02b00x00p04n02i01253ent IS
BEGIN
TESTING: PROCESS
variable k : real;
BEGIN
assert FALSE
report "Report this Note"
severity k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01253 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01253arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd | 4 | 2419 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_11_01 is
end entity fg_11_01;
architecture test of fg_11_01 is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd | 4 | 1781 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00219ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00219ent;
ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
BEGIN
TESTING: PROCESS
variable e1:integer;
BEGIN
e1 := e'pos(EMIN);
assert NOT(e1=0)
report "***PASSED TEST: c03s01b01x00p06n03i00219"
severity NOTE;
assert (e1=0)
report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00219arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd | 4 | 3200 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-br.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_rtl of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(rtl)
port map (clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= ( 0.5, 0.5); y <= ( 0.5, 0.5); clr <= '0'; wait until clk = '0';
x <= ( 0.5, 0.5); y <= ( 0.1, 0.1); clr <= '0'; wait until clk = '0';
x <= ( 0.5, 0.5); y <= ( 0.5, 0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, 0.5); y <= (-0.5, 0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_rtl;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd | 4 | 2158 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc635.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:49 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00635ent IS
END c03s04b01x00p01n01i00635ent;
ARCHITECTURE c03s04b01x00p01n01i00635arch OF c03s04b01x00p01n01i00635ent IS
type four_value is ('Z','0','1','X');
type four_value_vector is array (natural range <>) of four_value;
type four_value_vector_file is file of four_value_vector;
constant C38 : four_value_vector := ('1','0','1','0');
BEGIN
TESTING: PROCESS
file filein : four_value_vector_file open write_mode is "iofile.39";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00635 - The output file will be verified by test s010280.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00635arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3003.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3003.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p05n01i03003pkg is
end c02s06b00x00p05n01i03003pkg;
package body c02s06b00x00p05n01i03003 is --Failure here
end c02s06b00x00p05n01i03003;
ENTITY c02s06b00x00p05n01i03003ent IS
END c02s06b00x00p05n01i03003ent;
ARCHITECTURE c02s06b00x00p05n01i03003arch OF c02s06b00x00p05n01i03003ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p05n01i03003 - The simple name at the start of a package body must repeat the package identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p05n01i03003arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug21500/resolv1.vhdl | 3 | 449 | entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
function resolv (vec : arr3) return arr2
is
begin
return vec (vec'left);
end resolv;
signal s : resolv arr2;
begin
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd | 4 | 2179 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc993.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p08n02i00993pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p08n02i00993pkg;
use work.c06s03b00x00p08n02i00993pkg.all;
ENTITY c06s03b00x00p08n02i00993ent IS
END c06s03b00x00p08n02i00993ent;
ARCHITECTURE c06s03b00x00p08n02i00993arch OF c06s03b00x00p08n02i00993ent IS
BEGIN
TESTING: PROCESS
variable V1 : T2 ;
BEGIN
V1.S12.S2 := 10 ; -- No_Failure_here
wait for 10 ns;
assert NOT(V1.S12.S2 = 10)
report "***PASSED TEST: c06s03b00x00p08n02i00993"
severity NOTE;
assert (V1.S12.S2 = 10)
report "***FAILED TEST: c06s03b00x00p08n02i00993 - The expanded name denotes all primary units contained in a library if the prefix denotes the library and the suffix is the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n02i00993arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc240.vhd | 4 | 1699 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc240.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00240ent IS
END c03s01b02x00p04n01i00240ent;
ARCHITECTURE c03s01b02x00p04n01i00240arch OF c03s01b02x00p04n01i00240ent IS
type a is range (1+1) to 10;
type b is range (10+1) to 100;
type c is range a to b;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00240 - The bounds in the range constraint are not locally static expressions of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00240arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd | 4 | 1953 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01450ent IS
END c08s07b00x00p01n01i01450ent;
ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
begin
p: process
variable j : integer := 1;
variable i : integer := 0;
variable k : integer := 0;
variable m : integer := 0;
begin
if j = 1 then
i := 1;
elsif j = 2 then
k := 1;
else
m := 1;
end if;
assert (i = 0) and (k = 1) and (m = 1)
report "***PASSED TEST: c08s07b00x00p01n01i01450"
severity NOTE;
assert NOT((i = 0) and (k = 1) and (m = 1))
report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01450arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd | 4 | 1644 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
type state_type is (init_state, state1, state2, state3);
type state_vector is array (integer range <>) of state_type;
function resolve_state ( drivers : state_vector ) return state_type is
begin
return drivers(drivers'left);
end function resolve_state;
-- code from book:
signal interrupt_request : pulled_up bit bus;
signal stored_state : resolve_state state_type register := init_state;
-- end of code from book
begin
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd | 4 | 1788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02180ent IS
END c07s02b05x00p01n02i02180ent;
ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := abs m;
assert NOT( k = 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02180"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02180arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd | 4 | 3153 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p07n01i03114ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p07n01i03114ent_a;
ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p07n01i03114arch_a;
configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
for c05s02b00x00p07n01i03114arch_a
end for;
end c05s02b00x00p07n01i03114cfg_a;
ENTITY c05s02b00x00p07n01i03114ent IS
END c05s02b00x00p07n01i03114ent;
ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
for u1 : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
for others : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b00x00p07n01i03114"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p07n01i03114arch;
configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
for c05s02b00x00p07n01i03114arch
end for;
end c05s02b00x00p07n01i03114cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd | 4 | 11524 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00486ent IS
END c03s02b01x01p19n01i00486ent;
ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
type array_rec_rec is array (integer range <>) of record_of_records;
function resolution13(i:in array_rec_rec) return record_of_records is
variable temp : record_of_records :=C55 ;
begin
return temp;
end resolution13;
subtype array_rec_rec_state is resolution13 record_of_records;
constant C66 : array_rec_rec_state := C55;
function complex_scalar(s : array_rec_rec_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec_state;
signal S2 : array_rec_rec_state;
signal S3 : array_rec_rec_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00486"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00486arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd | 4 | 2093 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p05n01i02761ent IS
END c13s07b00x00p05n01i02761ent;
-- Dale Martin modified this file to make the bit string literal comparisons
-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5") = O"1_75")
and ( bit_vector'(X"7D") = X"7_D"))
report "***PASSED TEST: c13s07b00x00p05n01i02761"
severity NOTE;
assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5")=O"1_75")
and ( bit_vector'(X"7D")=X"7_D"))
report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p05n01i02761arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd | 4 | 7463 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_20_06 is
end entity ch_20_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of ch_20_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
| gpl-2.0 |
daniw/add | cpu/cpu.vhd | 2 | 2550 | -------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
bus_in : in t_bus2cpu;
bus_out : out t_cpu2bus
);
end cpu;
architecture rtl of cpu is
signal ctr2prc : t_ctr2prc;
signal prc2ctr : t_prc2ctr;
signal ctr2alu : t_ctr2alu;
signal alu2ctr : t_alu2ctr;
signal ctr2reg : t_ctr2reg;
signal reg2ctr : t_reg2ctr;
signal alu_res, alu_op1, alu_op2 : std_logic_vector(DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- Control Unit--------------------------------------------------------------
i_ctrl: entity work.cpu_ctrl
port map(
rst => rst,
clk => clk,
data_in => bus_in.data,
addr => bus_out.addr,
data_out => bus_out.data,
r_wb => bus_out.r_wb,
reg_in => reg2ctr,
reg_out => ctr2reg,
prc_in => prc2ctr,
prc_out => ctr2prc,
alu_in => alu2ctr,
alu_out => ctr2alu
);
-- Address Generation -------------------------------------------------------
i_prc: entity work.cpu_prc
port map(
rst => rst,
clk => clk,
ctr_in => ctr2prc,
ctr_out => prc2ctr
);
-- ALU ----------------------------------------------------------------------
i_alu: entity work.cpu_alu
port map(
clk => clk,
alu_in => ctr2alu,
alu_out => alu2ctr,
oper1 => alu_op1,
oper2 => alu_op2,
result => alu_res
);
-- Register Block -----------------------------------------------------------
i_reg: entity work.cpu_reg
port map(
rst => rst,
clk => clk,
reg_in => ctr2reg,
reg_out => reg2ctr,
alu_res => alu_res,
alu_op1 => alu_op1,
alu_op2 => alu_op2
);
end rtl;
| gpl-2.0 |
daniw/add | floppy/mcu/cpu_alu.vhd | 2 | 6822 | -------------------------------------------------------------------------------
-- Entity: cpu_alu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ALU for the RISC-CPU of the von-Neuman MCU.
-- The ALU is purely combinational, and thus no .enb signal in the alu_in
-- is required.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_alu is
port(clk : in std_logic;
-- CPU internal interfaces
alu_in : in t_ctr2alu;
alu_out : out t_alu2ctr;
oper1 : in std_logic_vector(DW-1 downto 0);
oper2 : in std_logic_vector(DW-1 downto 0);
result : out std_logic_vector(DW-1 downto 0)
);
end cpu_alu;
architecture rtl of cpu_alu is
signal result_int : std_logic_vector(DW-1 downto 0);
signal imml : std_logic_vector(DW-1 downto 0);
signal immh : std_logic_vector(DW-1 downto 0);
constant ext_0 : std_logic_vector(IOWW-1 downto 0) := (others => '0');
constant ext_1 : std_logic_vector(IOWW-1 downto 0) := (others => '1');
begin
-- output assignment
result <= result_int;
-- helper signals for addil/addih instructions with sign extension
imml <= (ext_0 & alu_in.imm) when alu_in.imm(alu_in.imm'left) = '0' else
(ext_1 & alu_in.imm);
immh <= alu_in.imm & ext_0;
-----------------------------------------------------------------------------
-- ISE workaround (:-((
-----------------------------------------------------------------------------
g_ISE: if ISE_TOOL generate
with to_integer(unsigned(alu_in.op)) select result_int <=
-- Opcode 0: add
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when 0,
-- Opcode 1: sub
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when 1,
-- Opcode 2: and
oper1 and oper2 when 2,
-- Opcode 3: or
oper1 or oper2 when 3,
-- Opcode 4: xor
oper1 xor oper2 when 4,
-- Opcode 5: slai
oper1(DW-2 downto 0) & '0' when 5,
-- Opcode 6: srai
oper1(DW-1) & oper1(DW-1 downto 1) when 6,
-- Opcode 7: mov
oper1 when 7,
-- Opcode 12: addil
std_logic_vector(unsigned(oper1) + unsigned(imml)) when 12,
-- Opcode 13: addih
std_logic_vector(unsigned(oper1) + unsigned(immh)) when 13,
-- other (ensures memory-less process)
(others => '0') when others;
end generate g_ISE;
-----------------------------------------------------------------------------
-- More elegant solution using type attribute 'val. Unfortunately, this
-- attribute is not supported by ISE XST, but works fine with Vivado.
-- (also note that the complementary attribute to 'val is 'pos)
-----------------------------------------------------------------------------
g_NOT_ISE: if not ISE_TOOL generate
with t_alu_instr'val(to_integer(unsigned(alu_in.op))) select result_int <=
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when add,
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when sub,
oper1 and oper2 when andi,
oper1 or oper2 when ori,
oper1 xor oper2 when xori,
oper1(DW-2 downto 0) & '0' when slai,
oper1(DW-1) & oper1(DW-1 downto 1) when srai,
oper1 when mov,
std_logic_vector(unsigned(oper1) + unsigned(imml)) when addil,
std_logic_vector(unsigned(oper1) + unsigned(immh)) when addih,
(others =>'0') when others;
end generate g_NOT_ISE;
-----------------------------------------------------------------------------
-- Update and register flags N, Z, C, O with valid ALU results
-----------------------------------------------------------------------------
P_flag: process(clk)
variable v_op2 : std_logic_vector(DW-1 downto 0);
begin
if rising_edge(clk) then
if alu_in.enb = '1' then
-- get correct Operand 2 for add/addil/addih
if (to_integer(unsigned(alu_in.op)) = 0) then
v_op2 := oper2; --add
elsif (to_integer(unsigned(alu_in.op)) = 12) then
v_op2 := imml; --addil
else
v_op2 := immh; --addih
end if;
-- N, updated with each operation -------------------------------------
alu_out.flag(N) <= result_int(DW-1);
-- Z, updated with each operation -------------------------------------
alu_out.flag(Z) <= '0';
if to_integer(unsigned(result_int)) = 0 then
alu_out.flag(Z) <= '1';
end if;
-- C, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(C) <= (oper1(DW-1) and v_op2(DW-1)) or
(oper1(DW-1) and not result_int(DW-1)) or
(v_op2(DW-1) and not result_int(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(C) <= (oper2(DW-1) and not oper1(DW-1)) or
(result_int(DW-1) and not oper1(DW-1)) or
(oper2(DW-1) and result_int(DW-1));
end if;
-- O, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(O) <= (not oper1(DW-1) and not v_op2(DW-1) and result_int(DW-1)) or
( oper1(DW-1) and v_op2(DW-1) and not result_int(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(O) <= ( oper1(DW-1) and not oper2(DW-1) and not result_int(DW-1)) or
(not oper1(DW-1) and oper2(DW-1) and result_int(DW-1));
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
daniw/add | rot_enc/cpu_reg.vhd | 3 | 2773 | -------------------------------------------------------------------------------
-- Entity: cpu_reg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Register block for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 x 16
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_reg is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
reg_in : in t_ctr2reg;
reg_out : out t_reg2ctr;
alu_res : in std_logic_vector(DW-1 downto 0);
alu_op1 : out std_logic_vector(DW-1 downto 0);
alu_op2 : out std_logic_vector(DW-1 downto 0)
);
end cpu_reg;
architecture rtl of cpu_reg is
signal reg_blk : t_regblk;
begin
-----------------------------------------------------------------------------
-- Mux and register data/address to Control Unit depending on source info.
-----------------------------------------------------------------------------
P_mux: process(clk)
begin
if rising_edge(clk) then
reg_out.data <= reg_blk(to_integer(unsigned(reg_in.dest)));
reg_out.addr <= reg_blk(to_integer(unsigned(reg_in.src1)))(AW-1 downto 0);
end if;
end process;
-----------------------------------------------------------------------------
-- Mux input data to ALU combinationally depending on source info from
-- control unit.
-----------------------------------------------------------------------------
alu_op1 <= reg_blk(to_integer(unsigned(reg_in.src1)));
alu_op2 <= reg_blk(to_integer(unsigned(reg_in.src2)));
-----------------------------------------------------------------------------
-- CPU register block
-- Store ALU result or data from control unit depending on different enable
-- signals and destination info given from the control unit.
-- Note: Some CPU registers have non-zero reset values to allow simulation
-- of register-to-register instructions without load-instructions.
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
reg_blk <= (others => (others => '0'));
elsif rising_edge(clk) then
if reg_in.enb_res = '1' then
-- store result from ALU
reg_blk(to_integer(unsigned(reg_in.dest))) <= alu_res;
elsif reg_in.enb_data = '1' then
-- store data from Ctrl (ld instruction)
reg_blk(to_integer(unsigned(reg_in.dest))) <= reg_in.data;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
daniw/add | rot_enc/cpu_alu.vhd | 3 | 7503 | -------------------------------------------------------------------------------
-- Entity: cpu_alu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ALU for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_alu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
alu_in : in t_ctr2alu;
alu_out : out t_alu2ctr;
oper1 : in std_logic_vector(DW-1 downto 0);
oper2 : in std_logic_vector(DW-1 downto 0);
result : out std_logic_vector(DW-1 downto 0)
);
end cpu_alu;
architecture rtl of cpu_alu is
signal result_reg : std_logic_vector(DW-1 downto 0);
signal alu_enb_reg : std_logic;
signal imml : std_logic_vector(DW-1 downto 0);
signal immh : std_logic_vector(DW-1 downto 0);
constant ext_0 : std_logic_vector(IOWW-1 downto 0) := (others => '0');
constant ext_1 : std_logic_vector(IOWW-1 downto 0) := (others => '1');
begin
-- output assignment
result <= result_reg;
-- helper signals for addil/addih instructions with sign extension
imml <= (ext_0 & alu_in.imm) when alu_in.imm(alu_in.imm'left) = '0' else
(ext_1 & alu_in.imm);
immh <= alu_in.imm & ext_0;
-----------------------------------------------------------------------------
-- ALU operations (ISE workaround)
-----------------------------------------------------------------------------
P_alu: process(clk)
begin
if rising_edge(clk) then
if to_integer(unsigned(alu_in.op)) = 0 then -- add
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(oper2));
elsif to_integer(unsigned(alu_in.op)) = 1 then -- sub
result_reg <= std_logic_vector(unsigned(oper1) - unsigned(oper2));
elsif to_integer(unsigned(alu_in.op)) = 2 then -- and
result_reg <= oper1 and oper2;
elsif to_integer(unsigned(alu_in.op)) = 3 then -- or
result_reg <= oper1 or oper2;
elsif to_integer(unsigned(alu_in.op)) = 4 then -- xor
result_reg <= oper1 xor oper2;
elsif to_integer(unsigned(alu_in.op)) = 5 then -- slai
result_reg <= oper1(DW-2 downto 0) & '0';
elsif to_integer(unsigned(alu_in.op)) = 6 then -- srai
result_reg <= oper1(DW-1) & oper1(DW-1 downto 1);
elsif to_integer(unsigned(alu_in.op)) = 7 then -- mov
result_reg <= oper1;
elsif to_integer(unsigned(alu_in.op)) = 12 then -- addil
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(imml));
elsif to_integer(unsigned(alu_in.op)) = 13 then -- addih
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(immh));
elsif to_integer(unsigned(alu_in.op)) = 14 then -- setil
result_reg <= oper1(DW-1 downto DW/2) & alu_in.imm;
elsif to_integer(unsigned(alu_in.op)) = 15 then -- setih
result_reg <= alu_in.imm & oper1(DW/2-1 downto 0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- More elegant solution using type attribute 'val. Unfortunately, this
-- attribute is not supported by ISE XST, but works fine with Vivado.
-- (also note that the complementary attribute to 'val is 'pos)
-- ToDo: register!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-----------------------------------------------------------------------------
g_NOT_ISE: if not ISE_TOOL generate
with t_alu_instr'val(to_integer(unsigned(alu_in.op))) select result_reg <=
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when add,
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when sub,
oper1 or oper2 when andi,
oper1 or oper2 when ori,
oper1 xor oper2 when xori,
oper1(DW-2 downto 0) & '0' when slai,
oper1(DW-1) & oper1(DW-1 downto 1) when srai,
oper1 when mov,
std_logic_vector(unsigned(oper1) + unsigned(imml)) when addil,
std_logic_vector(unsigned(oper1) + unsigned(immh)) when addih,
(others =>'0') when others;
end generate g_NOT_ISE;
-----------------------------------------------------------------------------
-- Update and register flags N, Z, C, O from registerd ALU results
-----------------------------------------------------------------------------
P_flag: process(clk)
variable v_op2 : std_logic_vector(DW-1 downto 0);
begin
if rising_edge(clk) then
-- regsiter enable from CPU_CTRL ----------------------------------------
alu_enb_reg <= alu_in.enb;
-- flag update with registered enable and registered ALU result ---------
if alu_enb_reg = '1' then
-- get correct Operand 2 for add/addil/addih
if (to_integer(unsigned(alu_in.op)) = 0) then
v_op2 := oper2; --add
elsif (to_integer(unsigned(alu_in.op)) = 12) then
v_op2 := imml; --addil
else
v_op2 := immh; --addih
end if;
-- N, updated with each operation -------------------------------------
alu_out.flag(N) <= result_reg(DW-1);
-- Z, updated with each operation -------------------------------------
alu_out.flag(Z) <= '0';
if to_integer(unsigned(result_reg)) = 0 then
alu_out.flag(Z) <= '1';
end if;
-- C, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(C) <= (oper1(DW-1) and v_op2(DW-1)) or
(oper1(DW-1) and not result_reg(DW-1)) or
(v_op2(DW-1) and not result_reg(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(C) <= (oper2(DW-1) and not oper1(DW-1)) or
(result_reg(DW-1) and not oper1(DW-1)) or
(oper2(DW-1) and result_reg(DW-1));
end if;
-- O, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(O) <= (not oper1(DW-1) and not v_op2(DW-1) and result_reg(DW-1)) or
( oper1(DW-1) and v_op2(DW-1) and not result_reg(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(O) <= ( oper1(DW-1) and not oper2(DW-1) and not result_reg(DW-1)) or
(not oper1(DW-1) and oper2(DW-1) and result_reg(DW-1));
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
daniw/add | edk/IVK_HW/t01_hello/hdl/lmb_bram_wrapper.vhd | 1 | 2861 | -------------------------------------------------------------------------------
-- lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of lmb_bram_wrapper : entity is "yes";
end lmb_bram_wrapper;
architecture STRUCTURE of lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan6"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
| gpl-2.0 |
daniw/add | edk/IVK_HW/t01_hello/hdl/dlmb_cntlr_wrapper.vhd | 1 | 14262 | -------------------------------------------------------------------------------
-- dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_bram_if_cntlr_v3_00_b.all;
entity dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_00_b";
end dlmb_cntlr_wrapper;
architecture STRUCTURE of dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| gpl-2.0 |
daniw/add | edk/IVK_HW/t01_hello/hdl/leds_8bit_wrapper.vhd | 1 | 7771 | -------------------------------------------------------------------------------
-- leds_8bit_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_gpio_v2_00_a;
use xps_gpio_v2_00_a.all;
entity leds_8bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 7);
GPIO_IO_O : out std_logic_vector(0 to 7);
GPIO_IO_T : out std_logic_vector(0 to 7);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute x_core_info of leds_8bit_wrapper : entity is "xps_gpio_v2_00_a";
end leds_8bit_wrapper;
architecture STRUCTURE of leds_8bit_wrapper is
component xps_gpio is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_FAMILY : STRING;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector;
C_TRI_DEFAULT : std_logic_vector;
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector;
C_TRI_DEFAULT_2 : std_logic_vector
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1))
);
end component;
begin
LEDs_8Bit : xps_gpio
generic map (
C_BASEADDR => X"81420000",
C_HIGHADDR => X"8142ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_FAMILY => "spartan6",
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
| gpl-2.0 |
daniw/add | cpu/mcu_pkg.vhd | 2 | 8581 | -------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- tool chain selection (because no suppoprt of 'val attritube in ISE XST)
-----------------------------------------------------------------------------
constant ISE_TOOL : boolean := true; -- true = ISE XST
-- false = other synthesizer (e.g. Vivado)
-----------------------------------------------------------------------------
-- design parameters
-----------------------------------------------------------------------------
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 8; -- total address width
constant AWH : natural range 1 to 64 := 2; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, LCD); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => X"00",
RAM => X"40",
GPIO => X"80",
LCD => X"C0"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM)(AW-1 downto AW-AWH),
RAM => BA(RAM)(AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
LCD => BA(LCD)(AW-1 downto AW-AWH)
);
-- CPU instruction set
-- Note: Defining the OPcode in the way shown below, allows assembler-style
-- programming with mnemonics rather than machine coding (see rom.vhd).
constant OPCW : natural range 1 to DW := 5; -- Opcode word width
constant OPAW : natural range 1 to DW := 4; -- ALU operation word width
constant IOWW : natural range 1 to DW := 8; -- immediate operand word width
type t_instr is (add, sub, andi, ori, xori, slai, srai, mov,
ld, st,
addil, addih, setil, setih,
jmp, bne, bge, blt, bca, bov,
nop);
-- Instructions targeted at the ALU are defined by means of a sub-type.
-- This allows changing the opcode of instructions without having to
-- modify the source code of the ALU.
subtype t_alu_instr is t_instr range add to mov;
type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0);
constant OPC : t_opcode := ( -- OPcode
-- ALU operations -------------------------------
add => "00000", -- 0: addition
sub => "00001", -- 1: subtraction
andi => "00010", -- 2: bit-wise AND
ori => "00011", -- 3: bit-wise OR
xori => "00100", -- 4: bit-wise XOR
slai => "00101", -- 5: shift-left arithmetically
srai => "00110", -- 6: shift-right arithmetically
mov => "00111", -- 7: move between register
-- Immediate Operands ---------------------------
addil => "01100", -- 12: add imm. constant low
addih => "01101", -- 13: add imm. constant high
setil => "01110", -- 14: set imm. constant low
setih => "01111", -- 15: set imm. constant high
-- Memory load/store ----------------------------
ld => "10000", -- 16: load from memory
st => "10001", -- 17: store to memory
-- Jump/Branch ----------------------------------
jmp => "11000", -- 24: absolute jump
bne => "11001", -- 25: branch if not equal (not Z)
bge => "11010", -- 26: branch if greater/equal (not N or Z)
blt => "11011", -- 27: branch if less than (N)
bca => "11100", -- 28: branch if carry set (C)
bov => "11101", -- 29: branch if overflow set (O)
-- Others ---------------------------------------
nop => "11111" -- 31: no operation
);
type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow)
type t_flag_arr is array (t_flags) of std_logic;
-- register block
constant RIDW : natural range 1 to DW := 3; -- register ID word width
type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0);
constant reg : t_regid := ("000","001","010","011","100","101","110","111");
type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0);
-- CPU address generation
type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi
type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions
-- LCD peripheral
constant LCD_PW : natural := 7; -- # of LCD control + data signal
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
r_wb : std_logic;
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
addr : std_logic_vector(AWL-1 downto 0);
data : std_logic_vector(DW-1 downto 0);
we : std_logic;
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- GPIO ---------------------------------------------------------------------
type t_gpio_pin_in is record
in_0 : std_logic_vector(DW-1 downto 0);
in_1 : std_logic_vector(DW-1 downto 0);
in_2 : std_logic_vector(DW-1 downto 0);
in_3 : std_logic_vector(DW-1 downto 0);
end record;
type t_gpio_pin_out is record
out_0 : std_logic_vector(DW-1 downto 0);
out_1 : std_logic_vector(DW-1 downto 0);
out_2 : std_logic_vector(DW-1 downto 0);
out_3 : std_logic_vector(DW-1 downto 0);
enb_0 : std_logic_vector(DW-1 downto 0);
enb_1 : std_logic_vector(DW-1 downto 0);
enb_2 : std_logic_vector(DW-1 downto 0);
enb_3 : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types
-----------------------------------------------------------------------------
-- Control Unit / Register Block interface ----------------------------------
type t_ctr2reg is record
src1 : std_logic_vector(RIDW-1 downto 0);
src2 : std_logic_vector(RIDW-1 downto 0);
dest : std_logic_vector(RIDW-1 downto 0);
enb_res : std_logic;
data : std_logic_vector(DW-1 downto 0);
enb_data_low : std_logic;
enb_data_high : std_logic;
end record;
type t_reg2ctr is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
-- Control Unit / Program Counter interface --------------------------------
type t_ctr2prc is record
enb : std_logic;
mode : t_pc_mode;
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_prc2ctr is record
pc : std_logic_vector(AW-1 downto 0);
exc : t_addr_exc;
end record;
-- Control Unit / ALU interface ---------------------------------------------
type t_ctr2alu is record
op : std_logic_vector(OPAW-1 downto 0); -- operation
imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand
enb : std_logic; -- enable flag update
end record;
type t_alu2ctr is record
flag : t_flag_arr;
end record;
end mcu_pkg;
| gpl-2.0 |
daniw/add | lab1/Ex3/FIR_5x5_load_coeff/vhd/fir_2d_modules.vhd | 1 | 6366 | -------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: Components for 2D 5x5-FIR filter
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Multiplier
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity MULT is
generic(
DW_IN_1 : integer;
DW_IN_2 : integer;
DELAY : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
FACTOR_IN_1 : in std_logic_vector(DW_IN_1-1 downto 0);
FACTOR_IN_2 : in std_logic_vector(DW_IN_2-1 downto 0);
PRODUCT_OUT : out std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0)
);
end MULT;
architecture structural of MULT is
type DELAY_TYPE is array(DELAY-1 downto 0) of std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0);
signal FACTOR_1_BUF : unsigned(DW_IN_1-1 downto 0);
signal FACTOR_2_BUF : unsigned(DW_IN_2-1 downto 0);
signal DelayLine : DELAY_TYPE := (others => (others => '0'));
begin
FACTOR_1_BUF <= unsigned(FACTOR_IN_1);
FACTOR_2_BUF <= unsigned(FACTOR_IN_2);
x0_multiply : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
DelayLine(DELAY-1) <= std_logic_vector(FACTOR_1_BUF * FACTOR_2_BUF);
DelayLine(DELAY-2 downto 0) <= DelayLine(DELAY-1 downto 1);
PRODUCT_OUT <= DelayLine(0);
end if;
end if;
end process x0_multiply;
end structural;
-------------------------------------------------------------------------------
-- Adder
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ADDER is
generic(
DW_IN : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
S_IN_1 : in std_logic_vector(DW_IN-1 downto 0);
S_IN_2 : in std_logic_vector(DW_IN-1 downto 0);
SUM_OUT : out std_logic_vector(DW_IN downto 0)
);
end ADDER;
architecture structural of ADDER is
signal IN_Sign1 : signed(DW_IN downto 0);
signal IN_Sign2 : signed(DW_IN downto 0);
begin
-- sign-extension of inputs
IN_Sign1 <= signed(S_IN_1(DW_IN-1) & '1' & S_IN_1(DW_IN-2 downto 0)) when S_IN_1(DW_IN-1) = '1' else
signed(S_IN_1(DW_IN-1) & '0' & S_IN_1(DW_IN-2 downto 0));
IN_Sign2 <= signed(S_IN_2(DW_IN-1) & '1' & S_IN_2(DW_IN-2 downto 0)) when S_IN_2(DW_IN-1) = '1' else
signed(S_IN_2(DW_IN-1) & '0' & S_IN_2(DW_IN-2 downto 0));
x0_ADD : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
SUM_OUT <= std_logic_vector(signed(IN_Sign1 + IN_Sign2));
end if;
end if;
end process x0_ADD;
end structural;
-------------------------------------------------------------------------------
-- absolute Value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ABS_VAL is
generic(
DW: integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
VAL_IN : in std_logic_vector(DW-1 downto 0);
VAL_OUT : out std_logic_vector(DW-1 downto 0)
);
end ABS_VAL;
architecture structural of ABS_VAL is
signal OutReg : std_logic_vector(DW-1 downto 0);
begin
x0_abs : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to generate absolute value of VAL_IN
-----------------------------------------------------------------------
OutReg <= .....
-- additional output register
VAL_OUT <= OutReg;
end if;
end if;
end process x0_abs;
end structural;
-------------------------------------------------------------------------------
-- Pipeline register
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity Pipeline_Reg is
generic(
DW_IN : integer
);
port(
clk_1 : in std_logic;
en : in std_logic;
D : in std_logic_vector(DW_IN-1 downto 0);
Q : out std_logic_vector(DW_IN-1 downto 0)
);
end Pipeline_Reg;
architecture structural of Pipeline_Reg is
begin
p_reg : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if en = '1' then
Q <= D;
end if;
end if;
end process p_reg;
end structural;
-------------------------------------------------------------------------------
-- Truncation/Saturation unit
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity CONVERT is
generic(
DW_IN : integer;
DW_OUT : integer;
BIN_PNT : integer
);
port(
clk_1 : in std_logic;
ce_1 : in std_logic;
din : in std_logic_vector(DW_IN-1 downto 0);
dout : out std_logic_vector(DW_OUT-1 downto 0)
);
end CONVERT;
architecture structural of CONVERT is
begin
x0_CONV : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to scale the unsigned value din, which has a total
-- number of DW_IN bits and BIN_PNT fractional bits, such that
-- a) dout has a total number of DW_OUT bits and zero fractional bits
-- b) saturation is applied if the value of din exceeds the maximum
-- unsigned value of dout
-----------------------------------------------------------------------
dout <= .....
end if;
end if;
end process;
end structural;
| gpl-2.0 |
daniw/add | cpu/lcd.vhd | 3 | 1538 | -------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.we = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
dtysky/3D_Displayer_Controller | VHDL_PLANB/FIFO.vhd | 1 | 6837 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: FIFO.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
END FIFO;
ARCHITECTURE SYN OF fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(127 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone IV E",
lpm_numwords => 128,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 128,
lpm_widthu => 7,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
aclr => aclr,
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "128"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "128"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "128"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 |
hitomi2500/wasca | fpga_firmware/buffered_spi_tb.vhd | 1 | 6438 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10 ns;
Ava_Wri <= '1';
wait for 10 ns;
Ava_Wri <= '0';
wait for 10 ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10 ns;
Ava_Re <= '1';
wait for 10 ns;
Ava_Re <= '0';
wait for 10 ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
reset => reset,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 300 ns;
reset <= '1';
wait for 300 ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100 ns;
--write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
--write_avalon_16("10"&X"003",X"0010",avalon_address,avalon_writedata,avalon_write); --cs, /10 clock
--write_avalon_16("10"&X"003",X"0020",avalon_address,avalon_writedata,avalon_write); --cs, /12 clock
write_avalon_16("10"&X"003",X"0030",avalon_address,avalon_writedata,avalon_write); --cs, /16 clock
wait for 100 ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100 ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100 ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100 ns;
--read
wait for 500 ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500 ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
--wait for 320 ns;
wait for 160 ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
| gpl-2.0 |
dtysky/3D_Displayer_Controller | VHDL/DDR2/DDR_CONTROL.vhd | 1 | 16690 | --FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
----The wr_num or rd_num must be less than x"0100"----
----It means Only 1 line would be read/write per operation----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity DDR2_CONTROL is
generic
(
----------------------timing-------------------
constant tRPA:integer:=4; --PRC ALL Period
constant tMRD:integer:=2; --LM Cycle
constant tRFC:integer:=25; --RF to BA/RF
constant tRP:integer:=3; --PRC ONE Period
constant tWR:integer:=3; --Write Recovery
constant tRCD:integer:=3; --BA TO WR/RD
constant tXSRD:integer:=200; --EXT SRF TO OTHER
constant AL:integer:=2;
constant CL:integer:=3;
constant BL:integer:=4;
constant BLC:integer:=2; ---BL/2
constant WL:integer:=4; ----AL+CL-1
constant RL:integer:=5; ----AL+CL
constant SETUP:integer:=35000;
-----------------------CMD---------------------
constant CMD_INIT:std_logic_vector(4 downto 0):="01000";
constant CMD_LM:std_logic_vector(4 downto 0):="10000";
constant CMD_RF:std_logic_vector(4 downto 0):="10001";
constant CMD_SRF_IN:std_logic_vector(4 downto 0):="00001";
constant CMD_SRF_OUT:std_logic_vector(4 downto 0):="10111";
constant CMD_PRC:std_logic_vector(4 downto 0):="10010";
constant CMD_BA:std_logic_vector(4 downto 0):="10011";
constant CMD_WR:std_logic_vector(4 downto 0):="10100";
constant CMD_RD:std_logic_vector(4 downto 0):="10101";
constant CMD_NOP:std_logic_vector(4 downto 0):="10111";
----------PD FAST,WR=2,CL=3,BT SE,BL=4------------
----------------MR with DLL RESET-----------------
constant MR1:std_logic_vector(12 downto 0):="0010100110010";
---------------MR without DLL RESET---------------
constant MR2:std_logic_vector(12 downto 0):="0010000110010";
--RDQS/DQS# OFF,OCD/DLL ON,ODS FULL,RTT=50,AL=2---
---------------EMR with OCD default---------------
constant EMR_0:std_logic_vector(12 downto 0):="0011111010100";
-----------------EMR with OCD exit----------------
constant EMR_1:std_logic_vector(12 downto 0):="0010001010100";
---------------------default----------------------
constant EMR2:std_logic_vector(12 downto 0):="0000000000000";
constant EMR3:std_logic_vector(12 downto 0):="0000000000000"
);
port
(
pll_lock:in std_logic;
clk_control_p,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='0';
bank:out std_logic_vector(2 downto 0):="000";
addr:out std_logic_vector(12 downto 0):="0000000000000";
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='0';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end entity;
architecture ddr2_con of DDR2_CONTROL is
---------------------clock-----------------------
signal clk_self,clk_out:std_logic;
----------cke,n_cs,n_ras,n_cas,n_we--------------
signal cmd:std_logic_vector(4 downto 0):=CMD_INIT;
--------------------flags------------------------
type states is (start,wr,rd,prc,srf,arf,reset);
--attribute states_encoding:string;
--attribute states_encoding of states:type is "000 001 010 011 100 101 110";
signal state:states:=start;
-------------------addr buffer-------------------
signal addr_row:std_logic_vector(12 downto 0):="1111111111111";
signal addr_other_row_s:std_logic_vector(12 downto 0);
signal addr_col:std_logic_vector(9 downto 0);
signal bank_s:std_logic_vector(2 downto 0);
--------------------others-----------------------
signal wr_start,rd_start:std_logic:='0';
signal wr_ready_s,rd_ready_s:std_logic:='0';
signal rd_ready_s_1,rd_ready_s_2:std_logic:='0';
signal wr_rqu_s,rd_rqu_s:std_logic;
signal udqs_last,udqs_last_last:std_logic:='0';
signal write_num_s,read_num_s:std_logic_vector(15 downto 0);
signal dqs_en_s:std_logic:='0';
begin
clk<=clk_out_p;
n_clk<=clk_out_n;
cke<=cmd(4);
n_cs<=cmd(3);
n_ras<=cmd(2);
n_cas<=cmd(1);
n_we<=cmd(0);
rd_ready_s<=rd_ready_s_1 or rd_ready_s_2;
wr_ready<=wr_ready_s;
rd_ready<=rd_ready_s;
CONTROL:process(clk_control_p,pll_lock)
variable con_init:integer range 0 to 65535:=0;
variable con_srf:integer range 0 to 255:=0;
variable con_arf:integer range 0 to 31:=0;
variable con_prc:integer range 0 to 7:=0;
variable con_write:integer range 0 to 15:=0;
variable con_write_trans:integer range 0 to 3:=0;
variable con_write_total:integer range 0 to 65536;
variable con_read:integer range 0 to 63:=0;
variable con_read_trans:integer range 0 to 3:=0;
variable con_read_total:integer range 0 to 65536:=0;
variable con_reset:integer range 0 to 31:=0;
begin
if clk_control_p'event and clk_control_p='1' and pll_lock='1' then
if ram_reset='1' then
state<=reset;
else
case state is
---------------------INIT---------------------
when start=>
con_init:=con_init+1;
case con_init is
when 10 =>
odt<='0';
when SETUP=>
cmd<=CMD_NOP;
when SETUP+100=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+1=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+1=>
cmd<=CMD_LM;
bank<="010";
addr<=EMR2;
when SETUP+100+tRPA+2=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+2=>
cmd<=CMD_LM;
bank<="011";
addr<=EMR3;
when SETUP+100+tRPA+tMRD+3=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+3=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+4=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+4=>
cmd<=CMD_LM;
bank<="000";
addr<=MR1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+5=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+5=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+6=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+6=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+7=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+7=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+8=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+8=>
cmd<=CMD_LM;
bank<="000";
addr<=MR2;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+9=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+9=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+10=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+10=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+11=>
cmd<=CMD_NOP;
when SETUP+1000=>
state<=srf;
con_init:=0;
when others=>
con_init:=con_init;
end case;
------------------AUTO REFRESH----------------
when arf=>
if dqs_en_s='0' then
wr_end<='0';
rd_end<='0';
case con_arf is
when 0 =>
con_arf:=con_arf+1;
cmd<=CMD_RF;
when 1=>
cmd<=CMD_NOP;
con_arf:=con_arf+1;
when 1+tRFC=>
con_arf:=0;
if wr_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=wr;
elsif rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
read_num_s<=read_num;
state<=rd;
else
state<=arf;
end if;
when others=>
con_arf:=con_arf+1;
end case;
elsif wr_ready_s='1' then
case con_write is
when WL =>---WL?未定
wr_end<='1';
wr_ready_s<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_write:=0;
when others=>
con_write:=con_write+1;
end case;
elsif rd_ready_s='1' then
case con_read is
when RL =>---RL?未定
rd_end<='1';
rd_ready_s_1<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_read:=0;
when others=>
con_read:=con_read+1;
end case;
else
state<=reset;
end if;
------------------SELF REFRESH----------------
when srf=>
case con_srf is
when 0 =>
cmd<=CMD_SRF_IN;
con_srf:=con_srf+1;
when 1 =>
if wr_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
elsif rd_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
else
con_srf:=con_srf;
end if;
when 1+tXSRD =>
if wr_rqu_s='1' or rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
wr_end<='0';
rd_end<='0';
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=prc;
con_srf:=0;
else
state<=reset;
end if;
when others =>
con_srf:=con_srf+1;
end case;
-------------------PRECHARGE------------------
when prc=>
case con_prc is
when 0 =>
bank<=bank_s;
addr<=addr_row;
con_prc:=con_prc+1;
when 1 =>
cmd<=CMD_PRC;
con_prc:=con_prc+1;
when 2 =>
cmd<=CMD_NOP;
con_prc:=con_prc+1;
when 1+tRP =>
con_prc:=0;
state<=arf;
when others=>
con_prc:=con_prc+1;
end case;
---------------------WRITE--------------------
when wr=>
if dqs_en_s='0' then
case con_write is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='1';
bank<=bank_s;
addr<=addr_row;
con_write_total:=1;
con_write:=con_write+1;
when 2 =>
cmd<=CMD_NOP;
con_write:=con_write+1;
when 2+tRCD =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write:=con_write+1;
when 3+tRCD =>
cmd<=CMD_NOP;
wr_start<='1';
addr_col<=addr_col+BL;
con_write:=con_write+1;
when 3+tRCD+WL-2 =>
dqs_en<='1';
--wr_ready_s<='1';
con_write:=con_write+1;
when 3+tRCD+WL-1 =>
dqs_en_s<='1';
wr_ready_s<='1';
con_write:=0;
when others =>
con_write:=con_write+1;
end case;
else
state<=state;
end if;
if wr_start='1' then
case con_write_trans is
when BLC-1 =>
cmd<=CMD_NOP;
addr_col<=addr_col+BL;
con_write_trans:=0;
con_write_total:=con_write_total+1;
if con_write_total=conv_integer(write_num_s) then
-- dqs_en_s<='0';
-- ram_data_en<='0';
wr_start<='0';
state<=prc;
else
wr_start<=wr_start;
end if;
when 0 =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write_trans:=con_write_trans+1;
when others =>
con_write_trans:=con_write_trans+1;
end case;
else
state<=state;
end if;
---------------------READ---------------------
when rd=>
if rd_ready_s_2='1' then
rd_ready_s_1<='1';
else
rd_ready_s_1<=rd_ready_s_1;
end if;
if dqs_en_s='0' then
case con_read is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='0';
bank<=bank_s;
addr<=addr_row;
con_read:=con_read+1;
when 2 =>
cmd<=CMD_NOP;
con_read:=con_read+1;
when 2+tRCD =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read:=con_read+1;
when 3+tRCD =>
cmd<=CMD_NOP;
rd_start<='1';
addr_col<=addr_col+BL;
con_read:=con_read+1;
when 3+tRCD+RL-2 =>
con_read:=con_read+1;
when 3+tRCD+RL-1 =>
dqs_en_s<='1';
con_read:=0;
when others =>
con_read:=con_read+1;
end case;
else
state<=state;
end if;
if rd_start='1' then
case con_read_trans is
when BLC-1 =>
addr_col<=addr_col+BL;
cmd<=CMD_NOP;
if con_read_total=conv_integer(read_num_s) then
rd_start<='0';
con_read_total:=0;
state<=prc;
else
rd_start<=rd_start;
end if;
con_read_trans:=0;
when 0 =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read_total:=con_read_total+1;
con_read_trans:=con_read_trans+1;
--when 1 =>
--cmd<=CMD_NOP;
--con_read_total:=con_read_total+1;
when others =>
state<=reset;
end case;
else
state<=state;
end if;
---------------------RESET--------------------
when reset=>
con_arf:=0;
con_prc:=0;
con_read:=0;
con_read_total:=0;
con_read_trans:=0;
con_srf:=0;
con_write:=0;
con_write_total:=0;
con_write_trans:=0;
wr_ready_s<='0';
rd_ready_s_1<='0';
rd_start<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
cmd<=CMD_NOP;
case con_reset is
when 20 =>
state<=prc;
con_reset:=0;
when others =>
con_reset:=con_reset+1;
end case;
--------------------OTHERS--------------------
when others=>
state<=reset;
end case;
wr_rqu_s<=wr_rqu;
rd_rqu_s<=rd_rqu;
end if;
end if;
end process;
--------------------dqs/dq-write---------------------
with dqs_en_s select
udqs_out<=
clk_control_p when '1',
'0' when others;
with dqs_en_s select
ldqs_out<=
clk_control_p when '1',
'0' when others;
ram_data_out<=data_other_in;
--------------------dqs/dq-read----------------------
data_other_out<=ram_data_in;
DQS_FLAG:process(clk_data,pll_lock)
begin
if clk_data'event and clk_data='1' and pll_lock='1' then
if state=rd then
if udqs_last='0' and udqs_last_last/='0' then
rd_ready_s_2<='1';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
elsif rd_ready_s_1='0' then
rd_ready_s_2<='0';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
udqs_last<=udqs_in;
udqs_last_last<=udqs_last;
end if;
end process;
end ddr2_con;
| gpl-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/heartbeat.vhd | 1 | 4435 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity heartbeat is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
heartbeat_out : out std_logic := '0';
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0' -- .readdatavalid
);
end entity heartbeat;
architecture rtl of heartbeat is
signal heartbeat_counter : unsigned(31 downto 0) := (others => '0');
signal heartbeat_counter_logic : std_logic_vector(31 downto 0) := (others => '0');
signal heartbeat_divider : unsigned(4 downto 0) := to_unsigned(27,5); --initial division is 2^27 = 0.86Hz
signal heartbeat_divider_16 : std_logic_vector(15 downto 0) := (others => '0');
signal heartbeat_divider_int : integer range 31 downto 0 := 27;
signal heartbeat_force_flag : std_logic := '0';
signal heartbeat_force_value : std_logic := '0';
begin
heartbeat_divider_16 <= std_logic_vector(resize(heartbeat_divider,16));
heartbeat_divider_int <= to_integer(heartbeat_divider);
heartbeat_counter_logic <= std_logic_vector(heartbeat_counter);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"00" =>
avalon_regs_readdata <= heartbeat_divider_16;
when X"04" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(15 downto 0));
when X"06" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(31 downto 16));
when others =>
avalon_regs_readdata <= X"0000";
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"00" =>
heartbeat_divider <= unsigned(avalon_regs_writedata(4 downto 0));
heartbeat_force_value <= avalon_regs_writedata(6);
heartbeat_force_flag <= avalon_regs_writedata(7);
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
--Counter
heartbeat_counter <= heartbeat_counter + 1 when rising_edge(clock);
--Heartbeat selector
process (clock)
begin
if rising_edge(clock) then
if heartbeat_force_flag = '1' then
heartbeat_out <= heartbeat_force_value;
else
case heartbeat_divider_int is
when 21 =>
heartbeat_out <= heartbeat_counter_logic(20); -- 54 Hz
when 22 =>
heartbeat_out <= heartbeat_counter_logic(21); -- 28 Hz
when 23 =>
heartbeat_out <= heartbeat_counter_logic(22); -- 14 Hz
when 24 =>
heartbeat_out <= heartbeat_counter_logic(23); -- 7 Hz
when 25 =>
heartbeat_out <= heartbeat_counter_logic(24); --3.2 Hz
when 26 =>
heartbeat_out <= heartbeat_counter_logic(25); --1.6 Hz
when 27 =>
heartbeat_out <= heartbeat_counter_logic(26); --0.8 Hz
when 28 =>
heartbeat_out <= heartbeat_counter_logic(27);
when 29 =>
heartbeat_out <= heartbeat_counter_logic(28);
when 30 =>
heartbeat_out <= heartbeat_counter_logic(29);
when 31 =>
heartbeat_out <= heartbeat_counter_logic(30);
when others =>
heartbeat_out <= heartbeat_counter_logic(26);
end case;
end if;
end if;
end process;
end architecture rtl; | gpl-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/pwm_gen.vhd | 4 | 4352 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--!needs an input as level counter from the avalon reg to form the pwm it decides the duty cycle
--!needs an period counter number it decides the frequency
--!for dead zone, the level counter should has upper lower limit
--!flow of control: set the duty cycle 1 and 2, set the period of pwm, then
--enable the module by asserting the saw_en signal to high and keep it
entity pwm_gen is
-- generic (
-- G_WIDTH : integer:= 32;
-- G_reset_polarity : std_logic := '1' -- active high reset
-- );
port(
csi_I_clk: in std_logic;
csi_I_rst: in std_logic;
--!interface to Avalon
avs_address: in std_logic_vector(2 downto 0);
avs_write: in std_logic;
avs_I_cs: in std_logic;
avs_I_wr_data: in std_logic_vector(31 downto 0);
coe_O_pwm1: out std_logic;
coe_O_pwm2: out std_logic
-- I_saw_en : in std_logic;
-- I_period: in std_logic_vector(G_WIDTH-1 downto 0);
-- I_duty1: in std_logic_vector(G_WIDTH-1 downto 0);
-- I_duty2: in std_logic_vector(G_WIDTH-1 downto 0)
);
end pwm_gen;
architecture A_rtl of pwm_gen is
signal S_saw_cnt : unsigned(31 downto 0); --!saw wave gen counter
signal S_period : unsigned(31 downto 0) ; --!period of signal
signal S_duty1,S_duty2 : unsigned(31 downto 0) ; --!duty cycle
signal S_phase1,S_phase2: unsigned(31 downto 0);--!phase register
signal S_saw_en1,S_saw_en2 : std_logic ; --! enable signal for generation
begin -- A_rtl
--!triangle waveform gen
process(csi_I_clk,csi_I_rst,S_saw_cnt,S_saw_en1,S_saw_en2)
begin
if rising_edge(csi_I_clk) then
if csi_I_rst='0' then
S_saw_cnt<=(others=>'0');
else
if S_saw_en1='1' or S_saw_en2='1' then
if S_saw_cnt=S_period then
S_saw_cnt<=(others=>'0');
else
S_saw_cnt<=S_saw_cnt+1;
end if;
end if;
end if;
end if;
end process;
--!comparator duty1 and duty2 should not be the same as the deadzone exits
coe_O_pwm1<='1' when (S_saw_cnt>S_phase1 and S_saw_cnt<S_phase1+S_duty1 and S_saw_en1='1') else
'0' ;
coe_O_pwm2<='1' when (S_saw_cnt<S_phase2+S_duty2 and S_saw_cnt>S_phase2 and S_saw_en2='1') else
'0' ;
--!register
-- process(csi_I_clk,csi_I_rst,I_period)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_period<=(others=>'0');
-- else
-- S_period<=I_period;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_duty1)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_duty1<=(others=>'0');
-- else
-- S_duty1<=I_duty1;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_duty2)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_duty2<=(others=>'0');
-- else
-- S_duty2<=I_duty2;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_saw_en)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_saw_en<='0';
-- else
-- S_saw_en<=I_saw_en;
-- end if;
-- end if;
-- end process;
--avalon interface
process(csi_I_clk,csi_I_rst,avs_address,avs_write,avs_I_cs,avs_I_wr_data)
begin
if rising_edge(csi_I_clk) then
if csi_I_rst='0' then
S_saw_en1<='0';
S_saw_en2<='0';
S_period<=(others=>'0');
S_duty1<=(others=>'0');
S_duty2<=(others=>'0');
S_phase1<=(others=>'0');
S_phase2<=(others=>'0');
else
if avs_write='1' and avs_I_cs='1' then
case avs_address is
when "000"=> --enable register
S_saw_en1<=avs_I_wr_data(0);
S_saw_en2<=avs_I_wr_data(1);
when "001"=> --period register
S_period<=unsigned(avs_I_wr_data);
when "010"=> --duty1 register
S_duty1<=unsigned(avs_I_wr_data);
when "011"=> --duty2 register
S_duty2<=unsigned(avs_I_wr_data);
when "100"=> --phase register
S_phase1<=unsigned(avs_I_wr_data);
when "101"=>
S_phase2<=unsigned(avs_I_wr_data);
when others=> null;
end case;
end if;
end if;
end if;
end process;
end A_rtl;
| gpl-2.0 |
dtysky/3D_Displayer_Controller | USB_TEST/COUNTER_TIMEOUT.vhd | 2 | 4580 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: COUNTER_TIMEOUT.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COUNTER_TIMEOUT;
ARCHITECTURE SYN OF counter_timeout IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 12
)
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "12"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd | 15 | 22296 | -------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
use proc_sys_reset_v5_0_9.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_9.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_9.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_9.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_9.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
| gpl-2.0 |
hitomi2500/wasca | fpga_firmware/abus_avalon_sdram_bridge.vhd | 2 | 54999 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
abus_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.data
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_interrupt_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;
--xilinx mode
--component sniff_fifo
-- PORT
-- (
-- clk : IN STD_LOGIC;
-- srst : IN STD_LOGIC;
-- din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- wr_en : IN STD_LOGIC;
-- rd_en : IN STD_LOGIC;
-- dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-- full : OUT STD_LOGIC;
-- empty : OUT STD_LOGIC;
-- data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
-- );
--end component;
signal abus_address_ms : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_data_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_data_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MAPPER_READ : std_logic_vector(63 downto 0) := (others => '1');
signal REG_MAPPER_WRITE : std_logic_vector(63 downto 0) := (others => '1');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal avalon_regs_readdatavalid_p1 : std_logic := '0';
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_in_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(15 downto 0) := (others => '0');
--signal sniffer_data_out_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_prefifo : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_prefifo_full : std_logic := '0';
--signal sniffer_data_write_p1 : std_logic := '0';
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(10 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
signal sniffer_last_active_block : std_logic_vector(15 downto 0) := (others => '1');
signal sniffer_pending_set : std_logic := '0';
signal sniffer_pending_reset : std_logic := '0';
signal sniffer_pending_flag : std_logic := '0';
signal sniffer_pending_block : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_pending_timeout : std_logic := '0';
signal sniffer_pending_timeout_counter : std_logic_vector(31 downto 0) := (others => '0');
signal mapper_write_enable : std_logic := '1';
signal mapper_read_enable : std_logic := '1';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_interrupt_disable_out <= '1'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_data_ms <= abus_data;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_data_buf <= abus_data_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
abus_address_latched_prepatch <= abus_address;
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(24 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--mapper write enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(48);
end if;
end if;
end process;
--mapper read enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_read_enable <= REG_MAPPER_READ(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_read_enable <= REG_MAPPER_READ(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_read_enable <= REG_MAPPER_READ(48);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
when DIR_READ =>
abus_direction_internal <= mapper_read_enable;--'1'; --active
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
elsif avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"F4" =>
REG_MODE <= avalon_regs_writedata;
case (avalon_regs_writedata (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (avalon_regs_writedata (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (avalon_regs_writedata (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
abus_data_in <= abus_data_buf;
--working only if direction is 1
abus_data <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid_p1 <= '0';
sniffer_data_ack <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid_p1 <= '1';
case avalon_regs_address(7 downto 0) is
when X"C0" =>
avalon_regs_readdata <= REG_MAPPER_READ(15 downto 0);
when X"C2" =>
avalon_regs_readdata <= REG_MAPPER_READ(31 downto 16);
when X"C4" =>
avalon_regs_readdata <= REG_MAPPER_READ(47 downto 32);
when X"C6" =>
avalon_regs_readdata <= REG_MAPPER_READ(63 downto 48);
when X"C8" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(15 downto 0);
when X"CA" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(31 downto 16);
when X"CC" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(47 downto 32);
when X"CE" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(63 downto 48);
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out;
sniffer_data_ack <= '1';
--E2 to E6 are reserved
when X"E8" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata(15 downto 12) <= "0000";
avalon_regs_readdata(11) <= sniffer_fifo_full;
avalon_regs_readdata(10 downto 0) <= sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
avalon_regs_readdatavalid <= avalon_regs_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"C0" =>
REG_MAPPER_READ(15 downto 0) <= avalon_regs_writedata;
when X"C2" =>
REG_MAPPER_READ(31 downto 16) <= avalon_regs_writedata;
when X"C4" =>
REG_MAPPER_READ(47 downto 32) <= avalon_regs_writedata;
when X"C6" =>
REG_MAPPER_READ(63 downto 48) <= avalon_regs_writedata;
when X"C8" =>
REG_MAPPER_WRITE(15 downto 0) <= avalon_regs_writedata;
when X"CA" =>
REG_MAPPER_WRITE(31 downto 16) <= avalon_regs_writedata;
when X"CC" =>
REG_MAPPER_WRITE(47 downto 32) <= avalon_regs_writedata;
when X"CE" =>
REG_MAPPER_WRITE(63 downto 48) <= avalon_regs_writedata;
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
--E2 to E6 are reserved
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(23 downto 11);
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);
sdram_dqm(1) <= not avalon_sdram_byteenable(1);
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE and mapper_write_enable = '1' then --if mapper write is not enabled, doing read instead
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_cas_n <= '0';
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_dq <= avalon_sdram_pending_data;
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_readdata_latched <= sdram_dq;
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
--fifo should be written in 2 cases
-- 1) write was done to a different block
-- 2) no write within 10 ms
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_set <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
end if;
end if;
end process;
--if an access passed thru filter, set the request as pending
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_flag <= '1';
sniffer_pending_block <= abus_address_latched(24 downto 9);
elsif sniffer_pending_reset = '1' then
sniffer_pending_flag <= '0';
end if;
end if;
end process;
--if we have a pending request, and it's for a different block, fill prefifo
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_reset <= '0';
if sniffer_pending_flag = '1' and sniffer_pending_block /= sniffer_last_active_block then
sniffer_last_active_block <= sniffer_pending_block;
sniffer_prefifo <= sniffer_pending_block;
sniffer_pending_reset <= '1';
end if;
end if;
end process;
--if we have a pending request, and it's for a different block, and prefifo is full, flush prefifo
--if we don't have eny requests, but the timeout fired, flush prefifo as well
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if sniffer_pending_flag = '1' and sniffer_pending_block /= sniffer_last_active_block then
sniffer_prefifo_full <= '1';
if sniffer_prefifo_full='1' then
sniffer_data_in <= sniffer_prefifo;
sniffer_data_write <= '1';
end if;
elsif sniffer_pending_timeout = '1' then
sniffer_data_write <= '1';
sniffer_data_in <= sniffer_prefifo;
sniffer_prefifo_full <= '0';
end if;
end if;
end process;
--timeout counter. resets when another pending is set
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_timeout_counter <= (others => '0');
elsif sniffer_pending_timeout_counter < std_logic_vector(to_unsigned(134217728,32)) then
sniffer_pending_timeout_counter <= std_logic_vector(unsigned(sniffer_pending_timeout_counter) + 1);
end if;
end if;
end process;
--timeout comparator @ 10ms = 1160000
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_timeout <= '0';
if sniffer_pending_timeout_counter = std_logic_vector(to_unsigned(1160000,32)) then
sniffer_pending_timeout <= '1';
end if;
end if;
end process;
--sniffer_data_in_p1(15 downto 0) <= sniffer_last_active_block when rising_edge(clock);
--sniffer_data_in <= sniffer_data_in_p1 when rising_edge(clock);
--sniffer_data_write <= sniffer_data_write_p1 when rising_edge(clock);
--sniffer_data_out_p1 <= sniffer_data_out when rising_edge(clock);
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
-- --xilinx mode
-- sniff_fifo_inst : sniff_fifo PORT MAP (
-- clk => clock,
-- srst => '0',
-- din => sniffer_data_in,
-- rd_en => sniffer_data_ack,
-- wr_en => sniffer_data_write,
-- empty => sniffer_fifo_empty,
-- full => sniffer_fifo_full,
-- dout => sniffer_data_out,
-- data_count => sniffer_fifo_content_size
-- );
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 |
ktuan89/geany-1.22 | data/filetypes.vhdl | 5 | 2985 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/openfilter-rtl-ea.vhd | 3 | 12569 | -------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditions are checked:
--! * RxDV >163.64µsec HIGH -> invalid
--! * RxDV <0.64µsec LOW -> invalid
--! * RxDV 4x <5.12µsec HIGH -> invalid
--! * RxDV >5.12µsec HIGH -> valid
--! * iRxError HIGH -> invalid
--! If invalid deactivation of port, until RxDv and iRxError > 10.24µsec low
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openfilter is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive path in
iRx : in tRmiiPath;
--! RMII receive path out
oRx : out tRmiiPath;
--! RMII transmit path in
iTx : in tRmiiPath;
--! RMII transmit path out
oTx : out tRmiiPath;
--! RMII receive error
iRxError : in std_logic
);
end entity openfilter;
architecture rtl of openfilter is
--! Filter FSM type
type tFiltState is (
fs_init,
fs_GAP2short, fs_GAPext, fs_GAPok,
fs_FRMnopre, fs_FRMpre2short, fs_FRMpreOk,
fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll
);
signal FiltState : tFiltState;
signal RxDel : tRmiiPathArray(3 downto 0);
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
begin
---------------------------------------------------------------------------
-- INPUT
---------------------------------------------------------------------------
RxDel(0) <= iRx;
BlockRxPort <= cActivated when (FiltState = fs_FRMnopre or
FiltState = fs_BlockAll or
LastFrameNOK = cActivated) else
cInactivated;
---------------------------------------------------------------------------
-- OUTPUT MUX
---------------------------------------------------------------------------
oRx <= cRmiiPathInit when BlockRxPort = cActivated else
RxDel(3) when FrameShift = cActivated else
RxDel(1);
oTx <= iTx;
doFsm : process(iRst, iClk)
variable RstStCnt : std_logic;
begin
if iRst = cActivated then
StCnt <= (others => cInactivated);
FiltState <= fs_init;
FrameShift <= cInactivated;
RxDel(3 downto 1) <= (others => cRmiiPathInit);
LastFrameNOK <= cInactivated;
elsif rising_edge(iClk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := cInactivated;
case FiltState is
---------------------------------------------------------------
-- INIT
---------------------------------------------------------------
when fs_init =>
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
---------------------------------------------------------------
-- GAP 2 SHORT
---------------------------------------------------------------
when fs_GAP2short =>
FrameShift <= cInactivated;
if StCnt(4) = cActivated then
-- 360ns
FiltState <= fs_GAPext;
end if;
if RxDel(0).enable = cActivated then
-- Gap < 360 ns -> too short -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- GAP EXTend
---------------------------------------------------------------
when fs_GAPext =>
if StCnt(5 downto 0) = "101110" then
FiltState <= fs_GAPok;
end if;
if RxDel(0).enable = cActivated then
-- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := cActivated;
FrameShift <= cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- GAP OK
---------------------------------------------------------------
when fs_GAPok =>
if RxDel(0).enable = cActivated then
RstStCnt := cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- FRAME, BUT STILL NO PREAMBLE
---------------------------------------------------------------
when fs_FRMnopre =>
if (StCnt(5) = cActivated or
RxDel(0).data = "11" or RxDel(0).data = "10" or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- no preamble for >=660 ns or preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif RxDel(0).data = "01" then
-- preamble starts -> Check Preamble
FiltState <= fs_FRMpre2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE TOO SHORT
---------------------------------------------------------------
when fs_FRMpre2short =>
if (RxDel(0).data /= "01" or (RxDel(0).enable = cInactivated and
RxDel(1).enable = cInactivated)) then
-- preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif StCnt(3) = cActivated then
-- preamble ok for 180 ns -> Preamble OK
FiltState <= fs_FRMpreOk;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE OK
---------------------------------------------------------------
when fs_FRMpreOk =>
if RxDel(0).data /= "01" then
-- preamble done -> Start Frame
FiltState <= fs_FRMok;
end if;
if ((StCnt(5) = cActivated and StCnt(2) = cActivated) or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- preamble to long for 740 ns -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- preamble is OK
LastFrameNOK <= cInactivated;
---------------------------------------------------------------
-- FRAME OK
---------------------------------------------------------------
when fs_FRMok =>
if StCnt(13) = cActivated then
-- FRAME > 163,842 us -> too long -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated then
-- FRAME [163,842 us] -> OK -> Start GAP
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- BLOCK FILTER
---------------------------------------------------------------
when fs_BlockAll =>
if StCnt(2) = cActivated then
-- Block for 100 nsec
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cActivated then
-- Rxdv != cInactivated -> Reset Wait Period
RstStCnt := cActivated;
end if;
-- block next rx frame (until receive a valid preamble)
LastFrameNOK <= cActivated;
when others =>
FiltState <= fs_init;
end case;
if iRxError = cActivated then
-- iRxError -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- State Counter --
StCnt <= std_logic_vector(unsigned(StCnt) + 1);
if RstStCnt = cActivated then
StCnt <= (others => cInactivated);
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/edgedetectorRtl.vhd | 3 | 4148 | -------------------------------------------------------------------------------
--! @file edgedetectorRtl.vhd
--
--! @brief Edge detector
--
--! @details This is an edge detector circuit providing any, rising and falling
--! edge outputs.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity edgedetector is
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Enable detection
iEnable : in std_logic;
--! Data to be sampled
iData : in std_logic;
--! Rising edge detected (unregistered)
oRising : out std_logic;
--! Falling edge detected (unregistered)
oFalling : out std_logic;
--! Any edge detected (unregistered)
oAny : out std_logic
);
end edgedetector;
architecture rtl of edgedetector is
--! Register to delay input by one clock cycle
signal reg : std_logic;
--! Register next
signal reg_next : std_logic;
--! Second register
signal reg_l : std_logic;
--! Second register next
signal reg_l_next : std_logic;
begin
-- assign input data to register
reg_next <= iData;
--! Detection
comb : process (
iEnable,
reg,
reg_l
)
begin
-- default
oRising <= cInactivated;
oFalling <= cInactivated;
oAny <= cInactivated;
if iEnable = cActivated then
-- rising edge
if reg_l = cInactivated and reg = cActivated then
oRising <= cActivated;
oAny <= cActivated;
end if;
-- falling edge
if reg_l = cActivated and reg = cInactivated then
oFalling <= cActivated;
oAny <= cActivated;
end if;
end if;
end process;
reg_l_next <= reg;
--! Clock process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= cInactivated;
reg_l <= cInactivated;
elsif rising_edge(iClk) then
reg <= reg_next;
reg_l <= reg_l_next;
end if;
end process;
end rtl;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/registerFileRtl.vhd | 3 | 5435 | -------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/memory/src/dpRamSplxNbe-e.vhd | 3 | 3451 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-e.vhd
--
--! @brief Simplex Dual Port Ram without byteenables entity
--
--! @details This is the Simplex DPRAM without byteenables entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplxNbe is
generic (
--! Word width [bit]
gWordWidth : natural := 16;
--! Number of words
gNumberOfWords : natural := 1024;
--! Word width [bit]
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRamSplxNbe;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/altera/memory/src/dpRamOpenmac-rtl-a.vhd | 3 | 3998 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram for openMAC Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--!
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamOpenmac is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8,
read_during_write_mode_mixed_ports => "OLD_DATA"
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamSplxNbe-rtl-a.vhd | 3 | 3991 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 |
SylvainLesne/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/bcd2ledRtl.vhd | 3 | 3310 | -------------------------------------------------------------------------------
--! @file bcd2ledRtl.vhd
--
--! @brief BCD to 7-segement LED
--
--! @details This compontent decodes a binary coded input to 7-segement LED
--! display.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd2led is
port (
--! BCD input
iBcdVal : in std_logic_vector(3 downto 0);
--! LED output (high-active)
oLed : out std_logic_vector(6 downto 0);
--! LED output (low-active)
onLed : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of bcd2led is
--! Array type for conversion lut
type tDecArray is array (natural range <>) of std_logic_vector(6 downto 0);
--! Lut holding the decode values
constant cDecodeLut : tDecArray(0 to 15) := (
-- 0 1 2 3
"0111111", "0000110", "1011011", "1001111",
-- 4 5 6 7
"1100110", "1101101", "1111101", "0000111",
-- 8 9 A B
"1111111", "1101111", "1110111", "1111100",
-- C D E F
"0111001", "1011110", "1111001", "1110001"
);
--! High active decoded
signal led : std_logic_vector(oLed'range);
begin
-- output
oLed <= led;
onLed <= not led;
-- assign lut
led <= cDecodeLut(to_integer(unsigned(iBcdVal)));
end architecture;
| gpl-2.0 |
thasti/arca-fpga | rc_filt/rc_filt.vhd | 1 | 1646 | -- digital rc filter
--
-- data is unsigned samples
-- output is rc-filtered
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rc_filt is
generic (
time_const : positive := 8;
iowidth : positive := 8;
procwidth : positive := 12;
pd_min : std_logic := '0';
pd_max : std_logic := '0'
);
port (
clk : in std_logic;
inclk : in std_logic;
outclk : out std_logic;
rst : in std_logic;
d : in std_logic_vector(iowidth-1 downto 0);
q : out std_logic_vector(iowidth-1 downto 0)
);
end rc_filt;
architecture behav of rc_filt is
signal fil_out : unsigned(procwidth-1 downto 0);
signal padding : std_logic_vector(procwidth-iowidth-1 downto 0);
constant alpha : unsigned(procwidth-1 downto 0) := to_unsigned(integer(real((2**(procwidth-1)-1))/(real(time_const)+1.0)), procwidth);
begin
process
begin
wait until rising_edge(clk);
outclk <= '0';
if rst = '1' then
fil_out <= (others => '0');
else
if inclk = '1' then
-- y[i] := y[i-1] + tc * (x[i] - y[i-1])
fil_out <= fil_out +
resize(shift_right(alpha * unsigned(d & padding) - alpha * fil_out,procwidth),procwidth);
if pd_min = '1' then
if unsigned(d & padding) < fil_out then
fil_out <= unsigned(d & padding);
end if;
end if;
if pd_max = '1' then
if unsigned(d & padding) > fil_out then
fil_out <= unsigned(d & padding);
end if;
end if;
outclk <= '1';
end if;
end if;
end process;
pad_rc : for i in 0 to padding'high generate
padding(i) <= d(0);
end generate;
q <= std_logic_vector(fil_out(procwidth-1 downto procwidth-iowidth));
end behav;
| gpl-2.0 |
MeFoDy/poit-labs | MasterCourses/POVS/lab3/lab3/src/2/RS_latch.vhd | 1 | 1427 | -------------------------------------------------------------------------------
--
-- Title : RS_latch
-- Design : lab3
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : RS_latch.vhd
-- Generated : Fri Dec 12 13:46:57 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {RS_latch} architecture {RS_latch}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RS_latch is
port(
S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC;
nQ : out STD_LOGIC
);
end RS_latch;
--}} End of automatically maintained section
architecture Struct of RS_latch is
component NOR2
port (
a, b: in std_logic;
z: out std_logic
);
end component;
signal t1, t2: std_logic;
begin
U1: nor2 port map (S, t2, t1);
U2: nor2 port map (t1, R, t2);
nQ <= t1;
Q <= t2;
end Struct;
architecture Beh of RS_latch is
signal t1, t2: std_logic;
begin
t2 <= R nor t1;
t1 <= S nor t2;
nQ <= t1;
Q <= t2;
end Beh;
| gpl-2.0 |
thasti/arca-fpga | adsb_recv/adsb_recv.vhd | 1 | 3542 | -- ads-b receiver
--
-- www.bexus-arca.de
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adsb_recv is
generic (
width : positive := 8;
samp_rate : positive := 16
);
port (
clk : in std_logic;
rst : in std_logic;
adcclk : in std_logic;
adc_d : in std_logic_vector(width-1 downto 0);
adsb_tx : out std_logic;
uart_tx : out std_logic;
sof_led : out std_logic;
full_led : out std_logic
);
end adsb_recv;
architecture behav of adsb_recv is
-- matched filter
signal mf_clk : std_logic;
signal mf_q : std_logic_vector(width-1 downto 0);
-- clock recovery
signal rec_clk : std_logic;
-- data slicer output
signal ds_d : std_logic;
signal ds_clk : std_logic;
-- manchester decoder output
signal bit_d : std_logic;
signal bit_clk : std_logic;
signal manchester_err : std_logic;
-- preamble detector
signal preamble_found : std_logic;
-- UART FIFO
signal fifo_d : std_logic_vector(7 downto 0);
signal fifo_we : std_logic;
signal bit_reset : std_logic;
signal fifo_full : std_logic;
signal cnt_trg :std_logic;
signal cnt : std_logic_vector(22 downto 0) := (others => '0');
begin
adsb_gen : entity work.adsb_gen
generic map (clk_div => samp_rate/2)
port map (clk => clk,
rst => rst,
trigger => cnt_trg,
q => adsb_tx,
busy => open);
matched_filt : entity work.matched_filt
generic map (filter_len => samp_rate/2, width => width)
port map (clk => clk,
rst => rst,
inclk => adcclk,
outclk => mf_clk,
d => adc_d,
q => mf_q);
early_late : entity work.early_late
generic map (width => width, sam_per_bit => samp_rate/2)
port map (clk => clk,
rst => bit_reset,
inclk => mf_clk,
d => mf_q,
outclk => rec_clk);
data_slicer : entity work.data_slicer
generic map (width => width, sam_per_bit => samp_rate/2)
port map (clk => clk,
rst => rst,
inclk => mf_clk,
d => mf_q,
outclk => ds_clk,
q => ds_d);
manchester_dec : entity work.manchester_dec
port map (clk => clk,
rst => bit_reset,
inclk => rec_clk,
d => ds_d,
outclk => bit_clk,
q => bit_d,
err => manchester_err);
preamble_det : entity work.preamble_det
generic map (sam_per_bit => samp_rate/2)
port map (clk => clk,
rst => rst,
inclk => ds_clk,
d => ds_d,
valid => preamble_found);
uart_fifo : entity work.uart
generic map (fifo_depth => 512)
port map (clk => clk,
rst => rst,
we => fifo_we,
d => fifo_d,
tx => uart_tx,
full => fifo_full);
frame_ctrl : entity work.frame_ctrl
port map (clk => clk,
rst => rst,
sof => preamble_found,
inclk => bit_clk,
d => bit_d,
fifo_d => fifo_d,
fifo_we => fifo_we);
sof_led_timer : entity work.led_timer
generic map (on_time_exp => 22)
port map (clk => clk,
rst => rst,
input => preamble_found,
led => sof_led);
full_led_timer : entity work.led_timer
generic map (on_time_exp => 22)
port map (clk => clk,
rst => rst,
input => fifo_full,
led => full_led);
bit_reset <= rst or preamble_found;
process
begin
wait until rising_edge(clk);
if rst = '1' then
-- reset all outputs that are not reset by other components
cnt <= (others => '0');
cnt_trg <= '0';
else
-- whatever
cnt <= std_logic_vector(unsigned(cnt) + 1);
if unsigned(cnt) = to_unsigned(0, cnt'length) then
cnt_trg <= '1';
else
cnt_trg <= '0';
end if;
end if; -- reset
end process;
end behav;
| gpl-2.0 |
MeFoDy/poit-labs | 9/POCP/lab2/lab2/src/and3.vhd | 2 | 1058 | -------------------------------------------------------------------------------
--
-- Title : and3
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : and3.vhd
-- Generated : Fri Oct 3 18:46:42 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {and3} architecture {and3}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and3 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Z : out STD_LOGIC
);
end and3;
--}} End of automatically maintained section
architecture and3 of and3 is
begin
Z <= A and B and C;
end and3;
| gpl-2.0 |
thasti/arca-fpga | preamble_det/preamble_det.vhd | 1 | 1087 | -- preamble detector
--
-- data is sliced chips on inclk
-- output is valid-flag
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity preamble_det is
generic (
sam_per_bit : positive := 8
);
port (
clk : in std_logic;
inclk : in std_logic;
rst : in std_logic;
d : in std_logic;
valid : out std_logic
);
end preamble_det;
architecture behav of preamble_det is
constant pattern : std_logic_vector(15 downto 0) := b"1010000101000000";
constant sr_len : positive := sam_per_bit * pattern'length;
signal sr : std_logic_vector(sr_len downto 0) := (others => '0');
begin
process
variable match_result : std_logic;
begin
wait until rising_edge(clk);
valid <= '0';
if rst = '1' then
sr <= (others => '0');
else
if inclk = '1' then
sr(sr_len downto 0) <= sr(sr_len-1 downto 0) & d;
match_result := '0';
for i in 0 to 15 loop
match_result := match_result or (pattern(i) xor sr(i*sam_per_bit));
end loop;
if match_result = '0' then
valid <= '1';
end if;
end if;
end if;
end process;
end behav;
| gpl-2.0 |
daiogo/vhdl-microprocessor | reg16bits/reg16bits.vhd | 1 | 631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg16bits is
port(
clk: in std_logic;
rst: in std_logic;
wr_en: in std_logic;
data_in: in unsigned(15 downto 0);
data_out: out unsigned(15 downto 0)
);
end entity;
architecture a_reg16bits of reg16bits is
signal register_data: unsigned(15 downto 0);
begin
process(clk, rst, wr_en)
begin
if rst = '1' then
register_data <= "0000000000000000";
elsif wr_en = '1' then
if rising_edge(clk) then
register_data <= data_in;
end if;
end if;
end process;
data_out <= register_data;
end architecture; | gpl-2.0 |
daiogo/vhdl-microprocessor | alu/alu.vhd | 1 | 2096 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port(
operand0: in unsigned(15 downto 0);
operand1: in unsigned(15 downto 0);
operation: in unsigned(3 downto 0);
alu_out: out unsigned(15 downto 0);
c_flag: out std_logic; --carry flag
z_flag: out std_logic; --zero flag
n_flag: out std_logic; --negative flag
lt_flag: out std_logic --overflow flag
);
end entity;
architecture a_alu of alu is
component mux4x1 is
port(
in0: in unsigned(15 downto 0);
in1: in unsigned(15 downto 0);
in2: in unsigned(15 downto 0);
in3: in unsigned(15 downto 0);
sel: in unsigned(3 downto 0);
out0: out unsigned(15 downto 0)
);
end component;
component arithmetic_circuit is
port(
a: in unsigned(15 downto 0);
b: in unsigned(15 downto 0);
sum: out unsigned(15 downto 0);
sub: out unsigned(15 downto 0);
slt: out unsigned(15 downto 0);
sneg: out unsigned(15 downto 0)
);
end component;
signal sum_sig, sub_sig, slt_sig, sneg_sig: unsigned(15 downto 0);
signal A_17bits_sig, B_17bits_sig,sum_17bits_sig: unsigned(16 downto 0);
signal alu_out_sig: unsigned(15 downto 0);
begin
A_17bits_sig <= "0"&operand0 when operand0(15)='0' else
"1"&operand0 when operand0(15)='1';
B_17bits_sig <= "0"&operand1 when operand1(15)='0' else
"1"&operand1 when operand1(15)='1';
sum_17bits_sig <= A_17bits_sig + B_17bits_sig;
c_flag <= sum_17bits_sig(16) when operation="0001" else
'1' when operation="0010" and operand1 <= operand0 else
'0';
z_flag <= '1' when alu_out_sig="0000000000000000" else '0';
n_flag <= '1' when alu_out_sig(15)='1' else '0';
lt_flag <= '1' when slt_sig="0000000000000001" else '0';
alu_out <= alu_out_sig;
alu_mux: mux4x1 port map(in0=>sum_sig,in1=>sub_sig,in2=>slt_sig,in3=>sneg_sig,sel=>operation,out0=>alu_out_sig);
alu_arithmetic_circuit: arithmetic_circuit port map(a=>operand0,b=>operand1,sum=>sum_sig,sub=>sub_sig,slt=>slt_sig,sneg=>sneg_sig);
end architecture;
| gpl-2.0 |
MeFoDy/poit-labs | MasterCourses/POVS/lab3/lab3/src/NOR2.vhd | 3 | 180 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is
port (
a, b: in std_logic;
z : out std_logic
);
end NOR2;
architecture Arch of NOR2 is
begin
Z <= a nor b;
end Arch; | gpl-2.0 |
MeFoDy/poit-labs | MasterCourses/POVS/lab3/lab3/src/TestBench/bistableelement_TB.vhd | 1 | 1011 | library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity bistableelement_tb is
end bistableelement_tb;
architecture TB_ARCHITECTURE of bistableelement_tb is
-- Component declaration of the tested unit
component bistableelement
port(
Q : out STD_LOGIC;
nQ : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
-- Observed signals - signals mapped to the output ports of tested entity
signal Q : STD_LOGIC;
signal nQ : STD_LOGIC;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : bistableelement
port map (
Q => Q,
nQ => nQ
);
-- Add your stimulus here ...
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_bistableelement of bistableelement_tb is
for TB_ARCHITECTURE
for UUT : bistableelement
use entity work.bistableelement(bistableelement);
end for;
end for;
end TESTBENCH_FOR_bistableelement;
| gpl-2.0 |
MeFoDy/poit-labs | 9/POCP/Lab03/Lab03/src/Testbenches/D_Latch_Test.vhd | 1 | 2169 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity D_Latch_Test is
end D_Latch_Test;
architecture Beh of D_Latch_Test is
component D_Latch
port(
D: in std_logic;
Q, nQ: out std_logic
);
end component;
signal stimuli: std_logic_vector(0 downto 0) := (others => '0');
signal response_struct, response_struct_q, response_beh, response_beh_q: std_logic;
signal d_latch_q, d_latch_q1, d_latch_beh_q, d_latch_beh_q1: std_logic;
signal sampled_response_struct, sampled_response_struct_q, sampled_response_beh, sampled_response_beh_q: std_logic;
signal error: std_logic;
constant min_time_between_events: time := 10 ns;
constant sampling_period: time := min_time_between_events / 2;
begin
stimuli_generation: process
variable buf : LINE;
begin
while(stimuli /= (stimuli'range => '1')) loop
wait for min_time_between_events;
stimuli <= stimuli + 1;
end loop;
write(buf, "The operation has been completed successfully.");
writeline(output, buf);
wait;
end process;
D_Latch_Struct: entity D_Latch(Struct) port map(
D => stimuli (0),
Q => response_struct,
nQ => response_struct_q
);
D_Latch_Beh: entity D_Latch(Beh) port map(
D => stimuli (0),
Q => response_beh,
nQ => response_beh_q
);
d_latch_q <= response_struct;
d_latch_beh_q <= response_beh;
d_latch_q1 <= response_struct_q;
d_latch_beh_q1 <= response_beh_q;
sampled_response_struct <= response_struct after sampling_period;
sampled_response_beh <= response_beh after sampling_period;
sampled_response_struct_q <= response_struct_q after sampling_period;
sampled_response_beh_q <= response_beh_q after sampling_period;
error <= (sampled_response_struct xor sampled_response_beh) and (sampled_response_struct_q xor sampled_response_beh_q);
assert error /= '1' report "The device doesn't work as expected." severity failure;
end Beh;
| gpl-2.0 |
daiogo/vhdl-microprocessor | ram/ram.vhd | 1 | 638 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
port(
clk: in std_logic;
address: in unsigned(15 downto 0);
wr_en: in std_logic;
data_in: in unsigned(15 downto 0);
data_out: out unsigned(15 downto 0)
);
end entity;
architecture a_ram of ram is
type mem is array (0 to 127) of unsigned(15 downto 0);
signal ram_content : mem;
begin
process(clk,wr_en)
begin
if rising_edge(clk) then
if wr_en='1' then
ram_content(to_integer(address)) <= data_in;
end if;
end if;
end process;
data_out <= ram_content(to_integer(address));
end architecture; | gpl-2.0 |
andygikling/BBot | Source Code/BBotFPGA/BBot HDL Source Code/OpenCores SPI Interface/rtl/spi_master_slave/spi_loopback_test.vhd | 4 | 13776 | --------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
| gpl-2.0 |
guillaumeWBres/zynq7-sdr | src/xps-edk/iq_ram_top_v1_00_a/hdl/vhdl/dual_port_ram.vhd | 1 | 1449 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dual_port_ram is
generic (
DATA : integer := 72;
ADDR : integer := 10
);
port (
clk_a : in std_logic;
clk_b : in std_logic;
--reset : in std_logic;
-- state machine interface
we_a : in std_logic;
addr_a: in std_logic_vector(ADDR-1 downto 0);
din_a : in std_logic_vector(DATA-1 downto 0);
dout_a : out std_logic_vector(DATA-1 downto 0);
we_b : in std_logic;
addr_b: in std_logic_vector(ADDR-1 downto 0);
din_b : in std_logic_vector(DATA-1 downto 0);
dout_b: out std_logic_vector(DATA-1 downto 0)
);
end entity;
architecture rtl of dual_port_ram is
-- Shared memory
type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(clk_a)
begin
if(clk_a'event and clk_a='1') then
if(we_a='1') then
mem(to_integer(unsigned(addr_a))) := din_a;
end if;
dout_a <= mem(to_integer(unsigned(addr_a)));
end if;
end process;
-- Port B
process(clk_b)
begin
if(clk_b'event and clk_b='1') then
if(we_b='1') then
mem(to_integer(unsigned(addr_b))) := din_b;
end if;
dout_b <= mem(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture rtl;
--end architecture ram_hard;
| gpl-2.0 |
andygikling/BBot | Source Code/BBotFPGA/BBot HDL Source Code/OpenCores SPI Interface/syn/spi_master_atlys_top.vhd | 1 | 31803 | ----------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 01:21:32 06/30/2011
-- Design Name:
-- Module Name: spi_master_atlys_top
-- Project Name: spi_master_slave
-- Target Devices: Spartan-6 LX45
-- Tool versions: ISE 13.1
-- Description:
-- This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
--
-- See the "spi_master_atlys.ucf" file for pin assignments.
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
-- digital pod port.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board pclk_i to clock all registers.
-- this change made the design go up to 288MHz, after synthesis.
-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
-- external monitoring pins to the VHDCI ports.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
--
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity spi_master_atlys_top is
Generic (
N : positive := 8; -- 8bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3; -- prefetch lookahead cycles
CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz)
DEBOUNCE_TIME : time := 2 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
Port (
sclk_i : in std_logic := 'X'; -- board clock input 100MHz
pclk_i : in std_logic := 'X'; -- board clock input 100MHz
--- SPI interface ---
spi_ssel_o : out std_logic; -- spi port SSEL
spi_sck_o : out std_logic; -- spi port SCK
spi_mosi_o : out std_logic; -- spi port MOSI
spi_miso_o : out std_logic; -- spi port MISO
--- input slide switches ---
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
--- input buttons ---
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
--- debug outputs ---
s_do_o : out std_logic_vector (7 downto 0);
m_do_o : out std_logic_vector (7 downto 0);
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
);
end spi_master_atlys_top;
architecture rtl of spi_master_atlys_top is
--=============================================================================================
-- Constants
--=============================================================================================
-- clock divider count values from pclk_i (100MHz board clock)
-- these constants shall not be zero
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
-- button definitions
constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
constant btUP : integer := 1;
constant btLEFT : integer := 2;
constant btDOWN : integer := 3;
constant btRIGHT : integer := 4;
constant btCENTER : integer := 5;
--=============================================================================================
-- Type definitions
--=============================================================================================
type fsm_master_write_state_type is
(st_reset, st_wait_spi_idle, st_wait_new_switch, st_send_spi_data_sw, st_wait_spi_ack_sw,
st_send_spi_data_1, st_wait_spi_ack_1, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3);
type fsm_slave_write_state_type is
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, st_wait_spi_do_valid_1,
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end);
type fsm_slave_read_state_type is
(st_reset, st_wait_spi_do_valid_1, st_wait_spi_n_do_valid_1, st_wait_spi_do_valid_2,
st_wait_spi_n_do_valid_2, st_wait_spi_do_valid_3, st_wait_spi_n_do_valid_3);
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
signal m_wr_st_reg : fsm_master_write_state_type := st_reset;
signal m_wr_st_next : fsm_master_write_state_type := st_reset;
signal s_wr_st_reg : fsm_slave_write_state_type := st_reset;
signal s_wr_st_next : fsm_slave_write_state_type := st_reset;
signal s_rd_st_reg : fsm_slave_read_state_type := st_reset;
signal s_rd_st_next : fsm_slave_read_state_type := st_reset;
--=============================================================================================
-- Signals for internal operation
--=============================================================================================
--- clock enable signals ---
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
signal new_switch : std_logic := '0'; -- detector for new switch data
--- pushbutton debouncer signals ---
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
signal new_button : std_logic := '0'; -- detector for new button data
--- spi port signals ---
-- spi bus wires
signal spi_ssel : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
-- spi master port control signals
signal spi_rst_reg : std_logic := '1';
signal spi_rst_next : std_logic := '1';
signal spi_ssel_reg : std_logic;
signal spi_wren_reg_m : std_logic := '0';
signal spi_wren_next_m : std_logic := '0';
-- spi master port flow control flags
signal spi_di_req_m : std_logic;
signal spi_do_valid_m : std_logic;
-- spi master port parallel data bus
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_m : std_logic_vector (N-1 downto 0);
signal spi_wr_ack_m : std_logic;
-- spi slave port control signals
signal spi_wren_reg_s : std_logic := '1';
signal spi_wren_next_s : std_logic := '1';
-- spi slave port flow control flags
signal spi_di_req_s : std_logic;
signal spi_do_valid_s : std_logic;
-- spi slave port parallel data bus
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_s : std_logic_vector (N-1 downto 0);
signal spi_wr_ack_s : std_logic;
signal spi_rx_bit_s : std_logic;
-- spi debug data --
signal spi_state_m : std_logic_vector (3 downto 0);
signal spi_state_s : std_logic_vector (3 downto 0);
-- slave data output regs --
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_next : std_logic_vector (N-1 downto 0) := (others => '0');
-- other signals
signal clear : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0);
signal leds_next : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
begin
--=============================================================================================
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi master port: data and control signals driven by the master fsm
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => sclk_i, -- system clock is used for serial and parallel ports
pclk_i => pclk_i,
rst_i => spi_rst_reg,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso, -- driven by the spi slave
di_req_o => spi_di_req_m,
di_i => spi_di_reg_m,
wren_i => spi_wren_reg_m,
wr_ack_o => spi_wr_ack_m,
do_valid_o => spi_do_valid_m,
do_o => spi_do_m,
------------ debug pins ------------
state_dbg_o => spi_state_m -- debug: internal state register
);
-- spi slave port: data and control signals driven by the slave fsm
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => pclk_i,
spi_ssel_i => spi_ssel, -- driven by the spi master
spi_sck_i => spi_sck, -- driven by the spi master
spi_mosi_i => spi_mosi, -- driven by the spi master
spi_miso_o => spi_miso,
di_req_o => spi_di_req_s,
di_i => spi_di_reg_s,
wren_i => spi_wren_reg_s,
wr_ack_o => spi_wr_ack_s,
do_valid_o => spi_do_valid_s,
do_o => spi_do_s,
------------ debug pins ------------
state_dbg_o => spi_state_s -- debug: internal state register
);
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
port map(
clk_i => pclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data -- registered stable output data
);
-- debounce for the input pushbuttons, with new data strobe output
Inst_btn_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
port map(
clk_i => pclk_i, -- system clock
data_i => btn_i, -- noisy input data
data_o => btn_data -- registered stable output data
);
--=============================================================================================
-- CONSTANTS CONSTRAINTS CHECKING
--=============================================================================================
-- clock dividers shall not be zero
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
severity FAILURE;
-- minimum prefetch lookahead check
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
severity FAILURE;
-- maximum prefetch lookahead check
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- All registers are clocked directly from the 100MHz system clock.
-- The clock generation block derives 2 clock enable signals, divided down from the 100MHz input
-- clock.
-- input sample clock enable,
-- fsm clock enable,
-----------------------------------------------------------------------------------------------
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
begin
if pclk_i'event and pclk_i = '1' then
if clk_cnt = SAMP_CE_DIV-1 then
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
clk_cnt := 0;
else
samp_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process samp_ce_gen_proc;
-- generate the fsm clock enable from the 100MHz board input clock
fsm_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
begin
if pclk_i'event and pclk_i = '1' then
if clk_cnt = FSM_CE_DIV-1 then
fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
clk_cnt := 0;
else
fsm_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process fsm_ce_gen_proc;
--=============================================================================================
-- INPUTS LOGIC
--=============================================================================================
-- registered inputs
samp_inputs_proc: process (pclk_i) is
begin
if pclk_i'event and pclk_i = '1' then
if samp_ce = '1' then
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= leds_next; -- update LEDs with spi_slave received data
end if;
end if;
end process samp_inputs_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the system clock
fsm_reg_proc : process (pclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if pclk_i'event and pclk_i = '1' then
if clear = '1' then -- sync reset
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
else
if fsm_ce = '1' then
m_wr_st_reg <= m_wr_st_next; -- master write state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge and cleared on ssel = '1'
if pclk_i'event and pclk_i = '1' then
if spi_ssel = '1' then -- sync reset
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
s_rd_st_reg <= st_reset;
else
if fsm_ce = '1' then
s_wr_st_reg <= s_wr_st_next; -- slave write state register update
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if pclk_i'event and pclk_i = '1' then
if fsm_ce = '1' then
--------- master write fsm signals -----------
spi_wren_reg_m <= spi_wren_next_m;
spi_di_reg_m <= spi_di_next_m;
spi_rst_reg <= spi_rst_next;
spi_ssel_reg <= spi_ssel;
sw_reg <= sw_next;
btn_reg <= btn_next;
--------- slave write fsm signals -----------
spi_wren_reg_s <= spi_wren_next_s;
spi_di_reg_s <= spi_di_next_s;
--------- slave read fsm signals -----------
s_do_1_reg <= s_do_1_next;
s_do_2_reg <= s_do_2_next;
s_do_3_reg <= s_do_3_next;
end if;
end if;
end process fsm_reg_proc;
--=============================================================================================
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
--=============================================================================================
-- edge detector for new switch data
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for change edge
-- edge detector for new button data
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for change edge
-- master port write fsmd logic
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
new_button, clear) is
begin
spi_rst_next <= spi_rst_reg;
spi_di_next_m <= spi_di_reg_m;
spi_wren_next_m <= spi_wren_reg_m;
sw_next <= sw_reg;
btn_next <= btn_reg;
m_wr_st_next <= m_wr_st_reg;
case m_wr_st_reg is
when st_reset =>
spi_rst_next <= '1'; -- place spi interface on reset
spi_di_next_m <= (others => '0'); -- clear spi data port
spi_wren_next_m <= '0'; -- deassert write enable
m_wr_st_next <= st_wait_spi_idle;
when st_wait_spi_idle =>
spi_wren_next_m <= '0'; -- remove write strobe on next clock
if spi_ssel_reg = '1' then
spi_rst_next <= '0'; -- remove reset when interface is idle
m_wr_st_next <= st_wait_new_switch;
end if;
when st_wait_new_switch =>
if new_switch = '1' then -- wait for new stable switch data
sw_next <= sw_data; -- load new switch data (end the mismatch condition)
m_wr_st_next <= st_send_spi_data_sw;
elsif new_button = '1' then
btn_next <= btn_data; -- load new button data (end the mismatch condition)
if clear = '0' then
if btn_data(btDOWN) = '1' then
m_wr_st_next <= st_send_spi_data_sw;
elsif btn_data(btLEFT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btCENTER) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btRIGHT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
end if;
end if;
end if;
when st_send_spi_data_sw =>
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_sw;
when st_wait_spi_ack_sw => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_send_spi_data_1 =>
spi_di_next_m <= X"A1"; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_1;
when st_wait_spi_ack_1 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A2";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A3";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_3;
end if;
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_idle; -- wait transmission end
end if;
when others =>
m_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_m_wr_combi_proc;
-- slave port write fsmd logic
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s,
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
begin
spi_wren_next_s <= spi_wren_reg_s;
spi_di_next_s <= spi_di_reg_s;
s_wr_st_next <= s_wr_st_reg;
case s_wr_st_reg is
when st_reset =>
spi_di_next_s <= X"51"; -- write first data word
spi_wren_next_s <= '1'; -- set write enable
s_wr_st_next <= st_wait_spi_start;
when st_wait_spi_start =>
if spi_ssel_reg = '0' then -- wait for slave select
spi_wren_next_s <= '0'; -- remove write enable
s_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_s = '1' then
-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss)
-- spi_wren_next_s <= '1';
-- s_wr_st_next <= st_wait_spi_ack_2;
s_wr_st_next <= st_wait_spi_do_valid_1;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D3";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_3;
end if;
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_end; -- wait transmission end
end if;
when st_wait_spi_end => -- wait interface to be deselected
if spi_ssel_reg = '1' then
s_wr_st_next <= st_reset; -- wait transmission start
end if;
when others =>
s_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_wr_combi_proc;
-- slave port read fsmd logic
fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
s_do_1_next <= s_do_1_reg;
s_do_2_next <= s_do_2_reg;
s_do_3_next <= s_do_3_reg;
s_rd_st_next <= s_rd_st_reg;
case s_rd_st_reg is
when st_reset =>
s_rd_st_next <= st_wait_spi_do_valid_1;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_1_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_1;
end if;
when st_wait_spi_n_do_valid_1 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_2;
end if;
when st_wait_spi_do_valid_2 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_2_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_2;
end if;
when st_wait_spi_n_do_valid_2 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_3;
end if;
when st_wait_spi_do_valid_3 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_3_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_3;
end if;
when st_wait_spi_n_do_valid_3 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_reset;
end if;
when others =>
s_rd_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_rd_combi_proc;
leds_combi_proc: process (btn_data, leds_reg, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
leds_next <= leds_reg;
if btn_data(btRIGHT) = '1' then
leds_next <= s_do_3_reg;
elsif btn_data(btCENTER) = '1' then
leds_next <= s_do_2_reg;
elsif btn_data(btLEFT) = '1' then
leds_next <= s_do_1_reg;
elsif btn_data(btDOWN) = '1' then
leds_next <= s_do_1_reg;
end if;
end process leds_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- connect the spi output wires
spi_ssel_o_proc: spi_ssel_o <= spi_ssel;
spi_sck_o_proc: spi_sck_o <= spi_sck;
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
spi_miso_o_proc: spi_miso_o <= spi_miso;
-- connect leds_reg signal to LED outputs
led_o_proc: led_o <= leds_reg;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- connect the debug vector outputs
dbg_o_proc: dbg_o <= dbg;
-- connect debug port pins to spi ports instances interface signals
-- master signals mapped on dbg
dbg(11) <= spi_wren_reg_m;
dbg(10) <= spi_wr_ack_m;
dbg(9) <= spi_di_req_m;
dbg(8) <= spi_do_valid_m;
-- slave signals mapped on dbg
dbg(7) <= spi_wren_reg_s;
dbg(6) <= spi_wr_ack_s;
dbg(5) <= spi_di_req_s;
dbg(4) <= spi_do_valid_s;
dbg(3 downto 0) <= spi_state_s;
-- specific ports to test on testbench
s_do_o <= spi_do_s;
m_do_o <= spi_do_m;
m_state_o <= spi_state_m; -- master spi fsm state
s_state_o <= spi_state_s; -- slave spi fsm state
end rtl;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 9/Parte III/Ram2_Demo.vhd | 2 | 970 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram2_Demo is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(17 downto 0);
KEY : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(7 downto 0));
end Ram2_Demo;
architecture Structural of Ram2_Demo is
signal clk : std_logic;
signal s_count : std_logic_vector(3 downto 0);
begin
ram:entity work.Ram_2Port_16_8(Behavioral)
port map(clk => clk,
writeEnable => KEY(0),
writeAddress=> SW(17 downto 14),
writeData => SW(7 downto 0),
readAddress => s_count,
readData => LEDG(7 downto 0));
counter:entity work.CounterUpDownN(Behavioral)
generic map(N => 4)
port map(clk => clk,
updown=> '1',
reset => '0',
count => s_count);
freq_div:entity work.FreqDivider(Behavioral)
generic map(K => 50000000)
port map(clkIn => CLOCK_50,
clkOut=> clk);
end Structural; | gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 4/Parte III/Counter_Demo.vhd | 1 | 1259 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter_Demo is
port( KEY : in std_logic_vector(3 downto 3);
SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(3 downto 0);
HEX7 : out std_logic_vector(7 downto 0));
end Counter_Demo;
architecture Structural of Counter_Demo is
signal s_count : std_logic_vector(3 downto 0);
begin
-- CounterUpDown: entity work.CounterUpDown4(Behavioral)
-- port map(clk => KEY(3),
-- updown => SW(0),
-- reset => SW(1),
-- count => s_count);
--
--LEDR(3 downto 0) <= s_count;
--
-- bin7seg_core : entity work.Bin7SegDecoder(Behavioral)
-- port map(enable => not SW(1),
-- binInput => s_count,
-- decOut_n => HEX7(6 downto 0));
counterloadupdown4: entity work.CounterLoadupdown4(Behavioral)
port map(clk => KEY(3),
reset => SW(7),
enable => SW(6),
load => SW(5),
updown => SW(4),
dataIn => SW(3 downto 0),
count => s_count);
LEDR(3 downto 0) <= s_count;
bin7seg_core : entity work.Bin7SegDecoder(Behavioral)
port map(enable => not SW(6),
binInput => s_count,
decOut_n => HEX7(6 downto 0));
end Structural; | gpl-2.0 |
vinodpa/openPowerlink-FPGA | Examples/ipcore/common/lib/src/clkXingRtl.vhd | 3 | 6586 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
signal slowCs : std_logic_vector(gCsNum-1 downto 0);
signal anyCs : std_logic;
signal slowRnw : std_logic;
signal wr, wr_s, wr_rising : std_logic;
signal rd, rd_s, rd_rising : std_logic;
signal readRegister : std_logic_vector(gDataWidth-1 downto 0);
signal fastWrAck, fastRdAck, fastAnyAck, slowAnyAck : std_logic;
begin
-- WELCOME TO SLOW CLOCK DOMAIN --
genThoseCs : for i in slowCs'range generate
begin
theSyncCs : entity work.sync
port map (
rst => iArst,
clk => iSlowClk,
din => iFastCs(i),
dout => slowCs(i)
);
end generate;
anyCs <= OR_REDUCE(slowCs);
wr_s <= anyCs and not(slowRnw) and not slowAnyAck;
rd_s <= anyCs and slowRnw and not slowAnyAck;
process(iArst, iSlowClk)
begin
if iArst = '1' then
readRegister <= (others => '0');
wr <= '0';
rd <= '0';
elsif rising_edge(iSlowClk) then
if rd = '1' and iSlowRdAck = '1' then
readRegister <= iSlowReaddata;
end if;
if iSlowWrAck = '1' then
wr <= '0';
elsif wr_rising = '1' then
wr <= '1';
end if;
if iSlowRdAck = '1' then
rd <= '0';
elsif rd_rising = '1' then
rd <= '1';
end if;
end if;
end process;
oSlowCs <= slowCs when wr = '1' or rd = '1' else (others => '0');
oSlowRNW <= rd;
theWriteEdge : entity work.edgeDet
port map (
rst => iArst,
clk => iSlowClk,
din => wr_s,
any => open,
rising => wr_rising,
falling => open
);
theReadEdge : entity work.edgeDet
port map (
rst => iArst,
clk => iSlowClk,
din => rd_s,
any => open,
rising => rd_rising,
falling => open
);
theSyncRnw : entity work.sync
port map (
rst => iArst,
clk => iSlowClk,
din => iFastRNW,
dout => slowRnw
);
theSyncAnyAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iSlowClk,
rstSrc => iArst,
clkSrc => iFastClk,
dataSrc => fastAnyAck,
dataDst => slowAnyAck
);
-- WELCOME TO FAST CLOCK DOMAIN --
process(iArst, iFastClk)
begin
if iArst = '1' then
fastAnyAck <= '0';
elsif rising_edge(iFastClk) then
fastAnyAck <= fastWrAck or fastRdAck;
end if;
end process;
theSyncWrAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iFastClk,
rstSrc => iArst,
clkSrc => iSlowClk,
dataSrc => iSlowWrAck,
dataDst => fastWrAck
);
oFastWrAck <= fastWrAck;
theSyncRdAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iFastClk,
rstSrc => iArst,
clkSrc => iSlowClk,
dataSrc => iSlowRdAck,
dataDst => fastRdAck
);
oFastRdAck <= fastRdAck;
genThoseRdq : for i in readRegister'range generate
begin
theSyncRdq : entity work.sync
port map (
rst => iArst,
clk => iFastClk,
din => readRegister(i),
dout => oFastReaddata(i)
);
end generate;
end architecture;
| gpl-2.0 |
ee-lco/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/voltage_source_arc.vhdl | 15 | 543 | ARCHITECTURE sinusodial OF voltage_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
v == (amplitude * sin(k * MATH_2_PI * now)) + offset;
END architecture sinusodial;
ARCHITECTURE pulse OF voltage_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
SIGNAL source_sig: real := 0.0;
BEGIN
p:PROCESS
BEGIN
source_sig <= (amplitude/2.0) + offset;
WAIT FOR width;
source_sig <= - (amplitude/2.0) + offset;
WAIT FOR period - width;
END process p;
-- BREAK v => 0.0;
v == source_sig;
END architecture pulse;
| gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Micro-Projeto/Fase 3/blink.vhd | 1 | 1317 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity blink is
port( binIn : in std_logic_vector(6 downto 0);
binOut: out std_logic_vector(6 downto 0);
clk : in std_logic;
reset : in std_logic;
outLed: out std_logic);
end blink;
architecture Behavioral of blink is
signal last_binIn : std_logic_vector(6 downto 0);
signal counter : natural;
begin
process(clk, reset)
begin
if(reset='1') then
counter <= 0;
last_binIn <= "0000000";
elsif(rising_edge(clk)) then
outLed <= '1';
if(last_binIn= "1100011" and not (binIn="1100011"))then
outLed <= '0';
if(counter=8 or counter=10 or counter=12) then
binOut <=(others => '1');
counter <= counter+1;
elsif(counter=7 or counter=9 or counter=11 or counter=13) then
binOut <= "1111110";
counter <= counter+1;
else
binOut <=(others => '1');
counter <= 0;
end if;
else
if(not(last_binIn = binIn)) then
last_binIn <= binIn;
counter <=0;
end if;
if(counter=1 or counter=3 or counter=5) then
binOut <=(others => '1');
counter <= counter+1;
elsif(counter=0 or counter=2 or counter=4 or counter=6) then
binOut <= binIn;
counter <= counter+1;
else
binOut <=(others => '1');
end if;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 |
diogodanielsoaresferreira/VHDLExercises | Aula 1/EqCmpDemo.vhd | 1 | 378 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity EqCmpDemo is
port(SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(0 downto 0));
end EqCmpDemo;
architecture Shell of EqCmpDemo is
begin
system_core : entity work.EqCmp4(Behavioral)
port map(input0 => SW(3 downto 0),
input1 => SW(7 downto 4),
cmpout =>LEDR(0));
end Shell; | gpl-2.0 |
spoorcc/realtimestagram | src/lomo_tb.vhd | 2 | 6699 | -- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity lomo_tb is
generic (
input_file: string := "tst/input/amersfoort.pnm"; --! Input file of test
output_file: string := "tst/output/lomo_output.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of lomo_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component lomo is
generic (
wordsize: integer := wordsize; --! input image wordsize in bits
image_width: integer := image_width; --! width of input image
image_height: integer := image_height --! height of input image
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
--! x-coordinate of input pixel
h_count: in std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0);
--! y-coordinate of input pixel
v_count: in std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0);
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! the input pixel
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: lomo
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
pixel_red_o => red_pixel_to_file,
pixel_green_o => green_pixel_to_file,
pixel_blue_o => blue_pixel_to_file
);
end architecture;
| gpl-2.0 |
ncareol/nidas | src/firmware/analog/a2dstatio.vhd | 1 | 12561 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : a2dstatio.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:29
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w a2dstatio.sch a2dstatio.vhf
--Design Name: a2dstatio
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FTCE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end FTCE_MXILINX_a2dstatio;
architecture BEHAVIORAL of FTCE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
signal TQ : std_logic;
signal Q_DUMMY : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q <= Q_DUMMY;
I_36_32 : XOR2
port map (I0=>T,
I1=>Q_DUMMY,
O=>TQ);
I_36_35 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>TQ,
Q=>Q_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity CB4CE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end CB4CE_MXILINX_a2dstatio;
architecture BEHAVIORAL of CB4CE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal T2 : std_logic;
signal T3 : std_logic;
signal XLXN_1 : std_logic;
signal Q0_DUMMY : std_logic;
signal Q1_DUMMY : std_logic;
signal Q2_DUMMY : std_logic;
signal Q3_DUMMY : std_logic;
signal TC_DUMMY : std_logic;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component FTCE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of U0 : label is "U0_0";
attribute HU_SET of U1 : label is "U1_1";
attribute HU_SET of U2 : label is "U2_2";
attribute HU_SET of U3 : label is "U3_3";
begin
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
Q3 <= Q3_DUMMY;
TC <= TC_DUMMY;
I_36_31 : AND4
port map (I0=>Q3_DUMMY,
I1=>Q2_DUMMY,
I2=>Q1_DUMMY,
I3=>Q0_DUMMY,
O=>TC_DUMMY);
I_36_32 : AND3
port map (I0=>Q2_DUMMY,
I1=>Q1_DUMMY,
I2=>Q0_DUMMY,
O=>T3);
I_36_33 : AND2
port map (I0=>Q1_DUMMY,
I1=>Q0_DUMMY,
O=>T2);
I_36_58 : VCC
port map (P=>XLXN_1);
I_36_67 : AND2
port map (I0=>CE,
I1=>TC_DUMMY,
O=>CEO);
U0 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>XLXN_1,
Q=>Q0_DUMMY);
U1 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>Q0_DUMMY,
Q=>Q1_DUMMY);
U2 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T2,
Q=>Q2_DUMMY);
U3 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T3,
Q=>Q3_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE16_MXILINX_a2dstatio is
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end BUFE16_MXILINX_a2dstatio;
architecture BEHAVIORAL of BUFE16_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_30 : BUFE
port map (E=>E,
I=>I(8),
O=>O(8));
I_36_31 : BUFE
port map (E=>E,
I=>I(9),
O=>O(9));
I_36_32 : BUFE
port map (E=>E,
I=>I(10),
O=>O(10));
I_36_33 : BUFE
port map (E=>E,
I=>I(11),
O=>O(11));
I_36_34 : BUFE
port map (E=>E,
I=>I(15),
O=>O(15));
I_36_35 : BUFE
port map (E=>E,
I=>I(14),
O=>O(14));
I_36_36 : BUFE
port map (E=>E,
I=>I(13),
O=>O(13));
I_36_37 : BUFE
port map (E=>E,
I=>I(12),
O=>O(12));
I_36_38 : BUFE
port map (E=>E,
I=>I(6),
O=>O(6));
I_36_39 : BUFE
port map (E=>E,
I=>I(7),
O=>O(7));
I_36_40 : BUFE
port map (E=>E,
I=>I(0),
O=>O(0));
I_36_41 : BUFE
port map (E=>E,
I=>I(1),
O=>O(1));
I_36_42 : BUFE
port map (E=>E,
I=>I(2),
O=>O(2));
I_36_43 : BUFE
port map (E=>E,
I=>I(3),
O=>O(3));
I_36_44 : BUFE
port map (E=>E,
I=>I(4),
O=>O(4));
I_36_45 : BUFE
port map (E=>E,
I=>I(5),
O=>O(5));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity a2dstatio is
port ( A2DIOEBL : in std_logic;
PLLOUT : in std_logic;
SIOR : in std_logic;
SIOW : in std_logic;
A2DRS : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
PLLDBN : out std_logic;
-- TEST45 : out std_logic;
A2DBUS : inout std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0));
end a2dstatio;
architecture BEHAVIORAL of a2dstatio is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
-- signal Latch_A2DBUS: std_logic_vector(15 downto 0);
signal XLXN_199 : std_logic;
signal XLXN_200 : std_logic;
signal XLXN_201 : std_logic;
signal XLXN_202 : std_logic;
signal XLXN_203 : std_logic;
signal XLXN_238 : std_logic;
signal XLXN_239 : std_logic;
signal my_data : std_logic_vector(15 downto 0);
-- component FD16_MXILINX_a2dstatio
-- port ( C : in std_logic;
-- D : in std_logic_vector (15 downto 0);
-- Q : out std_logic_vector (15 downto 0));
-- end component;
component BUFE16_MXILINX_a2dstatio
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component CB4CE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
attribute HU_SET of XLXI_17 : label is "XLXI_17_4";
attribute HU_SET of XLXI_84 : label is "XLXI_84_5";
attribute HU_SET of XLXI_160 : label is "XLXI_160_6";
attribute HU_SET of XLXI_166 : label is "XLXI_166_7";
begin
process(A2DRS)
begin
if A2DRS = '1' then
my_data <= X"AAAA";
else
my_data <= X"5555";
end if;
end process;
-- MY_XLXI : FD16_MXILINX_a2dstatio
-- port map (C=>PLLOUT,
-- D(15 downto 0)=>A2DBUS(15 downto 0),
-- Q(15 downto 0)=>Latch_A2DBUS(15 downto 0));
XLXI_17 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_238,
-- I(15 downto 0)=>X"AAAA",
I(15 downto 0)=>A2DBUS(15 downto 0),
O(15 downto 0)=>BSD(15 downto 0));
XLXI_18 : AND2
port map (I0=>SIOR,
I1=>A2DIOEBL,
O=>XLXN_238);
XLXI_84 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_239,
-- port map (E=>FIFOCTL(1),
-- I(15 downto 0)=>my_data(15 downto 0),
I(15 downto 0)=>BSD(15 downto 0),
O(15 downto 0)=>A2DBUS(15 downto 0));
XLXI_160 : CB4CE_MXILINX_a2dstatio
port map (C=>PLLOUT,
CE=>XLXN_200,
CLR=>XLXN_199,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>open,
Q3=>XLXN_203,
TC=>open);
XLXI_161 : VCC
port map (P=>XLXN_200);
XLXI_162 : GND
port map (G=>XLXN_199);
XLXI_164 : VCC
port map (P=>XLXN_201);
XLXI_165 : GND
port map (G=>XLXN_202);
XLXI_166 : CB4CE_MXILINX_a2dstatio
port map (C=>XLXN_203,
CE=>XLXN_201,
CLR=>XLXN_202,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>PLLDBN,
Q3=>open,
TC=>open);
-- XLXI_185 : BUF
-- port map (I=>XLXN_238,
-- O=>TEST45);
XLXI_186 : AND2
port map (I0=>A2DIOEBL,
I1=>SIOW,
O=>XLXN_239);
end BEHAVIORAL;
| gpl-2.0 |
spoorcc/realtimestagram | src/config_const_pkg.vhd | 2 | 919 | -- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
package config_const_pkg is
constant const_wordsize :integer := 8;
constant const_imageheight :integer := 512;
constant const_imagewidth :integer := 512;
end config_const_pkg;
| gpl-2.0 |
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