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peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1738.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p09n01i01738ent IS
END c09s04b00x00p09n01i01738ent;
ARCHITECTURE c09s04b00x00p09n01i01738arch OF c09s04b00x00p09n01i01738ent IS
signal s1 : bit;
BEGIN
s1 <= not s1 after 70 ns;
block_label1 : BLOCK (s1 = '1')
begin
assert not GUARD
report "PASSED TEST"
severity NOTE;
end block block_label1;
TESTING: PROCESS(s1)
BEGIN
if (now = 70 ns) then
assert FALSE
report "***PASSED TEST: c09s04b00x00p09n01i01738 - This test needs manual check, 'PASSED TEST' assertion should fire at 70 ns, 210 ns, 350 ns ...( the cycle is 140 ns)."
severity NOTE;
end if;
END PROCESS TESTING;
END c09s04b00x00p09n01i01738arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc331.vhd | 4 | 1764 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc331.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00331ent IS
END c03s02b01x00p05n01i00331ent;
ARCHITECTURE c03s02b01x00p05n01i00331arch OF c03s02b01x00p05n01i00331ent IS
type bit_vctor is array (natural range <>) of bit;
type str_vctor is array (natural range <>) of character;
type matrix is array (integer range ) of real; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00331 - The box (<>) in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00331arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug15993/cells.vhdl | 3 | 958 | -------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
--| c | a | b | s | c
--|---+---+---+---+--
--| 0 | 0 | 0 | 0 | 0
--| 0 | 0 | 1 | 1 | 0
--| 0 | 1 | 0 | 1 | 0
--| 0 | 1 | 1 | 0 | 1
--| 1 | 0 | 0 | 1 | 0
--| 1 | 0 | 1 | 0 | 1
--| 1 | 1 | 0 | 0 | 1
--| 1 | 1 | 1 | 1 | 1
ENTITY addern IS
GENERIC ( n : INTEGER );
PORT ( a, b : IN STD_LOGIC_VECTOR ( n-1 DOWNTO 0 );
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR ( n DOWNTO 0 ) );
END addern;
ARCHITECTURE behave OF addern IS
SIGNAL carry : STD_LOGIC;
BEGIN
carry <= cin;
suma : FOR i IN 0 TO n - 1 GENERATE
sum(i) <= ( a(i) XOR b(i) ) XOR carry ;
carry <= ( a(i) AND b(i) ) OR (carry AND ( a(i) XOR b(i) ));
END GENERATE;
sum(n) <= carry;
END behave;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-low-attribute.vhdl | 4 | 294 | entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'low = 0 report "TEST FAILED low = 0" severity failure;
report "TEST PASSED low = 0";
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2310.vhd | 4 | 1754 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2310.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02310ent IS
END c07s02b07x00p01n01i02310ent;
ARCHITECTURE c07s02b07x00p01n01i02310arch OF c07s02b07x00p01n01i02310ent IS
BEGIN
TESTING: PROCESS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
-- Local declarations.
variable SWITCHV : SWITCH_LEVEL := '0';
BEGIN
SWITCHV := ABS SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02310 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02310arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd | 4 | 2195 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc619.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00619ent IS
END c03s04b01x00p01n01i00619ent;
ARCHITECTURE c03s04b01x00p01n01i00619arch OF c03s04b01x00p01n01i00619ent IS
constant C4 : natural := 3 ;
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_st is natural_vector(0 to 15);
type natural_vector_st_file is file of natural_vector_st;
constant C27 : natural_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : natural_vector_st_file open write_mode is "iofile.30";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00619 - The output file will be verified by test s010266.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00619arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd | 4 | 4662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc667.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:26 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00667ent IS
END c03s04b01x00p01n01i00667ent;
ARCHITECTURE c03s04b01x00p01n01i00667arch OF c03s04b01x00p01n01i00667ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C58 : array_rec_cons (0 to 7) := (others => C27);
type array_rec_cons_file is file of array_rec_cons;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_cons_file open read_mode is "iofile.13";
variable v : array_rec_cons(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C58) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00667"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00667 - File reading of array_rec_cons_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00667arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug21500/resolv2.vhdl | 3 | 404 | entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (natural range <>) of rec1;
function resolv (vec : arr2) return rec1
is
begin
return vec (vec'left);
end resolv;
signal s : resolv rec1;
begin
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd | 4 | 2514 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc609.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:42 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00609ent IS
END c03s04b01x00p01n01i00609ent;
ARCHITECTURE c03s04b01x00p01n01i00609arch OF c03s04b01x00p01n01i00609ent IS
type record_std_package is record
a: boolean;
b: bit;
c: character;
d: severity_level;
e: integer;
f: real;
g: time;
h: natural;
i: positive;
end record;
type record_std_package_file is file of record_std_package;
constant C19 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
BEGIN
TESTING: PROCESS
file filein : record_std_package_file open write_mode is "iofile.33";
BEGIN
for i in 1 to 100 loop
write(filein, C19);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00609 - The output file will be verified by test s010252.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00609arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd | 4 | 1768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2568.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p02n01i02568ent IS
END c07s05b00x00p02n01i02568ent;
ARCHITECTURE c07s05b00x00p02n01i02568arch OF c07s05b00x00p02n01i02568ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(6.023E+24 = (2.003E+24 + 4.02E+24))
report "***PASSED TEST: c07s05b00x00p02n01i02568"
severity NOTE;
assert (6.023E+24 = (2.003E+24 + 4.02E+24))
report "***FAILED TEST: c07s05b00x00p02n01i02568 - The same operations are defined for the type universal_integer as for any integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p02n01i02568arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd | 4 | 2128 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1761.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p21n01i01761ent IS
END c09s05b01x00p21n01i01761ent;
ARCHITECTURE c09s05b01x00p21n01i01761arch OF c09s05b01x00p21n01i01761ent IS
signal TS1,TS2 : integer;
signal B,C : integer;
signal D,E,F : bit;
BEGIN
TS1 <= transport 1 after 10 ns when B = C else
2 after 10 ns when B > C else
3 after 10 ns;
TS2 <= transport 4-1 after 10 ns when D = '1' else
5+1 after 10 ns when E = '1' else
6*2 after 10 ns when F = '1' else
8/2 after 10 ns;
TESTING: PROCESS(TS1,TS2)
BEGIN
if ( now > 1 ns) then
assert NOT(TS1=1 and TS2=4)
report "***PASSED TEST: c09s05b01x00p21n01i01761"
severity NOTE;
assert (TS1=1 and TS2=4)
report "***FAILED TEST: c09s05b01x00p21n01i01761 - Conditions in the conditional signal assignment statement should be valid."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b01x00p21n01i01761arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc970.vhd | 4 | 1936 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc970.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00970ent IS
END c06s03b00x00p05n01i00970ent;
ARCHITECTURE c06s03b00x00p05n01i00970arch OF c06s03b00x00p05n01i00970ent IS
BEGIN
TESTING: PROCESS
type x is
record
y : integer;
z : boolean;
end record;
type a is
record
b : real;
c : integer;
end record;
variable r : a;
variable p : x;
BEGIN
p.b := 1; -- the prefix is not of an appropriate type as the 'p' does
a.y := 1; -- not have field 'b' and 'a' does not have field 'y'.
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00970 - Prefix is not apropraite for the type of the suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00970arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd | 4 | 3447 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00737ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00737ent_a;
architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00737"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00737arch_a;
ENTITY c01s01b01x01p04n01i00737ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00737ent;
ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToInt(bin : boolean) return integer is
begin
if bin then
return 5;
else
return 99;
end if;
end;
function IntegerToReal(iin : integer) return real is
begin
return 0.1234;
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00737arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd | 4 | 1959 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01021ent IS
END c06s03b00x00p10n01i01021ent;
ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS
BEGIN
B1:Block
signal s1 : BIT;
begin
TESTING: PROCESS
BEGIN
wait for 1 ns;
END PROCESS TESTING;
B2:Block
signal s2 : BIT;
begin
TEST : PROCESS
BEGIN
s2 <= B1.s1;
wait for 2 ns;
assert NOT(s2='0')
report "***PASSED TEST: c06s03b00x00p10n01i01021"
severity NOTE;
assert (s2='0')
report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
END PROCESS TEST;
end block B2;
end block B1;
END c06s03b00x00p10n01i01021arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd | 4 | 2948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc641.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:15 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:29 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00641ent IS
END c03s04b01x00p01n01i00641ent;
ARCHITECTURE c03s04b01x00p01n01i00641arch OF c03s04b01x00p01n01i00641ent IS
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : primary_memory_file open read_mode is "iofile.42";
variable v : primary_memory;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C44) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00641"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00641 - File reading operation (primary_memory file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00641arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2596.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2596.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02596ent IS
END c13s03b01x00p02n01i02596ent;
ARCHITECTURE c13s03b01x00p02n01i02596arch OF c13s03b01x00p02n01i02596ent IS
BEGIN
TESTING: PROCESS
variable k[ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02596 - Identifier can not end with '['."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02596arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2254.vhd | 4 | 1645 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2254.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02254ent IS
END c07s02b06x00p01n01i02254ent;
ARCHITECTURE c07s02b06x00p01n01i02254arch OF c07s02b06x00p01n01i02254ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
BEGIN
I := 1 / 0; -- should yield divide-by-zero error
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02254 - Integer can not divided by zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02254arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug23165/mwe_working/counter.vhd | 6 | 598 | -- counter
-- clk: clock input
-- en: enable input
-- rst: reset input
-- dir: direction pin (1 = up, 0 = down)
-- q: output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic (
width : positive := 16
);
port (
clk : in std_logic;
q : out std_logic_vector(width-1 downto 0)
);
end counter;
architecture behav of counter is
signal cnt : unsigned(width-1 downto 0) := to_unsigned(0, width);
begin
process
begin
wait until rising_edge(clk);
cnt <= cnt + to_unsigned(1, cnt'length);
end process;
q <= std_logic_vector(cnt);
end behav;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3088.vhd | 4 | 1731 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3088.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p01n01i03088ent IS
attribute ill1 : real;
signal s1, s2 : integer;
attribute ill1 of s1 : signal is 10.0;
attribute LAST_EVENT of s2 : signal is 20; -- Failure_here
END c05s01b00x00p01n01i03088ent;
ARCHITECTURE c05s01b00x00p01n01i03088arch OF c05s01b00x00p01n01i03088ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p01n01i03088 - The attribute must be declared before."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p01n01i03088arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2312.vhd | 4 | 1681 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2312.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02312ent IS
END c07s02b07x00p01n01i02312ent;
ARCHITECTURE c07s02b07x00p01n01i02312arch OF c07s02b07x00p01n01i02312ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable CHARV : CHARACTER := '0';
BEGIN
CHARV := ABS CHARV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02312 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02312arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2993.vhd | 4 | 1814 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2993.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p02n01i02993pkg is
package P2 is -- Failure_here
-- ERROR: PACKAGE DECLARATIONS ARE NOT ALLOWED IN PACKAGES
type INIT_1 is RANGE 1 to 10;
end P2;
end c02s05b00x00p02n01i02993pkg;
ENTITY c02s05b00x00p02n01i02993ent IS
END c02s05b00x00p02n01i02993ent;
ARCHITECTURE c02s05b00x00p02n01i02993arch OF c02s05b00x00p02n01i02993ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s05b00x00p02n01i02993 - Package declarations are not allowed within packages."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p02n01i02993arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2402.vhd | 4 | 1902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2402.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n02i02402ent IS
END c07s03b02x00p08n02i02402ent;
ARCHITECTURE c07s03b02x00p08n02i02402arch OF c07s03b02x00p08n02i02402ent IS
BEGIN
TESTING: PROCESS
type rec_type is record
ele_1 : integer;
ele_2 : integer;
end record;
variable v20 : rec_type;
BEGIN
v20 := (1 + 1 => 20, ele_2 => 0); -- Failure_here
-- simple expression
-- associations allowed only in array agregates.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n02i02402 - Element associations by simple expressions allowed only in array aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n02i02402arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3020.vhd | 4 | 1589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3020.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ; --- Failure_here
ENTITY c11s02b00x00p02n01i03020ent IS
END c11s02b00x00p02n01i03020ent;
ARCHITECTURE c11s02b00x00p02n01i03020arch OF c11s02b00x00p02n01i03020ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s02b00x00p02n01i03020 - Missing library logical name list."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p02n01i03020arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc821.vhd | 4 | 1839 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc821.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00821ent IS
END c01s02b02x00p02n01i00821ent;
ARCHITECTURE c01s02b02x00p02n01i00821arch OF c01s02b02x00p02n01i00821ent IS
signal err : boolean := true;
BEGIN
case err is -- illegal location for case statement
when true | false =>
assert false
report "'case' statement accepted in an entity statement."
severity note ;
end case;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00821 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00821arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd | 4 | 1830 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01646ent IS
END c08s13b00x00p03n01i01646ent;
ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if TRUE then
k := 5;
NULL;
elsif FALSE then
k := 5;
NULL;
end if;
assert NOT(k = 5)
report "***PASSED TEST: c08s13b00x00p03n01i01646"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01646arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1685.vhd | 4 | 1733 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1685.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p02n01i01685ent IS
port (A : bit);
END c09s02b00x00p02n01i01685ent;
ARCHITECTURE c09s02b00x00p02n01i01685arch OF c09s02b00x00p02n01i01685ent IS
signal B : bit;
BEGIN
P1:process (A)
begin
B <= A;
end ; -- Failure_here
-- the reserved word 'process' expected.
TESTING : PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p02n01i01685 - Reserved word process is missing after the reserved word end."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p02n01i01685arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1282.vhd | 4 | 1688 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1282.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01282ent IS
END c08s04b00x00p04n01i01282ent;
ARCHITECTURE c08s04b00x00p04n01i01282arch OF c08s04b00x00p04n01i01282ent IS
type INIT_1 is range 16#1# to 16#FF#;
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
INIT_1(S1) <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01282 - Type Conversions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01282arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd | 4 | 1545 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_cg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavior of clock_gen is
constant clock_period : delay_length := 2 * (Tpw + Tps);
begin
reset_driver :
reset <= '1', '0' after 2.5 * clock_period + Tps;
clock_driver : process is
begin
phi1 <= '0';
phi2 <= '0';
wait for clock_period / 2;
loop
phi1 <= '1', '0' after Tpw;
phi2 <= '1' after clock_period / 2,
'0' after clock_period / 2 + Tpw;
wait for clock_period;
end loop;
end process clock_driver;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd | 4 | 2067 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1810.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01810ent IS
END c07s01b00x00p08n01i01810ent;
ARCHITECTURE c07s01b00x00p08n01i01810arch OF c07s01b00x00p08n01i01810ent IS
BEGIN
TESTING: PROCESS
variable a1 : boolean := true;
variable b1 : boolean;
variable x1 : integer := 12;
variable y1 : real := 12.3;
variable p1 : real := 12.5;
variable z1 : integer := 10;
BEGIN
b1 := (x1 < z1) or (y1 > p1) or (x1 = z1) or a1; -- No_failure_here
assert NOT(b1 = true)
report "***PASSED TEST: c07s01b00x00p08n01i01810"
severity NOTE;
assert ( b1 = true )
report "***FAILED TEST: c07s01b00x00p08n01i01810 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01810arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd | 4 | 1616 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtstb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_behavior of dlx_test is
for bench
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc : dlx
use entity work.dlx(behavior)
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for;
end configuration dlx_test_behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug17127/bug2.vhdl | 3 | 809 | library ieee;
use ieee.std_logic_1164.all;
entity bug2 is
end;
architecture this of bug2 is
function f return integer is
constant cc1: std_logic_vector := "1100";
constant cc2: std_logic_vector := cc1;
variable r: std_logic_vector(3 downto 0);
begin
assert false report "case2-a: "&integer'image(cc1'length) severity note;
assert false report "case2-b: "&integer'image(cc2'length) severity note;--This reports "0". Correct one would be "4"!
return 0;
end;
constant c1: std_logic_vector := "1010";
constant c2: std_logic_vector := c1;
signal i: integer;
begin
process
begin
assert false report "case1-a: "&integer'image(c1'length) severity note;
assert false report "case1-b: "&integer'image(c2'length) severity note;
i <= f;
wait;
end process;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd | 4 | 6100 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s06b00x00p04n05i01787ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end c09s06b00x00p04n05i01787ent_a;
architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
begin
port0 <= g0 after 11 ns;
port1 <= g1 after 11 ns;
port2 <= g2 after 11 ns;
port3 <= g3 after 11 ns;
port4 <= g4 after 11 ns;
port5 <= g5 after 11 ns;
port6 <= g6 after 11 ns;
port7 <= g7 after 11 ns;
port8 <= g8 after 11 ns;
port9 <= g9 after 11 ns;
portA <= gA after 11 ns;
end c09s06b00x00p04n05i01787arch_a;
ENTITY c09s06b00x00p04n05i01787ent IS
END c09s06b00x00p04n05i01787ent;
ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal signal0 : Boolean ;
signal signal1 : Bit ;
signal signal2 : Character ;
signal signal3 : SEVERITY_LEVEL ;
signal signal4 : Integer ;
signal signal5 : Real ;
signal signal6 : TIME ;
signal signal7 : Natural ;
signal signal8 : Positive ;
signal signal9 : String16 ;
signal signalA : Reg32 ;
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
)
port map (
signal0 ,
signal1 ,
signal2 ,
signal3 ,
signal4 ,
signal5 ,
signal6 ,
signal7 ,
signal8 ,
signal9 ,
signalA
);
TESTING: PROCESS
BEGIN
wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
assert NOT( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***PASSED TEST: c09s06b00x00p04n05i01787"
severity NOTE;
assert ( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n05i01787arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2064.vhd | 4 | 2411 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02064ent IS
END c07s02b04x00p01n02i02064ent;
ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
INTV := INTV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02064arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd | 4 | 1897 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03186ent IS
END c14s03b00x00p42n01i03186ent;
ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : TEXT open write_mode is "iofile.01";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
WRITELINE (FILEV, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03186arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd | 4 | 2402 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity tb_05_02 is
end entity tb_05_02;
architecture test of tb_05_02 is
signal a1, a2, b1, b2, y : bit;
begin
dut : entity work.and_or_inv(primitive)
port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
y => y );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111" );
begin
for i in stim_vector'range loop
(a1, a2, b1, b2) <= stim_vector(i);
wait for 10 ns;
assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
or (stim_vector(i)(2) and stim_vector(i)(3)) );
end loop;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1391.vhd | 4 | 1826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1391.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n03i01391ent IS
END c08s05b00x00p04n03i01391ent;
ARCHITECTURE c08s05b00x00p04n03i01391arch OF c08s05b00x00p04n03i01391ent IS
BEGIN
TESTING: PROCESS
type ARR is array(0 to 1) of bit;
variable i : integer := 1;
variable j : integer := 2;
variable S : BIT_VECTOR(0 to 1);
variable T : BIT_VECTOR(0 to 2);
BEGIN
(S(i),T(j)) := ARR'('0','1');
assert FALSE
report "***FAILED TEST: c08s05b00x00p04n03i01391 - Each element association of the aggregate must be a locally static name that denotes a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n03i01391arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1098.vhd | 4 | 2039 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1098.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01098ent IS
END c06s05b00x00p03n01i01098ent;
ARCHITECTURE c06s05b00x00p03n01i01098arch OF c06s05b00x00p03n01i01098ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V2 := A5'(others=>TRUE)(3 to 3);
-- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01098 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01098arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc999.vhd | 4 | 1824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc999.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i00999pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i00999pkg;
use work.c06s03b00x00p09n01i00999pkg.all;
ENTITY c06s03b00x00p09n01i00999ent IS
END c06s03b00x00p09n01i00999ent;
ARCHITECTURE c06s03b00x00p09n01i00999arch OF c06s03b00x00p09n01i00999ent IS
BEGIN
TESTING: PROCESS
subtype ST3 is c06s03b00x00p09n01i00999pkg.c06s03b00x00p09n01i00999ent.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i00999 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i00999arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd | 4 | 1796 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofp-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of to_fp is
begin
behavior : process (vec) is
variable temp : bit_vector(vec'range);
variable negative : boolean;
variable int_result : integer;
begin
temp := to_bitvector(vec);
negative := temp(temp'left) = '1';
if negative then
temp := not temp;
end if;
int_result := 0;
for index in vec'range loop -- sign bit of temp = '0'
int_result := int_result * 2 + bit'pos(temp(index));
end loop;
if negative then
int_result := (-int_result) - 1;
end if;
-- convert to floating point and scale to [-1, +1)
r <= real(int_result) / real(2**15);
end process behavior;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd | 4 | 1805 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1641.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p06n01i01641ent IS
END c08s12b00x00p06n01i01641ent;
ARCHITECTURE c08s12b00x00p06n01i01641arch OF c08s12b00x00p06n01i01641ent IS
BEGIN
TESTING: PROCESS
function ts (x1:bit) return integer is
begin
return (5);
end ts;
variable k : integer := 0;
BEGIN
k := ts('1');
assert NOT(k=5)
report "***PASSED TEST: c08s12b00x00p06n01i01641"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c08s12b00x00p06n01i01641 - Value of the expression is of different subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01641arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2503.vhd | 4 | 1721 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2503.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p02n01i02503ent IS
END c07s03b04x00p02n01i02503ent;
ARCHITECTURE c07s03b04x00p02n01i02503arch OF c07s03b04x00p02n01i02503ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
variable S :rec_type;
BEGIN
S := rec_type(bit'('0'), 1, true);
assert FALSE
report "***FAILED TEST: c07s03b04x00p02n01i02503 - Missing apostrophe."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p02n01i02503arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2031.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2031.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02031ent IS
END c07s02b04x00p01n01i02031ent;
ARCHITECTURE c07s02b04x00p01n01i02031arch OF c07s02b04x00p01n01i02031ent IS
BEGIN
TESTING: PROCESS
variable CHARV : CHARACTER := '0';
BEGIN
CHARV := '0' + '2';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02031 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02031arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket69/bug.vhdl | 3 | 264 | library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0);
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2245.vhd | 4 | 1653 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2245.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02245ent IS
END c07s02b06x00p01n01i02245ent;
ARCHITECTURE c07s02b06x00p01n01i02245arch OF c07s02b06x00p01n01i02245ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := B"1010101010" rem X"FFFF";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02245 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02245arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd | 4 | 21292 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_arithmetic_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package body bv_arithmetic is
----------------------------------------------------------------
-- Type conversions
----------------------------------------------------------------
function bv_to_natural ( bv : in bit_vector ) return natural is
variable result : natural := 0;
begin
for index in bv'range loop
result := result * 2 + bit'pos( bv(index) );
end loop;
return result;
end function bv_to_natural;
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
begin
for index in result'reverse_range loop
result(index) := bit'val( temp rem 2 );
temp := temp / 2;
exit when temp = 0;
end loop;
return result;
end function natural_to_bv;
function bv_to_integer ( bv : in bit_vector ) return integer is
variable temp : bit_vector(bv'range);
variable result : integer := 0;
begin
if bv(bv'left) = '1' then -- negative number
temp := not bv;
else
temp := bv;
end if;
for index in bv'range loop -- sign bit of temp = '0'
result := result * 2 + bit'pos( temp(index) );
end loop;
if bv(bv'left) = '1' then
result := (-result) - 1;
end if;
return result;
end function bv_to_integer;
function integer_to_bv ( int : in integer;
length : in natural ) return bit_vector is
variable temp : integer;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
begin
if int < 0 then
temp := - (int + 1);
else
temp := int;
end if;
for index in result'reverse_range loop
result(index) := bit'val( temp rem 2 );
temp := temp / 2;
exit when temp = 0;
end loop;
if int < 0 then
result := not result;
result(result'left) := '1';
end if;
return result;
end function integer_to_bv;
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
procedure bv_add ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_add: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end if;
end procedure bv_add;
function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
if bv1'length /= bv2'length then
report """+"": operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function "+";
procedure bv_sub ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_sub: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end if;
end procedure bv_sub;
function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
if bv1'length /= bv2'length then
report """-"": operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
end if;
return result;
end function "-";
procedure bv_addu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_addu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry = '1';
end if;
end procedure bv_addu;
function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "bv_addu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function bv_addu;
procedure bv_subu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable borrow : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_subu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := borrow = '1';
end if;
end procedure bv_subu;
function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable borrow : bit := '0';
begin
if bv1'length /= bv2'length then
report "bv_subu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function bv_subu;
procedure bv_neg ( bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
constant zero : bit_vector(bv'range) := (others => '0');
begin
bv_sub( zero, bv, bv_result, overflow );
end procedure bv_neg;
function "-" ( bv : in bit_vector ) return bit_vector is
constant zero : bit_vector(bv'range) := (others => '0');
begin
return zero - bv;
end function "-";
procedure bv_mult ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable multu_result : bit_vector(bv1'range);
variable multu_overflow : boolean;
variable abs_min_int : bit_vector(bv1'range) := (others => '0');
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_mult: operands of different lengths"
severity failure;
else
abs_min_int(bv1'left) := '1';
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
bv_multu(op1, op2, multu_result, multu_overflow);
if negative_result then
overflow := multu_overflow or (multu_result > abs_min_int);
bv_result := - multu_result;
else
overflow := multu_overflow or (multu_result(multu_result'left) = '1');
bv_result := multu_result;
end if;
end if;
end procedure bv_mult;
function "*" ( bv1, bv2 : in bit_vector ) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length then
report """*"": operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
result := bv_multu(op1, op2);
if negative_result then
result := - result;
end if;
end if;
return result;
end function "*";
procedure bv_multu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
constant len : natural := bv1'length;
constant accum_len : natural := len * 2;
variable accum : bit_vector(accum_len - 1 downto 0) := (others => '0');
constant zero : bit_vector(accum_len - 1 downto len):= (others => '0');
variable addu_overflow : boolean;
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_multu: operands of different lengths"
severity failure;
else
for count in 0 to len - 1 loop
if op2(count) = '1' then
bv_addu( accum(count + len - 1 downto count), op1,
accum(count + len - 1 downto count), addu_overflow);
accum(count + len) := bit'val(boolean'pos(addu_overflow));
end if;
end loop;
bv_result := accum(len - 1 downto 0);
overflow := accum(accum_len-1 downto len) /= zero;
end if;
end procedure bv_multu;
function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector is
-- Use bv_multu with overflow detection, but ignore overflow flag
variable result : bit_vector(bv1'range);
variable tmp_overflow : boolean;
begin
bv_multu(bv1, bv2, result, tmp_overflow);
return result;
end function bv_multu;
procedure bv_div ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean ) is
-- Need overflow, in case divide b"10...0" (min_int) by -1
-- Don't use bv_to_int, in case size bigger than host machine!
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable divu_result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_div: operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
bv_divu(op1, op2, divu_result, div_by_zero);
if negative_result then
overflow := false;
bv_result := - divu_result;
else
overflow := divu_result(divu_result'left) = '1';
bv_result := divu_result;
end if;
end if;
end procedure bv_div;
function "/" ( bv1, bv2 : in bit_vector ) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length then
report """/"": operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
result := bv_divu(op1, op2);
if negative_result then
result := - result;
end if;
end if;
return result;
end function "/";
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
bv_remainder : out bit_vector;
div_by_zero : out boolean ) is
constant len : natural := bv1'length;
constant zero_divisor : bit_vector(len-1 downto 0) := (others => '0');
alias dividend : bit_vector(bv1'length-1 downto 0) is bv1;
variable divisor : bit_vector(bv2'length downto 0) := '0' & bv2;
variable quotient : bit_vector(len-1 downto 0);
variable remainder : bit_vector(len downto 0) := (others => '0');
variable ignore_overflow : boolean;
begin
if bv1'length /= bv2'length
or bv1'length /= bv_quotient'length or bv1'length /= bv_remainder'length then
report "bv_divu: operands of different lengths"
severity failure;
else
-- check for zero divisor
if bv2 = zero_divisor then
div_by_zero := true;
return;
end if;
-- perform division
for iter in len-1 downto 0 loop
if remainder(len) = '0' then
remainder := remainder sll 1;
remainder(0) := dividend(iter);
bv_sub(remainder, divisor, remainder, ignore_overflow);
else
remainder := remainder sll 1;
remainder(0) := dividend(iter);
bv_add(remainder, divisor, remainder, ignore_overflow);
end if;
quotient(iter) := not remainder(len);
end loop;
if remainder(len) = '1' then
bv_add(remainder, divisor, remainder, ignore_overflow);
end if;
bv_quotient := quotient;
bv_remainder := remainder(len - 1 downto 0);
div_by_zero := false;
end if;
end procedure bv_divu;
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
div_by_zero : out boolean ) is
variable ignore_remainder : bit_vector(bv_quotient'range);
begin
bv_divu(bv1, bv2, bv_quotient, ignore_remainder, div_by_zero);
end procedure bv_divu;
function bv_divu ( bv1, bv2 : in bit_vector ) return bit_vector is
variable result : bit_vector(bv1'range);
variable tmp_div_by_zero : boolean;
begin
bv_divu(bv1, bv2, result, tmp_div_by_zero);
return result;
end function bv_divu;
----------------------------------------------------------------
-- Arithmetic comparison operators.
-- Perform comparisons on bit vector encoded signed integers.
-- (For unsigned integers, built in lexical comparison does
-- the required operation.)
----------------------------------------------------------------
function bv_lt ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_lt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 < tmp2;
end function bv_lt;
function bv_le ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_le: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 <= tmp2;
end function bv_le;
function bv_gt ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_gt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 > tmp2;
end function bv_gt;
function bv_ge ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_ged: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 >= tmp2;
end function bv_ge;
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
function bv_sext ( bv : in bit_vector;
length : in natural ) return bit_vector is
alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
variable result : bit_vector(length - 1 downto 0) := (others => bv(bv'left));
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
return result;
end function bv_sext;
function bv_zext ( bv : in bit_vector;
length : in natural ) return bit_vector is
alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
return result;
end function bv_zext;
end package body bv_arithmetic;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket32/muxcy.vhdl | 3 | 211 | library ieee;
use ieee.std_logic_1164.all;
entity muxcy is
port (s, di, ci : std_logic;
o : out std_logic);
end muxcy;
architecture behav of muxcy is
begin
o <= di when s = '0' else ci;
end behav;
| gpl-2.0 |
peteut/ghdl | libraries/std/env_body.vhdl | 5 | 2191 | -- Std.Env package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package body Env is
procedure control_simulation (Is_Stop : Boolean;
Has_Status : Boolean;
Status : Integer);
attribute foreign of control_simulation : procedure is "GHDL intrinsic";
procedure control_simulation (Is_Stop : Boolean;
Has_Status : Boolean;
Status : Integer) is
begin
assert false report "must not be called" severity failure;
end control_simulation;
procedure Stop (Status : Integer) is
begin
control_simulation (True, True, Status);
end Stop;
procedure Stop is
begin
control_simulation (True, False, -1);
end Stop;
procedure Finish (status : integer) is
begin
control_simulation (False, True, Status);
end Finish;
procedure Finish is
begin
control_simulation (False, False, -1);
end Finish;
function Get_Resolution_Limit return Delay_Length;
attribute foreign of Get_Resolution_Limit : function is "GHDL intrinsic";
function Get_Resolution_Limit return Delay_Length is
begin
assert false report "must not be called" severity failure;
end Get_Resolution_Limit;
function Resolution_Limit return Delay_Length is
begin
return Get_Resolution_Limit;
end Resolution_Limit;
end package body Env;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2544.vhd | 4 | 1998 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02544ent IS
END c07s03b05x00p14n01i02544ent;
ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
IN2 := IN2 - IN1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02544arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2935.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02935pkg is
procedure proc1 (i,l:integer; res: boolean);
end c02s02b00x00p07n03i02935pkg;
package body c02s02b00x00p07n03i02935pkg is
--ERROR : non-existent body for procedure proc1
end c02s02b00x00p07n03i02935pkg;
ENTITY c02s02b00x00p07n03i02935ent IS
END c02s02b00x00p07n03i02935ent;
ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02935arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd | 4 | 2049 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3193.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03193ent IS
END c14s03b00x00p42n01i03193ent;
ARCHITECTURE c14s03b00x00p42n01i03193arch OF c14s03b00x00p42n01i03193ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open read_mode is "iofile.08";
variable L : LINE;
variable vbit : bit;
variable fail : integer := 0;
BEGIN
for I in 1 to 100 loop
READLINE (F, L);
READ (L, vbit);
if (vbit /= '1') then
fail := 1;
end if;
end loop;
assert NOT(fail = 0)
report "***PASSED TEST: c14s03b00x00p42n01i03193"
severity NOTE;
assert (fail = 0)
report "***FAILED TEST: c14s03b00x00p42n01i03193 - procedure READLINE for bit TEXT file test failed, plese check s010108.vhd file also."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03193arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc191.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc191.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s05b00x00p02n01i00191ent IS
END c04s05b00x00p02n01i00191ent;
ARCHITECTURE c04s05b00x00p02n01i00191arch OF c04s05b00x00p02n01i00191ent IS
component A2 generic (constant G2 : buffer BOOLEAN); -- Failure_here
-- ERROR: the
-- only mode allowed in a
-- local generic list is in.
end component ;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s05b00x00p02n01i00191 - Mode buffer is not allowed in a local generic."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s05b00x00p02n01i00191arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd | 4 | 1470 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_21_01 is
end entity ch_21_01;
----------------------------------------------------------------
architecture test of ch_21_01 is
type std_ulogic is (t1, t2, t3);
subtype std_logic is std_ulogic;
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
-- end of code from book
begin
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd | 4 | 2143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2097.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02097ent IS
END c07s02b04x00p20n01i02097ent;
ARCHITECTURE c07s02b04x00p20n01i02097arch OF c07s02b04x00p20n01i02097ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
BEGIN
TESTING : PROCESS
variable result : boolean_8;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = (true,false,true,false,false,false,true,true))
report "***PASSED TEST: c07s02b04x00p20n01i02097"
severity NOTE;
assert (result = (true,false,true,false,false,false,true,true))
report "***FAILED TEST: c07s02b04x00p20n01i02097 - Variable concatenation did not succeed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02097arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd | 4 | 2266 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity cache is
generic ( cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10) );
port ( halt : in bit );
end entity cache;
architecture instrumented of cache is
begin
-- code from book
cache_monitor : process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file
open append_mode is "cache-measurements";
-- . . .
-- not in book
constant miss_count : natural := 100;
constant total_accesses : natural := 1000;
constant total_delay : delay_length := 2400 ns;
-- end not in book
begin
-- . . .
loop
-- . . .
-- not in book
wait on halt;
-- end not in book
exit when halt = '1';
-- . . .
end loop;
write ( measurements,
measurement_record'(
-- write values of generics for this run
cache_size, block_size, associativity, benchmark_name,
-- calculate performance metrics
miss_rate => real(miss_count) / real(total_accesses),
ave_access_time => total_delay / total_accesses ) );
wait;
end process cache_monitor;
-- end code from book
end architecture instrumented;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd | 4 | 1895 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1675.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p06n01i01675ent IS
END c09s01b00x00p06n01i01675ent;
ARCHITECTURE c09s01b00x00p06n01i01675arch OF c09s01b00x00p06n01i01675ent IS
signal garde : boolean := true;
BEGIN
lab: block ( garde )
begin
garde <= not GUARD after 20 ns;
assert ( GUARD = garde )
report "***FAILED TEST: c09s01b00x00p06n01i01675 - Implicit signal GUARD changed state and does not match explicit signal garde (FAIL)"
severity ERROR;
end block lab;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p06n01i01675 - This test needed manual check, no failure test assertion report"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p06n01i01675arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc801.vhd | 4 | 1659 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc801.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00801ent IS
begin
next; -- illegal location for next statement
END c01s01b03x00p03n01i00801ent;
ARCHITECTURE c01s01b03x00p03n01i00801arch OF c01s01b03x00p03n01i00801ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00801 - Next statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00801arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc514.vhd | 4 | 1689 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc514.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p02n01i00514ent IS
END c03s03b00x00p02n01i00514ent;
ARCHITECTURE c03s03b00x00p02n01i00514arch OF c03s03b00x00p02n01i00514ent IS
type MY_WORD is array (0 to 31) of BIT;
type MEMORY is array (Integer range <>) of MY_WORD;
type ADDRESS is access ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b00x00p02n01i00514 - Missing subtype indication"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p02n01i00514arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd | 4 | 1751 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01914ent IS
END c07s02b01x00p01n01i01914ent;
ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := not b1;
assert NOT(b1 = '1')
report "***PASSED TEST: c07s02b01x00p01n01i01914"
severity NOTE;
assert (b1 = '1')
report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01914arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd | 4 | 1346 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-enumeration-assign.vhdl | 8 | 343 | entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : boolean := false;
begin -- process
x := true;
assert x = true report "TEST FAILED - x does not equal true" severity failure;
assert x /= true report "TEST PASSED" severity note;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc88.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p05n02i00088ent IS
END c04s03b01x03p05n02i00088ent;
ARCHITECTURE c04s03b01x03p05n02i00088arch OF c04s03b01x03p05n02i00088ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
a : bit;
b : character;
c : boolean;
end record;
variable x : rec_type ;
BEGIN
assert NOT( x.a = '0' and x.b = Nul and x.c = false )
report "***PASSED TEST:c04s03b01x03p05n02i00088"
severity NOTE;
assert ( x.a = '0' and x.b = Nul and x.c = false )
report "***FAILED TEST:c04s03b01x03p05n02i00088 - Variable default assignment failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p05n02i00088arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd | 4 | 1773 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1182.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p01n01i01182ent IS
END c08s01b00x00p01n01i01182ent;
ARCHITECTURE c08s01b00x00p01n01i01182arch OF c08s01b00x00p01n01i01182ent IS
BEGIN
TESTING: PROCESS
variable k : time := 0 ns;
BEGIN
k := now;
wait for 5 ns;
k := now - k;
assert NOT( k=5 ns )
report "***PASSED TEST: c08s01b00x00p01n01i01182"
severity NOTE;
assert ( k=5 ns)
report "***FAILED TEST: c08s01b00x00p01n01i01182 - A wait statement cause the suspension of the process statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p01n01i01182arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd | 4 | 1948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2415.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n01i02415ent IS
END c07s03b02x00p10n01i02415ent;
ARCHITECTURE c07s03b02x00p10n01i02415arch OF c07s03b02x00p10n01i02415ent IS
type sigrec1 is
record
B1 : bit;
B2 : integer;
B3 : bit;
end record;
signal S1 : bit;
signal S2 : integer;
signal S3 : bit;
BEGIN
TESTING: PROCESS
BEGIN
(S1, S2, S3) <= sigrec1'('0', 2, '1');
wait for 1 ns;
assert NOT(S1='0' and S2=2 and S3='1')
report "***PASSED TEST: c07s03b02x00p10n01i02415"
severity NOTE;
assert (S1='0' and S2=2 and S3='1')
report "***FAILED TEST: c07s03b02x00p10n01i02415 - Type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02415arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd | 4 | 3799 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00742pkg is
type arrtype is array (1 to 5) of integer;
type rectype is record
-- 'a',33,0.1234,TRUE
ch : character;
int : integer;
re : real;
bo : boolean;
end record;
end c01s01b01x01p04n01i00742pkg;
use work.c01s01b01x01p04n01i00742pkg.all;
entity c01s01b01x01p04n01i00742ent_a is
generic (
constant gc1 : arrtype;
constant gc2 : rectype;
constant gc3 : boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00742ent_a;
architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00742"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00742arch_a;
use work.c01s01b01x01p04n01i00742pkg.all;
ENTITY c01s01b01x01p04n01i00742ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00742ent;
ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : arrtype;
constant dgc2 : rectype;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToArr(bin : boolean) return arrtype is
begin
if bin then
return (1,2,3,4,5);
else
return (9,8,7,6,5);
end if;
end;
function IntegerToRec(iin : integer) return rectype is
begin
return ('a',33,0.1234,TRUE);
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00742arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd | 4 | 2277 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3043.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03043ent IS
END c12s02b02x00p02n03i03043ent;
ARCHITECTURE c12s02b02x00p02n03i03043arch OF c12s02b02x00p02n03i03043ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(i2=>-5, i1=>3, i4=>-4, i3=>6);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03043"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03043 - Named association of generics creates constnats without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03043arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1861.vhd | 4 | 1927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1861.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01861ent IS
END c07s01b00x00p08n01i01861ent;
ARCHITECTURE c07s01b00x00p08n01i01861arch OF c07s01b00x00p08n01i01861ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
obus(sig) <= 5 after 5 ns; --signal assignment label illegal here
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01861 - Signal assignment labels are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01861arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2009.vhd | 4 | 1793 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2009.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02009ent IS
END c07s02b02x00p10n01i02009ent;
ARCHITECTURE c07s02b02x00p10n01i02009arch OF c07s02b02x00p10n01i02009ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
i : integer;
end record;
variable j, k : rec_type;
BEGIN
j.i := 2;
k.i := 1;
if (k<j) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p10n01i02009 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02009arch;
| gpl-2.0 |
123gmax/Digital-Lab | AES128/Architecture1_Pipeline/decryptionLoopCore_V1_tb.vhd | 1 | 3479 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 08:22:22 PM
-- Design Name:
-- Module Name: decryptionLoopCore_V1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionLoopCore_V1_tb is
end decryptionLoopCore_V1_tb;
architecture Behavioral of decryptionLoopCore_V1_tb is
component decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC;
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0);
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
constant clk_period : time := 2ns;
signal CLK, RESET, ENABLE, memorySourceSelector : STD_LOGIC := '0';
signal keySelector : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal cipherKey : STD_LOGIC_VECTOR(127 downto 0) := (others => '0');
signal WORD_IN, WORD_OUT : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ENABLE <= '1';
uut: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => memorySourceSelector,
keySelector => keySelector,
cipherKey => cipherKey,
WORD_IN => WORD_IN,
WORD_OUT => WORD_OUT);
controlUnit0: controlUnit port map( CLK => CLK,
RESET => RESET,
ENABLE => ENABLE,
loadSourceSelector => memorySourceSelector,
addRoundKeySelector1 => open,
addRoundKeySelector2 => keySelector);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
--Source http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf decrypt ROUND 10
stim_process: process
begin
--Wait for one clk_period to synchronize the control unit.
--During this clk_period, the first addRoundKey would occur.
wait for clk_period;
cipherKey <= x"BFE2BF904559FAB2A16480B4F7F1CBD8";
WORD_IN <= x"013E8EA7";
wait for clk_period;
WORD_IN <= x"3AB004BC";
wait for clk_period;
WORD_IN <= x"8CE23D4D";
wait for clk_period;
WORD_IN <= x"2133B81C";
wait for clk_period;
WORD_IN <= (others => '0');
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd | 4 | 2499 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
entity fg_21_01 is
end entity fg_21_01;
architecture test of fg_21_01 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd | 4 | 1711 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1265.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n01i01265ent IS
END c08s02b00x00p06n01i01265ent;
ARCHITECTURE c08s02b00x00p06n01i01265arch OF c08s02b00x00p06n01i01265ent IS
BEGIN
TESTING: PROCESS
variable I : integer := 1;
BEGIN
assert (I=1);
assert TRUE
report "Report on the message";
assert FALSE
report "***PASSED TEST: c08s02b00x00p06n01i01265 - This test needs manual check. No other assertion messages should occur except this."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n01i01265arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc535.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n01i00535ent IS
END c03s03b00x00p05n01i00535ent;
ARCHITECTURE c03s03b00x00p05n01i00535arch OF c03s03b00x00p05n01i00535ent IS
type b is access BIT_VECTOR(0 to 10); -- Success_here
BEGIN
TESTING: PROCESS
variable k : b;
BEGIN
assert NOT(k=null)
report "***PASSED TEST: c03s03b00x00p05n01i00535"
severity NOTE;
assert ( k=null )
report "***FAILED TEST: c03s03b00x00p05n01i00535 - The only form of constraint that is allowed after the name of an access type in a subtype indication is an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n01i00535arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/block-statements/simple-grouping-block.vhdl | 3 | 621 | entity test is
end test;
architecture only of test is
signal delay_line_in : bit := '0';
signal delay_line_out : bit := '0';
begin -- only
delay: block
begin -- block delay
delay_line_out <= delay_line_in after 1 ns;
end block delay;
start: process
begin -- process
delay_line_in <= '1';
wait;
end process;
check: process( delay_line_out )
begin
if delay_line_out = '1' then
assert now = 1 ns report "TEST FAILED - delay did not happen as expected!" severity FAILURE;
assert not(now = 1 ns) report "TEST PASSED" severity WARNING;
end if;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd | 4 | 2844 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1076.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n01i01076ent IS
subtype line is integer range 0 to 15;
subtype cmd is integer range 0 to 3;
type d_lines is array (line range <>) of bit;
subtype data_line is d_lines(line);
subtype cmd_line is d_lines(cmd);
END c06s05b00x00p01n01i01076ent;
ARCHITECTURE c06s05b00x00p01n01i01076arch OF c06s05b00x00p01n01i01076ent IS
BEGIN
TESTING: PROCESS
variable d1 : data_line := (0 to 3 => '1', others => '0');
variable instr : cmd_line;
BEGIN
--
-- Test assigning a slice to a full array
--
instr := d1(0 to 3);
for i in 0 to 3 loop
assert instr(i) = '1'
report "Slice to full array assignment failed."
severity note ;
end loop;
--
-- Now try a full array to a slice
--
d1(8 to 11) := instr;
for i in 8 to 11 loop
assert d1(i) = '1'
report "Full array to slice assignment failed."
severity note ;
end loop;
--
-- Now try assigning a slice to a slice
--
d1(8 to 11) := d1(4 to 7);
for i in 4 to 15 loop
assert d1(i) = '0'
report "Slice to slice assignment failed."
severity note ;
end loop;
assert NOT( instr = "1111" and d1 = "1111000000000000" )
report "***PASSED TEST: c06s05b00x00p01n01i01076"
severity NOTE;
assert ( instr = "1111" and d1 = "1111000000000000" )
report "***FAILED TEST: c06s05b00x00p01n01i01076 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n01i01076arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd | 3 | 4325 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_20.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity control_section is
end entity control_section;
-- end not in book
architecture structural of control_section is
component reg is
generic ( width : positive );
port ( clk : in std_logic;
d : in std_logic_vector(0 to width - 1);
q : out std_logic_vector(0 to width - 1) );
end component reg;
for flag_reg : reg
use entity work.reg(gate_level)
-- workaround for MTI bug mt023
-- reverted for ghdl
port map ( clock => clk, data_in => d, data_out => q );
-- port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
-- end workaround
-- . . .
-- not in book
signal clock_phase1, zero_result, neg_result, overflow_result,
zero_flag, neg_flag, overflow_flag : std_logic;
-- end not in book
begin
flag_reg : component reg
generic map ( width => 3 )
port map ( clk => clock_phase1,
d(0) => zero_result, d(1) => neg_result,
d(2) => overflow_result,
q(0) => zero_flag, q(1) => neg_flag,
q(2) => overflow_flag );
-- . . .
-- not in book
stimulus : process is
begin
clock_phase1 <= '0';
zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture structural;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd | 4 | 1944 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc319.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p03n01i00319ent IS
END c03s02b01x00p03n01i00319ent;
ARCHITECTURE c03s02b01x00p03n01i00319arch OF c03s02b01x00p03n01i00319ent IS
type bit_vctor is array (natural range <>) of bit; -- Success_here
BEGIN
TESTING: PROCESS
subtype kk is bit_vctor(0 to 63);
variable k : kk;
BEGIN
k(5) := '0';
assert NOT(k(5)='0')
report "***PASSED TEST: c03s02b01x00p03n01i00319"
severity NOTE;
assert (k(5)='0')
report "***FAILED TEST: c03s02b01x00p03n01i00319 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p03n01i00319arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd | 4 | 1673 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3138.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p02n01i03138ent IS
END c05s02b02x00p02n01i03138ent;
ARCHITECTURE c05s02b02x00p02n01i03138arch OF c05s02b02x00p02n01i03138ent IS
component c05s02b02x00p02n01i03138ent_a
end component;
for comp1 : c05s02b02x00p02n01i03138ent_a use OPEN;
BEGIN
comp1 : c05s02b02x00p02n01i03138ent_a;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p02n01i03138"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p02n01i03138arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd | 4 | 2080 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tb_piston is
end tb_piston;
architecture TB_piston of tb_piston is
-- Component declarations
-- Signal declarations
terminal n1, n2 : translational;
begin
-- Signal assignments
-- Component instances
Force1 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n1,
trans_neg => TRANSLATIONAL_REF
);
mass1 : entity work.piston(simple)
port map(
motion => n1
);
Force2 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n2,
trans_neg => TRANSLATIONAL_REF
);
mass2 : entity work.mass_t(ideal)
generic map(
m => 10.0
)
port map(
trans1 => n2
);
end TB_piston;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc342.vhd | 4 | 1824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc342.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n03i00342ent IS
END c03s02b01x00p09n03i00342ent;
ARCHITECTURE c03s02b01x00p09n03i00342arch OF c03s02b01x00p09n03i00342ent IS
type array_type is array (1 to 10) of boolean;
BEGIN
TESTING: PROCESS
variable k : array_type;
BEGIN
k(12) := true;
assert NOT(k(12)=true)
report "***PASSED TEST: c03s02b01x00p09n03i00342"
severity NOTE;
assert ( k(12)=true )
report "***FAILED TEST: c03s02b01x00p09n03i00342 - The values in the given index range are not the values that belong to the corresponding range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n03i00342arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1046.vhd | 4 | 1839 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1046.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01046ent IS
END c06s04b00x00p03n01i01046ent;
ARCHITECTURE c06s04b00x00p03n01i01046arch OF c06s04b00x00p03n01i01046ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A1'(others=>TRUE)(2);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01046 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01046arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd | 4 | 2372 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc563.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:32 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:04 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00563ent IS
END c03s04b01x00p01n01i00563ent;
ARCHITECTURE c03s04b01x00p01n01i00563arch OF c03s04b01x00p01n01i00563ent IS
type severity_level_file is file of severity_level;
BEGIN
TESTING: PROCESS
file filein : severity_level_file open write_mode is "iofile.17";
BEGIN
for i in 1 to 100 loop
write(filein,note);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00563 - The output file will be verified by test s010208.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00563arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1279.vhd | 4 | 1644 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1279.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01279ent IS
END c08s04b00x00p04n01i01279ent;
ARCHITECTURE c08s04b00x00p04n01i01279arch OF c08s04b00x00p04n01i01279ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
5.2E1 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01279 - Literal expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01279arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd | 4 | 2329 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2326.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i02326ent IS
END c07s01b00x00p07n01i02326ent;
ARCHITECTURE c07s01b00x00p07n01i02326arch OF c07s01b00x00p07n01i02326ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
wait for 5 ns;
assert NOT( ( r1 = abs(r3)) and
( r2 = abs(r4)) and
( 50.0 = abs(-50.0)) and
( (-25.0) = (-abs(-25.0))) and
( 3.14E-2 = abs(-3.14E-2)) and
( (-0.379) = (-abs(-0.379))) )
report "***PASSED TEST: c07s01b00x00p07n01i02326"
severity NOTE;
assert ( ( r1 = abs(r3)) and
( r2 = abs(r4)) and
( 50.0 = abs(-50.0)) and
( (-25.0) = (-abs(-25.0))) and
( 3.14E-2 = abs(-3.14E-2)) and
( (-0.379) = (-abs(-0.379))) )
report "***FAILED TEST: c07s01b00x00p07n01i02326 - The result of the 'abs' operation must be the absolute value of the operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i02326arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd | 4 | 1363 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity analog_switch is
port ( terminal n1, n2 : electrical;
signal control : in std_ulogic );
end entity analog_switch;
----------------------------------------------------------------
architecture ideal of analog_switch is
quantity v across i through n1 to n2;
begin
if control = '1' or control = 'H' use
v == 0.0;
else
i == 0.0;
end use;
break on control;
end architecture ideal;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd | 4 | 30719 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : clock.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Digital clock with 50% duty cycle
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clock is
generic (
period : time); -- Clock period
port (
clk_out : out std_logic);
end entity clock;
architecture ideal of clock is
begin
CreateClock: process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process CreateClock;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Z-domain Lead Lag Filter
--
-- Z-Domain Transfer Function:
--
-- Y(z) a0(z) - a1(z-1)
-- ---- = k * ---------------
-- X(z) b0(z) - b1(z-1)
--
-- Normalizing Gain = k
--
-- Difference Equation:
--
-- Y(K) = AX(k) - BX(k-1) + CY(k-1)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity lead_lag_diff is
port (
signal clk : in std_logic; -- clock
terminal input: electrical;
terminal output: electrical);
end entity lead_lag_diff;
architecture bhv of lead_lag_diff is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
CONSTANT k : real := 400.0; -- Normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
variable z_new : real := 0.0; -- New output value this clk cycle
begin -- proc
zo_dly1 := z_out; -- Store previous output value
z_new := 0.6163507*vin - 0.6144184*zi_dly1 + 0.2307692*zo_dly1;
zi_dly1 := vin; -- Store previous input value
z_out <= z_new;
end process;
vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
end bhv;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo_z is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo_z;
architecture rudder_servo_z of rudder_servo_z is
-- Component declarations
-- Signal declarations
signal clk : std_logic;
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
clock1 : entity work.clock(ideal)
generic map(
period => 200us
)
port map(
CLK_OUT => clk
);
XCMP23 : entity work.lead_lag_diff(bhv)
port map(
input => ll_in,
output => limit_in,
clk => clk
);
end rudder_servo_z;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Z_Domain_Diff is
end TB_CS2_Z_Domain_Diff;
architecture TB_CS2_Z_Domain_Diff of TB_CS2_Z_Domain_Diff is
-- Component declarations
-- Signal declarations
terminal ctl_horn_in : rotational;
terminal fb_rot2v : electrical;
terminal gear_in : rotational_v;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
gear1 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => gear_in,
rot2 => ctl_horn_in
);
gain_fb : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => fb_rot2v,
input => ctl_horn_in
);
gear_horn : entity work.horn_r2t(bhv)
port map(
theta => ctl_horn_in,
pos => link_in
);
rudder_horn : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
r_wind => 2.2,
kt => 3.43e-3,
l => 2.03e-3,
d => 5.63e-6,
j => 168.0e-9
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => gear_in
);
stop1 : entity work.stop_r(ideal)
generic map(
damp_stop => 1.0e2,
k_stop => 1.0e6,
ang_max => 1.05,
ang_min => -1.05
)
port map(
ang1 => ctl_horn_in,
ang2 => ROTATIONAL_REF
);
\Linkage\ : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP5 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
rudder_servo_z1 : entity work.rudder_servo_z
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => fb_rot2v
);
v3 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Z_Domain_Diff;
--
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2056.vhd | 4 | 1743 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2056.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02056ent IS
END c07s02b04x00p01n01i02056ent;
ARCHITECTURE c07s02b04x00p01n01i02056arch OF c07s02b04x00p01n01i02056ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV: ADDRESS;
BEGIN
ADDRESSV := ADDRESSV - NULL;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02056 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02056arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd | 4 | 1933 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc376.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00376ent IS
END c03s02b01x01p03n03i00376ent;
ARCHITECTURE c03s02b01x01p03n03i00376arch OF c03s02b01x01p03n03i00376ent IS
type my_word is array (0 to 3) of bit;
type it is array (integer range my_word'range) of bit;
BEGIN
TESTING: PROCESS
variable itt : it;
BEGIN
assert NOT(itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0')
report "***PASSED TEST: c03s02b01x01p03n03i00376"
severity NOTE;
assert (itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0')
report "***FAILED TEST: c03s02b01x01p03n03i00376 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00376arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd | 4 | 1762 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2331.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02331ent IS
END c07s02b07x00p02n02i02331ent;
ARCHITECTURE c07s02b07x00p02n02i02331arch OF c07s02b07x00p02n02i02331ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 5;
BEGIN
k := 2 ** 2;
assert NOT(k=4)
report "***PASSED TEST: c07s02b07x00p02n02i02331"
severity NOTE;
assert (k=4)
report "***FAILED TEST: c07s02b07x00p02n02i02331 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02331arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2636.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2636.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02636ent IS
END c13s03b01x00p02n01i02636ent;
ARCHITECTURE c13s03b01x00p02n01i02636arch OF c13s03b01x00p02n01i02636ent IS
BEGIN
TESTING: PROCESS
variable k>k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02636 - Identifier can not contain '>'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02636arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1275.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1275.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01275ent IS
END c08s04b00x00p04n01i01275ent;
ARCHITECTURE c08s04b00x00p04n01i01275arch OF c08s04b00x00p04n01i01275ent IS
signal S1,S2,S3 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1 > S2 <= S3;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01275 - Relational expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01275arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3004.vhd | 4 | 1985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3004.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p06n02i03004pkg is
constant C1 : integer := 10;
end c02s06b00x00p06n02i03004pkg;
package body c02s06b00x00p06n02i03004pkg is
constant C2 : integer := 0;
end;
use work.c02s06b00x00p06n02i03004pkg.all;
ENTITY c02s06b00x00p06n02i03004ent IS
END c02s06b00x00p06n02i03004ent;
ARCHITECTURE c02s06b00x00p06n02i03004arch OF c02s06b00x00p06n02i03004ent IS
BEGIN
TESTING: PROCESS
variable A1 : integer := work.c02s06b00x00p06n02i03004pkg.C1;
variable A2 : integer := workc02s06b00x00p06n02i03004pkg.C2; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p06n02i03004 - Items declared in the body of the package cannot be made visible outside the package body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p06n02i03004arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_standard/simple-now-test.vhdl | 4 | 344 | entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
wait for 1 ns;
assert now = 1 ns report "TEST FAILED" severity FAILURE;
wait for 10 ns;
assert now = 11 ns report "TEST FAILED" severity FAILURE;
report "PASSED TEST" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd | 4 | 10449 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc857.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00857pkg_2;
package body c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00857pkg_2;
use work.c01s03b01x00p12n01i00857pkg_2.all;
package c01s03b01x00p12n01i00857pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00857pkg;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
entity c01s03b01x00p12n01i00857ent_a is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00857ent_a of c01s03b01x00p12n01i00857ent_a is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration c01s03b01x00p12n01i00857ent_abench of c01s03b01x00p12n01i00857ent_a is
for c01s03b01x00p12n01i00857ent_a
end for;
end;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
ENTITY c01s03b01x00p12n01i00857ent IS
END c01s03b01x00p12n01i00857ent;
ARCHITECTURE c01s03b01x00p12n01i00857arch OF c01s03b01x00p12n01i00857ent IS
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00857"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00857 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00857arch;
configuration c01s03b01x00p12n01i00857cfg of c01s03b01x00p12n01i00857ent is
for c01s03b01x00p12n01i00857arch
for K
for T5:c01s03b01x00p12n01i00857ent_a use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
for G(dumy'low to 3)
for T1:c01s03b01x00p12n01i00857ent_a
use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd | 4 | 1561 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1234.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01234ent IS
END c08s02b00x00p03n01i01234ent;
ARCHITECTURE c08s02b00x00p03n01i01234arch OF c08s02b00x00p03n01i01234ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 5;
BEGIN
assert ((k+1) < (k-3))
report "***PASSED TEST: c08s02b00x00p03n01i01234"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01234arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1588.vhd | 4 | 1632 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1588.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01588ent IS
END c08s11b00x00p03n01i01588ent;
ARCHITECTURE c08s11b00x00p03n01i01588arch OF c08s11b00x00p03n01i01588ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
end loop;
exit L;
assert FALSE
report "***FAILED TEST: c08s11b00x00p03n01i01588 - An EXIT statement with a loop label must be in a loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01588arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1477.vhd | 4 | 1919 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1477.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01477ent IS
END c08s08b00x00p04n01i01477ent;
ARCHITECTURE c08s08b00x00p04n01i01477arch OF c08s08b00x00p04n01i01477ent IS
BEGIN
TESTING: PROCESS
variable r1 : real := 0.1;
BEGIN
case r1 is -- illegal, must be discrete
when 0.0 to 1.0 =>
assert false
report "REAL allowed as case expression."
severity note ;
when others =>
assert false
report "REAL allowed as case expression."
severity note ;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p04n01i01477 - Real type is not allowed in expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01477arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket89/x_ieee_proposed/src/standard_additions_c.vhdl | 3 | 63492 | ------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd | 4 | 1897 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01459ent IS
END c08s07b00x00p04n01i01459ent;
ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
begin
transmit: process
variable delay : integer := 1;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 4 then
n := 1;
end if;
assert NOT((m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01459"
severity NOTE;
assert (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01459arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd | 4 | 2581 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tb_moving_mass is
end tb_moving_mass;
architecture TB_moving_mass of tb_moving_mass is
-- Component declarations
-- Signal declarations
terminal msd_discrete, msd_mdl : translational;
begin
-- Signal assignments
-- Component instances
mass1 : entity work.mass_t(ideal)
generic map(
m => 10.0
)
port map(
trans1 => msd_discrete
);
spring2 : entity work.spring_t(linear)
generic map(
k => 2.0
)
port map(
trans1 => msd_discrete,
trans2 => TRANSLATIONAL_REF
);
damper1 : entity work.damper_t(ideal)
generic map(
d => 5.0
)
port map(
trans1 => msd_discrete,
trans2 => TRANSLATIONAL_REF
);
Force1 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => msd_discrete,
trans_neg => TRANSLATIONAL_REF
);
Force2 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => msd_mdl,
trans_neg => TRANSLATIONAL_REF
);
moving_mass4 : entity work.moving_mass_wa(behavioral)
port map(
external_attachment => msd_mdl
);
end TB_moving_mass;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd | 4 | 1746 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc206.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p08n01i00206ent IS
type i is range 3 downto 1;
END c03s01b00x00p08n01i00206ent;
ARCHITECTURE c03s01b00x00p08n01i00206arch OF c03s01b00x00p08n01i00206ent IS
constant r:i:=2;
BEGIN
TESTING: PROCESS
variable m:i;
BEGIN
m := i'leftof(r);
assert NOT( m=3 )
report "***PASSED TEST: c03s01b00x00p08n01i00206"
severity NOTE;
assert ( m=3 )
report "***FAILED TEST: c03s01b00x00p08n01i00206 - Left of the value testing failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p08n01i00206arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2337.vhd | 4 | 1671 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2337.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02337ent IS
END c07s02b07x00p02n02i02337ent;
ARCHITECTURE c07s02b07x00p02n02i02337arch OF c07s02b07x00p02n02i02337ent IS
BEGIN
TESTING: PROCESS
variable SEVERV : SEVERITY_LEVEL := NOTE;
variable INTV : INTEGER;
BEGIN
INTV := SEVERV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02337 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02337arch;
| gpl-2.0 |
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