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peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd | 3 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p06n02i02369ent IS
END c07s03b01x00p06n02i02369ent;
ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( bit_vector'(O"4777") = B"100_111_111_111" )
report "***PASSED TEST: c07s03b01x00p06n02i02369"
severity NOTE;
assert ( bit_vector'(O"4777") = B"100_111_111_111" )
report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p06n02i02369arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc971.vhd | 4 | 2196 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc971.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00971ent IS
END c06s03b00x00p05n01i00971ent;
ARCHITECTURE c06s03b00x00p05n01i00971arch OF c06s03b00x00p05n01i00971ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
RE2: INTEGER;
RE3: BIT;
RE4: SEVERITY_LEVEL;
RE5: REAL;
RE6: CHARACTER;
RE7: TIME;
end record;
variable V1: BOOLEAN;
variable V2: INTEGER;
variable V3: BIT;
variable V4: SEVERITY_LEVEL;
variable V5: REAL;
variable V6: CHARACTER;
variable V7: TIME;
BEGIN
V1 := RE1;
V2 := RE2;
V3 := RE3;
V4 := RE4;
V5 := RE5;
V6 := RE6;
V7 := RE7;
-- ERROR: RECORD ELEMENT NAME CANNOT BE USED BY ITSELF
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00971 - Record element name cannot be used by itself as an expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00971arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1137.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n02i01137ent IS
type aray1 is array (integer range <>) of bit;
END c06s05b00x00p04n02i01137ent;
ARCHITECTURE c06s05b00x00p04n02i01137arch OF c06s05b00x00p04n02i01137ent IS
BEGIN
TESTING: PROCESS
variable nul : aray1(2 to 1); -- null array
variable nu2 : aray1(9 to 1); -- null array
BEGIN
--
-- Test the range direction
--
assert NOT(nul = nu2)
report "***PASSED TEST: c06s05b00x00p04n02i01137"
severity NOTE;
assert (nul = nu2)
report "***FAILED TEST: c06s05b00x00p04n02i01137- The slice is a null slice if the discrete range is a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n02i01137arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc847.vhd | 4 | 2415 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc847.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and2g is
end and2g;
architecture behavior of and2g is
begin
end behavior;
entity full_adder is
end full_adder;
architecture structural of full_adder is
component and2
end component;
begin
C1: and2;
end structural;
ENTITY c01s03b01x00p08n01i00847ent IS
END c01s03b01x00p08n01i00847ent;
ARCHITECTURE c01s03b01x00p08n01i00847arch OF c01s03b01x00p08n01i00847ent IS
component adder
end component;
BEGIN
A1 : adder;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p08n01i00847 - Architecture name in block configuration does not match block specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p08n01i00847arch;
configuration c01s03b01x00p08n01i00847cfg of c01s03b01x00p08n01i00847ent is
for c01s03b01x00p08n01i00847arch
for A1: adder use -- component configuration
entity work.full_adder(structural);
for bad_block_spec -- failure_here
for C1: and2 use
entity work.and2g(behavior);
end for;
end for;
end for;
end for;
end c01s03b01x00p08n01i00847cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc231.vhd | 4 | 1655 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc231.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00231ent IS
END c03s01b02x00p02n01i00231ent;
ARCHITECTURE c03s01b02x00p02n01i00231arch OF c03s01b02x00p02n01i00231ent IS
type a is range (1+1) to (10.0 + 20.0);
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p02n01i00231 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00231arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd | 4 | 2460 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity PLL is
generic ( Fp : real := 20.0e3; -- loop filter pole freq [Hz]
Fz : real := 1.0e6; -- loop filter zero freq [Hz]
Kv : real := 100.0e3; -- VCO gain [Hz/V]
Fc : real := 1.0e6 ); -- VCO center freq [Hz]
port ( terminal input, lf_out, vco_out : electrical );
end entity PLL;
----------------------------------------------------------------
architecture behavioral of PLL is
quantity v_in across input to electrical_ref;
quantity v_lf across i_lf through lf_out to electrical_ref;
quantity v_vco across i_vco through vco_out to electrical_ref;
-- internal quantities and constants
-- multiplier
quantity mult : real;
-- loop filter (Lag)
constant wp : real := math_2_pi * fp; -- pole freq in rad/s
constant wz : real := math_2_pi * fz; -- zero freq in rad/s
constant num : real_vector := (1.0, 1.0 / wz); -- numerator array
constant den : real_vector := (1.0, 1.0 / wp); -- denominator array
-- VCO
quantity phi : real; -- used in VCO equation
constant Kv_w : real := math_2_pi * Kv; -- change gain to (rad/s)/V
constant wc : real := math_2_pi * Fc; -- change freq to rad/s
begin
if domain = quiescent_domain use
phi == 0.0; -- initialize phi
else
phi'dot == wc + Kv_w * (v_lf); -- calculate VCO frequency
end use;
mult == v_in * v_vco; -- multiplier output
v_lf == mult'ltf(num, den); -- loop filter output
v_vco == cos(phi); -- VCO output
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd | 4 | 2273 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_06 is
end entity ch_16_06;
----------------------------------------------------------------
architecture test of ch_16_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2634.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2634.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02634ent IS
END c13s03b01x00p02n01i02634ent;
ARCHITECTURE c13s03b01x00p02n01i02634arch OF c13s03b01x00p02n01i02634ent IS
BEGIN
TESTING: PROCESS
variable k/k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02634 - Identifier can not contain '/'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02634arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd | 4 | 2201 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2091.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02091ent IS
END c07s02b04x00p20n01i02091ent;
ARCHITECTURE c07s02b04x00p20n01i02091arch OF c07s02b04x00p20n01i02091ent IS
TYPE bit_v is array (integer range <>) of bit;
SUBTYPE bit_8 is bit_v (1 to 8);
SUBTYPE bit_4 is bit_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : bit_4;
variable l_operand : bit_4 := ('1','0','1','0');
variable r_operand : bit_4 := ('0','0','1','1');
alias l_alias : bit_v (1 to 2) is l_operand (2 to 3);
alias r_alias : bit_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 5 ns;
assert NOT((result = ('0','1','1','1')) and (result(1) = '0'))
report "***PASSED TEST: c07s02b04x00p20n01i02091"
severity NOTE;
assert ((result = ('0','1','1','1')) and (result(1) = '0'))
report "***FAILED TEST: c07s02b04x00p20n01i02091 - Concatenation of two BOOLEAITses failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02091arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd | 4 | 1793 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2181.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02181ent IS
END c07s02b05x00p01n02i02181ent;
ARCHITECTURE c07s02b05x00p01n02i02181arch OF c07s02b05x00p01n02i02181ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
variable m : real := 5.5;
BEGIN
k := abs (-m);
assert NOT( k = 5.5 )
report "***PASSED TEST: c07s02b05x00p01n02i02181"
severity NOTE;
assert ( k = 5.5 )
report "***FAILED TEST: c07s02b05x00p01n02i02181 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02181arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd | 4 | 1404 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type log_file is file of string;
-- code from book:
file log_info : log_file open write_mode is "logfile";
-- end of code from book
begin
process is
begin
write(log_info, string'("AAAA"));
wait for 1 ns;
write(log_info, string'("BBBB"));
wait;
end process;
process is
begin
write(log_info, string'("CCCC"));
wait for 1 ns;
write(log_info, string'("DDDD"));
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd | 4 | 2452 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc777.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p10n01i00777ent_a IS
port (A : linkage integer;
B : linkage integer;
C : linkage integer;
D : linkage integer);
END c01s01b01x02p10n01i00777ent_a;
ARCHITECTURE c01s01b01x02p10n01i00777arch_a OF c01s01b01x02p10n01i00777ent_a IS
BEGIN
test : process
begin
wait;
end process test;
END c01s01b01x02p10n01i00777arch_a;
ENTITY c01s01b01x02p10n01i00777ent IS
port (X : linkage integer;
Y : buffer integer;
Z : inout integer);
END c01s01b01x02p10n01i00777ent;
ARCHITECTURE c01s01b01x02p10n01i00777arch OF c01s01b01x02p10n01i00777ent IS
component c01s01b01x02p10n01i00777ent_b
port (A : linkage integer;
B : linkage integer;
C : linkage integer;
D : linkage integer);
end component;
for L : c01s01b01x02p10n01i00777ent_b use entity work.c01s01b01x02p10n01i00777ent_a(c01s01b01x02p10n01i00777arch_a);
signal M : integer;
BEGIN
L:c01s01b01x02p10n01i00777ent_b port map
( A => M,
B => X,
C => Y,
D => Z);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p10n01i00777"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p10n01i00777arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd | 4 | 1642 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1508.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01508ent IS
END c08s09b00x00p02n01i01508ent;
ARCHITECTURE c08s09b00x00p02n01i01508arch OF c08s09b00x00p02n01i01508ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
loop
k := k + 1;
if k > 500 then
exit;
end if;
end loop;
assert FALSE
report "***PASSED TEST: c08s09b00x00p02n01i01508"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01508arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd | 4 | 1864 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity flipflop is
generic ( Tsetup : delay_length );
port ( clk, d : in bit; q : out bit );
end entity flipflop;
-- code from book
architecture behavior of flipflop is
begin
timing_check : process (clk) is
begin
if clk = '1' then
assert d'last_event >= Tsetup
report "set up violation detected in " & timing_check'path_name
severity error;
end if;
end process timing_check;
-- . . . -- functionality
end architecture behavior;
-- end code from book
entity fg_20_05 is
end entity fg_20_05;
architecture test of fg_20_05 is
signal clk, d, q : bit;
begin
dut : entity work.flipflop(behavior)
generic map ( Tsetup => 3 ns )
port map ( clk => clk, d => d, q => q );
clk <= '1' after 10 ns, '0' after 20 ns;
d <= '1' after 8 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2274.vhd | 4 | 2193 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2274.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02274ent IS
END c07s02b06x00p14n01i02274ent;
ARCHITECTURE c07s02b06x00p14n01i02274arch OF c07s02b06x00p14n01i02274ent IS
BEGIN
TESTING: PROCESS
type SINGLE_NUMERIC_ARRAY is array ( 1 to 1 ) of REAL;
function F ( A : SINGLE_NUMERIC_ARRAY ) return SINGLE_NUMERIC_ARRAY is
variable B : TIME := 1 sec;
begin
return A * B; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other
-- must be integer or floating point.
end F;
variable A : SINGLE_NuMERIC_ARRAY;
variable T : TIME := 1 sec;
BEGIN
T := 1 MS * F(A); -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02274 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02274arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1025.vhd | 4 | 2016 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1025.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n02i01025ent IS
END c06s03b00x00p10n02i01025ent;
ARCHITECTURE c06s03b00x00p10n02i01025arch OF c06s03b00x00p10n02i01025ent IS
BEGIN
B1 : block
constant C : integer := 10;
begin
B2 : block
constant C : integer := B1.c; -- Ok
begin
process
begin
null;
end process;
end block;
B3 : block
constant C : integer := B1.c; -- Ok
constant Bad_C : integer := B2.c;
-- Error : Initialization Expression is not visible.
begin
process
begin
null;
end process;
end block;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01025 - Expanded name visible only in the construct."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n02i01025arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd | 4 | 6568 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1359.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01359ent IS
END c08s05b00x00p03n01i01359ent;
ARCHITECTURE c08s05b00x00p03n01i01359arch OF c08s05b00x00p03n01i01359ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01359"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01359 - Target of a variable assignment is not a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01359arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd | 4 | 1808 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1729.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01729ent IS
END c09s03b00x00p02n01i01729ent;
ARCHITECTURE c09s03b00x00p02n01i01729arch OF c09s03b00x00p02n01i01729ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01729"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01729 - A label can be used before a procedure call statement."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
L1 : check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01729arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1057.vhd | 4 | 1885 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1057.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01057ent IS
END c06s04b00x00p03n02i01057ent;
ARCHITECTURE c06s04b00x00p03n02i01057arch OF c06s04b00x00p03n02i01057ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A21 is array (THREE, THREE) of BOOLEAN;
variable V1: BOOLEAN;
variable V21: A21 ;
BEGIN
V1 := V21(3, 2, 1); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01057 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01057arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2340.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2340.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02340ent IS
END c07s02b07x00p02n02i02340ent;
ARCHITECTURE c07s02b07x00p02n02i02340arch OF c07s02b07x00p02n02i02340ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable INTV : INTEGER;
BEGIN
INTV := BYTEV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02340 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02340arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd | 4 | 3133 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00695ent IS
END c03s04b01x00p23n01i00695ent;
ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BOOLEAN;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.10";
-- Declare a variable into which we will read.
constant CON : BOOLEAN := TRUE;
variable VAR : BOOLEAN;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00695"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00695arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd | 4 | 1900 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1496.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01496ent IS
END c08s08b00x00p14n01i01496ent;
ARCHITECTURE c08s08b00x00p14n01i01496arch OF c08s08b00x00p14n01i01496ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable p : integer := 0;
BEGIN
case p is
when 0 => k := 5;
when 1 => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p14n01i01496"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p14n01i01496 - Simple expression and discrete range given as choice in a case statement must be locally static"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01496arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd | 4 | 2678 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity computer_system is
end entity computer_system;
-- code from book
architecture abstract of computer_system is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- re-enable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu datapath processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd | 4 | 1859 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02421ent IS
END c07s03b02x01p01n01i02421ent;
ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
BEGIN
TESTING: PROCESS
type rec is record
a: integer;
b: real;
end record;
constant y: rec := (a => 12, b => 12.0);
BEGIN
assert NOT(y.a=12 and y.b=12.0)
report "***PASSED TEST: c07s03b02x01p01n01i02421"
severity NOTE;
assert (y.a=12 and y.b=12.0)
report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02421arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2521.vhd | 4 | 1821 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2521.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p03n04i02521ent IS
END c07s03b05x00p03n04i02521ent;
ARCHITECTURE c07s03b05x00p03n04i02521arch OF c07s03b05x00p03n04i02521ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
variable Macintosh : Apples;
variable Seville, valencia : Oranges;
BEGIN
Macintosh := Apples (Seville) ;
Seville := Oranges (Macintosh,10) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p03n04i02521 - Multiple expression are not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p03n04i02521arch;
| gpl-2.0 |
peteut/ghdl | libraries/std/env.vhdl | 5 | 1071 | -- Std.Env package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package Env is
procedure Stop (Status : Integer);
procedure Stop;
procedure Finish (status : Integer);
procedure Finish;
function Resolution_Limit return Delay_Length;
end package Env;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1093.vhd | 4 | 1703 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1093.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01093ent IS
END c06s05b00x00p03n01i01093ent;
ARCHITECTURE c06s05b00x00p03n01i01093arch OF c06s05b00x00p03n01i01093ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is range 1 to 10;
variable NUM1 : BIT_VECTOR;
BEGIN
NUM1(0 to 1) := 0; -- illegal.
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01093 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01093arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd | 4 | 1610 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc170.vhd | 4 | 1736 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc170.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00170ent IS
END c04s03b03x01p03n01i00170ent;
ARCHITECTURE c04s03b03x01p03n01i00170arch OF c04s03b03x01p03n01i00170ent IS
type x is range 1 to 10;
signal Addr : bit;
alias SIGN1 : x is x; -- fails_here
alias SIGN2 : bit is Addr;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b03x01p03n01i00170 - The name referred to in the alias declaration for SIGN1 is not a static name that refers to an object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00170arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd | 4 | 1673 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17 is
end entity inline_17;
----------------------------------------------------------------
architecture test of inline_17 is
signal s, r, q, q_n : bit := '0';
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
-- code from book:
check : process is
begin
assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
wait on s, r;
end process check;
-- end of code from book
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd | 4 | 3143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc655.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:21 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:33 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00655ent IS
END c03s04b01x00p01n01i00655ent;
ARCHITECTURE c03s04b01x00p01n01i00655arch OF c03s04b01x00p01n01i00655ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_range is integer_vector(hi_to_low_range);
constant C1 : integer_vector_range := (others => 3);
type integer_vector_range_file is file of integer_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_range_file open read_mode is "iofile.03";
variable v : integer_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00655"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00655 - File reading of integer_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00655arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd | 4 | 2125 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
library star_lib;
--use star_lib.edge_triggered_dff;
use star_lib.all;
configuration full of counter is
for registered -- architecture of counter
for all : digit_register
use entity work.reg4(struct);
for struct -- architecture of reg4
for bit0 : flipflop
use entity edge_triggered_Dff(hi_fanout);
end for;
for others : flipflop
use entity edge_triggered_Dff(basic);
end for;
end for; -- end of architecture struct
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration full;
-- not in book
entity fg_13_08 is
end entity fg_13_08;
use work.counter_types.all;
architecture test of fg_13_08 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.full
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc391.vhd | 4 | 1837 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc391.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n01i00391ent IS
END c03s02b01x01p06n01i00391ent;
ARCHITECTURE c03s02b01x01p06n01i00391arch OF c03s02b01x01p06n01i00391ent IS
type I1 is range 1 to 1;
type A1 is array (integer range <>) of bit;
BEGIN
TESTING: PROCESS
variable V2: A1 := B"00"; -- Failure_here
-- ERROR - SEMANTIC ERROR: SUBTYPE INDICATION OF ARRAY OBJECT DECLARATION
-- MUST DENOTE A CONSTRAINED ARRAY
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p06n01i00391 - Subtype indication of array object declaration must denote a constrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n01i00391arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1102.vhd | 4 | 2040 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1102.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01102ent IS
END c06s05b00x00p03n01i01102ent;
ARCHITECTURE c06s05b00x00p03n01i01102arch OF c06s05b00x00p03n01i01102ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(others=>TRUE) (2 to 4);
-- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01102 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01102arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd | 4 | 2016 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02286ent IS
END c07s02b06x00p14n01i02286ent;
ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 100000
units
A;
B = 100 A;
C = 100 B;
end units;
function F_PHYS ( A : PHYS ) return PHYS is
begin
return A;
end F_PHYS;
variable P : PHYS := 1 B;
variable Z : integer := time'(1 min) / time'(27 sec);
BEGIN
Z := P / F_PHYS(1 A);
assert NOT(Z = 100)
report "***PASSED TEST: c07s02b06x00p14n01i02286"
severity NOTE;
assert (Z = 100)
report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02286arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd | 4 | 4822 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_ch_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end buf;
architecture basic of buf is
begin
y <= a;
end basic;
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end fanout_tree;
--------------------------------------------------
architecture recursive of fanout_tree is
component buf
port ( a : in std_logic; y : out std_logic );
end component;
component fanout_tree
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end component;
signal buffered_input_0, buffered_input_1 : std_logic;
begin
degenerate_tree : if height = 0 generate
output(0) <= input;
end generate degenerate_tree;
compound_tree : if height > 0 generate
buf_0 : buf
port map ( a => input, y => buffered_input_0 );
-- code from book
block_0 : block
for subtree_0 : fanout_tree
use entity work.fanout_tree(recursive);
begin
subtree_0 : fanout_tree
generic map ( height => height - 1 )
port map ( input => buffered_input_0,
output => output(0 to 2**(height - 1) - 1) );
end block block_0;
-- end code from book
buf_1 : buf
port map ( a => input, y => buffered_input_1 );
block_1 : block
for subtree_1 : fanout_tree
use entity work.fanout_tree(recursive);
begin
subtree_1 : fanout_tree
generic map ( height => height - 1 )
port map ( input => buffered_input_1,
output => output(2**(height - 1) to 2**height - 1) );
end block block_1;
end generate compound_tree;
end recursive;
library ieee; use ieee.std_logic_1164.all;
entity ch_14_01 is
end ch_14_01;
architecture test of ch_14_01 is
component fanout_tree
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end component;
for clock_buffer_tree : fanout_tree
use entity work.fanout_tree(recursive);
signal unbuffered_clock : std_logic;
signal buffered_clock_array : std_logic_vector(0 to 7);
begin
clock_buffer_tree : fanout_tree
generic map ( height => 3 )
port map ( input => unbuffered_clock,
output => buffered_clock_array );
clock_gen : process
begin
unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
end process clock_gen;
end test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1741.vhd | 4 | 1720 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1741.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p02n01i01741ent IS
port (clk : inout bit);
END c09s05b00x00p02n01i01741ent;
ARCHITECTURE c09s05b00x00p02n01i01741arch OF c09s05b00x00p02n01i01741ent IS
constant period : Time := 50 ns;
BEGIN
osc clk <= not clk after period/2; -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p02n01i01741 - Colon is missing between the label and concurrent signal assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p02n01i01741arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-variable.vhdl | 4 | 362 | entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 1;
variable y : integer := 2;
begin -- process
x := x + y;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd | 4 | 1765 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.serial_interface_defs.all;
entity serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end entity serial_interface;
-- not in book
architecture test of serial_interface is
begin
end architecture test;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl | 4 | 371 | entity test_output is
port (
output : inout bit_vector( 1 downto 0 ) := "10"
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = "10" report "test failed" severity error;
assert output /= "10" report "test passed" severity note;
wait;
end process test;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd | 4 | 2228 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2290.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02290ent IS
END c07s02b06x00p32n01i02290ent;
ARCHITECTURE c07s02b06x00p32n01i02290arch OF c07s02b06x00p32n01i02290ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ms;
assert NOT( ((1 ms * 1000) = 1 sec) and
((1 sec * 60) = 1 min) and
((1 min * 60) = 1 hr) and
((1000 * 1 ms) = 1 sec) and
((60 * 1 sec) = 1 min) and
((60 * 1 min) = 1 hr))
report "***PASSED TEST: c07s02b06x00p32n01i02290"
severity NOTE;
assert ( ((1 ms * 1000) = 1 sec) and
((1 sec * 60) = 1 min) and
((1 min * 60) = 1 hr) and
((1000 * 1 ms) = 1 sec) and
((60 * 1 sec) = 1 min) and
((60 * 1 min) = 1 hr))
report "***FAILED TEST: c07s02b06x00p32n01i02290 - Multiplication of a predefined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02290arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2908.vhd | 4 | 1778 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2908.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02908ent IS
END c02s01b01x02p03n01i02908ent;
ARCHITECTURE c02s01b01x02p03n01i02908arch OF c02s01b01x02p03n01i02908ent IS
function func1 (signal S1: in bit) return bit is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a function
V1 := S1'delayed;
end func1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02908 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02908arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd | 4 | 2091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s04b02x00p02n01i03065ent IS
END c12s04b02x00p02n01i03065ent;
ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
type intvector is array (natural range <>) of integer;
signal V2 : intvector(1 to 5);
signal V0 : integer := 66;
BEGIN
FG2: for i in V2'range generate
IG1: if i = V2'left generate
V2(i) <= V0 after 1 ns;
end generate;
IG2: if i /= V2'left generate
V2(i) <= V2(i-1) after 1 ns;
end generate;
-- ..., V2(2) <= V2(1), V2(1) <= V0
end generate;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( V2 = (66,66,66,66,66) )
report "***PASSED TEST: c12s04b02x00p02n01i03065"
severity NOTE;
assert ( V2 = (66,66,66,66,66) )
report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
severity ERROR;
END PROCESS TESTING;
END c12s04b02x00p02n01i03065arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1676.vhd | 4 | 1662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1676.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p07n01i01676ent IS
port (p: in boolean);
END c09s01b00x00p07n01i01676ent;
ARCHITECTURE c09s01b00x00p07n01i01676arch OF c09s01b00x00p07n01i01676ent IS
BEGIN
B: block (p)
begin
GUARD <= p; -- Failure_here
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p07n01i01676 - Implicit signal GUARD can not have a source."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p07n01i01676arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1377.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1377.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01377ent IS
END c08s05b00x00p03n01i01377ent;
ARCHITECTURE c08s05b00x00p03n01i01377arch OF c08s05b00x00p03n01i01377ent IS
BEGIN
TESTING: PROCESS
type type1 is range 1 to 10;
variable v1 : type1 := 1;
BEGIN
--
-- The following variable assignment is illegal and
-- should generate an out-of-range error.
--
v1 := 0; -- zero is out of range
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01377 - Right-hand-side expression is out of range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01377arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1481.vhd | 4 | 1812 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1481.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01481ent IS
END c08s08b00x00p04n01i01481ent;
ARCHITECTURE c08s08b00x00p04n01i01481arch OF c08s08b00x00p04n01i01481ent IS
BEGIN
TESTING: PROCESS
function f return boolean is
variable v1 : natural := 6;
begin
case v1 is
when -1 to 5 => -- error : range violates constraint
return true;
when others =>
return false;
end case;
end f;
BEGIN
assert FALSE
report "***FAILED TEST: c08s08b00x00p04n01i01481 - Static range violation."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01481arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd | 4 | 2351 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity bidir_buffer is
port ( bidir : inout std_logic;
ena : in std_ulogic;
going_out : in std_ulogic;
coming_in : out std_ulogic );
end entity bidir_buffer;
--------------------------------------------------
architecture behavior of bidir_buffer is
begin
bidir <= going_out when ena = '1' else
'Z';
coming_in <= bidir;
end architecture behavior;
-- end code from book
entity fg_a_07 is
end entity fg_a_07;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_07 is
signal bidir : std_logic;
signal ena, going_out, coming_in : std_ulogic;
begin
dut : entity work.bidir_buffer
port map ( bidir, ena, going_out, coming_in );
ena <= '0', '1' after 10 ns, '0' after 30 ns;
going_out <= '0', '1' after 20 ns;
bidir <= 'Z', '0' after 40 ns, '1' after 50 ns, 'Z' after 60 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket18/psl_test_error.vhd | 3 | 1067 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_error is
end entity psl_test_error;
architecture test of psl_test_error is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_ERROR test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this don't work (error while analyse)
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd | 4 | 1424 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cos is
end entity tb_cos;
----------------------------------------------------------------
architecture test_fixed_length_series of tb_cos is
signal theta, result : real := 0.0;
begin
dut : entity work.cos(fixed_length_series)
port map ( theta => theta, result => result );
stimulus : process is
constant pi : real := 3.1415927;
begin
wait for 10 ns;
theta <= pi / 6.0; wait for 10 ns;
theta <= pi / 4.0; wait for 10 ns;
theta <= pi / 3.0; wait for 10 ns;
theta <= pi / 2.0; wait for 10 ns;
wait;
end process stimulus;
end architecture test_fixed_length_series;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd | 4 | 1922 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1995.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01995ent IS
END c07s02b02x00p07n01i01995ent;
ARCHITECTURE c07s02b02x00p07n01i01995arch OF c07s02b02x00p07n01i01995ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 260
units
A;
B = 10 A;
C = 10 B;
end units;
variable k : integer := 0;
variable m : PHYS := 10 A;
BEGIN
if (m /= 2 B) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01995"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01995 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01995arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd | 4 | 2550 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
subtype word is bit_vector(0 to 31);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
return drivers(drivers'left);
end function resolve_unique;
signal source1, source2 : resolve_unique word register;
-- . . .
-- not in book
type alu_op_type is (pass1, pass2, add, subtract);
procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
signal source1, source2 : in word;
signal destination : out word;
constant ignored : in integer := 0 ) is
begin
null;
end procedure perform_alu_op;
signal phase1, source1_reg_out_en,other_signal : bit;
signal alu_opcode : alu_op_type;
signal destination : word;
-- end not in book
begin
source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
-- not in book
other_signal) is
-- end not in book
variable stored_value : word;
begin
-- . . .
if source1_reg_out_en = '1' and phase1 = '1' then
source1 <= stored_value;
-- not in book
stored_value := not stored_value;
-- end not in book
else
source1 <= null;
end if;
end process source1_reg;
alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- not in book
process is
begin
wait for 10 ns;
source1_reg_out_en <= '1';
phase1 <= '1', '0' after 10 ns;
wait for 20 ns;
source1_reg_out_en <= '1';
phase1 <= '1', '0' after 10 ns;
wait;
end process;
-- end not in book
end architecture rtl;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd | 4 | 1057 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
----------------------------------------------------------------
library wasp_lib;
-- code from book:
use wasp_lib.all;
-- end of code from book
architecture test of inline_02a is
begin
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2222.vhd | 4 | 1684 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02222ent IS
END c07s02b06x00p01n01i02222ent;
ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02222arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1603.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01603ent IS
END c08s11b00x00p04n01i01603ent;
ARCHITECTURE c08s11b00x00p04n01i01603arch OF c08s11b00x00p04n01i01603ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when i = 6;
k := i;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p04n01i01603"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p04n01i01603 - Exit from the labeled loop when the condition of the WHEN clause evaluates to be true"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01603arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd | 4 | 1557 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity lead_lag_ztf is
generic ( a1 : real := 2.003140;
a2 : real := -1.996860;
b1 : real := 3.250000;
b2 : real := -0.750000;
k : real := 400.0; -- normalizing gain
tsampl : real := 0.1e-3; -- sample period
init_delay : real := 0.0 ); -- optional delay
port ( quantity input : in real;
quantity output : out real );
end entity lead_lag_ztf;
----------------------------------------------------------------
architecture simple of lead_lag_ztf is
constant num: real_vector := (a1, a2);
constant den: real_vector := (b1, b2);
begin
output == k * input'ztf(num, den, tsampl, init_delay); -- implement transfer function
end architecture simple;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd | 4 | 2824 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_02_a is
end entity fg_18_02_a;
architecture writer of fg_18_02_a is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity fg_18_02 is
end entity fg_18_02;
architecture test of fg_18_02 is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2560.vhd | 4 | 1866 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2560.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p05n02i02560ent IS
END c07s03b06x00p05n02i02560ent;
ARCHITECTURE c07s03b06x00p05n02i02560arch OF c07s03b06x00p05n02i02560ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Bit;
SUCC : Bit;
end record;
type T1 is access BIT_VECTOR ;
variable HEAD : LINK := new CELL'('1','0') ;
variable V2 : T1 := new BIT_VECTOR ; --- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b06x00p05n02i02560 - Subtype indication cannot be an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p05n02i02560arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd | 4 | 2379 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3143.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p10n01i03143ent_a IS
generic ( g1 : real := 22.0 );
END c05s02b02x00p10n01i03143ent_a;
ARCHITECTURE c05s02b02x00p10n01i03143arch_a OF c05s02b02x00p10n01i03143ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( g1 = 22.0 )
report "***PASSED TEST: c05s02b02x00p10n01i03143"
severity NOTE;
assert ( g1 = 22.0 )
report "***FAILED TEST: c05s02b02x00p10n01i03143 - The formal generics take on implicit OPENs."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p10n01i03143arch_a;
--
ENTITY c05s02b02x00p10n01i03143ent IS
END c05s02b02x00p10n01i03143ent;
ARCHITECTURE c05s02b02x00p10n01i03143arch OF c05s02b02x00p10n01i03143ent IS
component c05s02b02x00p10n01i03143ent_a
end component;
BEGIN
comp1 : c05s02b02x00p10n01i03143ent_a;
END c05s02b02x00p10n01i03143arch;
configuration c05s02b02x00p10n01i03143cfg of c05s02b02x00p10n01i03143ent is
for c05s02b02x00p10n01i03143arch
for comp1 : c05s02b02x00p10n01i03143ent_a use entity work.c05s02b02x00p10n01i03143ent_a(c05s02b02x00p10n01i03143arch_a)
generic map(OPEN);
end for;
end for;
end c05s02b02x00p10n01i03143cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd | 4 | 7959 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: Based on work by IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.4 JAT 4/15/93
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--synopsys synthesis_off
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
-- attribute FOREIGN: string; -- predefined attribute in VHDL-1992
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns FLOOR(X + 0.5) if X > 0.0;
-- return CEIL(X - 0.5) if X < 0.0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
function SRAND (seed: in integer ) return integer;
-- attribute FOREIGN of SRAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- sets value of seed for sequence of pseudo-random numbers.
-- returns the value of the seed.
-- It uses the native C function srand().
function RAND return integer;
-- attribute FOREIGN of RAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
-- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0.0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integral value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integral value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1.0
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1.0
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1.0
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
--synopsys synthesis_on
end MATH_REAL;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd | 4 | 1557 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
architecture test of inline_05 is
-- code from book
component nand3 is
port ( a, b, c : in bit := '1'; y : out bit );
end component nand3;
-- end code from book
signal s1, s2, s3 : bit;
begin
-- code from book
gate1 : component nand3
port map ( a => s1, b => s2, c => open, y => s3 );
-- end code from book
end architecture test;
-- code from book
entity nand2 is
port ( a, b : in bit := '1'; y : out bit );
end entity nand2;
-- end code from book
configuration inline_05_test of inline_05 is
for test
-- code from book
for gate1 : nand3
use entity work.nand2(basic);
end for;
-- end code from book
end for;
end configuration inline_05_test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1378.vhd | 4 | 1829 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1378.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01378ent IS
END c08s05b00x00p03n01i01378ent;
ARCHITECTURE c08s05b00x00p03n01i01378arch OF c08s05b00x00p03n01i01378ent IS
BEGIN
TESTING: PROCESS
type type1 is range 1 to 10;
variable v1 : type1 := 1;
BEGIN
--
-- The following variable assignment is illegal and
-- should generate a type mis-match error.
--
v1 := 1.0; -- mismatched types
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01378 - Right-hand-side expression type did not match the named variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01378arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1293.vhd | 4 | 1697 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1293.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p05n01i01293ent IS
END c08s04b00x00p05n01i01293ent;
ARCHITECTURE c08s04b00x00p05n01i01293arch OF c08s04b00x00p05n01i01293ent IS
signal done : bit;
BEGIN
TESTING: PROCESS
BEGIN
done <= '1' after 10 ns,
'0' after 20 ns
'1' after 35 ns;
wait for 70 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p05n01i01293 - Waveform elements should be separated by commas."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p05n01i01293arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc834.vhd | 4 | 1815 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc834.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration c01s03b00x00p05n02i00834cfg of c01s03b00x00p05n02i00834ent is --Failure here
for c01s03b00x00p05n02i00834arch
use work.all;
end for;
end for;
--ENTITY c01s03b00x00p05n02i00834ent IS
--END c01s03b00x00p05n02i00834ent;
--
--ARCHITECTURE c01s03b00x00p05n02i00834arch OF c01s03b00x00p05n02i00834ent IS
--
--BEGIN
-- TESTING: PROCESS
-- BEGIN
-- assert FALSE
-- report "***FAILED TEST: c01s03b00x00p05n02i00834 - Configuration declaration and corresponding entity declaration must reside in the same library."
-- severity ERROR;
-- wait;
-- END PROCESS TESTING;
--
--END c01s03b00x00p05n02i00834arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd | 4 | 1198 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11a is
end entity inline_11a;
----------------------------------------------------------------
architecture test of inline_11a is
-- code from book:
type real_vector is array (natural range <>) of real;
--
subtype gains is real_vector(15 downto 0);
--
quantity max_temperatures : real_vector(1 to 10);
-- end of code from book
begin
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd | 4 | 1538 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_mux2 is
end entity tb_mux2;
architecture test of tb_mux2 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd | 4 | 2182 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc684.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:02 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00684ent IS
END c03s04b01x00p23n01i00684ent;
ARCHITECTURE c03s04b01x00p23n01i00684arch OF c03s04b01x00p23n01i00684ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE is range 0 to INTEGER'HIGH;
type FT is file of POSITIVE;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : POSITIVE := 1;
variable VAR : POSITIVE := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00684 - The output file will tested by test file s010414.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00684arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd | 4 | 3385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_03 is
end entity ch_04_03;
----------------------------------------------------------------
architecture test of ch_04_03 is
subtype coeff_ram_address is integer range 0 to 63;
-- code from book:
type coeff_array is array (coeff_ram_address) of real;
-- end of code from book
begin
process_04_1_c : process is
-- code from book:
type point is array (1 to 3) of real;
constant origin : point := (0.0, 0.0, 0.0);
variable view_point : point := (10.0, 20.0, 0.0);
-- end of code from book
begin
wait;
end process process_04_1_c;
process_04_1_d : process is
type point is array (1 to 3) of real;
-- code from book:
variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_d;
process_04_1_e : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_e;
process_04_1_f : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_f;
process_04_1_g : process is
-- code from book:
variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_g;
process_04_1_h : process is
-- code from book:
-- error: Associations in array aggregate must be all named or all positional
-- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal
-- end of code from book
begin
wait;
end process process_04_1_h;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/left/simple-integer-test.vhdl | 4 | 265 | entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'left = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd | 4 | 1556 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd | 4 | 2724 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1932.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01932ent IS
END c07s02b01x00p01n02i01932ent;
ARCHITECTURE c07s02b01x00p01n02i01932arch OF c07s02b01x00p01n02i01932ent IS
SUBTYPE bit_8 is bit_vector(0 to 7);
SUBTYPE bit_4 is bit_vector(0 to 3);
BEGIN
TESTING: PROCESS
CONSTANT slice_8a : bit_8 := B"1010_0011";
VARIABLE slice_8b : bit_8 := B"1110_1001";
VARIABLE target_1 : bit_4;
VARIABLE target_2 : bit_4;
VARIABLE target_3 : bit_4;
VARIABLE target_4 : bit_4;
VARIABLE target_5 : bit_4;
VARIABLE target_6 : bit_4;
BEGIN
target_1 := slice_8a (3 to 6) AND slice_8b (4 to 7);
target_2 := slice_8a (3 to 6) OR slice_8b (4 to 7);
target_3 := slice_8a (3 to 6) NOR slice_8b (4 to 7);
target_4 := slice_8a (3 to 6) NAND slice_8b (4 to 7);
target_5 := slice_8a (3 to 6) XOR slice_8b (4 to 7);
target_6 := NOT slice_8b (0 to 3);
assert NOT(
target_1 = B"0001" and
target_2 = B"1001" and
target_3 = B"0110" and
target_4 = B"1110" and
target_5 = B"1000" and
target_6 = B"0001" )
report "***PASSED TEST: c07s02b01x00p01n02i01932"
severity NOTE;
assert (
target_1 = B"0001" and
target_2 = B"1001" and
target_3 = B"0110" and
target_4 = B"1110" and
target_5 = B"1000" and
target_6 = B"0001" )
report "***FAILED TEST: c07s02b01x00p01n02i01932 - Logical operators are valid for bit slice operations."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01932arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd | 4 | 2640 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc98.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n02i00098ent_a IS
GENERIC ( gen_in : IN INTEGER );
PORT ( prt_in : IN INTEGER );
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF gen_in : CONSTANT IS 100;
ATTRIBUTE attr1 OF prt_in : SIGNAL IS 200;
END c04s03b02x00p29n02i00098ent_a;
ARCHITECTURE c04s03b02x00p29n02i00098arch_a OF c04s03b02x00p29n02i00098ent_a IS
BEGIN
PROCESS
BEGIN
ASSERT gen_in'attr1 = 100 REPORT "ERROR: Bad value for gen_in'attr1" SEVERITY FAILURE;
ASSERT prt_in'attr1 = 200 REPORT "ERROR: Bad value for prt_in'attr1" SEVERITY FAILURE;
assert NOT(gen_in'attr1 = 100 and prt_in'attr1 = 200)
report "***PASSED TEST: c04s03b02x00p29n02i00098"
severity NOTE;
assert (gen_in'attr1 = 100 and prt_in'attr1 = 200)
report "***FAILED TEST: c04s03b02x00p29n02i00098 - Attribute reading fail."
severity ERROR;
wait;
END PROCESS;
END c04s03b02x00p29n02i00098arch_a;
ENTITY c04s03b02x00p29n02i00098ent IS
END c04s03b02x00p29n02i00098ent;
ARCHITECTURE c04s03b02x00p29n02i00098arch OF c04s03b02x00p29n02i00098ent IS
COMPONENT c04s03b02x00p29n02i00098ent_a
GENERIC ( gen_in : IN INTEGER );
PORT ( prt_in : IN INTEGER );
END COMPONENT;
FOR cmp1 : c04s03b02x00p29n02i00098ent_a USE ENTITY work.c04s03b02x00p29n02i00098ent_a(c04s03b02x00p29n02i00098arch_a);
SIGNAL s : INTEGER;
BEGIN
cmp1 : c04s03b02x00p29n02i00098ent_a
GENERIC MAP ( 0 )
PORT MAP ( s );
END c04s03b02x00p29n02i00098arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd | 4 | 10122 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc855.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00855pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00855pkg_b;
package body c01s03b01x00p12n01i00855pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00855pkg_b;
use work.c01s03b01x00p12n01i00855pkg_b.all;
package c01s03b01x00p12n01i00855pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00855pkg_a;
use work.c01s03b01x00p12n01i00855pkg_a.all;
use work.c01s03b01x00p12n01i00855pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00855pkg_a.all;
use work.c01s03b01x00p12n01i00855pkg_b.all;
ENTITY c01s03b01x00p12n01i00855ent IS
END c01s03b01x00p12n01i00855ent;
ARCHITECTURE c01s03b01x00p12n01i00855arch OF c01s03b01x00p12n01i00855ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00855"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00855 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00855arch;
configuration c01s03b01x00p12n01i00855cfg of c01s03b01x00p12n01i00855ent is
for c01s03b01x00p12n01i00855arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to 3)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd | 4 | 1328 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_join.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
entity join is
generic ( name : string;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_vector;
out_arc : out arc_type;
info_detail : in info_detail_type );
end join;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2422.vhd | 4 | 1933 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2422.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02422ent IS
END c07s03b02x01p01n01i02422ent;
ARCHITECTURE c07s03b02x01p01n01i02422arch OF c07s03b02x01p01n01i02422ent IS
BEGIN
TESTING: PROCESS
type A_RECORD is record
A : CHARACTER;
end record;
type B_RECORD is record
B : CHARACTER;
end record;
variable A : A_RECORD;
variable B : B_RECORD;
BEGIN
A := A_RECORD'(B=>'E'); -- Failure_here
-- SEMANTICS ERROR: choice does not denote record element
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n01i02422 - Given element name does not match the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02422arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd | 4 | 1237 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_23.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
begin
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end entity S_R_flipflop;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/perf02/decis_levl.vhd | 3 | 2193 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end decis_levl;
architecture augh of decis_levl is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd | 4 | 3005 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1120.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01120ent IS
type idx is range 1 to 10;
type aray1 is array (idx) of bit;
type aray2 is array (idx range <>) of aray1;
END c06s05b00x00p03n01i01120ent;
ARCHITECTURE c06s05b00x00p03n01i01120arch OF c06s05b00x00p03n01i01120ent IS
BEGIN
TESTING: PROCESS
variable v1, v2 : aray1;
variable v3 : aray2(1 to 2);
variable v4 : aray2(1 to 3);
BEGIN
--
-- Try slices consisting of slice names
--
v1 := "1111111111";
v1 := v3(1)(idx); -- slice is a whole array
assert v2 = v1
report "Slice of a slice name as a value failed."
severity note ;
v1 := "1111111111";
v4(2)(idx) := v1; -- slice is a whole array
assert v4(2) = v1
report "Slice of a slice name as a target failed."
severity note ;
v2(1) := v3(1)(1 to 1)(1 to 1)(1); -- a one element slice
assert v3(1)(1) = v2(1)
report "One element slice of a slice name as a value failed."
severity note ;
v3(1)(1 to 1)(1 to 1)(1) := v1(1); -- a one element slice
assert v3(1)(1) = v1(1)
report "One element slice of a slice name as a target failed."
severity note ;
assert NOT( v1 = "1111111111" and
v4(2) = "1111111111" and
v2(1) = '0' and
v3(1)(1) = '1')
report "***PASSED TEST: c06s05b00x00p03n01i01120"
severity NOTE;
assert ( v1 = "1111111111" and
v4(2) = "1111111111" and
v2(1) = '0' and
v3(1)(1) = '1')
report "***FAILED TEST: c06s05b00x00p03n01i01120 - The prefix of a slice may be a slice name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01120arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd | 4 | 2000 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2535.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n03i02535ent IS
END c07s03b05x00p13n03i02535ent;
ARCHITECTURE c07s03b05x00p13n03i02535arch OF c07s03b05x00p13n03i02535ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (1 to 6) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T1 := (2,3,6,3,4,5) ;
BEGIN
V1 := T2 (V2) ; -- No_Failure_here
wait for 1 ns;
assert NOT(V1 = (2,3,6,3,4,5))
report "***PASSED TEST: c07s03b05x00p13n03i02535"
severity NOTE;
assert (V1 = (2,3,6,3,4,5))
report "***FAILED TEST: c07s03b05x00p13n03i02535 - A check is made that for each element of the operand there is a matching element of the target subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n03i02535arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1687.vhd | 4 | 1701 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1687.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01687ent IS
port (B:Bit);
END c09s02b00x00p03n01i01687ent;
ARCHITECTURE c09s02b00x00p03n01i01687arch OF c09s02b00x00p03n01i01687ent IS
BEGIN
TESTING: PROCESS(B)
component C1 port ( B : BIT ); -- illegal: no component declaration here
end component ;
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01687 - Component declarations are not permitted in process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01687arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc734.vhd | 4 | 2626 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc734.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x00p05n01i00734ent_a is
generic (
constant gc1 : integer;
variable gc2 : natural;
signal gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00734ent_a;
architecture arch of c01s01b01x00p05n01i00734ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00734ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00734ent;
ARCHITECTURE c01s01b01x00p05n01i00734arch OF c01s01b01x00p05n01i00734ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00734ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (3,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00734 - The generic list in the formal generic clause defines generic constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00734arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd | 4 | 7999 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc758.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00758pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector:= (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector:= (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector:= (1,2,3,4);
constant C18 : positive_vector:= (1,2,3,4);
end c01s01b01x01p05n02i00758pkg;
use work.c01s01b01x01p05n02i00758pkg.ALL;
ENTITY c01s01b01x01p05n02i00758ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgen14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4) );
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen10 : string := "shishir";
Vgen11 : bit_vector := B"0011";
Vgen12 : boolean_vector:= (true,false);
Vgen13 : severity_level_vector := (note,error);
Vgen14 : integer_vector:= (1,2,3,4);
Vgen15 : real_vector := (1.0,2.0,3.0,4.0);
Vgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Vgen17 : natural_vector:= (1,2,3,4);
Vgen18 : positive_vector:= (1,2,3,4)
);
END c01s01b01x01p05n02i00758ent;
ARCHITECTURE c01s01b01x01p05n02i00758arch OF c01s01b01x01p05n02i00758ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p05n02i00758"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p05n02i00758 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00758arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd | 4 | 2146 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1732.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p14n01i01732ent IS
END c09s03b00x00p14n01i01732ent;
ARCHITECTURE c09s03b00x00p14n01i01732arch OF c09s03b00x00p14n01i01732ent IS
signal s1 : bit;
signal s2 : integer;
signal s3 : integer;
procedure unguarded_proc (where : in integer; signal here : out integer) is
begin
if where = 1 then
here <= 5;
else
here <= 6;
end if;
end;
BEGIN
s3 <= 1 after 20 ns;
block_label1 : BLOCK ( s1 = '1' )
begin
unguarded_proc (s3,s2);
end block block_label1;
TESTING: PROCESS(s2)
BEGIN
if (now > 1 ns) then
assert NOT( s2=5 )
report "***PASSED TEST: c09s03b00x00p14n01i01732"
severity NOTE;
assert ( s2=5 )
report "***FAILED TEST: c09s03b00x00p14n01i01732 - The value of an implicitly declared signal GUARD has no effect on evaluation of a concurrent procedure call."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s03b00x00p14n01i01732arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd | 4 | 2111 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2302.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02302ent IS
END c07s02b06x00p37n01i02302ent;
ARCHITECTURE c07s02b06x00p37n01i02302arch OF c07s02b06x00p37n01i02302ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test dividing the predefined type TIME.
assert ((1 us / 1 ns) = 1000);
assert ((1 ns / 1 ps) = 1000);
assert ((1 ps / 1 fs) = 1000);
wait for 5 fs;
assert NOT( ((1 us / 1 ns) = 1000) and
((1 ns / 1 ps) = 1000) and
((1 ps / 1 fs) = 1000) )
report "***PASSED TEST: c07s02b06x00p37n01i02302"
severity NOTE;
assert ( ((1 us / 1 ns) = 1000) and
((1 ns / 1 ps) = 1000) and
((1 ps / 1 fs) = 1000) )
report "***FAILED TEST: c07s02b06x00p37n01i02302 - Division of a physical type by another physical type (predefined TIME) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02302arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd | 4 | 2177 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02157ent IS
END c07s02b04x00p21n01i02157ent;
ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level_null;
variable r_operand : severity_level := NOTE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02157"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02157arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd | 4 | 1886 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package constraints is
-- code from book (in text)
group port_pair is ( signal, signal );
attribute max_prop_delay : time;
-- end code from book
end package constraints;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;
entity clock_buffer is
port ( clock_in : in std_logic;
clock_out1, clock_out2, clock_out3 : out std_logic );
group clock_to_out1 : port_pair ( clock_in, clock_out1 );
group clock_to_out2 : port_pair ( clock_in, clock_out2 );
group clock_to_out3 : port_pair ( clock_in, clock_out3 );
attribute max_prop_delay of clock_to_out1 : group is 2 ns;
attribute max_prop_delay of clock_to_out2 : group is 2 ns;
attribute max_prop_delay of clock_to_out3 : group is 2 ns;
end entity clock_buffer;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd | 4 | 1691 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity cos is
port ( theta : in real; result : out real );
end entity cos;
--------------------------------------------------
architecture series of cos is
begin
summation : process (theta) is
variable sum, term : real;
variable n : natural;
begin
sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E6) loop
n := n + 2;
term := (-term) * theta**2 / real(((n-1) * n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture series;
architecture fixed_length_series of cos is
begin
summation : process (theta) is
variable sum, term : real;
begin
sum := 1.0;
term := 1.0;
for n in 1 to 9 loop
term := (-term) * theta**2 / real(((2*n-1) * 2*n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture fixed_length_series;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket89/project/src93/license_open_pkg.vhd | 3 | 6924 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : license_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean;
impure function show_bitvis_utility_library_info(
constant dummy : in t_void
) return boolean;
impure function show_bitvis_utility_library_release_info(
constant dummy : in t_void
) return boolean;
end package license_pkg;
package body license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean is
constant C_VERSION : string := "v2.5.1"; -- June 2015
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
" Bitvis Utility Library " & C_VERSION & " is being used by this simulation." & LF &
" This is a *** LICENSED PRODUCT *** as given in the copyright notice of the VHDL code." & LF &
" The free license granted is subject to the conditions given in the VHDL copyright notice." & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
report (C_LICENSE_STR);
return true;
end;
impure function show_bitvis_utility_library_info(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This info section may be turned off via C_SHOW_BITVIS_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Simulator setup: " & LF &
"- Set simulator to break on severity 'FAILURE' " & LF &
"- Set simulator transcript to a monospace font (e.g. Courier new)" & LF & LF &
"Bitvis Utility Library setup:" & LF &
"- It is recommended to go through the two powerpoint presentations provided with the download" & LF &
"- There is a Quick-Reference in the doc-directory" & LF &
"- In order to change layout or behaviour - please check the src*/adaptations_pkg.vhd" & LF &
" This is intended for personal or company customization" & LF & LF &
"License conditions are given in License.txt" & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
report (C_LICENSE_STR);
end if;
return true;
end;
impure function show_bitvis_utility_library_release_info(
constant dummy : in t_void
) return boolean is
constant C_IMPORTANT_UPDATE_FOR_THIS_VERSION : boolean := true; -- ***** NOTE: Evaluate a change here
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This release info may be turned off via C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Issues for this version update: " & LF &
"- Two procedures have changed name (see CHANGES.TXT)" & LF &
" The old names will still work for a few more version updates, but a deprecate-message will be displayed" & LF &
" (The deprecate-message may be turned off, but we recommend to rather change the actual procedure names)" & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO and C_IMPORTANT_UPDATE_FOR_THIS_VERSION then
report (C_LICENSE_STR);
end if;
return true;
end;
end package body license_pkg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd | 4 | 1512 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration architectural of computer_system is
for block_level
-- . . . -- component configurations for cpu and memory, etc
for instrumentation
for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
use entity work.bus_monitor(general_purpose)
generic map ( verbose => true, dump_stats => true );
end for;
end for;
end for;
end configuration architectural;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd | 4 | 2172 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01570ent IS
END c08s10b00x00p03n01i01570ent;
ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
variable done : boolean := false;
BEGIN
L1: for i in boolean loop
k := 5;
while not done loop
done := true ;
next ;
k := 3;
end loop ;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01570"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01570arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2375.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2375.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p02n01i02375ent IS
END c07s03b02x00p02n01i02375ent;
ARCHITECTURE c07s03b02x00p02n01i02375arch OF c07s03b02x00p02n01i02375ent IS
BEGIN
TESTING: PROCESS
type x1 is array (1 to 2) of integer;
constant v1 : x1 := (0 0); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p02n01i02375 - A comma(,) is missing between the elements of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p02n01i02375arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc552.vhd | 4 | 1754 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc552.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n04i00552ent IS
END c03s04b00x00p03n04i00552ent;
ARCHITECTURE c03s04b00x00p03n04i00552arch OF c03s04b00x00p03n04i00552ent IS
type ARR ;
type LINK is access ARR;
type ARR is
record
V1 : Integer;
V2 : Integer;
V3 : LINK ;
end record;
type A1 is file of ARR; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p03n04i00552 - Subelement of an access type not allowed here."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n04i00552arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc959.vhd | 4 | 1830 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc959.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00959ent IS
END c06s03b00x00p02n01i00959ent;
ARCHITECTURE c06s03b00x00p02n01i00959arch OF c06s03b00x00p02n01i00959ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12S2 := 10 ; -- Failure_here
wait for 100 ns;
assert FALSE
report "***FAILED TEST: c06s03b00x00p02n01i00959 - Missing dot."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00959arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2328.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2328.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02328ent IS
END c07s02b07x00p02n02i02328ent;
ARCHITECTURE c07s02b07x00p02n02i02328arch OF c07s02b07x00p02n02i02328ent IS
BEGIN
TESTING: PROCESS
constant x : real := 4.5;
constant y : integer := 5;
variable z : integer;
BEGIN
z := y**x; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02328 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02328arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1308.vhd | 4 | 1763 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1308.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n01i01308ent IS
END c08s04b00x00p07n01i01308ent;
ARCHITECTURE c08s04b00x00p07n01i01308arch OF c08s04b00x00p07n01i01308ent IS
signal S : BIT;
signal T : BIT;
BEGIN
TESTING: PROCESS
BEGIN
(S,T) <= ('1','0') after 10 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n01i01308 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n01i01308arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd | 4 | 1914 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p85n01i03181ent IS
END c14s01b00x00p85n01i03181ent;
ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p85n01i03181"
severity NOTE;
assert ( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p85n01i03181arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1638.vhd | 4 | 1697 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1638.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n03i01638ent IS
END c08s12b00x00p05n03i01638ent;
ARCHITECTURE c08s12b00x00p05n03i01638arch OF c08s12b00x00p05n03i01638ent IS
BEGIN
TESTING: PROCESS
function f1(in1:real) return integer is
begin
exit;
end;
variable k : integer := 0;
BEGIN
k := f1(1.2);
assert FALSE
report "***FAILED TEST: c08s12b00x00p05n03i01638 - A function must be completed by a return statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n03i01638arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3030.vhd | 4 | 1690 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3030.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package body c11s04b00x00p02n01i03030pkg is
end c11s04b00x00p02n01i03030pkg;
ENTITY c11s04b00x00p02n01i03030ent IS
END c11s04b00x00p02n01i03030ent;
ARCHITECTURE c11s04b00x00p02n01i03030arch OF c11s04b00x00p02n01i03030ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s04b00x00p02n01i03030 - A primary unit must be analyzed prior to the analysis of any corresponding secondary unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s04b00x00p02n01i03030arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1812.vhd | 4 | 1699 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1812.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01812ent IS
END c07s01b00x00p08n01i01812ent;
ARCHITECTURE c07s01b00x00p08n01i01812arch OF c07s01b00x00p08n01i01812ent IS
type small_int is range 0 to 7;
signal s_int : small_int := 0;
BEGIN
TESTING: PROCESS
BEGIN
if (small_int > s_int) then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01812 - Type name are not permitted as primaries."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01812arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd | 4 | 2121 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_m;
----------------
block_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_n;
----------------
stimulus_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_3_m_n;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd | 4 | 1813 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3200.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03200ent IS
END c14s03b00x00p42n01i03200ent;
ARCHITECTURE c14s03b00x00p42n01i03200arch OF c14s03b00x00p42n01i03200ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.14";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,string'("niu"));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03200 - This test will write TEXT into file iofile.14."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03200arch;
| gpl-2.0 |
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