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peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd | 4 | 1576 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_16.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_20_16 is
end entity fg_20_16;
architecture test of fg_20_16 is
signal clk : bit;
attribute synthesis_hint : string;
begin
-- code from book
controller : process is
attribute synthesis_hint of control_loop : label is
"implementation:FSM(clk)";
-- . . .
begin
-- . . . -- initialization
control_loop : loop
wait until clk = '1';
-- . . .
end loop;
end process controller;
-- end code fom book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1865.vhd | 4 | 1934 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1865.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01865ent IS
END c07s01b00x00p08n01i01865ent;
ARCHITECTURE c07s01b00x00p08n01i01865arch OF c07s01b00x00p08n01i01865ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
s_int <= obus'right(lop) after 5 ns; -- loop label illegal here
end loop lop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01865 - Loop labels are not permitted as primaries in an attribute expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01865arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket56/bug.vhdl | 3 | 249 | entity test is
end entity;
architecture a of test is
function fun(var : boolean) return boolean is
begin
return var;
end function;
begin
main : process
constant c : boolean := fun;
begin
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc905.vhd | 4 | 1700 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc905.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00905ent IS
constant C : INTEGER := C; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00905ent;
ARCHITECTURE c10s03b00x00p05n01i00905arch OF c10s03b00x00p05n01i00905ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00905 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00905arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd | 4 | 2028 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1079.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01079ent IS
END c06s05b00x00p01n02i01079ent;
ARCHITECTURE c06s05b00x00p01n02i01079arch OF c06s05b00x00p01n02i01079ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
procedure subprogram ( signal v : out bit_vector_4 ) is
begin
v <= B"0101" after 10 ns;
end ;
BEGIN
TESTING: PROCESS
BEGIN
subprogram ( v_slice ( 0 to 3 ) );
wait for 11 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c06s05b00x00p01n02i01079"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c06s05b00x00p01n02i01079 - A slice of a signal should still be a signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01079arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd | 4 | 1913 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1522.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p07n01i01522ent IS
END c08s09b00x00p07n01i01522ent;
ARCHITECTURE c08s09b00x00p07n01i01522arch OF c08s09b00x00p07n01i01522ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L1 : Loop
k := k + 1;
if (k = 20) then
assert FALSE
report "PASSED TEST: c08s09b00x00p07n01i01522 - test executing indefinetely"
severity NOTE;
end if;
if (k > 50) then
exit;
end if;
end loop L1;
assert ( k<50 )
report "***PASSED TEST: c08s09b00x00p07n01i01522 - Loop statement without an iteration scheme specifies repeated execution of the statement"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s09b00x00p07n01i01522arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd | 4 | 2109 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02166ent IS
END c07s02b04x00p22n01i02166ent;
ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_2 is real_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : real_2;
variable l_operand : real := 12.345;
variable r_operand : real := -67.890;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ( 12.345, -67.890 )) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p22n01i02166"
severity NOTE;
assert ((result = ( 12.345, -67.890 )) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02166arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-integer-subtype.vhdl | 4 | 313 | entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype sub_integer is integer range 42 to 69;
constant x : sub_integer;
begin
assert x = sub_integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1244.vhd | 4 | 1664 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1244.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01244ent IS
END c08s02b00x00p04n01i01244ent;
ARCHITECTURE c08s02b00x00p04n01i01244arch OF c08s02b00x00p04n01i01244ent IS
BEGIN
TESTING: PROCESS
variable N2 : integer;
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01244 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01244arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd | 4 | 2471 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulate_network_write_data is
end entity stimulate_network_write_data;
architecture writer of stimulate_network_write_data is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity stimulate_network is
end entity stimulate_network;
architecture test of stimulate_network is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd | 4 | 2278 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02114ent IS
END c07s02b04x00p20n01i02114ent;
ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_4;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
alias l_alias : real_v (1 to 2) is l_operand (2 to 3);
alias r_alias : real_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***PASSED TEST:c07s02b04x00p20n01i02114"
severity NOTE;
assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02114arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd | 4 | 1863 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc916.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p10n01i00916pkg is
constant x : integer := 2;
end c10s03b00x00p10n01i00916pkg;
ENTITY c10s03b00x00p10n01i00916ent IS
END c10s03b00x00p10n01i00916ent;
ARCHITECTURE c10s03b00x00p10n01i00916arch OF c10s03b00x00p10n01i00916ent IS
-- selected use of package element
use work.c10s03b00x00p10n01i00916pkg.x;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( x=2 )
report "***PASSED TEST: c10s03b00x00p10n01i00916"
severity NOTE;
assert ( x=2 )
report "***FAILED TEST: c10s03b00x00p10n01i00916 - A declaration ina package can be made visible by selection."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p10n01i00916arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd | 4 | 2456 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03147ent_a IS
END c05s02b02x00p08n01i03147ent_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03147"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_b;
--
ENTITY c05s02b02x00p08n01i03147ent IS
END c05s02b02x00p08n01i03147ent;
ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
component c05s02b02x00p08n01i03147ent_c
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03147ent_c;
END c05s02b02x00p08n01i03147arch;
configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
for c05s02b02x00p08n01i03147arch
for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
end for;
end for;
end c05s02b02x00p08n01i03147cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd | 4 | 1836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n02i02394ent IS
END c07s03b02x00p07n02i02394ent;
ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
BEGIN
TESTING: PROCESS
type t26 is record
elem_1: integer;
end record;
variable v26 : t26;
BEGIN
v26 := (elem_1 => 26);
assert NOT(v26.elem_1=26)
report "***PASSED TEST: c07s03b02x00p07n02i02394"
severity NOTE;
assert (v26.elem_1=26)
report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n02i02394arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1618.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1618.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01618ent IS
END c08s12b00x00p03n01i01618ent;
ARCHITECTURE c08s12b00x00p03n01i01618arch OF c08s12b00x00p03n01i01618ent IS
BEGIN
TESTING: PROCESS
BEGIN
return;
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01618 - A return statement is only allowed within the body of a function"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01618arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc59.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n01i00059ent IS
END c04s03b01x01p05n01i00059ent;
ARCHITECTURE c04s03b01x01p05n01i00059arch OF c04s03b01x01p05n01i00059ent IS
signal S1 : integer := 10;
BEGIN
TESTING : PROCESS
variable TimeCount : time := 0 ns;
BEGIN
S1 <= transport N1 after T1 ; -- No_failure_here
wait for T1;
assert NOT(S1'active and S1 = 20)
report "***PASSED TEST:c04s03b01x01p05n01i00059"
severity NOTE;
assert (S1'active and S1 = 20)
report "***FAILED TEST:c04s03b01x01p05n01i00059 - Generics constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p05n01i00059arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd | 4 | 1943 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc229.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00229ent IS
type big is (a,b,c,d,e,f,g);
type small is (f,g,h,i);
END c03s01b01x00p07n01i00229ent;
ARCHITECTURE c03s01b01x00p07n01i00229arch OF c03s01b01x00p07n01i00229ent IS
BEGIN
TESTING: PROCESS
variable bigf : big;
variable smallf : small;
variable i,l : integer;
BEGIN
bigf := f;
smallf := f;
i := big'pos(f);
l := small'pos(f);
assert NOT(i > l)
report "***PASSED TEST: c03s01b01x00p07n01i00229"
severity NOTE;
assert (i > l)
report "***FAILED TEST: c03s01b01x00p07n01i00229 - The type of an overloaded enumeration literal is determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00229arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/integer-variable-persist-across-activations.vhdl | 4 | 588 | entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
signal last_x : integer := 0;
begin -- only
process (clock)
variable x : integer := 0;
begin -- process
last_x <= x;
x := x + 1;
wait for 1 fs;
assert x > last_x report "TEST FAILED" severity FAILURE;
assert x > 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
end process;
process
begin -- process
clock <= '1' after 1 ns,
'0' after 2 ns,
'1' after 3 ns;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd | 4 | 2234 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2287.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02287ent IS
END c07s02b06x00p32n01i02287ent;
ARCHITECTURE c07s02b06x00p32n01i02287arch OF c07s02b06x00p32n01i02287ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 fs;
assert NOT( ((1 fs * 1000) = 1 ps) and
((1 ps * 1000) = 1 ns) and
((1 ns * 1000) = 1 us) and
((1000 * 1 fs) = 1 ps) and
((1000 * 1 ps) = 1 ns) and
((1000 * 1 ns) = 1 us) )
report "***PASSED TEST: c07s02b06x00p32n01i02287"
severity NOTE;
assert ( ((1 fs * 1000) = 1 ps) and
((1 ps * 1000) = 1 ns) and
((1 ns * 1000) = 1 us) and
((1000 * 1 fs) = 1 ps) and
((1000 * 1 ps) = 1 ns) and
((1000 * 1 ns) = 1 us) )
report "***FAILED TEST: c07s02b06x00p32n01i02287 - Multiplication of a predefined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02287arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1788.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1788.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p02n01i01788ent IS
END c09s07b00x00p02n01i01788ent;
ARCHITECTURE c09s07b00x00p02n01i01788arch OF c09s07b00x00p02n01i01788ent IS
signal TS,SS : bit_vector(1 to 3);
BEGIN
for I in 1 to 3 generate -- Failure_here
-- generate label is missing TS(I) <= SS(I);
end generate;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p02n01i01788 - In the generate statement, the reserved word generate must be preceded by a generate label."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s07b00x00p02n01i01788arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd | 4 | 1737 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00649ent IS
END c03s04b01x00p01n01i00649ent;
ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
BEGIN
TESTING: PROCESS
file filein : resistance_file open write_mode is "iofile.63";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00649arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1856.vhd | 4 | 1786 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1856.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01856ent IS
END c07s01b00x00p08n01i01856ent;
ARCHITECTURE c07s01b00x00p08n01i01856arch OF c07s01b00x00p08n01i01856ent IS
signal sma_int : integer;
BEGIN
sig : sma_int <= 5 after 5 ns;
b: block ( sma_int = sig ) -- signal assignment label illegal here
begin
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01856 - Signal assignment labels are not permitted as primaries in a block guard expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01856arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd | 4 | 2380 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1071.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01071ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
END c06s04b00x00p03n01i01071ent;
ARCHITECTURE c06s04b00x00p03n01i01071arch OF c06s04b00x00p03n01i01071ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(1);
q(2) := func1(2);
q(3) := func1(3);
q(4) := func1(4);
q(5) := func1(5);
q(6) := func1(6);
q(7) := func1(3);
q(8) := func1(1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01071"
severity NOTE;
assert (q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST: c06s04b00x00p03n01i01071 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01071arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd | 4 | 1330 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture slew_limited of opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
v_amplified == gain * v_in;
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd | 4 | 1882 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_02 is
end entity test_bench_01_02;
architecture test_reg4_struct of test_bench_01_02 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(struct)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_struct;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd | 4 | 1931 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02448ent IS
END c07s03b02x02p02n02i02448ent;
ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
BEGIN
TESTING: PROCESS
type t13 is array (bit'('0') to bit'('0')) of integer;
variable v13 : t13;
BEGIN
v13 := (bit'('0') => 13); -- No_failure_here
assert NOT(v13(bit'('0'))=13)
report "***PASSED TEST: c07s03b02x02p02n02i02448"
severity NOTE;
assert (v13(bit'('0'))=13)
report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02448arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd | 4 | 1876 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2284.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02284ent IS
END c07s02b06x00p14n01i02284ent;
ARCHITECTURE c07s02b06x00p14n01i02284arch OF c07s02b06x00p14n01i02284ent IS
signal SS : TIME;
BEGIN
TESTING: PROCESS
variable A : TIME := 199 ns;
variable R : REAL := 7.9999;
variable S : INTEGER := 199;
BEGIN
SS <= A * R / S;
wait for 10 ns;
assert NOT(SS = 7.9999 ns)
report "***PASSED TEST: c07s02b06x00p14n01i02284"
severity NOTE;
assert (SS = 7.9999 ns)
report "***FAILED TEST: c07s02b06x00p14n01i02284 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02284arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd | 4 | 1788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2179.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02179ent IS
END c07s02b05x00p01n02i02179ent;
ARCHITECTURE c07s02b05x00p01n02i02179arch OF c07s02b05x00p01n02i02179ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := - m;
assert NOT( k = - 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02179"
severity NOTE;
assert ( k = - 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02179 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02179arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd | 4 | 3119 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2269.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p12n01i02269ent IS
END c07s02b06x00p12n01i02269ent;
ARCHITECTURE c07s02b06x00p12n01i02269arch OF c07s02b06x00p12n01i02269ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable A, B : INTEGER;
variable OKtest : INTEGER := 0;
BEGIN
-- Test integer mod operations.
-- 1. Both positive.
for A in 0 to 20 loop
for B in 1 to 20 loop
if NOT(((A - (A mod B)) rem B) = 0) then
Oktest := 1;
end if;
assert (((A - (A mod B)) rem B) = 0)
report "Mod operation has failed for integers.";
end loop;
end loop;
-- 2. A negative, B positive.
for A in -1 downto -20 loop
for B in 1 to 20 loop
if NOT(((A - (A mod B)) rem B) = 0) then
Oktest := 1;
end if;
assert (((A - (A mod B)) rem B) = 0)
report "Mod operation has failed for integers.";
end loop;
end loop;
-- 3. A positive, B negative.
for A in 0 to 20 loop
for B in -1 downto -20 loop
if NOT(((A - (A mod B)) rem B) = 0) then
Oktest := 1;
end if;
assert (((A - (A mod B)) rem B) = 0)
report "Mod operation has failed for integers.";
end loop;
end loop;
-- 4. Both negative.
for A in -1 downto -20 loop
for B in -1 downto -20 loop
if NOT(((A - (A mod B)) rem B) = 0) then
Oktest := 1;
end if;
assert (((A - (A mod B)) rem B) = 0)
report "Mod operation has failed for integers.";
end loop;
end loop;
wait for 5 ns;
assert NOT(OKtest=0)
report "***PASSED TEST: c07s02b06x00p12n01i02269"
severity NOTE;
assert (OKtest=0)
report "***FAILED TEST: c07s02b06x00p12n01i02269 - The result of the modulus operation satisfy the relation :A = B*N + (A mod B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p12n01i02269arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd | 4 | 1788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2183.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02183ent IS
END c07s02b05x00p01n02i02183ent;
ARCHITECTURE c07s02b05x00p01n02i02183arch OF c07s02b05x00p01n02i02183ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
variable m : real := 5.5;
BEGIN
k := + m;
assert NOT( k = 5.5 )
report "***PASSED TEST: c07s02b05x00p01n02i02183"
severity NOTE;
assert ( k = 5.5 )
report "***FAILED TEST: c07s02b05x00p01n02i02183 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02183arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd | 4 | 1129 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal node1, node2 : electrical );
end entity resistor;
architecture ideal of resistor is
constant R : real := 1000.0;
quantity v across i through node1 to node2;
begin
v == i * R;
end architecture ideal;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2595.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2595.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02595ent IS
END c13s03b01x00p02n01i02595ent;
ARCHITECTURE c13s03b01x00p02n01i02595arch OF c13s03b01x00p02n01i02595ent IS
BEGIN
TESTING: PROCESS
variable k} : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02595 - Identifier can not end with '}'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02595arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd | 4 | 1585 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity receiver is
end entity receiver;
architecture test of receiver is
begin
-- code from book
receiver : process is
use work.bounded_buffer_adt.all;
variable receive_buffer : bounded_buffer := new_bounded_buffer(2048);
variable buffer_overrun, buffer_underrun : boolean;
-- . . .
-- not in book
variable received_byte, check_byte : byte;
-- end not in book
begin
-- . . .
test_full(receive_buffer, buffer_overrun);
if not buffer_overrun then
write(receive_buffer, received_byte);
end if;
-- . . .
test_empty(receive_buffer, buffer_underrun);
if not buffer_underrun then
read(receive_buffer, check_byte);
end if;
-- . . .
end process receiver;
-- end code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd | 4 | 2273 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1530.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n01i01530ent IS
END c08s09b00x00p09n01i01530ent;
ARCHITECTURE c08s09b00x00p09n01i01530arch OF c08s09b00x00p09n01i01530ent IS
BEGIN
TESTING: PROCESS
variable VAR : REAL := 0.0;
variable k : integer := 0;
BEGIN
-- Outer scope's declaration of VAR is of type REAL.
assert (VAR = 0.0);
if (VAR /= 0.0) then
k := 1;
end if;
-- Loop using VAR as an integer.
for VAR in 0 to 10 loop
-- Verify that inner declaration is of type INTEGER.
assert (VAR <= 10);
if (VAR > 10) then
k := 1;
end if;
end loop;
-- Outer scope's declaration of VAR is of type REAL.
assert (VAR = 0.0);
if (VAR /= 0.0) then
k := 1;
end if;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p09n01i01530"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p09n01i01530 - The loop parameter specification is the declaration of the loop parameter with a given identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n01i01530arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2545.vhd | 4 | 1998 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2545.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02545ent IS
END c07s03b05x00p14n01i02545ent;
ARCHITECTURE c07s03b05x00p14n01i02545arch OF c07s03b05x00p14n01i02545ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
RE1 := RE2 - RE1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02545 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02545arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd | 4 | 1494 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_fg_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and_multiple is
port ( i : in bit_vector; y : out bit );
end entity and_multiple;
--------------------------------------------------
architecture behavioral of and_multiple is
begin
and_reducer : process ( i ) is
variable result : bit;
begin
result := '1';
for index in i'range loop
result := result and i(index);
end loop;
y <= result;
end process and_reducer;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1537.vhd | 4 | 1884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1537.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n05i01537ent IS
END c08s09b00x00p09n05i01537ent;
ARCHITECTURE c08s09b00x00p09n05i01537arch OF c08s09b00x00p09n05i01537ent IS
procedure copy ( variable v_in : in integer := 0;
variable v_out : out integer
) is
begin
v_out := v_in;
end copy;
BEGIN
TESTING: PROCESS
BEGIN
L1: for i in 4 to 5 loop
copy (6, i); -- illegal: 2nd param is mode "inout"
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n05i01537 - A loop parameter can not be an actual corresponding to a formal of mode out "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n05i01537arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd | 4 | 1667 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02 is
end entity inline_02;
----------------------------------------------------------------
architecture test of inline_02 is
-- code from book:
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word;
signal s : resolve_words word bus;
-- end of code from book
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
constant T_delay : delay_length := 2 ns;
begin
process is
begin
-- code from book (should fail)
s(0 to 15) <= X"003F" after T_delay;
s(16 to 31) <= null after T_delay;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd | 4 | 2912 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3156.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03156ent IS
END c05s03b00x00p01n01i03156ent;
ARCHITECTURE c05s03b00x00p01n01i03156arch OF c05s03b00x00p01n01i03156ent IS
begin
--Enclose the whole schematic in a block.
L : block
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block( GUARD = TRUE )
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03156"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03156 - Disconnect in block statement does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
end block L;
END c05s03b00x00p01n01i03156arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd | 4 | 12770 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
use work.alu_types.all,
work.reg_file_types.all;
architecture rtl of dlx is
component alu is
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end component alu;
component reg_file is
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end component reg_file;
component latch is
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end component latch;
component ir_extender is
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end component ir_extender;
component reg_multiple_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_out;
component reg_multiple_plus_one_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_plus_one_out;
component reg_multiple_plus_one_out_reset is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs);
reset : in std_logic );
end component reg_multiple_plus_one_out_reset;
component mux2 is
port ( i0, i1 : in dlx_word;
y : out dlx_word;
sel : in std_logic);
end component mux2;
component controller is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end component controller;
signal s1_bus, s2_bus : dlx_word;
signal dest_bus : dlx_word;
signal alu_in1, alu_in2 : dlx_word;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal mdr_in : dlx_word;
signal current_instruction : dlx_word;
signal pc_to_mem : dlx_address;
signal mar_to_mem : dlx_address;
signal alu_in_latch_en : std_logic;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : std_logic;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
signal reg_write : std_logic;
signal a_out_en, a_latch_en : std_logic;
signal b_out_en, b_latch_en : std_logic;
signal c_latch_en : std_logic;
signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
signal mem_addr_mux_sel : std_logic;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
signal mdr_mux_sel : std_logic;
signal ir_latch_en : std_logic;
signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
signal ir_immed1_en, ir_immed2_en : std_logic;
begin
alu_s1_reg : component latch
port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
alu_s2_reg : component latch
port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
the_alu : component alu
port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
the_reg_file : component reg_file
port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write );
c_reg : component latch
port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
a_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out1, q(1) => s1_bus,
latch_en => a_latch_en, out_en(1) => a_out_en );
b_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out2, q(1) => s2_bus,
latch_en => b_latch_en, out_en(1) => b_out_en );
temp_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => temp_latch_en,
out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
iar_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => iar_latch_en,
out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
pc_reg : component reg_multiple_plus_one_out_reset
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
latch_en => pc_latch_en,
out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
reset => reset );
mar_reg : component reg_multiple_plus_one_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
latch_en => mar_latch_en,
out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
mem_addr_mux : component mux2
port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel );
mdr_reg : component reg_multiple_out
generic map ( num_outputs => 3 )
port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
latch_en => mdr_latch_en,
out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
out_en(3) => mdr_out_en3 );
mdr_mux : component mux2
port map ( i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel );
instr_reg : component latch
port map ( d => d, q => current_instruction,
latch_en => ir_latch_en );
ir_extender1 : component ir_extender
port map ( d => current_instruction, q => s1_bus,
immed_size_26 => ir_immed1_size_26,
immed_unsigned => ir_immed1_unsigned,
immed_en => ir_immed1_en );
ir_extender2 : component ir_extender
port map ( d => current_instruction, q => s2_bus,
immed_size_26 => ir_immed2_size_26,
immed_unsigned => ir_immed2_unsigned,
immed_en => ir_immed2_en );
the_controller : component controller
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
width => width, write_enable => write_enable, mem_enable => mem_enable,
ifetch => ifetch, ready => ready,
alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
alu_zero => alu_zero, alu_negative => alu_negative,
alu_overflow => alu_overflow,
reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
reg_dest_addr => reg_dest_addr, reg_write => reg_write,
c_latch_en => c_latch_en,
a_latch_en => a_latch_en, a_out_en => a_out_en,
b_latch_en => b_latch_en, b_out_en => b_out_en,
temp_latch_en => temp_latch_en,
temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2,
iar_latch_en => iar_latch_en,
iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2,
pc_latch_en => pc_latch_en,
pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2,
mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2,
mdr_out_en3 => mdr_out_en3,
ir_latch_en => ir_latch_en,
ir_immed1_size_26 => ir_immed1_size_26,
ir_immed2_size_26 => ir_immed2_size_26,
ir_immed1_unsigned => ir_immed1_unsigned,
ir_immed2_unsigned => ir_immed2_unsigned,
ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,
current_instruction => current_instruction,
mem_addr => mar_to_mem(1 downto 0),
const1 => s1_bus, const2 => s2_bus );
end architecture rtl;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc540.vhd | 4 | 1654 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc540.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b01x00p02n01i00540ent IS
END c03s03b01x00p02n01i00540ent;
ARCHITECTURE c03s03b01x00p02n01i00540arch OF c03s03b01x00p02n01i00540ent IS
type ARR -- Failure_here
type L1 is access ARR;
type ARR is array (positive range <>) of BIT;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b01x00p02n01i00540 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b01x00p02n01i00540arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc77.vhd | 4 | 1759 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc77.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00077ent IS
END c04s03b01x02p10n04i00077ent;
ARCHITECTURE c04s03b01x02p10n04i00077arch OF c04s03b01x02p10n04i00077ent IS
type int_array is array(1 to 1) of integer;
signal s : int_array := (1 => 0);
BEGIN
s <= (1 => 1);
s <= (1 => 21); s <= (1 => 22);
s <= (1 => 31); s <= (1 => 32); s <= (1 => 33);
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b01x02p10n04i00077- Signal has multiple sources but is not a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00077arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd | 4 | 2015 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01456ent IS
END c08s07b00x00p04n01i01456ent;
ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
elsif delay = 0 then
m := 1;
else
n := 1;
end if;
assert NOT((k = 1) and (m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01456"
severity NOTE;
assert (k = 1) and (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01456arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2556.vhd | 4 | 1584 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2556.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02556ent IS
END c07s03b06x00p02n01i02556ent;
ARCHITECTURE c07s03b06x00p02n01i02556arch OF c07s03b06x00p02n01i02556ent IS
BEGIN
TESTING: PROCESS
variable b : real;
BEGIN
b := new real;
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02556 - Not an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02556arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd | 4 | 2020 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2083.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02083ent IS
END c07s02b04x00p20n01i02083ent;
ARCHITECTURE c07s02b04x00p20n01i02083arch OF c07s02b04x00p20n01i02083ent IS
TYPE int_vector is array (INTEGER range <>) of INTEGER;
BEGIN
TESTING: PROCESS
VARIABLE target : int_vector (1 to 7) ;
VARIABLE slice_1 : int_vector (1 to 4) := (1,2,3,4);
VARIABLE slice_2 : int_vector (-2 to 4) := (5,6,7,8,9,10,11);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1,2,3,6,7,8,9))
report "***PASSED TEST: c07s02b04x00p20n01i02083"
severity NOTE;
assert (target=(1,2,3,6,7,8,9))
report "***FAILED TEST: c07s02b04x00p20n01i02083 - One dimensional array of INTEGER type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02083arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2610.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2610.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02610ent IS
END c13s03b01x00p02n01i02610ent;
ARCHITECTURE c13s03b01x00p02n01i02610arch OF c13s03b01x00p02n01i02610ent IS
BEGIN
TESTING: PROCESS
variable k| : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02610 - Identifier can not end with '|'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02610arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket89/repro2.vhdl | 3 | 354 | entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd | 4 | 2059 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity XYZ3000_cpu is
port ( clock : in bit; addr_data : inout bit_vector(31 downto 0);
other_port : in bit := '0' );
end entity XYZ3000_cpu;
architecture full_function of XYZ3000_cpu is
begin
end architecture full_function;
entity memory_array is
port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' );
end entity memory_array;
architecture behavioral of memory_array is
begin
end architecture behavioral;
-- code from book
library chips;
configuration intermediate of single_board_computer is
for structural
for cpu : processor
use entity chips.XYZ3000_cpu(full_function)
port map ( clock => clk, addr_data => a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
end for;
for main_memory : memory
use entity work.memory_array(behavioral);
end for;
for all : serial_interface
use open;
end for;
-- . . .
end for;
end configuration intermediate;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd | 4 | 2065 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00791ent_1 IS
END ;
-- legal. with entity_simple_name
ENTITY c01s01b02x00p03n01i00791ent_2 IS
END c01s01b02x00p03n01i00791ent_2 ;
-- legal. begin with no statements following
ENTITY c01s01b02x00p03n01i00791ent_3 IS
begin
END c01s01b02x00p03n01i00791ent_3;
-- legal. no space before semicolon
ENTITY c01s01b02x00p03n01i00791ent_4 IS
END c01s01b02x00p03n01i00791ent_4;
-- legal. NEW line before semicolon
ENTITY c01s01b02x00p03n01i00791ent_5 IS
END c01s01b02x00p03n01i00791ent_5
;
--------------------------------
ENTITY c01s01b02x00p03n01i00791ent IS
END c01s01b02x00p03n01i00791ent;
ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00791"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00791arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1797.vhd | 4 | 1908 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1797.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01797ent IS
END c07s01b00x00p02n01i01797ent;
ARCHITECTURE c07s01b00x00p02n01i01797arch OF c07s01b00x00p02n01i01797ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s01b00x00p02n01i01797"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s01b00x00p02n01i01797"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s01b00x00p02n01i01797arch;
-- CONFIGURATION c07s01b00x00p02n01i01797cfg OF c07s01b00x00p02n01i01797ent IS
-- FOR c07s01b00x00p02n01i01797arch
-- END FOR;
-- END c07s01b00x00p02n01i01797cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd | 4 | 2076 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc277.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p07n01i00277ent IS
END c03s01b03x00p07n01i00277ent;
ARCHITECTURE c03s01b03x00p07n01i00277arch OF c03s01b03x00p07n01i00277ent IS
type twos_complement_integer1 is range -32768 to 0;
constant r1: twos_complement_integer1 := -32000;
type twos_complement_integer2 is range 0 to 32767;
constant r2: twos_complement_integer2 := 32000;
type J is
range r1 to r2 -- Success_here
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
BEGIN
TESTING: PROCESS
variable k : J := 31000 A;
BEGIN
k := 5 A;
assert NOT(k=5 A)
report "***PASSED TEST: c03s01b03x00p07n01i00277"
severity NOTE;
assert (k=5 A)
report "***FAILED TEST: c03s01b03x00p07n01i00277 - The bounds in the range constraint are not locally static expressions."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p07n01i00277arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd | 4 | 2075 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1600.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01600ent IS
END c08s11b00x00p03n01i01600ent;
ARCHITECTURE c08s11b00x00p03n01i01600arch OF c08s11b00x00p03n01i01600ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable done : boolean := false;
variable v_boolean : boolean := false;
BEGIN
L1 : while v_boolean /= boolean'High loop
for j in 1 to 3 loop
exit;
p := 0;
end loop;
p := p + 1;
v_boolean := boolean'Succ(v_boolean);
end loop L1;
assert NOT( p=1 )
report "***PASSED TEST: c08s11b00x00p03n01i01600"
severity NOTE;
assert ( p=1 )
report "***FAILED TEST: c08s11b00x00p03n01i01600 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01600arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2781.vhd | 4 | 1617 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2781.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ATTRIBUTE is
end ATTRIBUTE;
ENTITY c13s09b00x00p99n01i02781ent IS
END c13s09b00x00p99n01i02781ent;
ARCHITECTURE c13s09b00x00p99n01i02781arch OF c13s09b00x00p99n01i02781ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02781 - Reserved word ATTRIBUTE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02781arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-high-attribute.vhdl | 4 | 297 | entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'high = 3 report "TEST FAILED high = 3" severity failure;
report "TEST PASSED high = 3";
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1694.vhd | 4 | 1749 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1694.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01694ent IS
END c09s02b00x00p03n01i01694ent;
ARCHITECTURE c09s02b00x00p03n01i01694arch OF c09s02b00x00p03n01i01694ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Configuration specification.
for all : TEST use entity TEST( TEST_BEHAVIOR );
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01694 - Configuration specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01694arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket35/latin1.vhdl | 3 | 134 | -- This is iso 8859-1 (latin-1) encoding. élève.
-- Last chars of the last line are (hexa): e9 6c e8 76 65 2e
package p1 is
end p1;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc57.vhd | 4 | 1788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc57.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n02i00057ent IS
END c04s03b01x01p05n02i00057ent;
ARCHITECTURE c04s03b01x01p05n02i00057arch OF c04s03b01x01p05n02i00057ent IS
BEGIN
TESTING: PROCESS
variable i : integer; -- loop index
variable x : integer;
BEGIN
i := 10;
for i in 1 to 5 loop
x := X + 1;
i := 5; -- Failure_here - the loop index is being modified.
end loop;
assert FALSE
report "***FAILED TEST:c04s03b01x01p05n02i00057 - A loop index may not be altered within the loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p05n02i00057arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1885.vhd | 4 | 1854 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1885.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01885ent IS
END c07s01b00x00p08n01i01885ent;
ARCHITECTURE c07s01b00x00p08n01i01885arch OF c07s01b00x00p08n01i01885ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
obus <= (0 => TESTING, others => 5) after 5 ns; -- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01885 - Process labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01885arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd | 4 | 10186 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc853.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00853pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00853pkg_b;
package body c01s03b01x00p12n01i00853pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00853pkg_b;
use work.c01s03b01x00p12n01i00853pkg_b.all;
package c01s03b01x00p12n01i00853pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010";
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00853pkg_a;
use work.c01s03b01x00p12n01i00853pkg_a.all;
use work.c01s03b01x00p12n01i00853pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00853pkg_a.all;
use work.c01s03b01x00p12n01i00853pkg_b.all;
ENTITY c01s03b01x00p12n01i00853ent IS
END c01s03b01x00p12n01i00853ent;
ARCHITECTURE c01s03b01x00p12n01i00853arch OF c01s03b01x00p12n01i00853ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00853"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00853 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00853arch;
configuration c01s03b01x00p12n01i00853cfg of c01s03b01x00p12n01i00853ent is
for c01s03b01x00p12n01i00853arch
for K
for T5:test use configuration work.testbench;
end for;
for G(dumy'reverse_range)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd | 4 | 2927 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd | 4 | 1620 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and_multiple is
end entity tb_and_multiple;
----------------------------------------------------------------
architecture test_behavioral of tb_and_multiple is
-- code from book:
signal count_value : bit_vector(7 downto 0);
signal terminal_count : bit;
-- end of code from book
begin
-- code from book:
tc_gate : entity work.and_multiple(behavioral)
port map ( i => count_value, y => terminal_count);
-- end of code from book
stumulus : process is
begin
wait for 10 ns;
count_value <= "10000000"; wait for 10 ns;
count_value <= "11111110"; wait for 10 ns;
count_value <= "01111111"; wait for 10 ns;
count_value <= "11111111"; wait for 10 ns;
count_value <= "00000000"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd | 4 | 3862 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc438.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00438ent IS
END c03s02b01x01p19n01i00438ent;
ARCHITECTURE c03s02b01x01p19n01i00438arch OF c03s02b01x01p19n01i00438ent IS
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
function complex_scalar(s : record_std_package) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_std_package is
begin
return C10;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_std_package;
signal S2 : record_std_package;
signal S3 : record_std_package := C10;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C10) and (S2 = C10))
report "***PASSED TEST: c03s02b01x01p19n01i00438"
severity NOTE;
assert ((S1 = C10) and (S2 = C10))
report "***FAILED TEST: c03s02b01x01p19n01i00438 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00438arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/perf02/qq6_code6_table.vhd | 3 | 3360 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq6_code6_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(5 downto 0)
);
end qq6_code6_table;
architecture augh of qq6_code6_table is
-- Embedded RAM
type ram_type is array (0 to 63) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111001111100011000", "11111111111111111010101001110000", "11111111111111111011010111000000", "11111111111111111011111011000000", "11111111111111111100010101111000", "11111111111111111100101100111000", "11111111111111111101000000001000", "11111111111111111101010001001000", "11111111111111111101100000001000", "11111111111111111101101101110000", "11111111111111111101111010000000", "11111111111111111110000101010000", "11111111111111111110001111101000", "11111111111111111110011001010000", "11111111111111111110100010010000", "11111111111111111110101010110000", "11111111111111111110110010110000", "11111111111111111110111010010000", "11111111111111111111000001011000", "11111111111111111111001000001000", "11111111111111111111001110100000", "11111111111111111111010100101000", "11111111111111111111011010100000", "11111111111111111111100000010000", "11111111111111111111100101101000", "11111111111111111111101010110000", "11111111111111111111101111110000", "11111111111111111111110100101000", "00000000000000000110000011101000", "00000000000000000101010110010000", "00000000000000000100101001000000", "00000000000000000100000101000000", "00000000000000000011101010001000", "00000000000000000011010011001000", "00000000000000000010111111111000", "00000000000000000010101110111000", "00000000000000000010011111111000", "00000000000000000010010010010000", "00000000000000000010000110000000", "00000000000000000001111010110000", "00000000000000000001110000011000", "00000000000000000001100110110000", "00000000000000000001011101110000", "00000000000000000001010101010000", "00000000000000000001001101010000", "00000000000000000001000101110000", "00000000000000000000111110101000", "00000000000000000000110111111000", "00000000000000000000110001100000", "00000000000000000000101011011000", "00000000000000000000100101100000", "00000000000000000000011111110000", "00000000000000000000011010011000", "00000000000000000000010101010000", "00000000000000000000010000010000", "00000000000000000000001011011000", "00000000000000000000000110110000", "00000000000000000000000010001000", "11111111111111111111111001010000", "11111111111111111111111101111000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2841.vhd | 4 | 1617 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2841.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity TRANSPORT is
end TRANSPORT;
ENTITY c13s09b00x00p99n01i02841ent IS
END c13s09b00x00p99n01i02841ent;
ARCHITECTURE c13s09b00x00p99n01i02841arch OF c13s09b00x00p99n01i02841ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02841 - Reserved word TRANSPORT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02841arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd | 4 | 993 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_08 is
-- code from book
procedure uniform ( variable seed1, seed2 : inout positive;
variable x : out real);
-- end code from book
end package inline_08;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/sr2553/2553.vhd | 3 | 467 | library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal slv2: std_logic_vector(7 downto 0);
signal sl2: std_logic;
begin
tx: entity work.e1
port map(
r1 => real(r2_wrong),
slv1 => slv2,
sl1 => sl2
);
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd | 4 | 2151 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1321.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p09n03i01321ent IS
END c08s04b00x00p09n03i01321ent;
ARCHITECTURE c08s04b00x00p09n03i01321arch OF c08s04b00x00p09n03i01321ent IS
signal S1 : BIT := '1';
signal S2 : BIT := '1';
signal S : BIT := '1';
BEGIN
S1 <= transport '0' after 5 ns,
'1' after 10 ns;
S2 <= transport S1 after 15 ns;
TEST : PROCESS(S2)
variable k : integer := 0;
BEGIN
if ((S2 = '0') and (NOW = 20 ns)) then
k := 1;
end if;
if ((S2 = '1') and (NOW = 25 ns) and (k = 1)) then
S <= '0' after 10 ns;
end if;
END PROCESS TEST;
TESTING: PROCESS(S)
BEGIN
if (NOW > 1 ns) then
assert NOT(S = '0')
report "***PASSED TEST: c08s04b00x00p09n03i01321"
severity NOTE;
assert (S = '0')
report "***FAILED TEST: c08s04b00x00p09n03i01321 - Any pulse is transmitted, not matter how short its durtion"
severity ERROR;
end if;
END PROCESS TESTING;
END c08s04b00x00p09n03i01321arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd | 4 | 3197 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc446.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00446ent IS
END c03s02b01x01p19n01i00446ent;
ARCHITECTURE c03s02b01x01p19n01i00446arch OF c03s02b01x01p19n01i00446ent IS
type time_vector is array (natural range <>) of time;
subtype time_vector_st is time_vector(0 to 15);
constant C1 : time := 4 ns;
constant C70 : time_vector_st :=(others => C1);
function complex_scalar(s : time_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_vector_st;
signal S2 : time_vector_st;
signal S3 : time_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00446"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00446 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00446arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2628.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02628ent IS
END c13s03b01x00p02n01i02628ent;
ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
BEGIN
TESTING: PROCESS
variable k;k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02628arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd | 4 | 2319 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity example_entity is
end entity example_entity;
-- end not in book
architecture contrived of example_entity is
constant sig_width : positive := 16;
signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
signal sel : bit;
-- . . .
begin
mux : block is
generic ( width : positive );
generic map ( width => sig_width );
port ( d0, d1 : in bit_vector(0 to width - 1);
y : out bit_vector(0 to width - 1);
sel : in bit);
port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
constant zero : bit_vector(0 to width - 1) := ( others => '0' );
signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
begin
gated_d0 <= d0 when sel = '0' else zero;
gated_d1 <= d1 when sel = '1' else zero;
y <= gated_d0 or gated_d1;
end block mux;
-- . . .
-- not in book
stimulus : process is
begin
s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns;
s1 <= X"0101"; wait for 10 ns;
s2 <= X"0202"; wait for 10 ns;
sel <= '1'; wait for 10 ns;
s1 <= X"0001"; wait for 10 ns;
s2 <= X"0002"; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture contrived;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd | 4 | 2959 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1392.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n04i01392ent IS
END c08s05b00x00p04n04i01392ent;
ARCHITECTURE c08s05b00x00p04n04i01392arch OF c08s05b00x00p04n04i01392ent IS
--
TYPE rec_list IS RECORD
a,b,c,d : INTEGER;
END RECORD;
BEGIN
TESTING: PROCESS
--
VARIABLE rec1 : rec_list := (1,2,3,4);
VARIABLE rec2 : rec_list := (1,2,3,4);
VARIABLE rec3 : rec_list := (1,2,3,4);
VARIABLE rec4 : rec_list := (1,2,3,4);
VARIABLE rec5 : rec_list := (1,2,3,4);
VARIABLE rec6 : rec_list := (1,2,3,4);
--
BEGIN
--
rec1 := ( rec1.d, rec1.c, rec1.b, rec1.a);
--
( rec2.d, rec2.c, rec2.b, rec2.a) := rec2;
--
(rec3.d, rec3.c, rec3.b, rec3.a)
:= rec_list' (rec3.c, rec3.d, rec3.a, rec3.b);
--
(rec4.a, rec4.b, rec4.c, rec4.d)
:= rec_list' ( d=>rec4.a, c=>rec4.b, b=>rec4.c, a=>rec4.d);
--
( d=>rec5.a, c=>rec5.b, b=>rec5.c, a=>rec5.d) := rec5;
--
(rec6.d, rec6.c, rec6.b, rec6.a)
:= rec_list' ( d=>rec6.a, c=>rec6.b, b=>rec6.c, a=>rec6.d);
--
ASSERT NOT( rec1 = (4,3,2,1) and
rec2 = (4,3,2,1) and
rec3 = (2,1,4,3) and
rec4 = (4,3,2,1) and
rec5 = (4,3,2,1) and
rec6 = (1,2,3,4))
report "***PASSED TEST: c08s05b00x00p04n04i01392"
severity NOTE;
ASSERT ( rec1 = (4,3,2,1) and
rec2 = (4,3,2,1) and
rec3 = (2,1,4,3) and
rec4 = (4,3,2,1) and
rec5 = (4,3,2,1) and
rec6 = (1,2,3,4))
report "***FAILED TEST: c08s05b00x00p04n04i01392 - Record aggregates type variable assignment fail."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n04i01392arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd | 4 | 2110 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd | 4 | 1871 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00041ent IS
END c04s03b01x01p02n01i00041ent;
ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
constant B1 : Bit := '0'; -- No_failure_here
constant B2 : Character := '0'; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( B1 = '0' and B2 = '0' )
report "***PASSED TEST: c04s03b01x01p02n01i00041"
severity NOTE;
assert ( B1 = '0' and B2 = '0' )
report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00041arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd | 4 | 2139 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_21_02 is
end entity ch_21_02;
----------------------------------------------------------------
architecture test of ch_21_02 is
signal s : bit;
begin
-- code from book:
p : postponed process is
-- . . .
begin
-- . . .
wait until s = '1';
-- . . . -- s may not be '1'!!
-- not in book
report bit'image(s);
wait;
-- end not in book
end postponed process p;
-- end of code from book
stimulus : process is
begin
wait for 10 ns;
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1196.vhd | 4 | 1697 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1196.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01196ent IS
END c08s01b00x00p05n01i01196ent;
ARCHITECTURE c08s01b00x00p05n01i01196arch OF c08s01b00x00p05n01i01196ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable j : integer := 0;
BEGIN
k <= 5 after 5 ns;
j := 5;
wait until j;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01196 - Reserved word 'until' must be followed by a boolean expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01196arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd | 4 | 1489 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
architecture test of inline_03 is
signal clk, ready : bit;
begin
dut1 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, false )
-- end code from book
port map ( clk, ready, open, open );
dut2 : entity work.control_unit
-- code from book (in text)
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
-- end code from book
port map ( clk, ready, open, open );
dut3 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, debug => open )
-- end code from book
port map ( clk, ready, open, open );
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd | 4 | 6565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01374ent IS
END c08s05b00x00p03n01i01374ent;
ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01374"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01374arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc715.vhd | 4 | 1539 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc715.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p02n01i00715ent IS
END c01s01b00x00p02n01i00715ent;
ARCHITECTURE c01s01b00x00p02n01i00715arch OF c01s01b00x00p02n01i00715ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00715 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00715arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1663.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1663.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p03n01i01663ent IS
port (A, B: inout bit);
END c09s01b00x00p03n01i01663ent;
ARCHITECTURE c09s01b00x00p03n01i01663arch OF c09s01b00x00p03n01i01663ent IS
signal S1, S2, S3 : bit := '0';
BEGIN
BL: block
port map (S1, S2); --Failure_here
begin
end block BL;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p03n01i01663 - A port map can not appear without being preceded by a port clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p03n01i01663arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd | 4 | 1757 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1555.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p02n01i01555ent IS
END c08s10b00x00p02n01i01555ent;
ARCHITECTURE c08s10b00x00p02n01i01555arch OF c08s10b00x00p02n01i01555ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L1 : for i in 1 to 10 loop
next L1;
k := 5;
end loop L1;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p02n01i01555"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s10b00x00p02n01i01555 - The when clause is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p02n01i01555arch;
| gpl-2.0 |
peteut/ghdl | libraries/vital95/vital_primitives_body.vhdl | 6 | 235006 | -------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Default values for Primitives
-- ------------------------------------------------------------------------
-- default values for delay parameters
CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01;
CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z;
TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME;
-- default primitive model operation parameters
-- Glitch detection/reporting
TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch);
CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly;
-- ------------------------------------------------------------------------
-- Local Type and Subtype Declarations
-- ------------------------------------------------------------------------
---------------------------------------------------------------------------
-- enumeration value representing the transition or level of the signal.
-- See function 'GetEdge'
---------------------------------------------------------------------------
TYPE EdgeType IS ( 'U', -- Uninitialized level
'X', -- Unknown level
'0', -- low level
'1', -- high level
'\', -- 1 to 0 falling edge
'/', -- 0 to 1 rising edge
'F', -- * to 0 falling edge
'R', -- * to 1 rising edge
'f', -- rising to X edge
'r', -- falling to X edge
'x', -- Unknown edge (ie U->X)
'V' -- Timing violation edge
);
TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType;
TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType;
TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType;
TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType;
TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType;
TYPE GlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
CurrentValue : std_ulogic;
END RECORD;
TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF GlitchDataType;
-- Enumerated type used in selection of output path delays
TYPE SchedType IS
RECORD
inp0 : TIME; -- time (abs) of output change due to input change to 0
inp1 : TIME; -- time (abs) of output change due to input change to 1
InpX : TIME; -- time (abs) of output change due to input change to X
Glch0 : TIME; -- time (abs) of output glitch due to input change to 0
Glch1 : TIME; -- time (abs) of output glitch due to input change to 0
END RECORD;
TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType;
CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns);
CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns);
-- Constrained array declarations (common sizes used by primitives)
SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0);
SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0);
SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0);
SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0);
SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0);
SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0);
SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0);
SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0);
SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0);
SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0);
SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0);
SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0);
SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0);
SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0);
SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0);
SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0);
CONSTANT DefSchedArray2 : SchedArray2 :=
(OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns));
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT InitialEdge : LogicToLevelT := (
'1'|'H' => 'R',
'0'|'L' => 'F',
OTHERS => 'x'
);
CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current
-- old \ new: U X 0 1 Z W L H -
'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ),
'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ),
'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' )
);
CONSTANT LogicToLevel : LogicToLevelT := (
'1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X'
);
-- -----------------------------------
-- 3-state logic tables
-- -----------------------------------
CONSTANT BufIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT BufIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER;
CONSTANT To_StateChar : To_StateCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' );
TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER;
CONSTANT To_TruthChar : To_TruthCharType :=
( 'X', '0', '1', '-', 'B', 'Z' );
TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic;
CONSTANT TruthTableOutMap : TruthTableOutMapType :=
-- 'X', '0', '1', '-', 'B', 'Z'
( 'X', '0', '1', 'X', '-', 'Z' );
TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic;
-- does conversion to X01Z or '-' if invalid
CONSTANT StateTableOutMap : StateTableOutMapType :=
-- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v'
-- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S'
( '-','-','-','-','-','-','-','-','-','-','-','-',
'-','-','-','-','X','0','1','X','-','Z','W');
-- ------------------------------------------------------------------------
TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN;
-- checks if a symbol IS valid for the stimulus portion of a truth table
CONSTANT ValidTruthTableInput : ValidTruthTableInputType :=
-- 'X' '0' '1' '-' 'B' 'Z'
( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE );
TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN;
-- checks if an input matches th corresponding truth table symbol
-- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol)
CONSTANT TruthTableMatch : TruthTableMatchType := (
-- X, 0, 1, - B Z
( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X
( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0
( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1
);
-- ------------------------------------------------------------------------
TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN;
CONSTANT ValidStateTableInput : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
TRUE );
CONSTANT ValidStateTableState : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'p', 'n', 'R', 'F', '^', 'v',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'E', 'A', 'D', '*',
FALSE, FALSE, FALSE, FALSE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
FALSE );
TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT StateTableMatch : StateTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ),
(TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE )
)
);
TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z;
----------------------------------------------------------
-- table name : cvt_to_x01z
-- parameters : std_ulogic -- some logic value
-- returns : UX01Z -- state value of logic value
-- purpose : to convert state-strength to state only
----------------------------------------------------------
CONSTANT cvt_to_ux01z : Logic_UX01Z_Table :=
('U','X','0','1','Z','X','0','1','X' );
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MINIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return smaller of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 < in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MAXIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return larger of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 > in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-----------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
-----------------------------------------------------------------------
FUNCTION GlitchMinTime (
CONSTANT Time1, Time2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( Time1 >= NOW ) THEN
IF ( Time2 >= NOW ) THEN
RETURN Minimum ( Time1, Time2);
ELSE
RETURN Time1;
END IF;
ELSE
IF ( Time2 >= NOW ) THEN
RETURN Time2;
ELSE
RETURN 0 ns;
END IF;
END IF;
END;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrNegDel,
ErrInpSym,
ErrOutSym,
ErrStaSym,
ErrVctLng,
ErrTabWidSml,
ErrTabWidLrg,
ErrTabResSml,
ErrTabResLrg
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrNegDel => WARNING,
ErrInpSym => ERROR,
ErrOutSym => ERROR,
ErrStaSym => ERROR,
ErrVctLng => ERROR,
ErrTabWidSml => ERROR,
ErrTabWidLrg => WARNING,
ErrTabResSml => WARNING,
ErrTabResLrg => WARNING
);
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgInpSym : STRING :=
"Illegal symbol in the input portion of a Truth/State table.";
CONSTANT MsgOutSym : STRING :=
"Illegal symbol in the output portion of a Truth/State table.";
CONSTANT MsgStaSym : STRING :=
"Illegal symbol in the state portion of a State table.";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgTabWidSml : STRING :=
"Width of the Truth/State table is too small.";
CONSTANT MsgTabWidLrg : STRING :=
"Width of Truth/State table is too large. Extra elements are ignored.";
CONSTANT MsgTabResSml : STRING :=
"Result of Truth/State table has too many elements.";
CONSTANT MsgTabResLrg : STRING :=
"Result of Truth/State table has too few elements.";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN ErrInpSym => RETURN MsgInpSym;
WHEN ErrOutSym => RETURN MsgOutSym;
WHEN ErrStaSym => RETURN MsgStaSym;
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrTabWidSml => RETURN MsgTabWidSml;
WHEN ErrTabWidLrg => RETURN MsgTabWidLrg;
WHEN ErrTabResSml => RETURN MsgTabResSml;
WHEN ErrTabResLrg => RETURN MsgTabResLrg;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preemted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
-- Procedure : VitalGlitchOnEvent
-- :
-- Parameters : OutSignal ........ signal being driven
-- : OutSignalName..... name of the driven signal
-- : GlitchData........ internal data required by the procedure
-- : NewValue.......... new value being assigned
-- : NewDelay.......... Delay accompanying the assignment
-- : (Note: for vectors, this is an array)
-- : GlitchMode........ Glitch generation mode
-- : MessagePlusX, MessageOnly,
-- : XOnly, NoGlitch )
-- : GlitchDelay....... if <= 0 ns , then there will be no Glitch
-- : if > NewDelay, then there is no Glitch,
-- : otherwise, this is the time when a FORCED
-- : generation of a glitch will occur.
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataType;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN TIME := 0 ns;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
-- ------------------------------------------------------------------------
VARIABLE NoGlitchDet : BOOLEAN := FALSE;
VARIABLE OldGlitch : BOOLEAN := FALSE;
VARIABLE Dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
GlitchData.CurrentValue := GlitchData.SchedValue;
IF (GlitchDelay <= 0 ns) THEN
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
GlitchData.CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue) AND
(GlitchData.SchedTime = GlitchData.GlitchTime) AND
(GlitchDelay <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
GlitchData.SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal <= NewValue AFTER Dly;
ELSIF NoGlitchDet THEN
GlitchData.GlitchTime := NOW+Dly;
OutSignal <= NewValue AFTER Dly;
ELSE -- new glitch
GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime,
NOW+GlitchDelay );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(Dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER Dly;
ELSE
OutSignal <= NewValue AFTER Dly;
END IF;
END IF;
GlitchData.SchedValue := NewValue;
END IF;
RETURN;
END;
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataArrayType;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT NewDelay : IN VitalTimeArray;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN VitalTimeArray;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH)
IS GlitchData;
ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue;
ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH)
IS GlitchDelay;
ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay;
VARIABLE Index : INTEGER := OutSignal'LEFT;
VARIABLE Direction : INTEGER;
VARIABLE NoGlitchDet : BOOLEAN;
VARIABLE OldGlitch : BOOLEAN;
VARIABLE Dly, GlDly : TIME;
BEGIN
IF (OutSignal'LEFT > OutSignal'RIGHT) THEN
Direction := -1;
ELSE
Direction := 1;
END IF;
IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR
(OutSignal'LENGTH /= NewValue'LENGTH) OR
(OutSignal'LENGTH /= NewDelay'LENGTH) OR
(OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN
VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName );
RETURN;
END IF;
-- a call to the scalar function cannot be made since the actual
-- name associated with a signal parameter must be locally static
FOR n IN 1 TO OutSignal'LENGTH LOOP
NoGlitchDet := FALSE;
OldGlitch := FALSE;
Dly := NewDelAlias(n);
-- If nothing to schedule, just skip to next loop iteration
IF NewDelAlias(n) < 0 ns THEN
IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled (i.e. last scheduled
-- transaction already occurred)
IF GlDataAlias(n).SchedTime <= NOW THEN
GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue;
IF (GlDelayAlias(n) <= 0 ns) THEN
-- Next iteration if no change in value
IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN
Index := Index + Direction;
NEXT;
END IF;
-- since last transaction already occurred there is no glitch
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlDataAlias(n).GlitchTime <= NOW THEN
GlDataAlias(n).CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN
dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- Transaction currently scheduled
ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND
(GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND
(GlDelayAlias(n) <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- update last scheduled transaction
GlDataAlias(n).SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSIF NoGlitchDet THEN
-- if no glitch then update last glitch time
-- and OutSignal(actual_index)
GlDataAlias(n).GlitchTime := NOW+Dly;
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSE -- new glitch
GlDataAlias(n).GlitchTime := GlitchMinTime (
GlDataAlias(n).GlitchTime,
NOW+GlDelayAlias(n) );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlDataAlias(n).GlitchTime,
GlDataAlias(n).SchedValue,
(Dly + NOW), NewValAlias(n),
Index, TRUE, MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
GlDly := GlDataAlias(n).GlitchTime - NOW;
OutSignal(Index) <= 'X' AFTER GlDly;
OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly;
ELSE
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
END IF;
END IF; -- glitch / no-glitch
GlDataAlias(n).SchedValue := NewValAlias(n);
END IF; -- NewDelAlias(n) < 0 ns
Index := Index + Direction;
END LOOP;
RETURN;
END;
---------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : TruthOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- X01Zout - output converted to X01Z
-- err - true if illegal character is encountered
--
--
-- DESCRIPTION : converts the output of a truth table to a valid
-- std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE TruthOutputX01Z (
CONSTANT TableOut : IN VitalTruthSymbolType;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := TruthTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut));
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : StateOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- prev_out - previous output value
-- X01Zout - output cojnverted to X01Z
-- err - true if illegal character is encountered
--
-- DESCRIPTION : converts the output of a state table to a
-- valid std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE StateOutputX01Z (
CONSTANT TableOut : IN VitalStateSymbolType;
CONSTANT PrevOut : IN std_ulogic;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := StateTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut));
ELSIF (TempOut = 'W') THEN
TempOut := To_X01Z(PrevOut);
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: StateMatch
--
-- PARAMETERS : symbol - symbol from state table
-- in2 - input from VitalStateTble procedure
-- to state table
-- in2LastValue - previous value of input
-- state - false if the symbol is from the input
-- portion of the table,
-- true if the symbol is from the state
-- portion of the table
-- Err - true if symbol is not a valid input symbol
-- ReturnValue - true if match occurred
--
-- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches
-- symbol (from the state table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the state
-- table.
--
-- ------------------------------------------------------------------------
PROCEDURE StateMatch (
CONSTANT Symbol : IN VitalStateSymbolType;
CONSTANT in2 : IN std_ulogic;
CONSTANT in2LastValue : IN std_ulogic;
CONSTANT State : IN BOOLEAN;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (State) THEN
IF (NOT ValidStateTableState(Symbol)) THEN
VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
Err := FALSE;
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
END IF;
ELSE
IF (NOT ValidStateTableInput(Symbol) ) THEN
VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
Err := FALSE;
END IF;
END IF;
END;
-- -----------------------------------------------------------------------
-- FUNCTION NAME: StateTableLookUp
--
-- PARAMETERS : StateTable - state table
-- PresentDataIn - current inputs
-- PreviousDataIn - previous inputs and states
-- NumStates - number of state variables
-- PresentOutputs - current state and current outputs
--
-- DESCRIPTION : This function is used to find the output of the
-- StateTable corresponding to a given set of inputs.
--
-- ------------------------------------------------------------------------
FUNCTION StateTableLookUp (
CONSTANT StateTable : VitalStateTableType;
CONSTANT PresentDataIn : std_logic_vector;
CONSTANT PreviousDataIn : std_logic_vector;
CONSTANT NumStates : NATURAL;
CONSTANT PresentOutputs : std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH;
CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1;
CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2);
CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates;
VARIABLE Inputs : std_logic_vector(0 TO NumInputs);
VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs)
:= (OTHERS => 'X');
VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1))
:= (OTHERS => 'X');
VARIABLE Temp : std_ulogic;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= StateTable;
BEGIN
Inputs(0 TO InputSize-1) := PresentDataIn;
Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1);
PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1);
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the entry
FOR j IN 0 TO InputSize + NumStates LOOP
IF (j = InputSize + NumStates) THEN -- a match occurred
FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP
StateOutputX01Z (
TableAlias(i, TableWidth - k - 1),
PresentOutputs(PresentOutputs'LENGTH - k - 1),
Temp, Err);
ReturnValue(OutSize - k - 1) := Temp;
IF (Err) THEN
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END IF;
END LOOP;
RETURN ReturnValue;
END IF;
StateMatch ( TableAlias(i,j),
Inputs(j), PrevInputs(j),
j >= InputSize, Err, Match);
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END;
--------------------------------------------------------------------
-- to_ux01z
-------------------------------------------------------------------
FUNCTION To_UX01Z ( s : std_ulogic
) RETURN UX01Z IS
BEGIN
RETURN cvt_to_ux01z (s);
END;
---------------------------------------------------------------------------
-- Function : GetEdge
-- Purpose : Converts transitions on a given input signal into a
-- enumeration value representing the transition or level
-- of the signal.
--
-- previous "value" current "value" := "edge"
-- ---------------------------------------------------------
-- '1' | 'H' '1' | 'H' '1' level, no edge
-- '0' | 'L' '1' | 'H' '/' rising edge
-- others '1' | 'H' 'R' rising from X
--
-- '1' | 'H' '0' | 'L' '\' falling egde
-- '0' | 'L' '0' | 'L' '0' level, no edge
-- others '0' | 'L' 'F' falling from X
--
-- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level
-- 'Z' 'Z' 'X' unknown (X) level
-- 'U' 'U' 'U' 'U' level
--
-- '1' | 'H' others 'f' falling to X
-- '0' | 'L' others 'r' rising to X
-- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge
-- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge
-- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge
--
---------------------------------------------------------------------------
FUNCTION GetEdge (
SIGNAL s : IN std_logic
) RETURN EdgeType IS
BEGIN
IF (s'EVENT)
THEN RETURN LogicToEdge ( s'LAST_VALUE, s );
ELSE RETURN LogicToLevel ( s );
END IF;
END;
---------------------------------------------------------------------------
PROCEDURE GetEdge (
SIGNAL s : IN std_logic_vector;
VARIABLE LastS : INOUT std_logic_vector;
VARIABLE Edge : OUT EdgeArray ) IS
ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s;
ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS;
ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge;
BEGIN
IF s'LENGTH /= LastS'LENGTH OR
s'LENGTH /= Edge'LENGTH THEN
VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" );
END IF;
FOR n IN 1 TO s'LENGTH LOOP
EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) );
LastSAlias(n) := sAlias(n);
END LOOP;
END;
---------------------------------------------------------------------------
FUNCTION ToEdge ( Value : IN std_logic
) RETURN EdgeType IS
BEGIN
RETURN LogicToLevel( Value );
END;
-- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92
----------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataType
) RETURN std_logic IS
BEGIN
IF NOW >= GlitchData.SchedTime THEN
RETURN GlitchData.SchedValue;
ELSIF NOW >= GlitchData.GlitchTime THEN
RETURN 'X';
ELSE
RETURN GlitchData.CurrentValue;
END IF;
END;
---------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataArrayType
) RETURN std_logic_vector IS
VARIABLE Result : std_logic_vector(GlitchData'RANGE);
BEGIN
FOR n IN GlitchData'RANGE LOOP
IF NOW >= GlitchData(n).SchedTime THEN
Result(n) := GlitchData(n).SchedValue;
ELSIF NOW >= GlitchData(n).GlitchTime THEN
Result(n) := 'X';
ELSE
Result(n) := GlitchData(n).CurrentValue;
END IF;
END LOOP;
RETURN Result;
END;
---------------------------------------------------------------------------
-- function calculation utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Function : VitalSame
-- Returns : VitalSame compares the state (UX01) of two logic value. A
-- value of 'X' is returned if the values are different. The
-- common value is returned if the values are equal.
-- Purpose : When the result of a logic model may be either of two
-- separate input values (eg. when the select on a MUX is 'X'),
-- VitalSame may be used to determine if the result needs to
-- be 'X'.
-- Arguments : See the declarations below...
---------------------------------------------------------------------------
FUNCTION VitalSame (
CONSTANT a, b : IN std_ulogic
) RETURN std_ulogic IS
BEGIN
IF To_UX01(a) = To_UX01(b)
THEN RETURN To_UX01(a);
ELSE RETURN 'X';
END IF;
END;
---------------------------------------------------------------------------
-- delay selection utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure : BufPath, InvPath
--
-- Purpose : BufPath and InvPath compute output change times, based on
-- a change on an input port. The computed output change times
-- returned in the composite parameter 'schd'.
--
-- BufPath and InpPath are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the input ports of a model are
-- combined by the delay selection functions (VitalAND,
-- VitalOR, ...). The GetSchedDelay procedure converts the
-- combined output changes times to the single delay (delta
-- time) value for scheduling the output change (passed to
-- VitalGlitchOnEvent).
--
-- The values in 'schd' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- The output times are computed from the model INPUT value
-- and not the final value. For this reason, 'BufPath' should
-- be used to compute the output times for a non-inverting
-- delay paths and 'InvPath' should be used to compute the
-- ouput times for inverting delay paths. Delay paths which
-- include both non-inverting and paths require usage of both
-- 'BufPath' and 'InvPath'. (IE this is needed for the
-- select->output path of a MUX -- See the VitalMUX model).
--
--
-- Parameters : schd....... Computed output result times. (INOUT parameter
-- modified only on input edges)
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays from this input
--
---------------------------------------------------------------------------
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr01);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr10);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr10);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr01);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
---------------------------------------------------------------------------
-- Procedure : BufEnab, InvEnab
--
-- Purpose : BufEnab and InvEnab compute output change times, from a
-- change on an input enable port for a 3-state driver. The
-- computed output change times are returned in the composite
-- parameters 'schd1', 'schd0'.
--
-- BufEnab and InpEnab are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the non-enable input ports of
-- a model (See BufPath, InvPath) are combined using the delay
-- selection functions (VitalAND, VitalOR, ...). The
-- GetSchedDelay procedure combines the output times on the
-- enable path with the output times from the data path(s) and
-- computes the single delay (delta time) value for scheduling
-- the output change (passed to VitalGlitchOnEvent)
--
-- The values in 'schd*' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- 'schd1' contains output times for 1->Z, Z->1 transitions.
-- 'schd0' contains output times for 0->Z, Z->0 transitions.
--
-- 'BufEnab' is used for computing the output times for an
-- high asserted enable (output 'Z' for enable='0').
-- 'InvEnab' is used for computing the output times for an
-- low asserted enable (output 'Z' for enable='1').
--
-- Note: separate 'schd1', 'schd0' parameters are generated
-- so that the combination of the delay paths from
-- multiple enable signals may be combined using the
-- same functions/operators used in combining separate
-- data paths. (See exampe 2 below)
--
--
-- Parameters : schd1...... Computed output result times for 1->Z, Z->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- schd0...... Computed output result times for 0->Z, 0->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays for the enable -> output path.
--
---------------------------------------------------------------------------
PROCEDURE BufEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(trz1);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(trz0);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(tr1z);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(tr0z);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(tr1z);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(tr0z);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(trz1);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(trz0);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
---------------------------------------------------------------------------
-- Procedure : GetSchedDelay
--
-- Purpose : GetSchedDelay computes the final delay (incremental) for
-- for scheduling an output signal. The delay is computed
-- from the absolute output times in the 'NewSched' parameter.
-- (See BufPath, InvPath).
--
-- Computation of the output delay for non-3_state outputs
-- consists of selection the appropriate output time based
-- on the new output value 'NewValue' and subtracting 'NOW'
-- to convert to an incremental delay value.
--
-- The Computation of the output delay for 3_state output
-- also includes combination of the enable path delay with
-- the date path delay.
--
-- Parameters : NewDelay... Returned output delay value.
-- GlchDelay.. Returned output delay for the start of a glitch.
-- NewValue... New output value.
-- CurValue... Current value of the output.
-- NewSched... Composite containing the combined absolute
-- output times from the data inputs.
-- EnSched1... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 1->Z, Z->1)
-- EnSched0... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 0->Z, Z->0)
--
---------------------------------------------------------------------------
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType
) IS
VARIABLE Tim, Glch : TIME;
BEGIN
CASE To_UX01(NewValue) IS
WHEN '0' => Tim := NewSched.inp0;
Glch := NewSched.Glch1;
WHEN '1' => Tim := NewSched.inp1;
Glch := NewSched.Glch0;
WHEN OTHERS => Tim := NewSched.InpX;
Glch := -1 ns;
END CASE;
IF (CurValue /= NewValue)
THEN Glch := -1 ns;
END IF;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT VitalTimeArray;
VARIABLE GlchDelay : OUT VitalTimeArray;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT CurValue : IN std_logic_vector;
CONSTANT NewSched : IN SchedArray
) IS
VARIABLE Tim, Glch : TIME;
ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1)
IS NewDelay;
ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1)
IS GlchDelay;
ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1)
IS NewSched;
ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 )
IS NewValue;
ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 )
IS CurValue;
BEGIN
FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP
CASE To_UX01(NewValueAlias(n)) IS
WHEN '0' => Tim := NewSchedAlias(n).inp0;
Glch := NewSchedAlias(n).Glch1;
WHEN '1' => Tim := NewSchedAlias(n).inp1;
Glch := NewSchedAlias(n).Glch0;
WHEN OTHERS => Tim := NewSchedAlias(n).InpX;
Glch := -1 ns;
END CASE;
IF (CurValueAlias(n) /= NewValueAlias(n))
THEN Glch := -1 ns;
END IF;
NewDelayAlias(n) := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelayAlias(n) := Glch;
ELSE GlchDelayAlias(n) := Glch - NOW;
END IF; -- glch < 0 ns
END LOOP;
RETURN;
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType;
CONSTANT EnSched1 : IN SchedType;
CONSTANT EnSched0 : IN SchedType
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE Tim, Glch : TIME;
BEGIN
CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS
WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0);
WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := EnSched1.Glch0;
WHEN "0Z" => Tim := EnSched0.inp0;
Glch := NewSched.Glch1;
WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := EnSched0.Glch0;
WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0);
WHEN "1Z" => Tim := EnSched1.inp0;
Glch := NewSched.Glch0;
WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
IF NewSched.Glch0 > NOW
THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
IF NewSched.Glch1 > NOW
THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := 0 ns;
WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := 0 ns;
WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
END CASE;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
---------------------------------------------------------------------------
-- Operators and Functions for combination (selection) of path delays
-- > These functions support selection of the "appripriate" path delay
-- dependent on the logic function.
-- > These functions only "select" from the possable output times. No
-- calculation (addition) of delays is performed.
-- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay'
-- > See primitive PROCEDURE models for examples.
---------------------------------------------------------------------------
FUNCTION "not" (
CONSTANT a : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := a.inp0 ;
z.inp0 := a.inp1 ;
z.InpX := a.InpX ;
z.Glch1 := a.Glch0;
z.Glch0 := a.Glch1;
RETURN (z);
END;
FUNCTION "and" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp1 , b.inp1 );
z.inp0 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch1, b.Glch1 );
z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "or" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp0 , b.inp0 );
z.inp1 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch0, b.Glch0 );
z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
FUNCTION "nand" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp1 , b.inp1 );
z.inp1 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch1, b.Glch1 );
z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "nor" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp0 , b.inp0 );
z.inp0 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch0, b.Glch0 );
z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) NOR (a NOR b)
z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ),
Minimum (ab.inp1 , bb.inp1 ) );
z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ),
Maximum (ab.inp0 , bb.inp0 ) );
z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ),
Maximum (ab.InpX , bb.InpX ) );
z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0),
GlitchMinTime (ab.Glch1, bb.Glch1) );
z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1),
Maximum (ab.Glch0, bb.Glch0) );
RETURN (z);
END;
FUNCTION VitalXNOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) OR (a NOR b)
z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ),
Minimum (ai.inp1 , bi.inp1 ) );
z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ),
Maximum (ai.inp0 , bi.inp0 ) );
z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ),
Maximum (ai.InpX , bi.InpX ) );
z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0),
GlitchMinTime (ai.Glch1, bi.Glch1) );
z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1),
Maximum (ai.Glch0, bi.Glch0) );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi),
VitalXOR2 (ai,ab, bi,bb),
cb, ci );
END;
FUNCTION VitalXNOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
cb, ci );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 4-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
FUNCTION VitalXNOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for N-bit Logical gates.
-- ------------------------------------------------------------------------
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXNOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT d1, d0 : IN SchedType;
CONSTANT sb, SI : IN SchedType
) RETURN SchedType IS
BEGIN
RETURN (d1 AND sb) OR (d0 AND (NOT SI) );
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN SchedArray4;
CONSTANT sb : IN SchedArray2;
CONSTANT SI : IN SchedArray2
) RETURN SchedType IS
BEGIN
RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) )
OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) );
END;
FUNCTION VitalMUX8 (
CONSTANT Data : IN SchedArray8;
CONSTANT sb : IN SchedArray3;
CONSTANT SI : IN SchedArray3
) RETURN SchedType IS
BEGIN
RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) )
OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) );
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT sMsb : INTEGER := sb'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
BEGIN
IF sb'LENGTH = 1 THEN
RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) );
ELSIF sb'LENGTH = 2 THEN
RETURN VitalMUX4( Data, sb, SI );
ELSIF sb'LENGTH = 3 THEN
RETURN VitalMUX8( Data, sb, SI );
ELSIF sb'LENGTH > 3 THEN
RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ))
OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ));
ELSE
RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1
END IF;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT msb : INTEGER := 2**sb'LENGTH;
VARIABLE lDat : SchedArray(msb DOWNTO 1);
ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data;
ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb;
ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
FOR i IN msb DOWNTO Data'LENGTH+1 LOOP
lDat(i) := DefSchedAnd;
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
RETURN VInterMux( lDat, sbAlias, siAlias );
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT DataB : IN SchedType;
CONSTANT DataI : IN SchedType;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray2;
BEGIN
Result(1) := Enable AND ( DataB);
Result(0) := Enable AND (NOT DataI);
RETURN Result;
END;
FUNCTION VitalDECODER4 (
CONSTANT DataB : IN SchedArray2;
CONSTANT DataI : IN SchedArray2;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray4;
BEGIN
Result(3) := Enable AND ( DataB(1)) AND ( DataB(0));
Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0));
Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0));
Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER8 (
CONSTANT DataB : IN SchedArray3;
CONSTANT DataI : IN SchedArray3;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray8;
BEGIN
Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0));
Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0));
Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0));
Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0));
Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0));
Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0));
Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0));
Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER (
CONSTANT DataB : IN SchedArray;
CONSTANT DataI : IN SchedArray;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
CONSTANT DMsb : INTEGER := DataB'LENGTH - 1;
ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB;
ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI;
BEGIN
IF DataB'LENGTH = 1 THEN
RETURN VitalDECODER2 ( DataBAlias( 0 ),
DataIAlias( 0 ), Enable );
ELSIF DataB'LENGTH = 2 THEN
RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0),
DataIAlias(1 DOWNTO 0), Enable );
ELSIF DataB'LENGTH = 3 THEN
RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0),
DataIAlias(2 DOWNTO 0), Enable );
ELSIF DataB'LENGTH > 3 THEN
RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataBAlias(DMsb)) )
& VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataIAlias(DMsb)) );
ELSE
RETURN DefSchedArray2;
END IF;
END;
-------------------------------------------------------------------------------
-- PRIMITIVES
-------------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b);
END;
--
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b);
END;
--
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b);
END;
--
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NAND b);
END;
--
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NOR b);
END;
--
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b));
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c);
END;
--
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c);
END;
--
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c);
END;
--
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c));
END;
--
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c));
END;
--
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c));
END;
-- ---------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ---------------------------------------------------------------------------
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c AND d);
END;
--
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c OR d);
END;
--
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c XOR d);
END;
--
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c AND d));
END;
--
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c OR d));
END;
--
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c XOR d));
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01(Data));
END;
--
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf0_Table(Enable,Data));
END;
--
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf1_Table(Enable,Data));
END;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01Z(Data));
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT Data);
END;
--
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf0_Table(Enable,Data));
END;
--
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf1_Table(Enable,Data));
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect) IS
WHEN '0' => Result := To_UX01(Data0);
WHEN '1' => Result := To_UX01(Data1);
WHEN OTHERS => Result := VitalSame( Data1, Data0 );
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Slct : std_logic_vector2;
VARIABLE Result : UX01;
BEGIN
Slct := To_X01(dSelect);
CASE Slct IS
WHEN "00" => Result := To_UX01(Data(0));
WHEN "01" => Result := To_UX01(Data(1));
WHEN "10" => Result := To_UX01(Data(2));
WHEN "11" => Result := To_UX01(Data(3));
WHEN "0X" => Result := VitalSame( Data(1), Data(0) );
WHEN "1X" => Result := VitalSame( Data(2), Data(3) );
WHEN "X0" => Result := VitalSame( Data(2), Data(0) );
WHEN "X1" => Result := VitalSame( Data(3), Data(1) );
WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)),
VitalSame(Data(1),Data(0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect(2)) IS
WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0));
WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0));
WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0)),
VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector
) RETURN std_ulogic IS
CONSTANT sMsb : INTEGER := dSelect'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE Result : UX01;
BEGIN
IF dSelect'LENGTH = 1 THEN
Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) );
ELSIF dSelect'LENGTH = 2 THEN
Result := VitalMUX4( DataAlias, dSelAlias );
ELSIF dSelect'LENGTH > 2 THEN
CASE To_X01(dSelect(sMsb)) IS
WHEN '0' =>
Result := VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN '1' =>
Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN OTHERS =>
Result := VitalSame(
VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) ),
VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) )
);
END CASE;
ELSE
Result := 'X'; -- dselect'LENGTH < 1
END IF;
RETURN Result;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
CONSTANT msb : INTEGER := 2**dSelect'LENGTH;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X');
VARIABLE Result : UX01;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
Result := VInterMux( lDat, dSelAlias );
RETURN ResultMap(Result);
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2 IS
VARIABLE Result : std_logic_vector2;
BEGIN
Result(1) := ResultMap(Enable AND ( Data));
Result(0) := ResultMap(Enable AND (NOT Data));
RETURN Result;
END;
--
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4 IS
VARIABLE Result : std_logic_vector4;
BEGIN
Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0)));
Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0)));
Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0)));
Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0)));
RETURN Result;
END;
--
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8 IS
VARIABLE Result : std_logic_vector8;
BEGIN
Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0));
Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0));
Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(0) := ResultMap ( Enable AND Result(0) );
Result(1) := ResultMap ( Enable AND Result(1) );
Result(2) := ResultMap ( Enable AND Result(2) );
Result(3) := ResultMap ( Enable AND Result(3) );
Result(4) := ResultMap ( Enable AND Result(4) );
Result(5) := ResultMap ( Enable AND Result(5) );
Result(6) := ResultMap ( Enable AND Result(6) );
Result(7) := ResultMap ( Enable AND Result(7) );
RETURN Result;
END;
--
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector IS
CONSTANT DMsb : INTEGER := Data'LENGTH - 1;
ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data;
BEGIN
IF Data'LENGTH = 1 THEN
RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap );
ELSIF Data'LENGTH = 2 THEN
RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH = 3 THEN
RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH > 3 THEN
RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataAlias(DMsb)), ResultMap )
& VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataAlias(DMsb)), ResultMap );
ELSE RETURN "X";
END IF;
END;
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXOR ( Data );
new_schd := VitalXOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXNOR ( Data );
new_schd := VitalXNOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b;
new_schd := a_schd AND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b;
new_schd := a_schd OR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NAND b;
new_schd := a_schd NAND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NOR b;
new_schd := a_schd NOR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b;
new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b);
new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
--
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c;
new_schd := a_schd AND b_schd AND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c;
new_schd := a_schd OR b_schd OR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND c;
new_schd := (a_schd AND b_schd) NAND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR c;
new_schd := (a_schd OR b_schd) NOR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c;
new_schd := VitalXOR3 ( ab_schd,ai_schd,
bb_schd,bi_schd,
cb_schd,ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c);
new_schd := VitalXNOR3 ( ab_schd, ai_schd,
bb_schd, bi_schd,
cb_schd, ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c AND d;
new_schd := a_schd AND b_schd AND c_schd AND d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c OR d;
new_schd := a_schd OR b_schd OR c_schd OR d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND (c AND d);
new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR (c OR d);
new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c XOR d;
new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c XOR d);
new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(To_UX01(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := To_UX01(a); -- convert to forcing strengths
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF1( Data, Enable );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01Z) THEN
LOOP
q <= ResultMap(To_UX01Z(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS
WHEN "00" => Dly := tpd_a_q(tr10);
WHEN "01" => Dly := tpd_a_q(tr01);
WHEN "0Z" => Dly := tpd_a_q(tr0z);
WHEN "0X" => Dly := tpd_a_q(tr01);
WHEN "10" => Dly := tpd_a_q(tr10);
WHEN "11" => Dly := tpd_a_q(tr01);
WHEN "1Z" => Dly := tpd_a_q(tr1z);
WHEN "1X" => Dly := tpd_a_q(tr10);
WHEN "Z0" => Dly := tpd_a_q(trz0);
WHEN "Z1" => Dly := tpd_a_q(trz1);
WHEN "ZZ" => Dly := 0 ns;
WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0));
WHEN "X0" => Dly := tpd_a_q(tr10);
WHEN "X1" => Dly := tpd_a_q(tr01);
WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z));
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
NewValue := To_UX01Z(a);
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(NOT a);
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT a;
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF1( Data, Enable );
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE d1_Schd, d0_Schd : SchedType;
VARIABLE dSel_bSchd, dSel_iSchd : SchedType;
VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_d1_q = VitalZeroDelay01)
AND (tpd_d0_q = VitalZeroDelay01)
AND (tpd_dsel_q = VitalZeroDelay01) ) THEN
LOOP
q <= VitalMUX2 ( d1, d0, dSel, ResultMap );
WAIT ON d1, d0, dSel;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX2 ( d1, d0, dSel );
new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON d1, d0, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray4;
VARIABLE Data_Edge : EdgeArray4;
VARIABLE dSel_Edge : EdgeArray2;
VARIABLE dSel_bSchd : SchedArray2;
VARIABLE dSel_iSchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX4 ( Data, dSel );
new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray8;
VARIABLE Data_Edge : EdgeArray8;
VARIABLE dSel_Edge : EdgeArray3;
VARIABLE dSel_bSchd : SchedArray3;
VARIABLE dSel_iSchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX8 ( Data, dSel );
new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE dSel_Edge : EdgeArray(dSel'RANGE);
VARIABLE dSel_bSchd : SchedArray(dSel'RANGE);
VARIABLE dSel_iSchd : SchedArray(dSel'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX ( Data, dSel );
new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- Caution: If 'ResultMap' defines other than strength mapping, the
-- delay selection is not defined.
-- ------------------------------------------------------------------------
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : std_logic_vector2;
VARIABLE Glitch_Data : GlitchArray2;
VARIABLE new_schd : SchedArray2;
VARIABLE Dly, Glch : TimeArray2;
VARIABLE Enable_Schd : SchedType := DefSchedType;
VARIABLE Data_BSchd, Data_ISchd : SchedType;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN
LOOP
q <= VitalDECODER2(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER2 ( Data, Enable, ResultMap );
new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; -- SN
END;
--
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector4;
VARIABLE Glitch_Data : GlitchArray4;
VARIABLE new_schd : SchedArray4;
VARIABLE Dly, Glch : TimeArray4;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray2;
VARIABLE Data_BSchd, Data_ISchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER4(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER4 ( Data, Enable, ResultMap );
new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector8;
VARIABLE Glitch_Data : GlitchArray8;
VARIABLE new_schd : SchedArray8;
VARIABLE Dly, Glch : TimeArray8;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray3;
VARIABLE Data_BSchd, Data_ISchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER8 ( Data, Enable, ResultMap );
new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector(q'RANGE);
VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE);
VARIABLE new_schd : SchedArray(q'RANGE);
VARIABLE Dly, Glch : VitalTimeArray(q'RANGE);
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER ( Data, Enable, ResultMap );
new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1)
:= To_X01(DataIn);
VARIABLE Index : INTEGER;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1),
0 TO (TruthTable'LENGTH(2)-1))
:= TruthTable;
BEGIN
-- search through each row of the truth table
IF OutSize > 0 THEN
ColLoop:
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each input element of the entry
FOR j IN 0 TO InputSize LOOP
IF (j = InputSize) THEN -- This entry matches
-- Return the Result
Index := 0;
FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP
TruthOutputX01Z ( TableAlias(i,k),
ReturnValue(Index), Err);
EXIT WHEN Err;
Index := Index + 1;
END LOOP;
IF Err THEN
ReturnValue := (OTHERS => 'X');
END IF;
RETURN ReturnValue;
END IF;
IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN
VitalError ( "VitalTruthTable", ErrInpSym,
To_TruthChar(TableAlias(i,j)) );
EXIT ColLoop;
END IF;
EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j),
TableAlias(i, j)));
END LOOP RowLoop;
END LOOP ColLoop;
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
END IF;
RETURN ReturnValue;
END VitalTruthTable;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
IF (OutSize > 0) THEN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
RETURN (TempResult(0));
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
RETURN 'X';
END IF;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ResLeng : INTEGER := Result'LENGTH;
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng);
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF (ResLeng > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF (ResLeng < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0);
Result <= TempResult;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
IF (ActResLen > 0) THEN
Result <= TempResult(0);
END IF;
END VitalTruthTable;
-- ------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1)
:= To_X01(DataIn);
VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1)
:= To_X01(PreviousDataIn);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1)
:= To_X01(Result);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN
VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn<DataIn");
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSIF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevDataAlias, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result := ResultAlias;
PrevDataAlias(0 TO InputSize - 1) := DataInAlias;
PreviousDataIn := PrevDataAlias;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic; -- states
VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states
CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data
CONSTANT DataIn : IN std_logic_vector -- Inputs
) IS
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
BEGIN
ResultAlias(0) := Result;
VitalStateTable ( StateTable => StateTable,
DataIn => DataIn,
NumStates => 1,
Result => ResultAlias,
PreviousDataIn => PreviousDataIn
);
Result := ResultAlias(0);
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result <= ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
DataInAlias := To_X01(DataIn);
ResultAlias := To_X01(Result);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result <= ResultAlias;
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
Result <= 'X';
ELSE
IF ( 1 > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
ResultAlias(0) := To_X01(Result);
DataInAlias := To_X01(DataIn);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, 1, ResultAlias);
Result <= ExpResult(OutSize-1);
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
-- ------------------------------------------------------------------------
-- std_logic resolution primitive
-- ------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
CONSTANT Data : IN std_logic_vector
) IS
VARIABLE uData : std_ulogic_vector(Data'RANGE);
BEGIN
FOR i IN Data'RANGE LOOP
uData(i) := Data(i);
END LOOP;
q <= resolved(uData);
END;
END VITAL_Primitives;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2691.vhd | 4 | 1662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2691.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p03n01i02691ent IS
--ERROR: underline cannot trail an integer literal
constant a:integer:=567_; -- failure_here
END c13s04b01x00p03n01i02691ent;
ARCHITECTURE c13s04b01x00p03n01i02691arch OF c13s04b01x00p03n01i02691ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p03n01i02691 - Underlines cannot trail a decimal literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p03n01i02691arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd | 4 | 1148 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket65/bug1.vhdl | 3 | 476 | entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2275.vhd | 4 | 1851 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2275.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02275ent IS
END c07s02b06x00p14n01i02275ent;
ARCHITECTURE c07s02b06x00p14n01i02275arch OF c07s02b06x00p14n01i02275ent IS
BEGIN
TESTING: PROCESS
type ENUMERATION_TYPE is (ONE,TWO,THREE,FOUR);
variable T : TIME := 1 sec;
BEGIN
T := ONE * 1 MIN; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02275 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02275arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2717.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2717.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p02n01i02717ent IS
END c13s04b02x00p02n01i02717ent;
ARCHITECTURE c13s04b02x00p02n01i02717arch OF c13s04b02x00p02n01i02717ent IS
constant T2 : Real := 5#1234.4321 ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b02x00p02n01i02717 - Missing sharp."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p02n01i02717arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd | 4 | 2381 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1607.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01607ent IS
END c08s11b00x00p04n01i01607ent;
ARCHITECTURE c08s11b00x00p04n01i01607arch OF c08s11b00x00p04n01i01607ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
variable k : integer := 0;
BEGIN
for I in 0 to 10 loop
-- Check to see if we have gone through this more than once.
if (not(GONE_THROUGH_ONCE)) then
GONE_THROUGH_ONCE := TRUE;
else
assert (FALSE)
report "Going through loop more than once.";
end if;
-- Exit the loop.
exit;
k := 1;
-- The following should never be executed.
assert (FALSE)
report "This statement should NEVER be executed.";
end loop;
-- Verify that we went through at least once.
assert( GONE_THROUGH_ONCE )
report "Did not go through the loop at all.";
assert NOT(k=0)
report "***PASSED TEST: c08s11b00x00p04n01i01607"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s11b00x00p04n01i01607 - The loop should terminate when the condition is TRUE."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01607arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3108.vhd | 4 | 1950 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3108.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c05s01b00x00p17n01i03108pkg is
attribute A1 : INTEGER;
end c05s01b00x00p17n01i03108pkg;
use work.c05s01b00x00p17n01i03108pkg.all;
ENTITY c05s01b00x00p17n01i03108ent IS
END c05s01b00x00p17n01i03108ent;
ARCHITECTURE c05s01b00x00p17n01i03108arch OF c05s01b00x00p17n01i03108ent IS
attribute A1 of c05s01b00x00p17n01i03108pkg : package is 9 ; -- Failure_here
-- ERROR: package attribute specification can appear only immediatly
-- within the declarative region of a package
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p17n01i03108 - Package attribute specification can appear only immediately in package declarative part."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p17n01i03108arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1730.vhd | 4 | 1741 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1730.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01730ent IS
port (signal AA,BB: in bit);
END c09s03b00x00p02n01i01730ent;
ARCHITECTURE c09s03b00x00p02n01i01730arch OF c09s03b00x00p02n01i01730ent IS
procedure P1 (signal A,B: in bit; signal C: out bit) is
begin
C <= A and B;
end;
signal CC : bit;
BEGIN
PROC P1 (AA,BB,CC); -- Failure_here
-- Colon is misssing
assert FALSE
report "***FAILED TEST: c09s03b00x00p02n01i01730 - Colon between the label and a procedure call statement is missing."
severity ERROR;
END c09s03b00x00p02n01i01730arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd | 4 | 10326 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc861.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00861pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00861pkg_b;
package body c01s03b01x00p12n01i00861pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00861pkg_b;
use work.c01s03b01x00p12n01i00861pkg_b.all;
package c01s03b01x00p12n01i00861pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to six) ;
signal Sin2 : boolean_vector(zero to six) ;
signal Sin4 : severity_level_vector(zero to six) ;
signal Sin5 : integer_vector(zero to six) ;
signal Sin6 : real_vector(zero to six) ;
signal Sin7 : time_vector(zero to six) ;
signal Sin8 : natural_vector(zero to six) ;
signal Sin9 : positive_vector(zero to six) ;
signal Sin10: array_rec_std(zero to six) ;
end c01s03b01x00p12n01i00861pkg_a;
use work.c01s03b01x00p12n01i00861pkg_a.all;
use work.c01s03b01x00p12n01i00861pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00861pkg_a.all;
use work.c01s03b01x00p12n01i00861pkg_b.all;
ENTITY c01s03b01x00p12n01i00861ent IS
END c01s03b01x00p12n01i00861ent;
ARCHITECTURE c01s03b01x00p12n01i00861arch OF c01s03b01x00p12n01i00861ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
Gif : if fifteen = 15 generate
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
end generate;
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00861"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00861 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00861arch;
configuration c01s03b01x00p12n01i00861cfg of c01s03b01x00p12n01i00861ent is
for c01s03b01x00p12n01i00861arch
for K
for GIF
for T5:test use configuration work.testbench;
end for;
end for;
for G(zero to 1)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(2 to three)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1820.vhd | 4 | 1989 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1820.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01820ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01820ent;
ARCHITECTURE c07s01b00x00p08n01i01820arch OF c07s01b00x00p08n01i01820ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
case small_int is -- type name illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01820 - Type names are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01820arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd | 4 | 2327 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc922.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s03b00x00p17n01i00922ent_a is
port ( x : integer; y : real );
end c10s03b00x00p17n01i00922ent_a;
architecture c10s03b00x00p17n01i00922arch_a of c10s03b00x00p17n01i00922ent_a is
begin
TESTING : PROCESS
BEGIN
assert NOT( real(x)=y )
report "***PASSED TEST: c10s03b00x00p17n01i00922"
severity NOTE;
assert ( real(x)=y )
report "***FAILED TEST: c10s03b00x00p17n01i00922 - Named formal ports can be made visible by selection."
severity ERROR;
wait;
END PROCESS TESTING;
end c10s03b00x00p17n01i00922arch_a;
ENTITY c10s03b00x00p17n01i00922ent IS
END c10s03b00x00p17n01i00922ent;
ARCHITECTURE c10s03b00x00p17n01i00922arch OF c10s03b00x00p17n01i00922ent IS
component d
end component;
signal a : integer := 10;
signal b : real := 10.0;
BEGIN
instance : d;
END c10s03b00x00p17n01i00922arch;
configuration c10s03b00x00p17n01i00922cfg of c10s03b00x00p17n01i00922ent is
for c10s03b00x00p17n01i00922arch
for instance : d
use entity work.c10s03b00x00p17n01i00922ent_a(c10s03b00x00p17n01i00922arch_a) port map ( x => a, y => b );
end for;
end for;
end c10s03b00x00p17n01i00922cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2625.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2625.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02625ent IS
END c13s03b01x00p02n01i02625ent;
ARCHITECTURE c13s03b01x00p02n01i02625arch OF c13s03b01x00p02n01i02625ent IS
BEGIN
TESTING: PROCESS
variable k}k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02625 - Identifier can not contain '}'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02625arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd | 4 | 1902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00228ent IS
END c03s01b01x00p07n01i00228ent;
ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
type MVL is ('0', '1', 'Z') ;
type MVL1 is ('0', '1', 'Z', 'X') ;
signal S1 : MVL ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 10 ns,
'0' after 20 ns,
'Z' after 50 ns;
wait for 60 ns;
assert NOT( S1 = 'Z' )
report "***PASSED TEST: c03s01b01x00p07n01i00228"
severity NOTE;
assert ( S1 = 'Z' )
report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00228arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1990.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1990.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01990ent IS
END c07s02b02x00p07n01i01990ent;
ARCHITECTURE c07s02b02x00p07n01i01990arch OF c07s02b02x00p07n01i01990ent IS
BEGIN
TESTING: PROCESS
type ft is file of integer;
file f1 : ft is "01.vhdl";
file f2 : ft is "02.vhdl";
BEGIN
if (f1/=f2) then -- Failure_here
-- equality and inequality operators are
NULL; -- not defined for file types.
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i01990 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01990arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2889.vhd | 4 | 1745 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2889.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p04n03i02889ent IS
procedure proc1 (sig1 : inout real) is
begin
-- Failure_here: Inout parameters are assumed to be object class VARIABLE
sig1 <= 27.3;
end proc1;
END c02s01b01x00p04n03i02889ent;
ARCHITECTURE c02s01b01x00p04n03i02889arch OF c02s01b01x00p04n03i02889ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p04n03i02889 - The target of a signal assignment statement cannot be a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p04n03i02889arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1829.vhd | 4 | 1808 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1829.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01829ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of bit;
END c07s01b00x00p08n01i01829ent;
ARCHITECTURE c07s01b00x00p08n01i01829arch OF c07s01b00x00p08n01i01829ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus (c07s01b00x00p08n01i01829ent) <= '0' after 5 ns; -- entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01829 - Entity name are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01829arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd | 4 | 1826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01574ent IS
END c08s10b00x00p04n01i01574ent;
ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
next L when i > 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s10b00x00p04n01i01574"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01574arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc369.vhd | 4 | 1854 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc369.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00369ent IS
END c03s02b01x01p03n02i00369ent;
ARCHITECTURE c03s02b01x01p03n02i00369arch OF c03s02b01x01p03n02i00369ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A2 is array (FALSE to FALSE,
BFALSE range <>) of ONETWO; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00369 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00369arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd | 4 | 1997 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1156.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01156pkg is
type A1 is array (1 to 5) of BOOLEAN;
end c06s06b00x00p02n01i01156pkg;
use work.c06s06b00x00p02n01i01156pkg.all;
ENTITY c06s06b00x00p02n01i01156ent IS
port (PT: A1) ;
attribute AT1 : BOOLEAN;
attribute AT1 of PT : signal is TRUE;
END c06s06b00x00p02n01i01156ent;
ARCHITECTURE c06s06b00x00p02n01i01156arch OF c06s06b00x00p02n01i01156ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if PT'AT1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01156"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01156 - The prefix of an attribute name may be a slice name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01156arch;
| gpl-2.0 |
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