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6769/VHDL | Lab_6/UnitSingular/Control/simulation/qsim/work/@control_unit/_primary.vhd | 1 | 766 | library verilog;
use verilog.vl_types.all;
entity Control_unit is
port(
IRset : in vl_logic_vector(0 to 8);
IRin : out vl_logic;
Riout : out vl_logic_vector(0 to 7);
Gout : out vl_logic;
DINout : out vl_logic;
Rin : out vl_logic_vector(0 to 7);
Ain : out vl_logic;
Gin : out vl_logic;
AddSub : out vl_logic;
Tstep_Q : in vl_logic_vector(1 downto 0);
Clear : out vl_logic;
Run : in vl_logic;
Resetn : in vl_logic;
Done : out vl_logic
);
end Control_unit;
| gpl-2.0 |
6769/VHDL | Lab_1_partB/adjustAdder4.vhd | 1 | 631 | entity adjustAdder4 is
port(origin:in bit_vector(3 downto 0);
adjusted:out bit_vector(3 downto 0);
carryIn:in bit;
carryAdjusted:out bit);
end adjustAdder4;
architecture conversion of adjustAdder4 is
component Adder4
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit);
end component;
signal z:bit:='0';
signal never_use:bit;
signal S_mid:bit_vector(3 downto 0);
begin
z<=carryIn or (origin(3)and (origin(2) or origin(1)) );
carryAdjusted<=z;
FA4:Adder4 port map (origin,"0110",'0',S_mid,never_use);
adjusted<=origin when z='0'
else s_mid ;
end conversion;
| gpl-2.0 |
6769/VHDL | Lab_3/Part2/simulation/qsim/work/@view_input_vlg_vec_tst/_primary.vhd | 1 | 104 | library verilog;
use verilog.vl_types.all;
entity View_input_vlg_vec_tst is
end View_input_vlg_vec_tst;
| gpl-2.0 |
6769/VHDL | Lab_3/Part1/FSM_core.vhd | 1 | 1965 | --lab3-Part1
--FSM with 0-8 state
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:integer range 0 to 8;
begin
stateout<=state;
process(X,State)
begin
case State is
when 0=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=1;
end if;
when 1=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=2;
end if;
when 2=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=3;
end if;
when 3=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 4=>
Z<='1';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 5=>
Z<='0';
if X='0' then nextState<=6;
else nextState<=1;
end if;
when 6=>
Z<='0';
if X='0' then nextState<=7;
else nextState<=1;
end if;
when 7=>
Z<='0';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when 8=>
Z<='1';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when others=>null;
end case;
end process;
--nextStateRegister
process(CLK,reset)
begin
if reset='0' then State<=0;
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
| gpl-2.0 |
6769/VHDL | Lab_6/TheFinalCodeVersion/upcount.vhd | 2 | 476 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity upcount is
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end upcount;
architecture Behavior of upcount is
signal Count : STD_LOGIC_VECTOR(1 downto 0);
begin
process (Clock)
begin
if (Clock'EVENT and Clock = '1') then
if Clear = '1' then
Count <= "00";
else
Count <= Count + 1;
end if;
end if;
end process;
Q <= Count;
end Behavior; | gpl-2.0 |
6769/VHDL | Lab_2_part2/clock/simulation/qsim/work/clock_second_vlg_vec_tst/_primary.vhd | 1 | 108 | library verilog;
use verilog.vl_types.all;
entity clock_second_vlg_vec_tst is
end clock_second_vlg_vec_tst;
| gpl-2.0 |
gregani/la16fw | clock.vhd | 1 | 3843 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
generic(
CLK_FAST_DIV : integer;
CLK_FAST_MUL : integer;
STARTUP_WAIT : boolean := false
);
port(
clk_in : in std_logic;
reset : in std_logic;
clk : out std_logic;
clk_fb : in std_logic;
clk_fast : out std_logic;
locked : out std_logic
);
end clock;
architecture behavioral of clock is
begin
-- DCM_SP: Digital Clock Manager Circuit
-- Spartan-3A
-- Xilinx HDL Language Template, version 14.7
DCM_SP_inst : DCM_SP
generic map(
CLKDV_DIVIDE => 12.0, -- 4MHz on CLKDV
CLKFX_DIVIDE => CLK_FAST_DIV,
CLKFX_MULTIPLY => CLK_FAST_MUL, -- 100MHz on CLKFX
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.83333333333333333, -- 48MHz
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE--STARTUP_WAIT -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
)
port map(
CLKIN => clk_in, -- 48MHz clock input (from IBUFG, BUFG or DCM)
RST => reset, -- DCM asynchronous reset input
CLK0 => clk, -- 0 degree DCM CLK ouptput
CLK90 => open, -- 90 degree DCM CLK output
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_fast, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked, -- DCM LOCK status output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk_fb, -- DCM clock feedback
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
PSDONE => open -- Dynamic phase adjust done output
);
end behavioral;
| gpl-2.0 |
sorgelig/SAMCoupe_MIST | t80/T80_ALU.vhd | 2 | 12080 | --------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
-- 0240 : Added GB operations
-- 0242 : Cleanup
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
if IR(2 downto 0) = "110" or XY_State /= "00" then
F_Out(Flag_X) <= WZ(11);
F_Out(Flag_Y) <= WZ(13);
else
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
| gpl-2.0 |
6769/VHDL | Lab_5/SingluarUnit/controller/simulation/qsim/work/@controller/_primary.vhd | 1 | 674 | library verilog;
use verilog.vl_types.all;
entity Controller is
port(
Rb : in vl_logic;
Reset : in vl_logic;
Eq : in vl_logic;
D7 : in vl_logic;
D711 : in vl_logic;
D2312 : in vl_logic;
CLK : in vl_logic;
State_debug : out vl_logic_vector(1 downto 0);
Sp : out vl_logic;
Roll : out vl_logic;
Win : out vl_logic;
Lose : out vl_logic;
Clear : out vl_logic
);
end Controller;
| gpl-2.0 |
6769/VHDL | Lab_4/Part1/View_output.vhd | 1 | 1270 | library ieee;
use ieee.numeric_bit.all;
entity View_output is
port(clk:in bit; reset:in bit;
hex0_out:out bit_vector(7 downto 0);
hex1_out:out bit_vector(7 downto 0);
hex2_out:out bit_vector(7 downto 0));
end entity View_output;
architecture combination_of_View of View_output is
--type
component Threebit_BCD_counter is
port( clk:in bit;reset:in bit;
Counter_Result:out unsigned(11 downto 0) );
end component;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(7 downto 1) -- 7 bit decoded output.
);
end component;
signal mid_12bit_result:unsigned(11 downto 0);
alias mid_hex0:unsigned(3 downto 0) is mid_12bit_result(3 downto 0);
alias mid_hex1:unsigned(3 downto 0) is mid_12bit_result(7 downto 4);
alias mid_hex2:unsigned(3 downto 0) is mid_12bit_result(11 downto 8);
begin
Synthesis:Threebit_BCD_counter port map(clk,reset,mid_12bit_result);
hex0_out(0)<='1';
hex1_out(0)<='1';
hex2_out(0)<='1';
hex0_display:Segment7Decoder port map(bit_vector(mid_hex0),hex0_out(7 downto 1));
hex1_display:Segment7Decoder port map(bit_vector(mid_hex1),hex1_out(7 downto 1));
hex2_display:Segment7Decoder port map(bit_vector(mid_hex2),hex2_out(7 downto 1));
end architecture combination_of_View; | gpl-2.0 |
gregani/la16fw | test_mainmodule.vhd | 1 | 4742 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_main is
end test_main;
architecture behavior of test_main is
-- Component Declaration for the Unit Under Test (UUT)
component mainmodule
-- generic(
-- tick_1M_div : integer
-- );
port(
clk_in : in std_logic;
spi_ss_n : in std_logic;
spi_sclk : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic;
led_out : out std_logic;
fifo_clk : in std_logic;
fifo_empty : out std_logic;
fifo_read_n : in std_logic;
fifo_data : out std_logic_vector(15 downto 0);
logic_data : in std_logic_vector(15 downto 0)
-- logic_data : in std_logic_vector(15 downto 2);
-- debug, debug2 : out std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal spi_ss_n : std_logic := '1';
signal spi_sclk : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal fifo_read_n : std_logic := '1';
signal logic_data : std_logic_vector(15 downto 0) := (others=>'0');
--Outputs
signal spi_miso : std_logic;
signal led_out : std_logic;
signal fifo_empty : std_logic;
signal fifo_data : std_logic_vector(15 downto 0);
-- internal signals
-- Clock period definitions
constant clk_period : time := 20.83 ns;
constant sclk_period : time := 100 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: mainmodule
-- generic map(
-- tick_1M_div => 48
-- )
port map(
clk_in => clk,
spi_ss_n => spi_ss_n,
spi_sclk => spi_sclk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
led_out => led_out,
fifo_clk => clk,
fifo_empty => fifo_empty,
fifo_read_n => fifo_read_n,
fifo_data => fifo_data,
logic_data => logic_data(15 downto 2)
);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- send spi data
procedure spi_start is
begin
wait for 2*sclk_period;
spi_ss_n <= '0';
wait for 2*sclk_period;
end spi_start;
procedure spi_stop is
begin
wait for 2*sclk_period;
spi_ss_n <= '1';
wait for 2*sclk_period;
end spi_stop;
procedure spi_send(data: in unsigned(7 downto 0)) is
begin
for i in 0 to 7 loop
spi_mosi <= data(7-i);
wait for sclk_period/2;
spi_sclk <= '1';
wait for sclk_period/2;
spi_sclk <= '0';
end loop;
end spi_send;
begin
-- wait for internal reset
wait for clk_period*50;
-- insert stimulus here
-- -- read adress 0x00 (fpga bitstream version)
-- spi_start;
-- spi_send('1' & to_unsigned(0, 7));
-- spi_send(to_unsigned(0, 8));
-- spi_stop;
--
-- -- write adress 0x05, data 0x80 (set led pwm to 50%)
-- spi_start;
-- spi_send('0' & to_unsigned(5, 7));
-- spi_send(to_unsigned(128, 8));
-- spi_stop;
--
-- -- select channels
-- spi_start;
-- spi_send('0' & to_unsigned(2, 7));
-- spi_send(to_unsigned(255, 8));
-- spi_stop;
-- spi_start;
-- spi_send('0' & to_unsigned(3, 7));
-- spi_send(to_unsigned(255, 8));
-- spi_stop;
--
-- -- set base clock to 100MHz
-- spi_start;
-- spi_send('0' & to_unsigned(10, 7));
-- spi_send(to_unsigned(0, 8));
-- spi_stop;
--
-- -- set sample rate to 5Mhz => n = 20-1
-- spi_start;
-- spi_send('0' & to_unsigned(4, 7));
-- spi_send(to_unsigned(20 - 1, 8));
-- spi_stop;
--
-- -- start sampling
-- spi_start;
-- spi_send('0' & to_unsigned(1, 7));
-- spi_send(to_unsigned(1, 8));
-- spi_stop;
--
-- -- read some values from fifo
wait until fifo_empty = '0';
-- wait for 100 us;
-- wait for 50*clk_period;
-- wait until falling_edge(clk);
-- wait until rising_edge(clk);
-- for i in 1 to 1000 loop
-- fifo_read_n <= '0';
-- wait for clk_period;
-- fifo_read_n <= '1';
-- wait for clk_period;
-- end loop;
wait;
end process;
end;
| gpl-2.0 |
brandonpollack23/VHDL_pong | PONG/clk_refresh_gen.vhd | 1 | 913 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity clk_refresh_gen is
port
(
clk25Mhz,rst : in std_logic;
clk_refresh : out std_logic
);
end clk_refresh_gen;
architecture bhv of clk_refresh_gen is
constant THIS_WIDTH : integer := integer(ceil(log2(real(208333))));
constant overflow : unsigned := to_unsigned(208333,THIS_WIDTH);
signal count,next_count : unsigned(THIS_WIDTH-1 downto 0);
signal clk,next_clk : std_logic;
begin
process(clk25Mhz)
begin
if(rst = '1') then
count <= (others => '0');
clk <= '0';
elsif(rising_edge(clk25Mhz)) then
count <= next_count;
clk <= next_clk;
end if;
end process;
process(clk25Mhz)
begin
if(count /= overflow) then
next_count <= count + 1;
next_clk <= clk;
else
next_count <= to_unsigned(0,THIS_WIDTH);
next_clk <= not clk;
end if;
end process;
clk_refresh <= clk;
end bhv; | gpl-2.0 |
hwstar/PCIRADIO | urx.vhd | 1 | 6267 | --
-- urx.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2005, Stephen A. Rodgers
--
-- Steve Rodgers <[email protected]>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
--
-- UART receiver
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity urx is
port (
arn : in std_logic;
clk : in std_logic;
rxd : in std_logic;
bclken16: in std_logic;
rxce : out std_logic;
rxbyte : out std_logic_vector(7 downto 0)
);
end urx;
architecture rtl of urx is
type rxstate is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
signal cur_state, next_state : rxstate;
signal samplectren : std_logic;
signal initialsample: std_logic;
signal samplebit : std_logic;
signal shiftena : std_logic;
signal urxregister : std_logic_vector(7 downto 0);
signal samplectr : std_logic_vector(4 downto 0);
signal rxdbits : std_logic_vector(1 downto 0);
begin
-- synchronize RX data to our system clock
rxdsync : process(arn, clk)
begin
if(arn = '0') then
rxdbits <= "11";
elsif(clk'event) and (clk = '1') then
rxdbits(0) <= rxd;
rxdbits(1) <= rxdbits(0);
end if;
end process rxdsync;
-- count at 16x baudrate when enabled
-- This generates the bit sample signal at the right place in the bit cell.
cntsamples : process(arn, clk)
begin
if(arn = '0') then
samplectr <= "00000";
samplebit <= '0';
elsif(clk'event) and (clk = '1') then
samplebit <= '0';
if(samplectren= '1') then
if(bclken16 = '1') then
samplectr <= samplectr + 1;
if(initialsample = '1') then
if(samplectr = 7) then -- 1/2 a bit cell
samplebit <= '1';
samplectr <= "00000";
end if;
else
if(samplectr = 15) then -- a full bit cell
samplebit <= '1';
samplectr <= "00000";
end if;
end if;
end if;
else
samplectr <= "00000";
end if;
end if;
end process cntsamples;
-- receive shift register
rcv_sr : process(arn, clk)
begin
if(arn = '0') then
urxregister <= "00000000";
elsif(clk'event) and (clk = '1') then
if(samplebit = '1') and (shiftena = '1') then
urxregister <= rxdbits(1) & urxregister(7 downto 1);
end if;
end if;
end process rcv_sr;
-- async. part of receiver state machine
sm_async : process(rxdbits(1), bclken16, samplebit, cur_state)
begin
rxce <= '0';
shiftena <= '0';
samplectren <= '0';
initialsample <= '0';
case cur_state is
when s0 => -- start bit edge detect
if(bclken16 = '1') then
if(rxdbits(1) = '0') then
samplectren <= '1';
initialsample <= '1';
next_state <= s1;
else
next_state <= s0;
end if;
else
next_state <= s0;
end if;
when s1 => -- start bit detect, center of bit cell
samplectren <= '1';
initialsample <= '1';
if(samplebit = '1') then
if(rxdbits(1) = '0') then
shiftena <= '1';
initialsample <= '0';
next_state <= s2;
else
initialsample <= '0';
samplectren <= '0';
next_state <= s11; -- noise/glitch?
end if;
else
next_state <= s1;
end if;
when s2 => -- wait for bit cell center on bit 0
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s3;
else
next_state <= s2;
end if;
when s3 => -- wait for bit cell center on bit 1
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s4;
else
next_state <= s3;
end if;
when s4 => -- wait for bit cell center on bit 2
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s5;
else
next_state <= s4;
end if;
when s5 => -- wait for bit cell center on bit 3
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s6;
else
next_state <= s5;
end if;
when s6 => -- wait for bit cell center on bit 4
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s7;
else
next_state <= s6;
end if;
when s7 => -- wait for bit cell center on bit 5
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s8;
else
next_state <= s7;
end if;
when s8 => -- wait for bit cell center on bit 6
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s9;
else
next_state <= s8;
end if;
when s9 => -- wait for bit cell center on bit 7
shiftena <= '1';
samplectren <= '1';
if(samplebit = '1') then
next_state <= s10;
else
next_state <= s9;
end if;
when s10 => -- stop bit detect
samplectren <= '1';
if(samplebit = '1') then
if(rxdbits(1) = '1') then
next_state <= s12; -- done
else
samplectren <= '0';
next_state <= s11; -- framing err?
end if;
else
next_state <= s10;
end if;
when s11 => -- 0 detected for stop bit, framing err? Wait till line goes high
if(bclken16 = '1') then
if(rxdbits(1) = '1') then
next_state <= s0;
else
next_state <= s11;
end if;
else
next_state <= s11;
end if;
when s12 => -- pulse the rxce high for one clock to indicate a byte is ready
rxce <= '1';
next_state <= s0;
when others =>
next_state <= s0;
end case;
end process sm_async;
-- sync part of state machine
sm_sync : process(arn, clk)
begin
if(arn = '0') then
cur_state <= s0;
elsif(clk'event) and (clk = '1') then
cur_state <= next_state;
end if;
end process sm_sync;
rxbyte <= urxregister;
end rtl;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/moltiplicatore_booth.vhd | 1 | 4209 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:39:58 11/23/2015
-- Design Name:
-- Module Name: moltiplicatore_booth - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- Moltilplicando A, moltplicatore B
entity moltiplicatore_booth is
generic ( n : natural := 4;
m : natural := 4);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (m-1 downto 0);
enable : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
done : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0));
end moltiplicatore_booth;
architecture Structural of moltiplicatore_booth is
COMPONENT parte_controllo
generic ( n : natural := 4;
m : natural := 4);
PORT(
clock : in STD_LOGIC;
reset_n_all : in STD_LOGIC;
q0 : in STD_LOGIC;
q_1 : in STD_LOGIC;
enable : in STD_LOGIC;
conteggio : in STD_LOGIC;
load_a : out STD_LOGIC;
load_m : out STD_LOGIC;
load_q : out STD_LOGIC;
reset_n : out STD_LOGIC;
shift : out STD_LOGIC;
sub : out STD_LOGIC;
count_en : out STD_LOGIC;
done : out STD_LOGIC);
END COMPONENT;
COMPONENT parte_operativa
generic ( n : natural := 4;
m : natural := 4);
PORT(
X : in STD_LOGIC_VECTOR (n-1 downto 0);
Y : in STD_LOGIC_VECTOR (m-1 downto 0);
load_a : in STD_LOGIC;
load_q : in STD_LOGIC;
load_m : in STD_LOGIC;
reset_n : in STD_LOGIC;
shift : in STD_LOGIC;
sub : in STD_LOGIC;
clock : in STD_LOGIC;
q0 : out STD_LOGIC;
q_1 : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0)
);
END COMPONENT;
COMPONENT contatore_modulo_n
generic (n : natural := 4);
PORT ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
count_en : in STD_LOGIC;
up_down : in STD_LOGIC;
mod_n : out STD_LOGIC);
END COMPONENT;
signal reset_n_sig, q0_sig, load_a_sig, load_q_sig, load_m_sig, q_1_sig,
shift_sig, sub_sig, cnt_en_sig, mod_n_sig, done_sig : std_logic := '0';
signal p_sig : std_logic_vector(n+m-1 downto 0);
signal sign : std_logic := '0';
begin
-- L'assegnazione condizionata viene utilizzata per risolvere il problema del segno dello zero (la prima)
-- e della moltiplicazione per il massimo numero rappresentabile con n bit quando questo è il moltiplicatore
-- (seconda riga: risolto complementando a 2 il risultato) es. 1*(-8),
sign <= '0' when (A = (A'range => '0')) or (B = (B'range => '0')) else
(A(n-1) xor B(m-1));
P <= ((not p_sig) + 1) and (p_sig'range => done_sig) when ((A(n-1) = '1') and (unsigned(A(n-2 downto 0)) = 0)) else
(sign & p_sig(n+m-2 downto 0)) and (p_sig'range => done_sig);
done <= done_sig;
PC: parte_controllo
generic map(n,m)
PORT MAP(
clock => clock,
reset_n_all => reset_n,
q0 => q0_sig,
q_1 => q_1_sig,
enable => enable,
conteggio => mod_n_sig,
load_a => load_a_sig,
load_m => load_m_sig,
load_q => load_q_sig,
reset_n => reset_n_sig,
shift => shift_sig,
sub => sub_sig,
count_en => cnt_en_sig,
done => done_sig
);
PO: parte_operativa
generic map(n,m)
PORT MAP(
X => A,
Y => B,
sub => sub_sig,
load_a => load_a_sig,
load_q => load_q_sig,
load_m => load_m_sig,
reset_n => reset_n_sig,
shift => shift_sig,
clock => clock,
q0 => q0_sig,
q_1 => q_1_sig,
P => p_sig
);
contatore: contatore_modulo_n
generic map(m)
PORT MAP(
clock => clock,
reset_n => reset_n_sig,
count_en => cnt_en_sig,
up_down => '0',
mod_n => mod_n_sig
);
end Structural;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/comparatore.vhd | 1 | 1295 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:10:11 07/01/2017
-- Design Name:
-- Module Name: comparatore - DataFlow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comparatore is
Generic ( width : natural := 31 );
Port ( enable : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
AbiggerB : out STD_LOGIC);
end comparatore;
architecture DataFlow of comparatore is
signal AbiggerB_sig : std_logic;
begin
AbiggerB_sig <= '1' when A > B else '0';
AbiggerB <= AbiggerB_sig and enable;
end DataFlow;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/tb_ipcore_uniti.vhd | 1 | 6754 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.07.2017 14:41:37
-- Design Name:
-- Module Name: tb_ipcore_uniti - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ipcore_uniti is
end tb_ipcore_uniti;
architecture Behavioral of tb_ipcore_uniti is
component test_dds_wrapper
generic (
campioni : natural := 20460
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0);
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
done : out STD_LOGIC
);
end component test_dds_wrapper;
component complex_max
generic (
sample_width : natural := 32;
s : natural := 5;
d : natural := 4;
c : natural := 5
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC
);
end component complex_max;
constant clock_period : time := 200 ns; -- 5 MHz
constant sample_width : natural:= 32;
constant s : natural:= 2;
constant d : natural:= 11;
constant c : natural:= 6;
--Inputs
signal clock : STD_LOGIC := '0';
signal reset_n : STD_LOGIC := '0';
signal valid_in : STD_LOGIC := '0';
signal poff_pinc : STD_LOGIC_VECTOR ( 47 downto 0 );
signal poff : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal pinc : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
--Outputs
signal sample_max : std_logic_vector(sample_width-1 downto 0);
signal ready_out : STD_LOGIC := '0';
signal done : std_logic;
signal pos_campione : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
signal max : std_logic_vector(sample_width-1 downto 0);
signal valid_out : STD_lOGIC := '0';
signal complex_max_ready_sig : std_logic;
signal dds_valid_out : std_logic;
signal sample_sig : std_logic_vector(sample_width-1 downto 0);
begin
poff_pinc(47 downto 24) <= poff;
poff_pinc(23 downto 0) <= pinc;
test_dds_wrapper_i : test_dds_wrapper
generic map (
campioni => c
)
port map (
clock => clock,
reset_n => reset_n,
valid_in => valid_in,
ready_in => complex_max_ready_sig,
poff_pinc => poff_pinc,
sine_cosine => sample_sig,
valid_out => dds_valid_out,
ready_out => ready_out,
done => done
);
complex_max_i : complex_max
generic map (
sample_width => sample_width,
s => s,
d => d,
c => c
)
port map (
clock => clock,
reset_n => reset_n,
valid_in => dds_valid_out,
ready_in => '0',
sample => sample_sig,
sample_max => sample_max,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
valid_out => valid_out,
ready_out => complex_max_ready_sig
);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stimuli: process
begin
--LISTA DOPPLERS
--FFF597
--FFF797
--FFF998
--FFFB98
--FFFD99
--FFFF99
--19A
--39B
--59B
--79C
--99C
wait for clock_period*10;
reset_n <= '1';
ciclo_satelliti : for i in 0 to s-1 loop
--PRIMA DOPPLER
poff <= x"000000";
pinc <= x"FFF597";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SECONDA DOPPLER
poff <= x"000000";
pinc <= x"FFF797";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--TERZA DOPPLER
poff <= x"000FFF";
pinc <= x"FFF998";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--QUARTA DOPPLER
poff <= x"FFF000";
pinc <= x"FFFB98";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--QUINTA DOPPLER
poff <= x"0F0F0F";
pinc <= x"FFFD99";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SESTA DOPPLER (che presenta il massimo)
poff <= x"F0F0F0";
--poff <= x"00000F";
pinc <= x"FFFF99";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SETTIMA DOPPLER
poff <= x"FF0000";
pinc <= x"00019A";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--OTTAVA DOPPLER
poff <= x"00FF00";
pinc <= x"00039B";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--NONA DOPPLER
poff <= x"0000DC";
pinc <= x"00059B";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--DECIMA DOPPLER
poff <= x"003400";
pinc <= x"00079C";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--UNDICESIMA DOPPLER
poff <= x"220000";
pinc <= x"00099C";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
end loop;
wait until valid_out = '1';
-- METTERE QUI L'ASSERT PER LA VERIFICA DEL MAX ASSOLUTO
wait;
end process;
end Behavioral;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/add_sub/full_adder.vhd | 1 | 1542 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:05:40 11/13/2015
-- Design Name:
-- Module Name: full_adder - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c_in : in STD_LOGIC;
c_out : out STD_LOGIC;
s : out STD_LOGIC);
end full_adder;
architecture Structural of full_adder is
COMPONENT half_adder
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal internal_sig : std_logic_vector (2 downto 0);
begin
half_adder1: half_adder
port map(a => a, b => b, c=> internal_sig(1), s => internal_sig(0));
half_adder2: half_adder
port map(a => internal_sig(0), b => c_in, c=> internal_sig(2), s => s);
c_out <= internal_sig(2) or internal_sig(1);
end Structural;
| gpl-2.0 |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/parte_controllo.vhd | 1 | 3464 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:01 11/23/2015
-- Design Name:
-- Module Name: parte_controllo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity parte_controllo is
generic ( n : natural := 4;
m : natural := 4);
Port ( clock : in STD_LOGIC;
reset_n_all : in STD_LOGIC;
q0 : in STD_LOGIC;
q_1 : in STD_LOGIC;
enable : in STD_LOGIC;
conteggio : in STD_LOGIC;
load_a : out STD_LOGIC;
load_m : out STD_LOGIC;
load_q : out STD_LOGIC;
reset_n : out STD_LOGIC;
shift : out STD_LOGIC;
sub : out STD_LOGIC;
count_en : out STD_LOGIC;
done : out STD_LOGIC);
end parte_controllo;
architecture Behavioral of parte_controllo is
type state is (reset, init, scan, add, subtract, rshift, output, load);
signal current_state, next_state : state := reset;
begin
registro_stato : process(clock, reset_n_all)
begin
if(reset_n_all = '0') then
current_state <= reset;
elsif(clock = '1' and clock'event) then
current_state <= next_state;
end if;
end process;
f_stato_prossimo : process(current_state, reset_n_all, q0, q_1, enable, conteggio)
begin
case current_state is
when reset =>
if(enable = '1') then
next_state <= init;
else
next_state <= reset;
end if;
when init =>
next_state <= scan;
when scan =>
if(conteggio = '0') then
if(q0 = q_1) then
next_state <= rshift;
elsif(q0 = '0') then
next_state <= add;
elsif(q0 = '1') then
next_state <= subtract;
end if;
else
next_state <= output;
end if;
when add =>
next_state <= load;
when subtract =>
next_state <= load;
when rshift =>
next_state <= scan;
when output =>
next_state <= output;
when load =>
-- Stato fittizio incluso per far commutare l'uscita sh_out in maniera corretta
-- non so xkè ma questa si aggiorna un ciclo di clock dopo l'op di add o sub
next_state <= rshift;
end case;
end process;
f_uscita : process(current_state) --MOORE
begin
load_a <= '0';
load_m <= '0';
load_q <= '0';
reset_n <= '1';
shift <= '0';
sub <= '0';
count_en <= '0';
done <= '0';
case current_state is
when reset =>
reset_n <= '0';
when init =>
load_m <= '1';
load_q <= '1';
when scan =>
when add =>
load_a <= '1';
when subtract =>
load_a <= '1';
sub <= '1';
when rshift =>
shift <= '1';
count_en <= '1';
when output =>
done <= '1';
when load =>
end case;
end process;
end Behavioral;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/blk_mem_gen_outputMem_ste/example_design/bmg_wrapper.vhd | 1 | 10219 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_outputMem_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_outputMem_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/blk_mem_gen_outputMem_ste/example_design/blk_mem_gen_outputMem_top.vhd | 1 | 5018 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_outputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_outputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_outputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_outputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_outputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/RMEM/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-2.0 |
praveendath92/securePUF | ipcore_dir/RMEM/simulation/data_gen.vhd | 69 | 5024 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-2.0 |
freecores/minimips | miniMIPS/src/pps_ei.vhd | 1 | 4736 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Instruction extraction stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity pps_ei is
port (
clock : in std_logic;
reset : in std_logic;
clear : in std_logic; -- Clear the pipeline stage
stop_all : in std_logic; -- Evolution locking signal
-- Asynchronous inputs
stop_ei : in std_logic; -- Lock the EI_adr and Ei_instr registers
-- Bus controler interface
CTE_instr : in bus32; -- Instruction from the memory
ETC_adr : out bus32; -- Address to read in memory
-- Synchronous inputs from PF stage
PF_pc : in bus32; -- Current value of the pc
-- Synchronous outputs to DI stage
EI_instr : out bus32; -- Read interface
EI_adr : out bus32; -- Address from the read instruction
EI_it_ok : out std_logic -- Allow hardware interruptions
);
end pps_ei;
architecture rtl of pps_ei is
begin
ETC_adr <= PF_pc; -- Connexion of the PC to the memory address bus
-- Set the results
process (clock)
begin
if (clock='1' and clock'event) then
if reset='1' then
EI_instr <= INS_NOP;
EI_adr <= (others => '0');
EI_it_ok <= '0';
elsif stop_all='0' then
if clear='1' then
-- Clear the stage
EI_instr <= INS_NOP;
EI_it_ok <= '0';
elsif stop_ei='0' then
-- Normal evolution
EI_adr <= PF_pc;
EI_instr <= CTE_instr;
EI_it_ok <= '1';
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
freecores/minimips | miniMIPS/bench/bench_minimips.vhd | 1 | 5393 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library IEEE;
use IEEE.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.pack_mips.all;
entity sim_minimips is
end;
architecture bench of sim_minimips is
component minimips is
port (
clock : in std_logic;
reset : in std_logic;
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
it_mat : in std_logic
);
end component;
component ram is
generic (mem_size : natural := 256;
latency : time := 10 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic
);
end component;
component rom is
generic (mem_size : natural := 256;
start : natural := 0;
latency : time := 10 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
load : in std_logic;
fname : in string
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic;
signal it_mat : std_logic := '0';
-- Connexion with the code memory
signal load : std_logic;
signal fichier : string(1 to 7);
-- Connexion with the Ram
signal ram_req : std_logic;
signal ram_adr : bus32;
signal ram_r_w : std_logic;
signal ram_data : bus32;
signal ram_rdy : std_logic;
begin
U_minimips : minimips port map (
clock => clock,
reset => reset,
ram_req => ram_req,
ram_adr => ram_adr,
ram_r_w => ram_r_w,
ram_data => ram_data,
ram_ack => ram_rdy,
it_mat => it_mat
);
U_ram : ram port map (
req => ram_req,
adr => ram_adr,
data_inout => ram_data,
r_w => ram_r_w,
ready => ram_rdy
);
U_rom : rom port map (
adr => ram_adr,
donnee => ram_data,
ack => ram_rdy,
load => load,
fname => fichier
);
clock <= not clock after 20 ns;
reset <= '0', '1' after 5 ns, '0' after 70 ns;
ram_data <= (others => 'L');
process
variable command : line;
variable nomfichier : string(1 to 3);
begin
write (output, "Enter the filename : ");
readline(input, command);
read(command, nomfichier);
fichier <= nomfichier & ".bin";
load <= '1';
wait;
end process;
-- Memory Mapping
-- 0000 - 00FF ROM
process (ram_adr, ram_r_w, ram_data)
begin -- Emulation of an I/O controller
ram_data <= (others => 'Z');
case ram_adr is
when X"00001000" => -- declenche une lecture avec interruption
it_mat <= '1' after 1000 ns;
ram_rdy <= '1' after 5 ns;
when X"00001001" => -- fournit la donnee et lache l'it
it_mat <= '0';
ram_data <= X"FFFFFFFF";
ram_rdy <= '1' after 5 ns;
when others => ram_rdy <= 'L';
end case;
end process;
end bench;
| gpl-2.0 |
techwoes/sump | logic-analyzer-orig/fpga/sram_bram.vhd | 4 | 2555 | ----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer/BRAM8k32bit.vhd | 4 | 2519 | ----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM8k32bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (31 downto 0);
DIN : in STD_LOGIC_VECTOR (31 downto 0));
end BRAM8k32bit;
architecture Behavioral of BRAM8k32bit is
begin
BlockRAMS: for i in 0 to 15 generate
RAMB16_S2_inst : RAMB16_S2
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
ADDR => ADDR, -- 13-bit Address Input
CLK => CLK, -- Clock
DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
end generate;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic-analyzer-orig/fpga/flags.vhd | 4 | 1796 | ----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flags is
Port ( data : in STD_LOGIC_VECTOR(8 downto 0);
clock : in STD_LOGIC;
write : in STD_LOGIC;
demux : out STD_LOGIC;
filter : out STD_LOGIC;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
end flags;
architecture Behavioral of flags is
begin
-- write flags
process (clock)
begin
if rising_edge(clock) and write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
rle <= data(8);
end if;
end process;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer2/core.vhd | 4 | 7374 | ----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer/core.vhd | 4 | 7374 | ----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer2/prescaler.vhd | 3 | 2076 | ----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer/stage.vhd | 4 | 6303 | ----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the input channels
-- can be used as input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be software compensated. (By adjusting the before/after ratio.)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stage is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in STD_LOGIC;
wrValue : in STD_LOGIC;
wrConfig : in STD_LOGIC;
arm : in std_logic;
level : in STD_LOGIC_VECTOR (1 downto 0);
demuxed : in std_logic;
run : out STD_LOGIC;
match : out STD_LOGIC
);
end stage;
architecture Behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister, configRegister : STD_LOGIC_VECTOR (31 downto 0);
signal intermediateRegister, shiftRegister : STD_LOGIC_VECTOR (31 downto 0);
signal testValue: STD_LOGIC_VECTOR (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : STD_LOGIC;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- assign configuration bits to more meaningful signal names
cfgStart <= configRegister(27);
cfgSerial <= configRegister(26);
cfgChannel <= configRegister(24 downto 20);
cfgLevel <= configRegister(17 downto 16);
cfgDelay <= configRegister(15 downto 0);
-- use shift register or input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= input(i);
serialChannelH16 <= input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever input is ready
process(clock)
begin
if rising_edge(clock) then
if inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if reset = '1' then
state <= OFF;
elsif rising_edge(clock) then
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
configRegister <= data;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
techwoes/sump | logic_analyzer/trigger.vhd | 4 | 3460 | ----------------------------------------------------------------------------------
-- trigger.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Complex 4 stage 32 channel trigger.
--
-- All commands are passed on to the stages. This file only maintains
-- the global trigger level and it outputs the run condition if it is set
-- by any of the stages.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trigger is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in STD_LOGIC_VECTOR (3 downto 0);
wrValue : in STD_LOGIC_VECTOR (3 downto 0);
wrConfig : in STD_LOGIC_VECTOR (3 downto 0);
arm : in STD_LOGIC;
demuxed : in std_logic;
run : out STD_LOGIC
);
end trigger;
architecture Behavioral of trigger is
COMPONENT stage
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : IN std_logic;
data : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
reset : IN std_logic;
wrMask : IN std_logic;
wrValue : IN std_logic;
wrConfig : IN std_logic;
arm : IN std_logic;
level : in std_logic_vector(1 downto 0);
demuxed : IN std_logic;
run : OUT std_logic;
match : OUT std_logic
);
END COMPONENT;
signal stageRun, stageMatch: std_logic_vector(3 downto 0);
signal levelReg : std_logic_vector(1 downto 0);
begin
-- create stages
stages: for i in 0 to 3 generate
Inst_stage: stage PORT MAP(
input => input,
inputReady => inputReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrMask(i),
wrValue => wrValue(i),
wrConfig => wrConfig(i),
arm => arm,
level => levelReg,
demuxed => demuxed,
run => stageRun(i),
match => stageMatch(i)
);
end generate;
-- increase level on match
process(clock, arm)
variable tmp : std_logic;
begin
if arm = '1' then
levelReg <= "00";
elsif rising_edge(clock) then
tmp := stageMatch(0);
for i in 1 to 3 loop
tmp := tmp or stageMatch(i);
end loop;
if tmp = '1' then
levelReg <= levelReg + 1;
end if;
end if;
end process;
-- if any of the stages set run, capturing starts
process(stageRun)
variable tmp : std_logic;
begin
tmp := stageRun(0);
for i in 1 to 3 loop
tmp := tmp or stageRun(i);
end loop;
run <= tmp;
end process;
end Behavioral;
| gpl-2.0 |
freecores/minimips | miniMIPS/src/banc.vhd | 1 | 4778 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Register bank --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pack_mips.all;
entity banc is
port (
clock : in bus1;
reset : in bus1;
-- Register addresses to read
reg_src1 : in bus5;
reg_src2 : in bus5;
-- Register address to write and its data
reg_dest : in bus5;
donnee : in bus32;
-- Write signal
cmd_ecr : in bus1;
-- Bank outputs
data_src1 : out bus32;
data_src2 : out bus32
);
end banc;
architecture rtl of banc is
-- The register bank
type tab_reg is array (1 to 31) of bus32;
signal registres : tab_reg;
signal adr_src1 : integer range 0 to 31;
signal adr_src2 : integer range 0 to 31;
signal adr_dest : integer range 0 to 31;
begin
adr_src1 <= to_integer(unsigned(reg_src1));
adr_src2 <= to_integer(unsigned(reg_src2));
adr_dest <= to_integer(unsigned(reg_dest));
data_src1 <= (others => '0') when adr_src1=0 else
registres(adr_src1);
data_src2 <= (others => '0') when adr_src2=0 else
registres(adr_src2);
process(clock)
begin
if clock = '1' and clock'event then
if reset='1' then
for i in 1 to 31 loop
registres(i) <= (others => '0');
end loop;
elsif cmd_ecr = '1' and adr_dest /= 0 then
-- The data is saved
registres(adr_dest) <= donnee;
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
techwoes/sump | logic_analyzer/decoder.vhd | 4 | 3167 | ----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
| gpl-2.0 |
freecores/minimips | miniMIPS/src/pps_ex.vhd | 1 | 8966 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Execution stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
use work.alu;
entity pps_ex is
port(
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of outputs
clear : in std_logic; -- Clear the pipeline stage
-- Datas from DI stage
DI_bra : in std_logic; -- Branch instruction
DI_link : in std_logic; -- Branch with link
DI_op1 : in bus32; -- Operand 1 for alu
DI_op2 : in bus32; -- Operand 2 for alu
DI_code_ual : in alu_ctrl_type; -- Alu operation
DI_offset : in bus32; -- Offset for address calculation
DI_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
DI_ecr_reg : in std_logic; -- Effective writing of the result
DI_mode : in std_logic; -- Address mode (relative to pc ou index by a register)
DI_op_mem : in std_logic; -- Memory operation
DI_r_w : in std_logic; -- Type of memory operation (read or write)
DI_adr : in bus32; -- Instruction address
DI_exc_cause : in bus32; -- Potential cause exception
DI_level : in level_type; -- Availability stage of the result for bypassing
DI_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous outputs to MEM stage
EX_adr : out bus32; -- Instruction address
EX_bra_confirm : out std_logic; -- Branch execution confirmation
EX_data_ual : out bus32; -- Ual result
EX_adresse : out bus32; -- Address calculation result
EX_adr_reg_dest : out adr_reg_type; -- Destination register for the result
EX_ecr_reg : out std_logic; -- Effective writing of the result
EX_op_mem : out std_logic; -- Memory operation needed
EX_r_w : out std_logic; -- Type of memory operation (read or write)
EX_exc_cause : out bus32; -- Potential cause exception
EX_level : out level_type; -- Availability stage of result for bypassing
EX_it_ok : out std_logic -- Allow hardware interruptions
);
end entity;
architecture rtl of pps_ex is
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32; -- Operand 1
op2 : in bus32; -- Operand 2
ctrl : in alu_ctrl_type; -- Operation
res : out bus32; -- Result
overflow : out bus1 -- Overflow
);
end component;
signal res_ual : bus32; -- Alu result output
signal base_adr : bus32; -- Output of the address mode mux selection
signal pre_ecr_reg : std_logic; -- Output of mux selection for writing command to register
signal pre_data_ual : bus32; -- Mux selection of the data to write
signal pre_bra_confirm : std_logic; -- Result of the test in alu when branch instruction
signal pre_exc_cause : bus32; -- Preparation of the exception detection signal
signal overflow_ual : std_logic; -- Dectection of the alu overflow
begin
-- Alu instantiation
U1_alu : alu port map (clock => clock, reset => reset, op1=>DI_op1, op2=>DI_op2, ctrl=>DI_code_ual,
res=>res_ual, overflow=>overflow_ual);
-- Calculation of the future outputs
base_adr <= DI_op1 when DI_mode='0' else DI_adr;
pre_ecr_reg <= DI_ecr_reg when DI_link='0' else pre_bra_confirm;
pre_data_ual <= res_ual when DI_link='0' else bus32(unsigned(DI_adr) + 4);
pre_bra_confirm <= DI_bra and res_ual(0);
pre_exc_cause <= DI_exc_cause when DI_exc_cause/=IT_NOEXC else
IT_OVERF when overflow_ual='1' else
IT_NOEXC;
-- Set the synchronous outputs
process(clock) is
begin
if clock='1' and clock'event then
if reset='1' then
EX_adr <= (others => '0');
EX_bra_confirm <= '0';
EX_data_ual <= (others => '0');
EX_adresse <= (others => '0');
EX_adr_reg_dest <= (others => '0');
EX_ecr_reg <= '0';
EX_op_mem <= '0';
EX_r_w <= '0';
EX_exc_cause <= IT_NOEXC;
EX_level <= LVL_DI;
EX_it_ok <= '0';
elsif stop_all = '0' then
if clear = '1' then -- Clear the stage
EX_adr <= DI_adr;
EX_bra_confirm <= '0';
EX_data_ual <= (others => '0');
EX_adresse <= (others => '0');
EX_adr_reg_dest <= (others => '0');
EX_ecr_reg <= '0';
EX_op_mem <= '0';
EX_r_w <= '0';
EX_exc_cause <= IT_NOEXC;
EX_level <= LVL_DI;
EX_it_ok <= '0';
else -- Normal evolution
EX_adr <= DI_adr;
EX_bra_confirm <= pre_bra_confirm;
EX_data_ual <= pre_data_ual;
EX_adr_reg_dest <= DI_adr_reg_dest;
EX_ecr_reg <= pre_ecr_reg;
EX_op_mem <= DI_op_mem;
EX_r_w <= DI_r_w;
EX_exc_cause <= pre_exc_cause;
EX_level <= DI_level;
EX_it_ok <= DI_it_ok;
EX_adresse <= bus32(unsigned(DI_offset) + unsigned(base_adr));
end if;
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arbiter_ss_detector.vhd | 1 | 4527 | -------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Start/Stop detector
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_ss_detector.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-09-06
-- Last update: 2015-09-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to detect the START and STOP condition in a I2C bus.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_ss_detector is
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C input buses & ACK
input_sda_i : in std_logic;
input_scl_i : in std_logic;
start_ack_i : in std_logic;
stop_ack_i : in std_logic;
-- Start/Stop outputs
start_state_o : out std_logic;
stop_state_o : out std_logic
);
end i2c_arbiter_ss_detector;
architecture struct of i2c_arbiter_ss_detector is
-- Start FSM signals
type i2c_arb_start_st is (ARB_START_IDLE, ARB_START_WAIT_SDA, ARB_START_DETECTED);
signal arb_start_st : i2c_arb_start_st := ARB_START_IDLE;
-- Stop FSM signals
type i2c_arb_stop_st is (ARB_STOP_IDLE, ARB_STOP_WAIT_SDA, ARB_STOP_DETECTED);
signal arb_stop_st : i2c_arb_stop_st := ARB_STOP_IDLE;
begin
-- Start FSM
start_detector: process(clk_i,rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_start_st <= ARB_START_IDLE;
start_state_o <= '0';
else
case arb_start_st is
when ARB_START_IDLE =>
start_state_o <= '0';
if input_sda_i = '1' and input_scl_i = '1' then
arb_start_st <= ARB_START_WAIT_SDA;
end if;
when ARB_START_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '0' then
start_state_o <= '1';
arb_start_st <= ARB_START_DETECTED;
end if;
else
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when ARB_START_DETECTED =>
if start_ack_i = '1' then
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when others =>
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end case;
end if;
end if;
end process start_detector;
-- Stop FSM
stop_detector: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_stop_st <= ARB_STOP_IDLE;
stop_state_o <= '0';
else
case arb_stop_st is
when ARB_STOP_IDLE =>
stop_state_o <= '0';
if input_scl_i = '1' and input_sda_i = '0' then
arb_stop_st <= ARB_STOP_WAIT_SDA;
end if;
when ARB_STOP_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '1' then
stop_state_o <= '1';
arb_stop_st <= ARB_STOP_DETECTED;
end if;
else
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when ARB_STOP_DETECTED =>
if stop_ack_i = '1' then
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when others =>
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end case;
end if;
end if;
end process stop_detector;
end struct;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_receive_transmit_reg.vhd | 1 | 15627 | -------------------------------------------------------------------------------
-- qspi_receive_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_receive_reg.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_Reg_RdCE -- Read CE for receive register
-- IP2Bus_RdAck_sa -- IP2Bus read acknowledgement
-- IP2Bus_Receive_Reg_Data -- Data to be send on the bus
-- Receive_ip2bus_error -- Receive register error signal
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SR_7_Rx_Empty -- Receive register empty signal
-- SPI_Received_Data -- Data received from receive register
-- SPIXfer_done -- SPI transfer done flag
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_receive_transmit_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
---------------------
C_NUM_TRANSFER_BITS : integer -- Number of bits to be transferred
---------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
------------------------------------
-- RECEIVER RELATED SIGNALS
--=========================
Bus2IP_Receive_Reg_RdCE : in std_logic;
Receive_ip2bus_error : out std_logic;
IP2Bus_Receive_Reg_Data : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- SPI module ports
SPIXfer_done : in std_logic;
SPI_Received_Data : in std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- receive & transmit reg signals
-- DRR_Overrun : out std_logic;
SR_7_Rx_Empty : out std_logic;
------------------------------------
-- TRANSMITTER RELATED SIGNALS
--============================
-- Slave attachment ports
Bus2IP_Transmit_Reg_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Bus2IP_Transmit_Reg_WrCE : in std_logic;
Wr_ce_reduce_ack_gen : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
--SPI Transmitter signals
Transmit_ip2bus_error : out std_logic;
-- SPI module ports
DTR_underrun : in std_logic;
SR_5_Tx_Empty : out std_logic;
DTR_Underrun_strobe : out std_logic;
Transmit_Reg_Data_Out : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1))
);
end qspi_receive_transmit_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_receive_transmit_reg is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal Received_register_Data : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_7_Rx_Empty_reg : std_logic;
signal drr_Overrun_strobe : std_logic;
--------------------------------------------
signal sr_5_Tx_Empty_i : std_logic;
signal tx_Reg_Soft_Reset_op : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal dtr_underrun_d1 : std_logic;
signal SPIXfer_done_delay : std_logic;
constant RESET_ACTIVE : std_logic := '1';
--------------------------------------------
begin
-----
-- RECEIVER LOGIC
--=================
-- Combinatorial operations
----------------------------
SR_7_Rx_Empty <= sr_7_Rx_Empty_reg;
-- DRR_Overrun <= drr_Overrun_strobe;
DELAY_XFER_DONE_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_delay <= '0';
else
SPIXfer_done_delay <= SPIXfer_done;
end if;
end if;
end process DELAY_XFER_DONE_P;
-------------------------------------------------------------------------------
-- RECEIVE_REG_GENERATE : Receive Register Read Operation from SPI_Received_Data
-- register
--------------------------
RECEIVE_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
RECEIVE_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Received_register_Data(i) <= '0';
elsif (SPIXfer_done_delay = '1') then--((sr_7_Rx_Empty_reg and SPIXfer_done) = '1') then
Received_register_Data(i) <= SPI_Received_Data(i);
end if;
end if;
end process RECEIVE_REG_PROCESS_P;
-----
end generate RECEIVE_REG_GENERATE;
-------------------------------------------------------------------------------
-- RECEIVE_REG_RD_GENERATE : Receive Register Read Operation
-----------------------------
RECEIVE_REG_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
IP2Bus_Receive_Reg_Data(i) <= Received_register_Data(i) and
Bus2IP_Receive_Reg_RdCE;
end generate RECEIVE_REG_RD_GENERATE;
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS_P : Strobe error when receive register is empty
--------------------------------
RX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Receive_ip2bus_error <= sr_7_Rx_Empty_reg and
Bus2IP_Receive_Reg_RdCE;
end if;
end process RX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_7_RX_EMPTY_REG_PROCESS_P : SR_7_Rx_Empty register
-------------------------------
SR_7_RX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_7_Rx_Empty_reg <= '1';
elsif (SPIXfer_done = '1') then
sr_7_Rx_Empty_reg <= '0';
elsif ((rd_ce_reduce_ack_gen and Bus2IP_Receive_Reg_RdCE) = '1') then
sr_7_Rx_Empty_reg <= '1';
end if;
end if;
end process SR_7_RX_EMPTY_REG_PROCESS_P;
----******************************************************************************
-- TRANSMITTER LOGIC
--==================
-- Combinatorial operations
----------------------------
SR_5_Tx_Empty <= sr_5_Tx_Empty_i;
DTR_Underrun_strobe <= dtr_Underrun_strobe_i;
tx_Reg_Soft_Reset_op <= SPIXfer_done or Soft_Reset_op;
--------------------------------------
-------------------------------------------------------------------------------
-- TRANSMIT_REG_GENERATE : Transmit Register Write
---------------------------
TRANSMIT_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
TRANSMIT_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (tx_Reg_Soft_Reset_op = RESET_ACTIVE) then
Transmit_Reg_Data_Out(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1')then
Transmit_Reg_Data_Out(i) <=
Bus2IP_Transmit_Reg_Data
(C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS+i) after 100 ps;
end if;
end if;
end process TRANSMIT_REG_PROCESS_P;
-----
end generate TRANSMIT_REG_GENERATE;
-----------------------------------
-- TX_ERROR_ACK_REG_PROCESS_P : Strobe error when transmit register is full
--------------------------------
TX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Transmit_ip2bus_error <= not(sr_5_Tx_Empty_i) and
Bus2IP_Transmit_Reg_WrCE;
end if;
end process TX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_5_TX_EMPTY_REG_PROCESS_P : Tx Empty generate
-------------------------------
SR_5_TX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_5_Tx_Empty_i <= '1';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1') then
sr_5_Tx_Empty_i <= '0';
elsif (SPIXfer_done = '1') then
sr_5_Tx_Empty_i <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
dtr_Underrun_strobe_i <= DTR_underrun and (not dtr_underrun_d1);
--******************************************************************************
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_obp/obp_wbgen2_pkg.vhd | 1 | 2268 | ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for OBP
---------------------------------------------------------------------------------------
-- File : obp_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from obp_wb_slave.wb
-- Created : Fri Feb 27 10:07:37 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE obp_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package obp_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_obp_in_registers is record
cflags_prog_i : std_logic;
end record;
constant c_obp_in_registers_init_value: t_obp_in_registers := (
cflags_prog_i => '0'
);
-- Output registers (WB slave -> user design)
type t_obp_out_registers is record
n_prog_w_n_prog_w_o : unsigned(31 downto 0);
cflags_stp_o : std_logic;
end record;
constant c_obp_out_registers_init_value: t_obp_out_registers := (
n_prog_w_n_prog_w_o => (others => '0'),
cflags_stp_o => '0'
);
function "or" (left, right: t_obp_in_registers) return t_obp_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body obp_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
return x;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
tmp(i):=x(i);
end loop;
return tmp;
end function;
function "or" (left, right: t_obp_in_registers) return t_obp_in_registers is
variable tmp: t_obp_in_registers;
begin
tmp.cflags_prog_i := f_x_to_zero(left.cflags_prog_i) or f_x_to_zero(right.cflags_prog_i);
return tmp;
end function;
end package body;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_address_decoder.vhd | 1 | 22289 | -------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_address_decoder.vhd
-- Version: v3.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI4_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI4_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex7" -- "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity qspi_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of qspi_address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI4_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_quad_spi_v3_2.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_quad_spi_v3_2.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture imp;
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_mode_control_logic.vhd | 1 | 176939 | --
---- qspi_mode_control_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_control_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_mode_control_logic is
generic(
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SUB_FAMILY : string
);
port(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------
DTR_FIFO_Data_Exists : in std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Data_To_Rx_FIFO_1 : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
SPIXfer_done_Rx_Wr_en: out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
--SR_6_Rx_Full : in std_logic;
--Last_count : in std_logic;
---------------------- from control register
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
---------------------- from look up table
Data_Dir : in std_logic;
Data_Mode_1 : in std_logic;
Data_Mode_0 : in std_logic;
Data_Phase : in std_logic;
----------------------
Quad_Phase : in std_logic;
--Dummy_Bits : in std_logic_vector(3 downto 0);
----------------------
Addr_Mode_1 : in std_logic;
Addr_Mode_0 : in std_logic;
Addr_Bit : in std_logic;
Addr_Phase : in std_logic;
----------------------
CMD_Mode_1 : in std_logic;
CMD_Mode_0 : in std_logic;
CMD_Error : in std_logic;
CMD_decoded : in std_logic;
----------------------
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
IO0_I : in std_logic;
IO0_O : out std_logic; -- MOSI
IO0_T : out std_logic;
IO1_I : in std_logic; -- MISO
IO1_O : out std_logic;
IO1_T : out std_logic;
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
Control_bit_7_8 : in std_logic_vector(0 to 1); --(7 to 8)
pr_state_idle : out std_logic;
Rx_FIFO_Full : in std_logic ;
DRR_Overrun_reg : out std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic
);
end entity qspi_mode_control_logic;
----------------------------------
architecture imp of qspi_mode_control_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-- function declaration
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
return 2;
end if;
end spcl_log2;
-- type declaration
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
ADDR_SEND,TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,TEMP_DATA_SEND,
DATA_RECEIVE,TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ps: STATE_TYPE;
signal qspi_cntrl_ns: STATE_TYPE;
-----------------------------------------
-- signal declaration
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
signal Count_1 : std_logic_vector(COUNT_WIDTH downto 0);
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal Serial_Din_0 : std_logic;
signal Serial_Din_1 : std_logic;
signal Serial_Din_2 : std_logic;
signal Serial_Din_3 : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal serial_dout_int : std_logic;
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal master_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal MODF_strobe_int : std_logic;
signal Load_tx_data_to_shift_reg_int : std_logic;
signal mode_0 : std_logic;
signal mode_1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_d3 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SCK_O_1 : std_logic;-- :='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal pr_state_cmd_ph : std_logic;
signal pr_state_addr_ph : std_logic;
signal pr_state_dummy_ph : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal dummy_cnt : std_logic_vector(3 downto 0);
signal stop_clock : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal dummy : std_logic;
signal no_slave_selected : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Data_To_Rx_FIFO_2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
attribute IOB : string;
attribute IOB of QSPI_SCK_T : label is "true";
--attribute IOB of QSPI_SS_T : label is "true";
attribute IOB of QSPI_IO0_T : label is "false";-- MOSI_T
attribute IOB of QSPI_IO1_T : label is "false";-- MISO_T
--attribute IOB of QSPI_SPISEL : label is "true";-- SPISEL
signal Mst_Trans_inhibit_d1 : std_logic;
signal Mst_Trans_inhibit_pulse : std_logic;
signal stop_clock_reg : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse_11: std_logic;
signal DRR_Overrun_reg_int : std_logic;
signal Rx_FIFO_Full_reg : std_logic;
-----
begin
-----
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(Rx_FIFO_Full = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--------------------------------------
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
attribute IOB : string;
attribute IOB of QSPI_IO2_T : label is "false";
attribute IOB of QSPI_IO3_T : label is "false";
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not SPISEL_sync) and spisel_d1;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- __________|--|_____ -- SPISEL_pulse_op
SPISEL_pulse_op <= not SPISEL_sync; -- spisel_pulse;
SPISEL_d1_reg <= spisel_d1;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,
CPHA,
SPIXfer_done_int,
transfer_start_pulse,
Mst_Trans_inhibit_pulse) is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') then -- Tranfer not in progress
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
--------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF
)is
-----
begin
-----
if(Soft_Reset_op = RESET_ACTIVE) then
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
(--(Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
)
)
)then
Load_tx_data_to_shift_reg_int <= '1'; --Set flag
else
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
------------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1' -- core is in Data Receive State and DRR is not full
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') -- or
--(SPIXfer_done_int_pulse_d1 = '1')-- or
--(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- glitch at the end of
-- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
--------------------------------
--TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- (
-- (
-- SPI_En = '0' or -- enable not asserted or
-- (SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
-- SR_3_MODF = '1' or -- mode fault error
-- Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
-- stop_clock = '1' -- core is in Data Receive State and DRR is not full
-- )
-- )
-- )then
--
-- transfer_start <= '0';
-- else
---- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
---- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1')-- or
-- --(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
-- transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
-- end if;
-- end if;
--end process TRANSFER_START_PROCESS;
-------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
transfer_start_pulse_11 <= transfer_start_d2 and (not transfer_start_d3);
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_1 <= (others => '0');
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
receive_Data_int <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
receive_Data_int <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
receive_Data_int <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
RECEIVE_DATA_STROBE_PROCESS_1: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_2 <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
Data_To_Rx_FIFO_2 <= Data_To_Rx_FIFO_1;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_1;
--receive_Data_int <= Data_To_Rx_FIFO_2;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
-- SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_d1; -- SPIXfer_done_int_pulse_d1;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
-- SPIXfer_done_rd_tx_en <= SPIXfer_done_int;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if((Soft_Reset_op = RESET_ACTIVE) or
-- (transfer_start_d1 = '0') or
-- --(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
-- (Mst_N_Slv = '0')
-- )then
--
-- Count <= (others => '0');
-- elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
-- end if;
-- end if;
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPIXfer_done_int = '1') or
(transfer_start = '0')
--(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
--(Mst_N_Slv = '0')
)then
Count <= (others => '0');
elsif (Count(COUNT_WIDTH) = '0') and ((CPOL and CPHA) = '0') then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
--sck_o_int <= (not sck_o_int) xor Count(COUNT_WIDTH);
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
sck_d3 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
sck_d3 <= sck_d2;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then --SPIXfer_done_int_pulse_d2
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d3='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(C_SPI_MEMORY = 2
)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
------------------------------------------------------
-----
end generate RATIO_OF_2_GENERATE;
---------------------------------
--------==================================================================-----
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
------------------------------
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(CPHA = '0' and CPOL = '0') then
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(0) and Count(1);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);--- and
--(and_reduce(Ratio_Count));-- dual mode
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
else
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(1) and
Count(0);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of IO0_I_REG : label is "true";
-----
begin
-----
-------------------------------------------------------------------------------
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => IO0_I --MOSI_I
);
-----------------------
-- IO1_I_REG_IOB: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-------------
-- IO1_I_REG_IOB: if (C_SUB_FAMILY = "virtex7"
-- or
-- C_SUB_FAMILY = "kintex7"
-- or
-- C_SUB_FAMILY = "artix7"
-- -- or -- 1/23/2013
-- -- C_SUB_FAMILY = "spartan6" -- 1/23/2013
-- )
-- -- or
-- -- (
-- -- C_USE_STARTUP = 0
-- -- and
-- -- C_SUB_FAMILY = "virtex6"
-- -- )
-- generate
-----
--attribute IOB : string;
--attribute IOB of IO1_I_REG : label is "true";
-----
--begin
-----
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => IO1_I -- MISO_I
);
--end generate IO1_I_REG_IOB;
---------------------------
-- -- IO1_I_REG_NO_IOB: If C_USE_STARTUP is used and family is virtex6, then
-- -- IO1_I is registered only, but it is not pushed in IOB.
-- -- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- IO1_I_REG_NO_IOB: if ( C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- )generate
-- -----
-- begin
-- -----
-- IO1_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => IO1_I -- MISO_I
-- );
-- end generate IO1_I_REG_NO_IOB;
-- ------------------------------
NO_IO_x_I_SYNC_MODE_1_GEN: if C_SPI_MODE = 1 generate
-----
begin
-----
io2_i_sync <= '0';
io3_i_sync <= '0';
end generate NO_IO_x_I_SYNC_MODE_1_GEN;
---------------------------------------
IO_x_I_SYNC_MODE_2_GEN: if C_SPI_MODE = 2 generate
----------------
--attribute IOB : string;
--attribute IOB of IO2_I_REG : label is "true";
--attribute IOB of IO3_I_REG : label is "true";
-----
begin
-----
-----------------------
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => Bus2IP_Clk,
D => IO2_I
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => Bus2IP_Clk,
D => IO3_I
);
-----------------------
end generate IO_x_I_SYNC_MODE_2_GEN;
------------------------------------
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
OTHER_RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process OTHER_RATIO_COUNT_PROCESS;
--------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
--(SPIXfer_done_int = '1') or
(transfer_start = '0')
) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS;
--------------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)or
(SPIXfer_done_int = '1') or
(transfer_start = '0') then
Count <= (others => '0');
--elsif (transfer_start = '0') then
-- Count <= (others => '0');
elsif (Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
OTHER_RATIO_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process OTHER_RATIO_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
OTHER_RATIO_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process OTHER_RATIO_DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
OTHER_RATIO_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and
(transfer_start = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
--(pr_state_data_receive = '1')
) then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I;-- MISO_I
elsif((mode_1 = '0' and mode_0 = '1') -- for Dual transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I &-- MSB first
IO0_I;
elsif((mode_1 = '1' and mode_0 = '0') -- for Quad transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process OTHER_RATIO_CAPT_RX_FE_MODE_00_11;
---------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(C_SPI_MEMORY = 2)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
-------------------------------------------------------
end generate OTHER_RATIO_GENERATE;
----------------------------------
--------------------------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
--------------------------------
QSPI_DUAL_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 1 and
(
C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1
)
)generate
--------------------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => --if((SPIXfer_done_int_pulse='1')
-- )then
-- if (no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
-- else
-- stop_clock <= SR_5_Tx_Empty;
-- if(SR_5_Tx_Empty='1')then
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
-- else
-- qspi_cntrl_ns <= ADDR_SEND;
-- end if;
-- end if;
--else
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
--end if;
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
--if(no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
--else
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 2 and
(C_SPI_MEMORY = 1 or
C_SPI_MEMORY = 0
)
)
generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Error ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate QSPI_QUAD_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_DUAL_MODE_NM_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 2 ) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_NM_MEM_GEN;
--------------------------------
QSPI_DUAL_MODE_SP_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 3) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_SP_MEM_GEN;
--------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 2 )generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
QSPI_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 3)generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
-----
begin
-----
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= not (Mst_N_Slv); -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0'))then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
slave_mode <= not (Mst_N_Slv);-- dont allow SPI clock to go out when core is in slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv, -- in master mode
sck_o_int, -- value driven on sck_int
CPOL, -- CPOL mode thr SPICR
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH)
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')--and
--(pr_state_non_idle = '1')
)then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0') -- SM is in IDLE state or core in slave mode
)then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
---------------------
end architecture imp;
---------------------
| gpl-2.0 |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/255f4893/hdl/fifo_generator_v12_0.vhd | 17 | 90319 | `protect begin_protected
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| gpl-2.0 |
INTI-CMNB/Lattuino_IP_Core | devices/tmcounter.vhdl | 1 | 14608 | ------------------------------------------------------------------------------
---- ----
---- WISHBONE miscellaneous timer ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- Implements the micro and milliseconds timers. Also a CPU blocker, ----
---- used for small time delays. ----
---- This module also implements the 6 PWMs. ----
---- Lower 32 bits is a 32 bits microseconds counter ----
---- Upper 32 bits is a milliseconds counter ----
---- ----
---- Port Read Write ----
---- 0 µs B0 PWM0 ----
---- 1 µs B1 PWM1 ----
---- 2 µs B2 PWM2 ----
---- 3 µs B3 PWM3 ----
---- 4 ms B0 PWM4 ----
---- 5 ms B1 PWM5 ----
---- 6 ms B2 PWM Pin Enable ----
---- 7 ms B3 Block CPU µs ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TMCounter(RTL) (Entity and architecture) ----
---- File name: tmcounter.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Wishbone Datasheet ----
---- ----
---- 1 Revision level B.3 ----
---- 2 Type of interface SLAVE ----
---- 3 Defined signal names RST_I => wb_rst_i ----
---- CLK_I => wb_clk_i ----
---- ADR_I => wb_adr_i ----
---- DAT_I => wb_dat_i ----
---- DAT_O => wb_dat_o ----
---- WE_I => wb_we_i ----
---- ACK_O => wb_ack_o ----
---- STB_I => wb_stb_i ----
---- 4 ERR_I Unsupported ----
---- 5 RTY_I Unsupported ----
---- 6 TAGs None ----
---- 7 Port size 8-bit ----
---- 8 Port granularity 8-bit ----
---- 9 Maximum operand size 8-bit ----
---- 10 Data transfer ordering N/A ----
---- 11 Data transfer sequencing Undefined ----
---- 12 Constraints on the CLK_I signal None ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity TMCounter is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(2 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
pwm_o : out std_logic_vector(5 downto 0); -- 6 PWMs
pwm_e_o : out std_logic_vector(5 downto 0)); -- Pin enable for the PWMs
end entity TMCounter;
architecture RTL of TMCounter is
-- Microseconds counter
signal cnt_us_r : unsigned(31 downto 0):=(others => '0');
-- Microseconds counter for the ms counter
signal cnt_us2_r : unsigned(9 downto 0):=(others => '0');
signal tc_cnt_us2: std_logic;
-- Milliseconds counter
signal cnt_ms_r : unsigned(31 downto 0):=(others => '0');
-- Latched value
signal latched_r : unsigned(31 downto 0):=(others => '0');
-- Prescaler for the Microseconds counters
signal ena_cnt : std_logic;
signal pre_cnt_r : integer range 0 to CNT_PRESC-1;
-- Microseconds blocker counter
signal cnt_blk_r : unsigned(7 downto 0):=(others => '0');
-- Prescaler for the Microseconds blocker counter
signal ena_blk_cnt : std_logic;
signal pre_bk_r : integer range 0 to CNT_PRESC-1;
-- Blocker FSM
type state_t is (idle, delay);
signal state : state_t;
-- Blocker WE
signal blk_we : std_logic;
-- PWM values
type pwm_val_t is array (0 to 5) of unsigned(7 downto 0);
signal pwm_val_r : pwm_val_t;
-- PWM counter
signal pwm_count : unsigned(7 downto 0);
-- Auxiliar for config
signal wb_dat : std_logic_vector(7 downto 0); -- DataOut Bus
begin
----------------------------------------------------------------------------
-- 32 bits Microseconds counter
----------------------------------------------------------------------------
-- Microseconds time source for the counters
tmr_prescaler:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
pre_cnt_r <= 0;
else
pre_cnt_r <= pre_cnt_r+1;
if pre_cnt_r=CNT_PRESC-1 then
pre_cnt_r <= 0;
end if;
end if;
end if;
end process tmr_prescaler;
ena_cnt <= '1' when pre_cnt_r=CNT_PRESC-1 else '0';
-- Microseconds counter, 32 bits
do_cnt_us:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_us_r <= (others => '0');
elsif ena_cnt='1' then
cnt_us_r <= cnt_us_r+1;
end if;
end if;
end process do_cnt_us;
----------------------------------------------------------------------------
-- 32 bits Milliseconds counter
----------------------------------------------------------------------------
-- Microseconds counter, 10 bits (0 to 999)
do_cnt_us2:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' or tc_cnt_us2='1' then
cnt_us2_r <= (others => '0');
elsif ena_cnt='1' then
cnt_us2_r <= cnt_us2_r+1;
end if;
end if;
end process do_cnt_us2;
tc_cnt_us2 <= '1' when ena_cnt='1' and cnt_us2_r=999 else '0';
-- Milliseconds counter, 32 bits
do_cnt_ms:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_ms_r <= (others => '0');
elsif tc_cnt_us2='1' then
cnt_ms_r <= cnt_ms_r+1;
end if;
end if;
end process do_cnt_ms;
----------------------------------------------------------------------------
-- WISHBONE read
----------------------------------------------------------------------------
-- Latched value
do_cnt_usr:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
latched_r <= (others => '0');
elsif wb_stb_i='1' then
if wb_adr_i="000" then
latched_r <= cnt_us_r;
elsif wb_adr_i="100" then
latched_r <= cnt_ms_r;
end if;
end if;
end if;
end process do_cnt_usr;
with wb_adr_i select wb_dat <=
std_logic_vector( cnt_us_r( 7 downto 0)) when "000",
std_logic_vector(latched_r(15 downto 8)) when "001",
std_logic_vector(latched_r(23 downto 16)) when "010",
std_logic_vector(latched_r(31 downto 24)) when "011",
std_logic_vector( cnt_ms_r( 7 downto 0)) when "100",
std_logic_vector(latched_r(15 downto 8)) when "101",
std_logic_vector(latched_r(23 downto 16)) when "110",
std_logic_vector(latched_r(31 downto 24)) when "111",
(others => '0') when others;
wb_dat_o <= wb_dat when ENA_TMR='1' else (others => '0');
blk_we <= '1' when (wb_stb_i and wb_we_i)='1' and wb_adr_i="111" and ENA_TMR='1' else '0';
-- ACK all reads and writes when the counter is 0
wb_ack_o <= '1' when wb_stb_i='1' and (blk_we='0' or (state=delay and cnt_blk_r=0)) else '0';
----------------------------------------------------------------------------
-- Microseconds CPU blocker
----------------------------------------------------------------------------
-- Blocker FSM (idle and delay)
do_fsm:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if blk_we='1' then
state <= delay;
end if;
when others => -- delay
if cnt_blk_r=0 then
state <= idle;
end if;
end case;
end if;
end if;
end process do_fsm;
-- Blocker counter (down counter)
do_bk_cnt:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_blk_r <= (others => '0');
elsif state=idle and blk_we='1' then
cnt_blk_r <= unsigned(wb_dat_i);
elsif ena_blk_cnt='1' then
cnt_blk_r <= cnt_blk_r-1;
end if;
end if;
end process do_bk_cnt;
-- Microseconds time source for the Blocker counter
tmr_prescaler_bk:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' or
(state=idle and blk_we='1') then
pre_bk_r <= CNT_PRESC-1;
else
pre_bk_r <= pre_bk_r-1;
if pre_bk_r=0 then
pre_bk_r <= CNT_PRESC-1;
end if;
end if;
end if;
end process tmr_prescaler_bk;
ena_blk_cnt <= '1' when pre_bk_r=0 else '0';
----------------------------------------------------------------------------
-- 6 PWMs (8 bits, 250 kHz clock, 976.56 Hz carrier)
----------------------------------------------------------------------------
-- PWM value write
do_pwm_val_write:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='0' then
if (wb_stb_i and wb_we_i)='1' and
wb_adr_i/="111" and
wb_adr_i/="110" then
pwm_val_r(to_integer(unsigned(wb_adr_i))) <= unsigned(wb_dat_i);
end if;
end if;
end if;
end process do_pwm_val_write;
-- 8 bits counter (1 MHz/4)
pwm_count <= cnt_us_r(9 downto 2);
-- PWM outputs (comparators)
do_pwm_outs:
for i in 0 to 5 generate
pwm_o(i) <= '0' when pwm_count>pwm_val_r(i) else '1';
end generate do_pwm_outs;
-- PWM Pin Enable (1 the pin should use the PWM output)
do_pwm_ena_write:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
pwm_e_o <= (others => '0');
else
if (wb_stb_i and wb_we_i)='1' and wb_adr_i="110" then
pwm_e_o <= wb_dat_i(5 downto 0);
end if;
end if;
end if;
end process do_pwm_ena_write;
end architecture RTL; -- Entity: TMCounter
| gpl-2.0 |
blackducksoftware/ohcount | test/src_dir/vhdl1.vhdl | 5 | 703 | library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
architecture behav of tb is
-- toggle period
constant period_c : time := 1 ms;
-- we'll be poking on this signal
signal toggle_s : std_logic_vector(1 downto 0) := "01";
begin
-----------------------------------------------------------------------------
-- Process toggle
--
-- Purpose:
-- Flip the toggle_s signal periodically.
--
toggle: process
begin
wait for period_c/2;
toggle_s <= not toggle_s;
end process toggle;
--
-----------------------------------------------------------------------------
end behav;
configuration tb_behav_c0 of tb is
for behav
end for;
end tb_behav_c0;
| gpl-2.0 |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arb_wbgen2_pkg.vhd | 1 | 1732 | ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for I2C WB Arbiter
---------------------------------------------------------------------------------------
-- File : i2c_arb_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from i2c_arbiter_wb.wb
-- Created : Tue Jun 9 11:32:14 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE i2c_arbiter_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2c_arb_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_i2c_arb_out_registers is record
cr_bypass_mode_o : std_logic;
cr_bypass_src_o : std_logic_vector(4 downto 0);
end record;
constant c_i2c_arb_out_registers_init_value: t_i2c_arb_out_registers := (
cr_bypass_mode_o => '0',
cr_bypass_src_o => (others => '0')
);
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body i2c_arb_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
return x;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
tmp(i):=x(i);
end loop;
return tmp;
end function;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd | 4 | 2183 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc890.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c10s02b00x00p02n01i00890pkg is
function gimme_value return integer;
end c10s02b00x00p02n01i00890pkg;
package body c10s02b00x00p02n01i00890pkg is
constant x : integer := 10; -- should not be visible outside
function gimme_value return integer is
constant x : integer := 0; -- should only be visible inside
begin
return (x);
end;
end c10s02b00x00p02n01i00890pkg;
use work.c10s02b00x00p02n01i00890pkg.all;
ENTITY c10s02b00x00p02n01i00890ent IS
END c10s02b00x00p02n01i00890ent;
ARCHITECTURE c10s02b00x00p02n01i00890arch OF c10s02b00x00p02n01i00890ent IS
constant x : integer := 5;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( gimme_value = 0 )
report "***PASSED TEST: c10s02b00x00p02n01i00890"
severity NOTE;
assert ( gimme_value = 0 )
report "***FAILED TEST: c10s02b00x00p02n01i00890 - A declaration in a subprogram extends only within the subprogram body."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s02b00x00p02n01i00890arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket53/decl1.vhdl | 3 | 79 | context prj is
library ieee;
use ieee.std_logic_1164.all;
end context prj;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd | 4 | 5797 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mem-pl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture preloaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array
:= ( X"20020000", -- addi r2, r0, 0
X"ac020018", -- loop: sw counter(r0), r2
X"20420001", -- addi r2, r2, 1
X"6441000a", -- snei r1, r2, 10
X"1420fff0", -- bnez r1, loop
X"44000000", -- trap 0
X"00000000", -- counter: .word 0
others => X"00000000" );
variable byte_address, word_address : natural;
variable write_access : boolean;
procedure do_write is
subtype ls_2_bits is bit_vector(1 downto 0);
begin
case width is
when dlx_mem_width_word =>
mem(word_address) := to_bitvector(d);
when dlx_mem_width_halfword =>
if To_bit(a(1)) = '0' then -- ms half word
mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
else -- ls half word
mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
end if;
when dlx_mem_width_byte =>
case ls_2_bits'(To_bitvector(a(1 downto 0))) is
when b"00" =>
mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
when b"01" =>
mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
when b"10" =>
mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
when b"11" =>
mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
end case;
when others =>
report "illegal width indicator in write" severity error;
end case;
end do_write;
procedure do_read is
begin
d <= To_X01( mem(word_address) );
end do_read;
begin
-- initialize outputs
d <= disabled_dlx_word;
ready <= '0';
-- process memory cycles
loop
-- wait for a command, valid on leading edge of phi2
wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
-- decode address and perform command if selected
byte_address := bv_to_natural(To_bitvector(a));
write_access := To_bit(write_enable) = '1';
if byte_address <= high_address then
word_address := byte_address / 4;
if write_access then -- write cycle
do_write;
wait for Tac_first; -- write access time, 1st cycle
else -- read cycle
wait for Tac_first; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while To_bit(burst) = '1' loop
word_address := (word_address + 1) mod (mem_size / 4);
wait until rising_edge(phi2);
if write_access then -- write cycle
do_write;
wait for Tac_burst; -- write access time, burst cycle
else -- read cycle
wait for Tac_burst; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
end loop;
if not write_access then -- was read
d <= disabled_dlx_word after Tpd_clk_out;
end if;
end if;
end loop;
end process mem_behavior;
end architecture preloaded;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd | 3 | 2428 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_24.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity and3 is
port ( a, b, c : in bit := '1';
z, not_z : out bit);
end entity and3;
-- end of code from book
architecture functional of and3 is
begin
non_inverting:
z <= a and b and c;
inverting:
not_z <= not (a and b and c);
end architecture functional;
entity ch_05_24 is
end entity ch_05_24;
library stimulus;
architecture test of ch_05_24 is
signal s1, s2, ctrl1_a, ctrl1_b : bit;
signal test_input : bit_vector(1 to 2);
use stimulus.stimulus_generators.all;
begin
block_05_4_a : block is
port ( ctrl1 : out bit );
port map ( ctrl1 => ctrl1_a );
begin
-- code from book:
g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
-- end of code from book
end block block_05_4_a;
block_05_4_b : block is
port ( ctrl1 : out bit );
port map ( ctrl1 => ctrl1_b );
begin
-- code from book:
g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1,
c => open, z => open);
-- end of code from book
end block block_05_4_b;
stimulus_proc : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(s1, s2) <= test_input;
verifier :
assert ctrl1_a = ctrl1_b
report "versions differ";
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket69/repro.vhdl | 3 | 325 | library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3177.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p27n01i03177ent IS
END c14s01b00x00p27n01i03177ent;
ARCHITECTURE c14s01b00x00p27n01i03177arch OF c14s01b00x00p27n01i03177ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'low = 0.0 and
cba'low = 0.0 )
report "***PASSED TEST: c14s01b00x00p27n01i03177"
severity NOTE;
assert ( abc'low = 0.0 and
cba'low = 0.0 )
report "***FAILED TEST: c14s01b00x00p27n01i03177 - Predefined attribute LOW for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p27n01i03177arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1652.vhd | 4 | 1626 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1652.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s00b00x00p02n01i01652ent IS
END c09s00b00x00p02n01i01652ent;
ARCHITECTURE c09s00b00x00p02n01i01652arch OF c09s00b00x00p02n01i01652ent IS
signal S1 : integer;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 0;
;
assert FALSE
report "***FAILED TEST: c09s00b00x00p02n01i01652 - An empty statement is not permitted in a set of statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s00b00x00p02n01i01652arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd | 4 | 1793 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07a is
end entity inline_07a;
----------------------------------------------------------------
architecture test of inline_07a is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : real_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/sub_478.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_478 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_478;
architecture augh of sub_478 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd | 4 | 3137 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_16a_types is
subtype ILLUMINANCE is REAL tolerance "DEFAULT_ILLUMINANCE";
subtype OPTIC_FLUX is REAL tolerance "DEFAULT_OPTIC_FLUX";
nature RADIANT is
ILLUMINANCE across
OPTIC_FLUX through
RADIANT_REF reference;
subtype VOLTAGE is REAL tolerance "DEFAULT_VOLTAGE";
subtype CURRENT is REAL tolerance "DEFAULT_CURRENT";
nature ELECTRICAL is
VOLTAGE across
CURRENT through
ELECTRICAL_REF reference;
-- code from book
type illuminance_vector is array ( natural range <> ) of illuminance;
nature electrical_vector is array ( natural range <> ) of electrical;
-- end code from book
end package inline_16a_types;
use work.inline_16a_types.all;
-- code from book
entity seven_segment_led is
port ( terminal segment_anodes : electrical_vector ( 1 to 7 );
terminal common_cathode : electrical;
quantity segment_illuminances : out illuminance_vector ( 1 to 7 ) );
end entity seven_segment_led;
-- end code from book
architecture basic_optics of seven_segment_led is
begin
end architecture basic_optics;
use work.inline_16a_types.all;
entity inline_16a is
end entity inline_16a;
architecture test of inline_16a is
-- code from book
terminal hour_anode_2, hour_anode_3 : electrical;
terminal anodes_unused : electrical_vector(1 to 5);
terminal hour_display_source_2, hour_display_source_3 : radiant;
quantity hour_illuminance_2 across hour_display_source_2;
quantity hour_illuminance_3 across hour_display_source_3;
quantity illuminances_unused : illuminance_vector(1 to 5);
-- end code from book
begin
-- code from book
hour_digit : entity work.seven_segment_led(basic_optics)
port map ( segment_anodes(2) => hour_anode_2,
segment_anodes(3) => hour_anode_3,
segment_anodes(1) => anodes_unused(1),
segment_anodes(4 to 7) => anodes_unused(2 to 5),
common_cathode => electrical_ref,
segment_illuminances(2) => hour_illuminance_2,
segment_illuminances(3) => hour_illuminance_3,
segment_illuminances(1) => illuminances_unused(1),
segment_illuminances(4 to 7) => illuminances_unused(2 to 5) );
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd | 4 | 916 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.int_types.all;
entity small_adder is
port ( a, b : in small_int; s : out small_int );
end entity small_adder;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/integer-for-loop.vhdl | 4 | 329 | entity test is
end test;
architecture only of test is
begin -- only
p: process
variable x : integer;
begin -- process p
for i in 1 to 10 loop
x := i;
end loop; -- i
assert x = 10 report "TEST FAILED x was " & integer'image(x) severity ERROR;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd | 4 | 4235 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03075pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
end c12s06b02x00p06n01i03075pkg;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03075ent_a;
ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03075arch_a;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent IS
END c12s06b02x00p06n01i03075ent;
ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
signal S1 : severity_level_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03075"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03075arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd | 4 | 4038 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3069.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03069pkg is
type boolean_cons_vector is array (15 downto 0) of boolean;
constant C19 : boolean_cons_vector := (others => true);
end c12s06b02x00p06n01i03069pkg;
use work.c12s06b02x00p06n01i03069pkg.all;
ENTITY c12s06b02x00p06n01i03069ent_a IS
PORT
(
F1: OUT integer ;
F3: IN boolean_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03069ent_a;
ARCHITECTURE c12s06b02x00p06n01i03069arch_a OF c12s06b02x00p06n01i03069ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03069arch_a;
use work.c12s06b02x00p06n01i03069pkg.all;
ENTITY c12s06b02x00p06n01i03069ent IS
END c12s06b02x00p06n01i03069ent;
ARCHITECTURE c12s06b02x00p06n01i03069arch OF c12s06b02x00p06n01i03069ent IS
function scalar_complex(s : integer) return boolean_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN boolean_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03069ent_a(c12s06b02x00p06n01i03069arch_a);
signal S1 : boolean_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03069"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03069 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03069arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd | 4 | 1768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01958ent IS
END c07s02b01x00p02n02i01958ent;
ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a or b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01958"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01958arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc947.vhd | 4 | 1775 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00947ent IS
END c06s01b00x00p10n01i00947ent;
ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R1'(RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00947arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug22868/fails1.vhdl | 3 | 436 | library ieee;
use ieee.std_logic_1164.all;
entity fails1 is
generic (
w : integer := 8
);
port(
x : in std_logic;
y : out std_logic_vector(7 downto 0);
z : out std_logic
);
end entity;
architecture a of fails1 is
component subcomponent is
port(
x : in std_logic;
y : out std_logic_vector(8 downto 0)
);
end component;
begin
s : subcomponent
port map(
x => x,
y(w downto 1) => y,
y(0) => z
);
end a;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket78/bug.vhdl | 3 | 273 | entity ent is
end entity;
architecture a of ent is
procedure proc(bv : bit_vector) is
begin
report to_string(bv'length);
end procedure;
begin
main : process
variable bv : bit_vector(0 to 1);
begin
proc(bv);
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd | 4 | 1777 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1341.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01341ent IS
END c08s04b01x00p04n01i01341ent;
ARCHITECTURE c08s04b01x00p04n01i01341arch OF c08s04b01x00p04n01i01341ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 sec;
wait for 10 sec;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01341"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01341 - Predefined TIME unit sec as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01341arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2831.vhd | 4 | 1790 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2831.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RECORD is
end RECORD;
ENTITY c13s09b00x00p99n01i02831ent IS
END c13s09b00x00p99n01i02831ent;
ARCHITECTURE c13s09b00x00p99n01i02831arch OF c13s09b00x00p99n01i02831ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02831 - Reserved word RECORD can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02831arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug017/call5.vhdl | 2 | 325 | entity call5 is
end;
architecture behav of call5 is
procedure inc (p : inout integer) is
begin
wait for 1 ns;
p := p + 1;
end inc;
begin
process
variable v : integer := 2;
begin
inc (v);
wait for 2 ns;
inc (v);
assert not (v = 4) report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc282.vhd | 4 | 1813 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc282.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p08n02i00282ent IS
END c03s01b03x00p08n02i00282ent;
ARCHITECTURE c03s01b03x00p08n02i00282arch OF c03s01b03x00p08n02i00282ent IS
type time is range 0 to 1E8 units
fs;
-- -- Failure_here: min is not defined
ps = 10 min;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p08n02i00282 - Unit names declared in secondary unit declarations must be integral multiples of the base unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p08n02i00282arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd | 4 | 1647 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_01.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_01 is
end entity ch_03_01;
architecture test of ch_03_01 is
signal en : bit := '0';
signal data_in : integer := 0;
begin
process_3_1_a : process (en, data_in) is
variable stored_value : integer := 0;
begin
-- code from book:
if en = '1' then
stored_value := data_in;
end if;
-- end of code from book
end process process_3_1_a;
stimulus : process is
begin
en <= '1' after 10 ns, '0' after 20 ns;
data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/add_483.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_483;
architecture augh of add_483 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/add_184.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_184;
architecture augh of add_184 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd | 4 | 1347 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all;
entity alu is
generic ( Tpd : delay_length );
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end entity alu;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/cmp_132.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd | 4 | 1795 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_std_logic_to_analog is
end tb_std_logic_to_analog;
architecture TB_std_logic2analog of tb_std_logic_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical ;
signal ina : std_logic ;
begin
-- Signal assignments
-- Component instances
d2a1 : entity work.std_logic_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_std_logic2analog;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd | 4 | 1171 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity sum2 is
generic ( k1, k2 : real := 1.0 ); -- optional gain multipliers
port ( quantity in1, in2 : in real;
quantity output : out real );
end entity sum2;
----------------------------------------------------------------
architecture simple of sum2 is
begin
output == k1 * in1 + k2 * in2; -- sum of inputs (with optional gain)
end architecture simple;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd | 4 | 1800 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc877.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b02x00p02n01i00877ent IS
END c01s03b02x00p02n01i00877ent;
ARCHITECTURE c01s03b02x00p02n01i00877arch OF c01s03b02x00p02n01i00877ent IS
BEGIN
BB : block
component LOCAL
end component;
begin
CIS : LOCAL;
assert FALSE
report "***PASSED TEST: c01s03b02x00p02n01i00877"
severity NOTE;
end block BB;
END c01s03b02x00p02n01i00877arch;
configuration c01s03b02x00p02n01i00877cfg of c01s03b02x00p02n01i00877ent is
for c01s03b02x00p02n01i00877arch
for BB
for CIS : LOCAL -- Success_here
end for;
end for;
end for ;
end c01s03b02x00p02n01i00877cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1623.vhd | 4 | 1664 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1623.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01623ent IS
END c08s12b00x00p03n01i01623ent;
ARCHITECTURE c08s12b00x00p03n01i01623arch OF c08s12b00x00p03n01i01623ent IS
BEGIN
return true; -- illegal in architecture statement region.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01623 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01623arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd | 4 | 1502 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- analyze into resource library graphics
package graphics_pkg is
attribute graphic_symbol : string;
attribute graphic_style : string;
end package graphics_pkg;
-- code from book
library ieee; use ieee.std_logic_1164.all;
library graphics;
package gate_components is
use graphics.graphics_pkg.graphic_symbol,
graphics.graphics_pkg.graphic_style;
component and2 is
generic ( prop_delay : delay_length );
port ( a, b : in std_logic; y : out std_logic );
end component and2;
attribute graphic_symbol of and2 : component is "and2";
attribute graphic_style of and2 : component is "color:default, weight:bold";
-- . . .
end package gate_components;
-- end code from book
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd | 4 | 1850 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovect-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_vector_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real := 0.0;
begin
dut : entity work.to_vector(behavioral)
port map (r, vec);
stimulus : process is
begin
r <= 0.0; wait for 10 ns;
r <= -1.0; wait for 10 ns;
r <= -2.0; wait for 10 ns;
r <= +0.9999; wait for 10 ns;
r <= +2.0; wait for 10 ns;
r <= -0.5; wait for 10 ns;
r <= +0.5; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd | 4 | 3596 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start : in std_ulogic; -- Start signal
signal clk : in std_ulogic; -- Strobe clock
terminal ain : electrical; -- Analog input terminal
signal eoc : out std_ulogic := '0'; -- End of conversion pin
signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
end entity a2d_nbit;
----------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax : real := 5.0; -- ADC's maximum range
constant delay : time := 10 us; -- ADC's conversion time
type states is (input, convert); -- Two states of A2D Conversion
constant bit_range : integer := 9; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process is
variable thresh : real := Vmax; -- Threshold to test input voltage against
variable Vtmp : real := Vin; -- Snapshot of input voltage
-- when conversion starts
variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
variable status : states := input; -- Begin with "input" case
variable bit_cnt : integer := bit_range;
begin
case status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H';
bit_cnt := bit_range; -- Reset bit_cnt for conversion
thresh := Vmax;
Vtmp := Vin; -- Variable to hold input comparison voltage
eoc <= '0'; -- Reset end of conversion
status := convert; -- Go to convert state
when convert => -- Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh := thresh / 2.0; -- Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
Vtmp := Vtmp - thresh; -- Prepare for next comparison
else
dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := bit_cnt - 1; -- Decrement the bit count
else
dout <= dtmp; -- Put contents of dtmp on output pins
eoc <= '1' after delay; -- Signal end of conversion
status := input; -- Go to input state
end if;
end case;
end process sa_adc;
Iin == 0.0; -- Ideal input draws no current
end architecture sar;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd | 4 | 1909 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity tb_BuckConverter is
port ( ctrl : std_logic );
end tb_BuckConverter;
----------------------------------------------------------------
architecture tb_BuckConverter of tb_BuckConverter is
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
begin
L1 : entity work.inductor(ideal)
generic map ( ind => 6.5e-3 )
port map ( p1 => vmid, p2 => vout );
C1 : entity work.capacitor(ideal)
generic map ( cap => 1.5e-6 )
port map ( p1 => vout, p2 => electrical_ref );
VinDC : entity work.v_constant(ideal)
generic map ( level => 42.0 )
port map ( pos => vin, neg => electrical_ref );
RLoad : entity work.resistor(ideal)
generic map ( res => 2.4 )
port map ( p1 => vout, p2 => electrical_ref );
D1 : entity work.diode(ideal)
port map ( p => electrical_ref, n => vmid );
sw1 : entity work.switch_dig(ideal)
port map ( sw_state => ctrl, p2 => vmid, p1 => vin );
end architecture tb_BuckConverter;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd | 4 | 2115 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc956.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n02i00956ent IS
END c06s01b00x00p10n02i00956ent;
ARCHITECTURE c06s01b00x00p10n02i00956arch OF c06s01b00x00p10n02i00956ent IS
signal PT : boolean;
subtype ONE is integer range 1 to 1;
type R1 is record
X1: ONE;
RE1: BOOLEAN;
end record;
function rr1(i : integer) return R1 is
variable vr : r1;
begin
return vr;
end rr1;
attribute AT1 : R1;
attribute AT1 of PT : signal is rr1(3);
type A1 is array (BOOLEAN) of BOOLEAN;
BEGIN
TESTING: PROCESS
variable V1 : BOOLEAN;
variable V2 : A1;
BEGIN
V1 := V2(PT'AT1.RE1);
assert NOT( V1=FALSE )
report "***PASSED TEST: c06s01b00x00p10n02i00956"
severity NOTE;
assert ( V1=FALSE )
report "***FAILED TEST: c06s01b00x00p10n02i00956 - The prefix of a name is a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n02i00956arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd | 4 | 1368 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_08_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package ch_08_02;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd | 4 | 1962 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
use ieee_proposed.fluidic_systems.all;
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
-- code from book:
type engine_nodes is (intake, compressor, combustion, exhaust);
type engines is range 1 to 4;
nature aircraft_engine_flows is array (engine_nodes, engines) of fluidic;
--
nature sensor_matrix is array (1 to 100, 1 to 100) of translational;
--
terminal sensor_grid : sensor_matrix;
--
quantity sensor_data across sensor_grid to translational_ref;
-- end of code from book
begin
process_1_b : process is
variable total_displacement, average_displacement : real;
begin
-- code from book:
total_displacement := 0.0;
for x in 1 to 100 loop
for y in 1 to 100 loop
total_displacement := total_displacement + sensor_data(x, y);
end loop;
end loop;
average_displacement := total_displacement / 10000.0;
--end code from book
wait;
end process process_1_b;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd | 4 | 1948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02412ent IS
END c07s03b02x00p09n01i02412ent;
ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
type T1 is array (1 to 5) of integer;
constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***PASSED TEST: c07s03b02x00p09n01i02412"
severity NOTE;
assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02412arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc372.vhd | 4 | 1879 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00372ent IS
END c03s02b01x01p03n02i00372ent;
ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A5 is array (FALSE to FALSE,
BFALSE range <>,
1 to 2) of BIT; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00372arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00220ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00220ent;
ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(e'pos(ETYP) < e'pos(EMAX))
report "***PASSED TEST: c03s01b01x00p06n03i00220"
severity NOTE;
assert (e'pos(ETYP) < e'pos(EMAX))
report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00220arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd | 4 | 2035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1164.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01164pkg is
type A1 is array (1 to 2) of BOOLEAN;
type A2 is array (1 to 2) of A1;
end c06s06b00x00p02n01i01164pkg;
use work.c06s06b00x00p02n01i01164pkg.all;
ENTITY c06s06b00x00p02n01i01164ent IS
port (PT: A2);
attribute AT1 : BOOLEAN;
attribute AT1 of PT : signal is TRUE;
END c06s06b00x00p02n01i01164ent;
ARCHITECTURE c06s06b00x00p02n01i01164arch OF c06s06b00x00p02n01i01164ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if PT'AT1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01164"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01164 - The prefix of an attribute name may be an indexed name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01164arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd | 4 | 2379 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package random is
type distribution_type is (fixed, uniform, exponential);
subtype probability is real range 0.0 to 1.0;
type probability_vector is array (positive range <>) of probability;
type seed_type is record
seed1, seed2 : positive;
end record seed_type;
type seed_array is array ( natural range <> ) of seed_type;
constant sample_seeds : seed_array(0 to 50);
type random_info_record is record
seed : seed_type;
distribution : distribution_type;
mean : real;
lower_bound, upper_bound : real;
end record random_info_record;
procedure init_fixed ( random_info : out random_info_record;
mean : in real );
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type );
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type );
procedure generate_random ( random_info : inout random_info_record;
random_number : out real );
end package random;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd | 4 | 2251 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2117.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02117ent IS
END c07s02b04x00p20n01i02117ent;
ARCHITECTURE c07s02b04x00p20n01i02117arch OF c07s02b04x00p20n01i02117ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_8 is integer_v (1 to 8);
SUBTYPE integer_4 is integer_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : integer_4;
variable l_operand : integer_4 := (123,789,123,789);
variable r_operand : integer_4 := (789,789,123,123);
alias l_alias : integer_v (1 to 2) is l_operand (2 to 3);
alias r_alias : integer_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = (789,123,123,123)) and (result(1) = 789))
report "***PASSED TEST: c07s02b04x00p20n01i02117"
severity NOTE;
assert ((result = (789,123,123,123)) and (result(1) = 789))
report "***FAILED TEST: c07s02b04x00p20n01i02117 - Concatenation of two INTEGER aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02117arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue30/alu.vhdl | 2 | 40392 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_ccf_operation of ccf_operation is
begin
-- A point of disagreement has been found between the Z80 user manual
-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
-- The Z80 user manual says the half-carry bit gets the previous carry;
-- Levinthal says the half-carry bit is unchanged. For now, go with
-- Levinthal's version as the Z80 users manual is inconsistent with
-- itself on other instructions. At this time, no such inconsistencies
-- have been found with Levinthal's work.
flags_out <= ( carry_bit => not flags_in(carry_bit),
half_carry_bit => flags_in(carry_bit),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sll8bit of sll8bit is
signal sll_result: std_logic_vector(7 downto 0);
begin
-- This operation is not documented by Zilog, but seems to work in their
-- finished chip. This code may not work the same way as the Z80 hardware
-- works. The functionality is assumed from the SRL instruction.
sll_result <= operand(6 downto 0) & '0';
output <= sll_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (sll_result(7) or sll_result(6) or sll_result(5) or sll_result(4) or
sll_result(3) or sll_result(2) or sll_result(1) or sll_result(0)),
parity_overflow_bit => not (sll_result(7) xor sll_result(6) xor sll_result(5) xor
sll_result(4) xor sll_result(3) xor sll_result(2) xor
sll_result(1) xor sll_result(0)),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_srl8bit of srl8bit is
signal srl_result: std_logic_vector(7 downto 0);
begin
srl_result <= '0' & operand(7 downto 1);
output <= srl_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (srl_result(7) or srl_result(6) or srl_result(5) or srl_result(4) or
srl_result(3) or srl_result(2) or srl_result(1) or srl_result(0)),
parity_overflow_bit => not (srl_result(7) xor srl_result(6) xor srl_result(5) xor
srl_result(4) xor srl_result(3) xor srl_result(2) xor
srl_result(1) xor srl_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_and8bit of and8bit is
signal and_result: std_logic_vector(7 downto 0);
begin
and_result <= operand1 and operand2;
flags_out <= ( sign_bit => and_result(7),
zero_bit => not (and_result(7) or and_result(6) or and_result(5) or and_result(4) or
and_result(3) or and_result(2) or and_result(1) or and_result(0)),
half_carry_bit => '1',
parity_overflow_bit => not (and_result(7) xor and_result(6) xor and_result(5) xor
and_result(4) xor and_result(3) xor and_result(2) xor
and_result(1) xor and_result(0)),
others => '0');
output <= and_result;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_or8bit of or8bit is
signal or_result: std_logic_vector(7 downto 0);
begin
or_result <= operand1 or operand2;
output <= or_result;
flags_out <= ( sign_bit => or_result(7),
half_carry_bit => '1',
zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
or_result(3) or or_result(2) or or_result(1) or or_result(0)),
parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
or_result(4) xor or_result(3) xor or_result(2) xor
or_result(1) xor or_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sra8bit of sra8bit is
signal sra_result: std_logic_vector(7 downto 0);
begin
sra_result <= operand(7) & operand(7 downto 1);
output <= sra_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (sra_result(7) or sra_result(6) or sra_result(5) or sra_result(4) or
sra_result(3) or sra_result(2) or sra_result(1) or sra_result(0)),
parity_overflow_bit => not (sra_result(7) xor sra_result(6) xor sra_result(5) xor
sra_result(4) xor sra_result(3) xor sra_result(2) xor
sra_result(1) xor sra_result(0)),
sign_bit => operand(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_xor8bit of xor8bit is
signal xor_result: std_logic_vector(7 downto 0);
begin
xor_result <= operand1 xor operand2;
output <= xor_result;
flags_out <= ( sign_bit => xor_result(7),
half_carry_bit => '1',
zero_bit => not (xor_result(7) or xor_result(6) or xor_result(5) or xor_result(4) or
xor_result(3) or xor_result(2) or xor_result(1) or xor_result(0)),
parity_overflow_bit => not (xor_result(7) xor xor_result(6) xor xor_result(5) xor
xor_result(4) xor xor_result(3) xor xor_result(2) xor
xor_result(1) xor xor_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sla8bit of sla8bit is
signal sla_result: std_logic_vector(7 downto 0);
begin
sla_result <= operand(6 downto 0) & '0';
output <= sla_result;
flags_out <= ( sign_bit => sla_result(7),
half_carry_bit => '1',
zero_bit => not (sla_result(7) or sla_result(6) or sla_result(5) or sla_result(4) or
sla_result(3) or sla_result(2) or sla_result(1) or sla_result(0)),
parity_overflow_bit => not (sla_result(7) xor sla_result(6) xor sla_result(5) xor
sla_result(4) xor sla_result(3) xor sla_result(2) xor
sla_result(1) xor sla_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end;
architecture struct_subtractor of subtractor is
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with
-- a Karnaugh map.
difference <= (borrow_in and (not minuend) and (not subtrahend)) or
((not borrow_in) and (not minuend) and subtrahend) or
(borrow_in and minuend and subtrahend) or
((not borrow_in) and minuend and (not subtrahend));
borrow_out <= (not minuend and subtrahend) or
(borrow_in and (not minuend)) or
(borrow_in and subtrahend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractorN is
generic(
N: positive
);
port(
minuend: in std_logic_vector((N-1) downto 0);
subtrahend: in std_logic_vector((N-1) downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector((N-1) downto 0);
borrow_out: out std_logic
);
end;
architecture struct_subtractorN of subtractorN is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(N downto 0);
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with a
-- Karnaugh map.
-- d = difference, m = minuend, s = subtrahend, b = borrow
--
-- d(i) = (b(i) and (not m(i)) and (not s(i))) or
-- ((not b(i)) and (not m(i)) and s(i)) or
-- (b(i) and m(i) and s(i)) or
-- ((not b(i)) and m(i) and (not s(i)))
--
-- b(i+1) = (not m(i) and s(i)) or
-- (b(i) and (not m(i))) or
-- (b(i) and s(i)
borrow(0) <= borrow_in;
u1: for i in 0 to (N-1) generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => difference(i),
borrow_out => borrow(i+1)
);
end generate;
borrow_out <= borrow(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_subtractor8x2 of subtractor8x2 is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(8 downto 0);
signal d: std_logic_vector(7 downto 0);
begin
borrow(0) <= borrow_in;
u1: for i in 0 to 7 generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => d(i),
borrow_out => borrow(i+1)
);
end generate;
difference <= d;
flags_out <= ( sign_bit => d(7),
zero_bit => not (d(0) or d(1) or d(2) or d(3) or d(4) or d(5) or d(6) or d(7)),
half_carry_bit => borrow(4),
parity_overflow_bit => (minuend(7) xor subtrahend(7)) and (minuend(7) xor d(7)),
add_sub_bit => '1',
carry_bit => borrow(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end;
architecture struct_adder of adder is
begin
-- These expressions are derived from a single bit full adder truth table and simplified with a
-- Karnaugh map.
sum <= ((not (carry_in)) and (not addend) and augend) or
((not carry_in) and addend and (not augend)) or
(carry_in and (not addend) and (not augend)) or
(carry_in and addend and augend);
carry_out <= (addend and augend) or
(carry_in and addend) or
(carry_in and augend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity adderN is
generic(
N: positive
);
port(
addend: in std_logic_vector((N-1) downto 0);
augend: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
-- Tested with Modelsim 2015/12/11, works.
architecture struct_adderN of adderN is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal carry: std_logic_vector(N downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to (N-1) generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => sum(i),
carry_out => carry(i+1)
);
end generate;
carry_out <= carry(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
-- The adderN version is not used because access to carry out of bit 3 is required.
architecture struct_adder8x2 of adder8x2 is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal result: std_logic_vector(7 downto 0);
signal carry: std_logic_vector(8 downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to 7 generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => result(i),
carry_out => carry(i+1)
);
end generate;
sum <= result;
flags_out <= ( sign_bit => result(7),
zero_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
half_carry_bit => carry(4),
parity_overflow_bit => not (addend(7) xor augend(7)) and
(addend(7) xor result(7)),
add_sub_bit => '0',
carry_bit => carry(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_cpl of cpl is
begin
output <= not operand;
flags_out <= ( half_carry_bit => '1',
add_sub_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rlc8bit of rlc8bit is
signal rlc_result: std_logic_vector(7 downto 0);
begin
rlc_result(7 downto 1) <= operand(6 downto 0);
rlc_result(0) <= operand(7);
output <= rlc_result;
flags_out <= ( carry_bit => operand(7),
parity_overflow_bit => not (rlc_result(7) xor rlc_result(6) xor rlc_result(5) xor
rlc_result(4) xor rlc_result(3) xor rlc_result(2) xor
rlc_result(1) xor rlc_result(0)),
zero_bit => not (rlc_result(7) or rlc_result(6) or rlc_result(5) or rlc_result(4) or
rlc_result(3) or rlc_result(2) or rlc_result(1) or rlc_result(0)),
sign_bit => rlc_result(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrc8bit of rrc8bit is
signal rrc_result: std_logic_vector(7 downto 0);
begin
rrc_result(6 downto 0) <= operand(7 downto 1);
rrc_result(7) <= operand(0);
output <= rrc_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rrc_result(7) or rrc_result(6) or rrc_result(5) or rrc_result(4) or
rrc_result(3) or rrc_result(2) or rrc_result(1) or rrc_result(0)),
parity_overflow_bit => not (rrc_result(7) xor rrc_result(6) xor rrc_result(5) xor
rrc_result(4) xor rrc_result(3) xor rrc_result(2) xor
rrc_result(1) xor rrc_result(0)),
sign_bit => operand(0),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rl8bit of rl8bit is
signal rl_result: std_logic_vector(7 downto 0);
begin
rl_result (7 downto 1) <= operand(6 downto 0);
rl_result(0) <= carry_in;
output <= rl_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (rl_result(7) or rl_result(6) or rl_result(5) or rl_result(4) or
rl_result(3) or rl_result(2) or rl_result(1) or rl_result(0)),
parity_overflow_bit => not ((rl_result(7) xor rl_result(6) xor rl_result(5) xor
rl_result(4) xor rl_result(3) xor rl_result(2) xor
rl_result(1) xor rl_result(0))),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rr8bit of rr8bit is
signal rr_result: std_logic_vector(7 downto 0);
begin
rr_result(6 downto 0) <= operand(7 downto 1);
rr_result(7) <= carry_in;
output <= rr_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rr_result(7) or rr_result(6) or rr_result(5) or rr_result(4) or
rr_result(3) or rr_result(2) or rr_result(1) or rr_result(0)),
parity_overflow_bit => not (rr_result(7) xor rr_result(6) xor rr_result(5) xor
rr_result(4) xor rr_result(3) xor rr_result(2) xor
rr_result(1) xor rr_result(0)),
sign_bit => carry_in,
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Untested, this is nothing more than a stub with code to prevent unassigned variable warnings/errors.
architecture struct_daa of daa is
begin
output <= operand;
flags_out <= flags_in;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bit_op of bit_op is
signal zero: std_logic;
begin
zero <= '1' when (operand1 and operand2) = x"00" else '0';
flags_out <= ( zero_bit => zero,
half_carry_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rld of rld is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(7 downto 4);
result <= primary_result;
secondary_result(7 downto 4) <= secondary_op(3 downto 0);
secondary_result(3 downto 0) <= primary_op(3 downto 0);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrd of rrd is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(3 downto 0);
result <= primary_result;
secondary_result(7 downto 4) <= primary_op(3 downto 0);
secondary_result(3 downto 0) <= secondary_op(7 downto 4);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_in_rc_flags of in_rc_flags is
begin
flags_out <= ( zero_bit => not (operand(7) or operand(6) or operand(5) or operand(4) or
operand(3) or operand(2) or operand(1) or operand(0)),
sign_bit => operand(7),
parity_overflow_bit => not (operand(7) xor operand(6) xor operand(5) xor
operand(4) xor operand(3) xor operand(2) xor
operand(1) xor operand(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bmtc of bmtc is
signal result: std_logic_vector(7 downto 0);
begin
result <= operand1 or operand2;
output <= result;
flags_out <= ( parity_overflow_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested 2016/11/22, works on Modelsim simulator along with all components.
architecture struct_alu of alu is
component bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a: in std_logic_vector((N-1) downto 0);
b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
component rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component encoder32xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end component;
component encoder2xN_oe is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
enable: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end component;
signal add_result: std_logic_vector(7 downto 0);
signal add_carry_in: std_logic;
signal add_flags: std_logic_vector(7 downto 0);
signal and_result: std_logic_vector(7 downto 0);
signal and_flags: std_logic_vector(7 downto 0);
signal or_result: std_logic_vector(7 downto 0);
signal or_flags: std_logic_vector(7 downto 0);
signal xor_result: std_logic_vector(7 downto 0);
signal xor_flags: std_logic_vector(7 downto 0);
signal cpl_result: std_logic_vector(7 downto 0);
signal cpl_flags: std_logic_vector(7 downto 0);
signal subtract_result: std_logic_vector(7 downto 0);
signal subtract_borrow_in: std_logic;
signal subtract_flags: std_logic_vector(7 downto 0);
signal rlc_result: std_logic_vector(7 downto 0);
signal rlc_flags: std_logic_vector(7 downto 0);
signal rrc_result: std_logic_vector(7 downto 0);
signal rrc_flags: std_logic_vector(7 downto 0);
signal rl_result: std_logic_vector(7 downto 0);
signal rl_flags: std_logic_vector(7 downto 0);
signal rr_result: std_logic_vector(7 downto 0);
signal rr_flags: std_logic_vector(7 downto 0);
signal daa_result: std_logic_vector(7 downto 0);
signal daa_flags: std_logic_vector(7 downto 0);
signal scf_flags: std_logic_vector(7 downto 0);
signal ccf_carry: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal bit_zero: std_logic;
signal bit_flags: std_logic_vector(7 downto 0);
signal in_flags: std_logic_vector(7 downto 0); -- flags for IN r, C instruction
signal secondary_out_enable: std_logic; -- '1' when executing a rrd/rld
-- instruction
signal rld_result: std_logic_vector(7 downto 0);
signal secondary_rld_result: std_logic_vector(7 downto 0);
signal rld_flags: std_logic_vector(7 downto 0);
signal is_rld: std_logic;
signal rrd_result: std_logic_vector(7 downto 0);
signal secondary_rrd_result: std_logic_vector(7 downto 0);
signal rrd_flags: std_logic_vector(7 downto 0);
signal is_rrd: std_logic;
signal sla_result: std_logic_vector(7 downto 0);
signal sla_flags: std_logic_vector(7 downto 0);
signal sra_result: std_logic_vector(7 downto 0);
signal sra_flags: std_logic_vector(7 downto 0);
signal sll_result: std_logic_vector(7 downto 0);
signal sll_flags: std_logic_vector(7 downto 0);
signal srl_result: std_logic_vector(7 downto 0);
signal srl_flags: std_logic_vector(7 downto 0);
signal bmtc_result: std_logic_vector(7 downto 0);
signal bmtc_flags: std_logic_vector(7 downto 0); -- block move termination criterion
-- flags
begin
-- result multiplexer, 32x8
u1: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_result, -- add, ignore carry bit
data1 => add_result, -- add, add carry bit
data2 => subtract_result, -- sub, ignore borrow bit
data3 => subtract_result, -- sub, subtract borrow bit
data4 => and_result, -- and
data5 => xor_result, -- xor
data6 => or_result, -- or
data7 => subtract_result, -- compare (no-borrow sub with result
-- discarded, used to set flags)
data8 => rlc_result, -- RLC
data9 => rrc_result, -- RRC
data10 => rl_result, -- RL
data11 => rr_result, -- RR
data12 => daa_result, -- DAA
data13 => cpl_result, -- CPL
data14 => primary_operand, -- SCF
data15 => primary_operand, -- CCF
data16 => sla_result, -- SLA
data17 => sra_result, -- SRA
data18 => sll_result, -- SLL
data19 => srl_result, -- SRL
data20 => secondary_operand, -- BIT
data21 => and_result, -- RES
data22 => or_result, -- SET
data23 => primary_operand, -- IN r, (C)
data24 => rld_result, -- RLD
data25 => rrd_result, -- RRD
data26 => bmtc_result, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => output
);
-- result flags multiplexer
u2: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_flags, -- add
data1 => add_flags, -- adc
data2 => subtract_flags, -- sub
data3 => subtract_flags, -- sbc
data4 => and_flags, -- and
data5 => xor_flags, -- xor
data6 => or_flags, -- or
data7 => subtract_flags, -- cmp
data8 => rlc_flags, -- rlc
data9 => rrc_flags, -- rrc
data10 => rl_flags, -- rl
data11 => rr_flags, -- rr
data12 => daa_flags, -- daa
data13 => cpl_flags, -- cpl
data14 => scf_flags, -- scf
data15 => ccf_flags, -- ccf
data16 => sla_flags, -- SLA
data17 => sra_flags, -- SRA
data18 => sll_flags, -- SLL
data19 => srl_flags, -- SRL
data20 => bit_flags, -- BIT
data21 => (others => '0'), -- RES, no flags affected
data22 => (others => '0'), -- SET, no flags affected
data23 => in_flags, -- IN r, (C)
data24 => rld_flags, -- RLD
data25 => rrd_flags, -- RRD
data26 => bmtc_flags, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => flags_out
);
scf_flags <= (carry_bit => '1', others => '0');
-- adder: This version gets flagged by ModelSim on the carry_in line as an error. Only signals or
-- maybe variables are allowed. Expressions are not.
-- u3: adder8x2 port map(
-- addend => primary_operand,
-- augend => secondary_operand,
-- carry_in => (flags_in(carry_bit) and operation(0)), -- carry only with adc opcode, others
-- -- made irrelevant by result mux
-- sum => add_result,
-- carry_out => carry_out,
-- overflow => add_overflow,
-- interdigit_carry => interdigit_carry,
-- zero => add_zero
-- );
-- adder
u3: adder8x2 port map(
addend => primary_operand,
augend => secondary_operand,
carry_in => add_carry_in,
sum => add_result,
flags_out => add_flags
);
add_carry_in <= flags_in(carry_bit) and operation(0); -- carry only with adc opcode, others made
-- irrelevant by result mux
-- subtractor
u4: subtractor8x2 port map(
minuend => primary_operand,
subtrahend => secondary_operand,
borrow_in => subtract_borrow_in,
difference => subtract_result,
flags_out => subtract_flags
);
-- borrow only with sbc opcode, must remove compare opcode (operation(2 downto 0) = "111"), others
-- made irrelevant by result mux
subtract_borrow_in <= flags_in(carry_bit) and (not operation(2)) and operation(1) and operation(0);
-- bitwise and operation
u5: and8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => and_result,
flags_out => and_flags
);
-- bitwise exclusive-or operation
u6: xor8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => xor_result,
flags_out => xor_flags
);
-- bitwise or operation
u7: or8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => or_result,
flags_out => or_flags
);
-- RLC generator
u8: rlc8bit port map(
operand => primary_operand,
output => rlc_result,
flags_out => rlc_flags
);
-- RRC generator
u9: rrc8bit port map(
operand => primary_operand,
output => rrc_result,
flags_out => rrc_flags
);
-- RL generator
u10: rl8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rl_result,
flags_out => rl_flags
);
-- RR generator
u11: rr8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rr_result,
flags_out => rr_flags
);
-- DAA
u12: daa port map(
operand => primary_operand,
flags_in => flags_in,
output => daa_result,
flags_out => daa_flags
);
-- bit testing of secondary operand against mask in primary operand
u13: bit_op port map(
operand1 => primary_operand,
operand2 => secondary_operand,
flags_out => bit_flags
);
u14: rld port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rld_result,
secondary_result => secondary_rld_result,
flags_out => rld_flags
);
u15: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rrd_operation,
equal => is_rrd,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rld_operation,
equal => is_rld,
lt => open,
gt => open
);
u17: rrd port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rrd_result,
secondary_result => secondary_rrd_result,
flags_out => rrd_flags
);
u18: encoder2xN_oe
generic map(
N => 8
)
port map(
data0 => secondary_rld_result,
data1 => secondary_rrd_result,
selector => is_rrd,
enable => secondary_out_enable,
output => secondary_out
);
secondary_out_enable <= is_rrd or is_rld;
u19: cpl port map(
operand => primary_operand,
output => cpl_result,
flags_out => cpl_flags
);
u20: ccf_operation port map(
flags_in => flags_in,
flags_out => ccf_flags
);
u21: in_rc_flags port map(
operand => primary_operand,
flags_out => in_flags
);
u22: sla8bit port map(
operand => primary_operand,
output => sla_result,
flags_out => sla_flags
);
u23: sra8bit port map(
operand => primary_operand,
output => sra_result,
flags_out => sra_flags
);
u24: sll8bit port map(
operand => primary_operand,
output => sll_result,
flags_out => sll_flags
);
u25: srl8bit port map(
operand => primary_operand,
output => srl_result,
flags_out => srl_flags
);
u26: bmtc port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => bmtc_result,
flags_out => bmtc_flags
);
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd | 4 | 2340 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc654.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:54 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00654ent IS
END c03s04b01x00p01n01i00654ent;
ARCHITECTURE c03s04b01x00p01n01i00654arch OF c03s04b01x00p01n01i00654ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_range is integer_vector(hi_to_low_range);
constant C1 : integer_vector_range := (others => 3);
type integer_vector_range_file is file of integer_vector_range;
BEGIN
TESTING: PROCESS
file filein : integer_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00654 - The output file will be verified by test s010104.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00654arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd | 4 | 2588 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2450.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02450ent IS
END c07s03b02x02p03n02i02450ent;
ARCHITECTURE c07s03b02x02p03n02i02450arch OF c07s03b02x02p03n02i02450ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE );
type A_ARRAY is array ( integer range <> ) of integer;
type B_ARRAY is array ( boolean range <> ) of real;
type C_ARRAY is array ( ENUM range <>, ENUM range <>) of bit;
subtype A_CON is A_ARRAY ( 1 to 4 );
subtype B_CON is B_ARRAY ( FALSE to TRUE );
subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
function F_A ( PAR : A_ARRAY ) return A_CON is
begin return (1,2,3,4);
end F_A;
function F_B ( PAR : B_ARRAY ) return B_CON is
begin return (1.0, 2.0);
end F_B;
function F_C ( PAR : C_ARRAY ) return C_CON is
begin return (ONE=>(ONE=>'0'));
end F_C;
variable V_A : A_CON ;
variable V_B : B_CON ;
variable V_C : C_CON ;
BEGIN
V_A := F_A( F_A( (1,2,others=>3) ) ); -- Failure_here
-- SEMANTIC ERROR: "others" used in aggregate which corresponds to
-- an unconstrained formal parameter
assert FALSE
report "***FAILED TEST: c07s03b02x02p03n02i02450 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02450arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc75.vhd | 4 | 1745 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc75.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00075ent IS
END c04s03b01x02p10n04i00075ent;
ARCHITECTURE c04s03b01x02p10n04i00075arch OF c04s03b01x02p10n04i00075ent IS
signal X : bit;
BEGIN
TESTING: PROCESS(P)
BEGIN
X <= P;
END PROCESS TESTING;
TESTING1: PROCESS(Q)
BEGIN
X <= Q; --Failure Here
END PROCESS TESTING1;
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p10n04i00075 - A signal with multiple source should be a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
ENDc04s03b01x02p10n04i00075arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd | 4 | 1959 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2904.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x01p02n03i02904ent IS
END c02s01b01x01p02n03i02904ent;
ARCHITECTURE c02s01b01x01p02n03i02904arch OF c02s01b01x01p02n03i02904ent IS
procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer);
procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer) is
begin
I2 := I1;
I3 := 10;
end PX;
BEGIN
TESTING: PROCESS
variable V1 : Bit;
variable V2 : Integer;
BEGIN
PX('1',V1,V2);
wait for 5 ns;
assert NOT( V1='1' and V2=10 )
report "***PASSED TEST: c02s01b01x01p02n03i02904"
severity NOTE;
assert ( V1='1' and V2=10 )
report "***FAILED TEST: c02s01b01x01p02n03i02904 - Mode out for procedures are not copied properly"
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x01p02n03i02904arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2182.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02182ent IS
END c07s02b05x00p01n02i02182ent;
ARCHITECTURE c07s02b05x00p01n02i02182arch OF c07s02b05x00p01n02i02182ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
variable m : real := 5.5;
BEGIN
k := - m;
assert NOT( k = - 5.5 )
report "***PASSED TEST: c07s02b05x00p01n02i02182"
severity NOTE;
assert ( k = - 5.5 )
report "***FAILED TEST: c07s02b05x00p01n02i02182 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02182arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd | 4 | 1903 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1634.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01634ent IS
END c08s12b00x00p05n01i01634ent;
ARCHITECTURE c08s12b00x00p05n01i01634arch OF c08s12b00x00p05n01i01634ent IS
BEGIN
TESTING: PROCESS
type E is (A,B,C,D);
subtype E1 is E range C to D;
function F return E is
variable V : E1 := C;
begin
return V;
end F;
variable k : E := A;
BEGIN
k := F;
assert NOT(k = C)
report "***PASSED TEST: c08s12b00x00p05n01i01634"
severity NOTE;
assert (k = C)
report "***FAILED TEST: c08s12b00x00p05n01i01634 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01634arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd | 4 | 1920 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc318.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p03n01i00318ent IS
END c03s02b01x00p03n01i00318ent;
ARCHITECTURE c03s02b01x00p03n01i00318arch OF c03s02b01x00p03n01i00318ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_vector is array (0 to 63)of MVL;
BEGIN
TESTING: PROCESS
variable k : MVL_vector;
BEGIN
k(5) := 'Z';
assert NOT(k(5)='Z')
report "***PASSED TEST: c03s02b01x00p03n01i00318"
severity NOTE;
assert (k(5)='Z')
report "***FAILED TEST: c03s02b01x00p03n01i00318 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p03n01i00318arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/mul_469.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_469;
architecture augh of mul_469 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd | 4 | 1899 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc399.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p07n01i00399ent IS
END c03s02b01x01p07n01i00399ent;
ARCHITECTURE c03s02b01x01p07n01i00399arch OF c03s02b01x01p07n01i00399ent IS
constant X : BIT_VECTOR(0 to 3) := "0101";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
report "***PASSED TEST: c03s02b01x01p07n01i00399"
severity NOTE;
assert (X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
report "***FAILED TEST: c03s02b01x01p07n01i00399 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p07n01i00399arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd | 4 | 1764 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1923.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01923ent IS
END c07s02b01x00p01n01i01923ent;
ARCHITECTURE c07s02b01x00p01n01i01923arch OF c07s02b01x00p01n01i01923ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 nand b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01923"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01923 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01923arch;
| gpl-2.0 |
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