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tgingold/ghdl | testsuite/gna/bug077/repro2.vhdl | 1 | 371 | entity child2 is
port (i : bit_vector);
end;
architecture behav of child2 is
begin
assert i = "10";
end behav;
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : bit_vector (7 downto 0);
begin
inst : entity work.child2
port map(
i(0) => s(1),
i(1) => s(0));
process
begin
s <= x"01";
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd | 4 | 2194 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01677ent IS
END c09s01b00x00p08n01i01677ent;
ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
BEGIN
labeled : block
port ( v : OUT bit_vector_4 := "1010");
port map ( v_slice ( 0 to 3 ));
begin
v <= B"0101" after 10 ns; -- only driver created ..
end block;
TESTING: PROCESS
BEGIN
assert (v_slice = B"1010_1100")
report "Condition error: value of signal V_SLICE incorrect"
severity failure;
wait for 10 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c09s01b00x00p08n01i01677"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p08n01i01677arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd | 4 | 1532 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture do_nothing of ROM is
begin
end architecture do_nothing;
entity tb_rom is
end entity tb_rom;
architecture test of tb_rom is
signal address : natural := 0;
signal data : bit_vector(0 to 7);
signal enable : bit := '0';
begin
dut : entity work.ROM(do_nothing)
port map ( address => address, data => data, enable => enable );
stimulus : process is
begin
wait for 100 ns;
address <= 1000; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1004; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1008; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/sub_189.vhd | 2 | 1740 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_189 is
port (
lt : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_189;
architecture augh of sub_189 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
lt <= not(tmp_ge);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd | 4 | 2120 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02298ent IS
END c07s02b06x00p35n01i02298ent;
ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 ns / 1000.0) < 1 ns);
assert ((1 ps / 1000.0) < 1 ps);
assert ((1 fs / 1000.0) < 1 fs);
wait for 5 fs;
assert NOT( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***PASSED TEST: c07s02b06x00p35n01i02298"
severity NOTE;
assert ( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02298arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1869.vhd | 4 | 1875 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1869.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01869ent IS
END c07s01b00x00p08n01i01869ent;
ARCHITECTURE c07s01b00x00p08n01i01869arch OF c07s01b00x00p08n01i01869ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01869 - Process labels are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
with TESTING select --process label illegal here
obus(0) <= 5 after 5 ns when true;
END c07s01b00x00p08n01i01869arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1330/tb_test3.vhdl | 1 | 598 | entity tb_test3 is
end tb_test3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test3 is
signal clk : std_logic;
signal wr : std_logic;
signal arst : std_logic;
begin
dut: entity work.test3
port map (clk, wr, arst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wr <= '0';
arst <= '1';
pulse;
report "cycle 2";
arst <= '0';
pulse;
report "cycle 3";
arst <= '1';
wr <= '1';
pulse;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd | 4 | 1730 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2567.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p02n01i02567ent IS
END c07s05b00x00p02n01i02567ent;
ARCHITECTURE c07s05b00x00p02n01i02567arch OF c07s05b00x00p02n01i02567ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E6 = (2E3*1E3))
report "***PASSED TEST: c07s05b00x00p02n01i02567"
severity NOTE;
assert (2E6 = (2E3*1E3))
report "***FAILED TEST: c07s05b00x00p02n01i02567 - The same operations are defined for the type universal_integer as for any integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p02n01i02567arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd | 4 | 1923 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00681ent IS
END c03s04b01x00p23n01i00681ent;
ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
file S1: FT open write_mode is "iofile.47";
BEGIN
WRITE(S1,3);
WRITE(S1,2);
WRITE(S1,1);
wait for 10 ns;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00681arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd | 4 | 1776 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
entity and2 is
generic ( Tpd : time );
port ( a, b : in bit; y : out bit );
end entity and2;
architecture simple of and2 is
begin
and2_function :
y <= a and b after Tpd;
end architecture simple;
-- end code from book
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
library util; use util.stimulus_generators.all;
architecture test of inline_01 is
signal a1, b1, sig1, sig2, sig_out : bit;
signal test_vector : bit_vector(1 to 3);
begin
-- code from book
gate1 : entity work.and2(simple)
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, y => sig_out );
gate2 : entity work.and2(simple)
generic map ( Tpd => 3 ns )
port map ( a => a1, b => b1, y => sig1 );
-- end code from book
stimulus : all_possible_values ( bv => test_vector,
delay_between_values => 10 ns );
(sig2, a1, b1) <= test_vector;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue328/t5.vhdl | 1 | 426 | entity t5 is
end t5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t5 is
signal s : std_logic := '0';
begin
b: block
port (p : out std_logic := 'Z');
port map (p => s);
begin
end block;
b2: block
port (p : out std_logic := '1');
port map (p => s);
begin
end block;
process
begin
wait for 1 ns;
assert s = 'X' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dispout01/rec01.vhdl | 1 | 225 | library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
entity rec01 is
port (inp : std_logic;
o : out myrec);
end rec01;
architecture behav of rec01 is
begin
o.a <= inp;
o.b <= not inp;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug21052/test.vhd | 3 | 2818 | library std;
use std.textio.all;
entity test is end entity;
architecture a of test is
component wrapper is end component;
begin
inst :if false generate inst :wrapper; end generate;
process
variable l :line;
begin
write(l, string'("OK")); writeline(output, l); wait;
end process;
end architecture;
package some_package is
-- this signal seems to be problematic
signal some_signal :bit;
component some_component end component;
end package;
entity wrapper is end entity;
architecture a of wrapper is begin
inst :work.some_package.some_component;
end architecture;
-- ################################################################################
-- $ ghdl -c test.vhd -e test
-- test.vhd:17:8:warning: component instance "inst" is not bound
-- test.vhd:16:14:warning: (in default configuration of wrapper(a))
-- $ ./test
-- OK
-- $ ./test --wave=test.ghw
-- Aborted (core dumped)
-- $ ghdl --version
-- GHDL 0.29 (20100109) [Sokcho edition]
-- Compiled with GNAT Version: 4.7.2
-- GCC back-end code generator
-- Written by Tristan Gingold.
--
-- Copyright (C) 2003 - 2010 Tristan Gingold.
-- GHDL is free software, covered by the GNU General Public License. There is NO
-- warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- ################################################################################
-- $ ghdl -c test.vhd -e test
-- test.vhd:19:8:warning: component instance "inst" is not bound
-- test.vhd:18:14:warning: (in default configuration of wrapper(a))
-- $ ./test
-- OK
-- $ ./test --wave=test.ghw
-- ^C
-- $ ghdl --version
-- GHDL 0.29 (20100109) [Sokcho edition]
-- Compiled with GNAT Version: 4.4.2 20091222 (Red Hat 4.4.2-20
-- GCC back-end code generator
-- Written by Tristan Gingold.
--
-- Copyright (C) 2003 - 2010 Tristan Gingold.
-- GHDL is free software, covered by the GNU General Public License. There is NO
-- warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- ################################################################################
-- $ ghdl -c test.vhd -e test
-- test.vhd:19:8:warning: component instance "inst" is not bound
-- test.vhd:18:14:warning: (in default configuration of wrapper(a))
-- $ ./test
-- OK
-- $ ./test --wave=test.ghw
--
-- raised CONSTRAINT_ERROR : grt-waves.adb:824 access check failed
-- $ ghdl --version
-- GHDL 0.30dev (20100112) [Sokcho edition]
-- Compiled with GNAT Version: 4.8.0 20130412 (Red Hat 4.8.0-2)
-- GCC back-end code generator
-- Written by Tristan Gingold.
--
-- Copyright (C) 2003 - 2010 Tristan Gingold.
-- GHDL is free software, covered by the GNU General Public License. There is NO
-- warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- ################################################################################
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd | 4 | 1610 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd | 4 | 1274 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
begin
-- code from book:
hiding_example : process is
variable a, b : integer;
begin
a := 10;
for a in 0 to 7 loop
b := a;
end loop;
-- a = 10, and b = 7
-- . . .
-- not in book:
wait;
-- end not in book
end process hiding_example;
-- end of code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd | 4 | 1803 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2022.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02022ent IS
END c07s02b04x00p01n01i02022ent;
ARCHITECTURE c07s02b04x00p01n01i02022arch OF c07s02b04x00p01n01i02022ent IS
BEGIN
TESTING: PROCESS
variable w : real := 3.0 - 2.0; -- No_failure_here
-- w should be 1.0
BEGIN
assert NOT(w=1.0)
report "***PASSED TEST: c07s02b04x00p01n01i02022"
severity NOTE;
assert (w=1.0)
report "***FAILED TEST: c07s02b04x00p01n01i02022 - The adding operators are predefined only for numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02022arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd | 4 | 2516 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3148.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03148ent_a IS
END c05s02b02x00p08n01i03148ent_a;
ARCHITECTURE c05s02b02x00p08n01i03148arch_a OF c05s02b02x00p08n01i03148ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03148 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03148arch_a;
--most recently analyzed ...
ARCHITECTURE c05s02b02x00p08n01i03148arch_b OF c05s02b02x00p08n01i03148ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03148"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03148arch_b;
--
ENTITY c05s02b02x00p08n01i03148ent IS
END c05s02b02x00p08n01i03148ent;
ARCHITECTURE c05s02b02x00p08n01i03148arch OF c05s02b02x00p08n01i03148ent IS
begin
blk : block
component c05s02b02x00p08n01i03148ent_c
end component;
for comp1 : c05s02b02x00p08n01i03148ent_c use entity work.c05s02b02x00p08n01i03148ent_a;
BEGIN
comp1 : c05s02b02x00p08n01i03148ent_c;
end block;
END c05s02b02x00p08n01i03148arch;
configuration c05s02b02x00p08n01i03148_cfg of c05s02b02x00p08n01i03148ent is
for c05s02b02x00p08n01i03148arch
end for;
end c05s02b02x00p08n01i03148_cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd | 4 | 2292 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cache is
end entity tb_cache;
architecture test of tb_cache is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity tb_cache_read_data is
end entity tb_cache_read_data;
architecture reader of tb_cache_read_data is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2818.vhd | 4 | 1596 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2818.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity OF is
end OF;
ENTITY c13s09b00x00p99n01i02818ent IS
END c13s09b00x00p99n01i02818ent;
ARCHITECTURE c13s09b00x00p99n01i02818arch OF c13s09b00x00p99n01i02818ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02818 - Reserved word OF can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02818arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd | 4 | 2817 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s02b00x00p10n01i01709pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c09s02b00x00p10n01i01709pkg;
package body c09s02b00x00p10n01i01709pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c09s02b00x00p10n01i01709pkg;
ENTITY c09s02b00x00p10n01i01709ent IS
END c09s02b00x00p10n01i01709ent;
use work.c09s02b00x00p10n01i01709pkg.all;
ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
signal A : WORD;
BEGIN
-- Test signal arrays indexed using literal constants. (locally static)
TESTING: PROCESS(A(1))
variable INITED : BOOLEAN := FALSE;
variable NewTime: TIME;
BEGIN
-- Perform the first piece of assignments.
if (not(INITED)) then
INITED := TRUE;
A( 1 ) <= 'X' after 10 ns;
NewTime := NOW + 10 ns;
end if;
if (now = NewTime) then
assert NOT( A(1) = 'X' )
report "***PASSED TEST: c09s02b00x00p10n01i01709"
severity NOTE;
assert ( A(1) = 'X' )
report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p10n01i01709arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue807/repro.vhdl | 1 | 295 | library ieee;
use ieee.std_logic_1164.all;
use work.test_pkg.all;
entity test is
end entity;
architecture a of test is
begin
process
variable rec : record_t(data(7 downto 0));
begin
test_procedure(rec);
report to_string(rec.data);
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug02/repro3.vhdl | 3 | 844 | entity repro3 is
end repro3;
package repro3_pkg is
procedure inc (a : inout integer);
type prot is protected
procedure get (a : integer);
end protected prot;
end repro3_pkg;
package body repro3_pkg is
procedure inc (a : inout integer) is
begin
a := a + 1;
end inc;
procedure inc (a : inout time) is
begin
a := a + 1 ns;
end inc;
type prot is protected body
variable v : integer;
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
procedure get (a : integer) is
begin
v := a;
end get;
end protected body prot;
end repro3_pkg;
use work.repro3_pkg.all;
architecture behav of repro3 is
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd | 3 | 10182 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc995.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p08n01i00995pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- ------------------------------------------------------------------------------------
-- Attribute Declarations
-- ------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
END;
USE WORK.c06s03b00x00p08n01i00995pkg.all;
ENTITY c06s03b00x00p08n01i00995ent IS
ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS TRUE;
ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS '0';
ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS 'z';
ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS 0;
ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10.0;
-- ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10 ns;
ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10000 pf;
ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS FX;
ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00995ent: ENTITY IS "entity";
ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00995ent: ENTITY IS "enty";
ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS TRUE;
ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS '0';
ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS 'z';
ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS 0;
ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10.0;
-- ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10 ns;
ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10000 pf;
ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS FX;
END c06s03b00x00p08n01i00995ent;
ARCHITECTURE c06s03b00x00p08n01i00995arch OF c06s03b00x00p08n01i00995ent IS
BEGIN
TESTING: PROCESS
BEGIN
ASSERT c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl4 = 0
REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
-- ASSERT c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
-- REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl8 = FX
REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl4 = 0
REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
-- ASSERT c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
-- REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl8 = FX
REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
assert NOT( c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
and c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'atr_scl4 = 0
and c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'atr_scl8 = FX
and c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
and c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
and c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
and c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'cat_scl4 = 0
and c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'cat_scl8 = FX )
report "***PASSED TEST: c06s03b00x00p08n01i00995"
severity NOTE;
assert ( c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
and c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'atr_scl4 = 0
and c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'atr_scl8 = FX
and c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
and c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
and c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
and c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'cat_scl4 = 0
and c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'cat_scl8 = FX )
report "***FAILED TEST: c06s03b00x00p08n01i00995 - Expanded name denotes a primary unit contained in design library test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n01i00995arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug0105/econcat1_87.vhdl | 1 | 449 | entity econcat1_87 is
end econcat1_87;
architecture behav of econcat1_87 is
constant c1 : string (21 downto 17) := "hello";
constant c2 : string (6 downto 1) := " world";
constant r : string := c1 & c2;
begin
process
begin
case True is
when c1 & c2 = "hello world" => null;
when false => null;
end case;
assert r'left = 21 severity failure;
assert r'right = 11 severity failure;
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2875.vhd | 4 | 1717 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2875.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n08i02875ent IS
-- Failure_here: Embedded spaces in string_literal of the overloaded operator
function "abs " return real is
begin
return 1.0;
end;
END c02s01b00x00p06n08i02875ent;
ARCHITECTURE c02s01b00x00p06n08i02875arch OF c02s01b00x00p06n08i02875ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p06n08i02875 - Extra spaces are not allowed in an operator symbol."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n08i02875arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1252/pkg.vhdl | 1 | 1272 | package pkg is
type c_int_prot is protected
impure function get return integer;
--------------------------------------------
impure function c_getInt return integer;
attribute foreign of c_getInt : function is "VHPIDIRECT getInt";
--------------------------------------------
end protected c_int_prot;
--------------------------------------------
-- impure function c_getInt return integer;
-- attribute foreign of c_getInt : function is "VHPIDIRECT getInt";
--------------------------------------------
shared variable c_int : c_int_prot;
end package;
package body pkg is
type c_int_prot is protected body
variable hidden_c_int : integer := c_getInt;
impure function get return integer is
begin
return hidden_c_int;
end function;
--------------------------------------------
impure function c_getInt return integer is
begin
assert false report "c_getInt VHPIDIRECT" severity failure;
end function;
--------------------------------------------
end protected body c_int_prot;
--------------------------------------------
-- impure function c_getInt return integer is
-- begin
-- assert false report "c_getInt VHPIDIRECT" severity failure;
-- end function;
--------------------------------------------
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd | 4 | 2353 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_sequencer is
port ( rd, wr, sel, width, burst : out std_ulogic;
addr_low_4 : out std_ulogic_vector(3 downto 0);
ready : out std_ulogic;
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
analog_out_wr_0,
other_signal : out std_ulogic );
end entity bus_sequencer;
----------------
library ieee; use ieee.std_logic_1164.all;
entity state_register is
port ( phi1, phi2 : in std_ulogic;
next_state : in std_ulogic_vector(3 downto 0);
current_state : out std_ulogic_vector(3 downto 0) );
end entity state_register;
architecture std_cell of state_register is
begin
end architecture std_cell;
-- end not in book
architecture fsm of bus_sequencer is
-- This architecture implements the sequencer as a finite-state machine.
-- NOTE: it uses the clock signals from clock_power_pkg to synchronize the fsm.
signal next_state_vector : -- . . .;
-- not in book
std_ulogic_vector(3 downto 0);
signal current_state_vector : std_ulogic_vector(3 downto 0);
-- end not in book
begin
bus_sequencer_state_register : entity work.state_register(std_cell)
port map ( phi1 => work.clock_power_pkg.clock_phase1,
phi2 => work.clock_power_pkg.clock_phase2,
next_state => next_state_vector,
-- . . . );
-- not in book
current_state => current_state_vector );
-- end not in book
-- . . .
end architecture fsm;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_163.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_163 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end add_163;
architecture augh of add_163 is
signal carry_inA : std_logic_vector(17 downto 0);
signal carry_inB : std_logic_vector(17 downto 0);
signal carry_res : std_logic_vector(17 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(16 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd | 4 | 1952 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00265ent IS
END c03s01b03x00p02n01i00265ent;
ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
type J is -- physical type decl
range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
type J1 is access J; -- Success_here
BEGIN
TESTING: PROCESS
variable k : J;
BEGIN
k := 10 C;
assert NOT( k=100 B )
report "***PASSED TEST: c03s01b03x00p02n01i00265"
severity NOTE;
assert ( k=100 B)
report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00265arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2772.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2772.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ABS is
end ABS;
ENTITY c13s09b00x00p99n01i02772ent IS
END c13s09b00x00p99n01i02772ent;
ARCHITECTURE c13s09b00x00p99n01i02772arch OF c13s09b00x00p99n01i02772ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02772 - Reserved word ABS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02772arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug016/pkg.vhdl | 3 | 24 | package pkg is
end pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd | 4 | 1252 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_latch.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity latch is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end entity latch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue458/repro.vhdl | 1 | 499 | entity repro is
end entity;
architecture A of repro is
signal S1 : bit := '0';
alias S1_delayed : bit is S1'delayed(100 ns);
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
process (S1) is
begin
assert false report "S1 = " & bit'image(S1) severity note;
end process;
process (S1_delayed) is
begin
assert false report "S1'delayed = " & bit'image(S1_delayed)
severity note;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd | 4 | 1881 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x01p01n02i00313ent IS
END c03s01b04x01p01n02i00313ent;
ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
constant C1 : REAL := -1.0E38 ;
constant C2 : REAL := +1.0E38 ;
BEGIN
TESTING: PROCESS
variable k1 : real;
variable k2 : real;
BEGIN
k1 := C1;
k2 := C2;
assert NOT(k1=C1 and k2=C2)
report "***PASSED TEST: c03s01b04x01p01n02i00313"
severity NOTE;
assert (k1=C1 and k2=C2)
report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x01p01n02i00313arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd | 4 | 1855 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p04n01i00965ent IS
END c06s03b00x00p04n01i00965ent;
ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
type Rcd is record
RE1: BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable var : Rcd;
BEGIN
var.RE1 := TRUE;
wait for 5 ns;
assert NOT(var.RE1 = TRUE)
report "***PASSED TEST: c06s03b00x00p04n01i00965"
severity NOTE;
assert (var.RE1 = TRUE)
report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00965arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1186/ent.vhdl | 1 | 236 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
component c is
generic (
G_REAL : real
);
end component;
begin
c_inst: c generic map (G_REAL => 1.5);
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue616/repro1.vhdl | 1 | 399 | package repro1 is
function return_true return boolean;
end repro1;
package body repro1 is
function slv_ones(constant width : in integer) return bit_vector is
begin
return (1 to width => '1');
end function;
function return_true return boolean is
constant ones_c : bit_vector(31 downto 0) := (others => '1');
begin
return ones_c = slv_ones(32);
end function;
end repro1;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd | 4 | 3531 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_18_06 is
end entity fg_18_06;
architecture test of fg_18_06 is
begin
-- code from book
stimulus_generator : process is
type directory_file is file of string;
file directory : directory_file open read_mode is "stimulus-directory";
variable file_name : string(1 to 50);
variable file_name_length : natural;
variable open_status : file_open_status;
subtype stimulus_vector is std_logic_vector(0 to 9);
type stimulus_file is file of stimulus_vector;
file stimuli : stimulus_file;
variable current_stimulus : stimulus_vector;
-- . . .
begin
file_loop : while not endfile(directory) loop
read( directory, file_name, file_name_length );
if file_name_length > file_name'length then
report "file name too long: " & file_name & "... - file skipped"
severity warning;
next file_loop;
end if;
file_open ( open_status, stimuli,
file_name(1 to file_name_length), read_mode );
if open_status /= open_ok then
report file_open_status'image(open_status) & " while opening file "
& file_name(1 to file_name_length) & " - file skipped"
severity warning;
next file_loop;
end if;
stimulus_loop : while not endfile(stimuli) loop
read(stimuli, current_stimulus);
-- . . . -- apply the stimulus
end loop stimulus_loop;
file_close(stimuli);
end loop file_loop;
wait;
end process stimulus_generator;
-- end code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-string-character.vhdl | 4 | 397 | entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable concatted : string(1 to 4);
begin -- process doit
concatted := "foo" & 'l';
assert concatted = "fool" report "TEST FAILED - concatted was not 'fool'" severity failure;
assert not(concatted = "fool") report "TEST PASSED" severity note;
wait;
end process doit;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1527.vhd | 4 | 1670 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1527.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01527ent IS
END c08s09b00x00p08n01i01527ent;
ARCHITECTURE c08s09b00x00p08n01i01527arch OF c08s09b00x00p08n01i01527ent IS
BEGIN
TESTING: PROCESS
variable NSS : integer := 5;
variable MIN : integer := 6;
BEGIN
while NSS * MIN loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01527 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01527arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd | 4 | 1750 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1521.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p05n01i01521ent IS
END c08s09b00x00p05n01i01521ent;
ARCHITECTURE c08s09b00x00p05n01i01521arch OF c08s09b00x00p05n01i01521ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
T:
while k < 5 loop
k := k + 1;
end loop T;
assert NOT(k = 5)
report "***PASSED TEST: c08s09b00x00p05n01i01521"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s09b00x00p05n01i01521 - Syntax of a labeled while loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p05n01i01521arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/arr01/arr09.vhdl | 1 | 509 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr09 is
port (val : std_logic_vector(3 downto 0);
res : out character);
end arr09;
architecture behav of arr09 is
type map_type is array (natural range 0 to 15) of character;
constant cmap : map_type := "0123456789abcdef";
function convert (v : natural range 0 to 15) return character
is
variable r : character;
begin
r := cmap (v);
return r;
end convert;
begin
res <= convert (3);
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2579.vhd | 4 | 1722 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p12n01i02579ent IS
port (PT:BOOLEAN) ;
ty
pe ONE is range 1 to 1;
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
END c13s02b00x00p12n01i02579ent;
ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
b
egin
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s02b00x00p12n01i02579arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1883.vhd | 4 | 1897 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1883.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01883ent IS
END c07s01b00x00p08n01i01883ent;
ARCHITECTURE c07s01b00x00p08n01i01883arch OF c07s01b00x00p08n01i01883ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
obus <= (0 =>c07s01b00x00p08n01i01883arch, others => 5) after 5 ns;
-- architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01883 - Architecture body names are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01883arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd | 4 | 2147 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity tb_ROM_write_data is
end entity tb_ROM_write_data;
architecture writer of tb_ROM_write_data is
begin
process is
subtype word is std_logic_vector(0 to 7);
type load_file_type is file of word;
file load_file : load_file_type open write_mode is "tb_ROM.dat";
begin
write(load_file, word'(X"00"));
write(load_file, word'(X"01"));
write(load_file, word'(X"02"));
write(load_file, word'(X"03"));
write(load_file, word'(X"04"));
write(load_file, word'(X"05"));
write(load_file, word'(X"06"));
write(load_file, word'(X"07"));
write(load_file, word'(X"08"));
write(load_file, word'(X"09"));
write(load_file, word'(X"0A"));
write(load_file, word'(X"0B"));
write(load_file, word'(X"0C"));
write(load_file, word'(X"0D"));
write(load_file, word'(X"0E"));
write(load_file, word'(X"0F"));
wait;
end process;
end architecture writer;
library ieee; use ieee.std_logic_1164.all;
entity tb_ROM is
end entity tb_ROM;
architecture test of tb_ROM is
signal sel : std_logic;
signal address : std_logic_vector(3 downto 0);
signal data : std_logic_vector(0 to 7);
begin
dut : entity work.ROM(behavioral)
generic map ( load_file_name => "tb_ROM.dat" )
port map ( sel, address, data );
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1396.vhd | 4 | 1638 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1396.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p06n01i01396ent IS
END c08s05b00x00p06n01i01396ent;
ARCHITECTURE c08s05b00x00p06n01i01396arch OF c08s05b00x00p06n01i01396ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := (1.0 + 2.0);
assert FALSE
report "***FAILED TEST: c08s05b00x00p06n01i01396 - The variable and assigned expression must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01396arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd | 4 | 1089 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity multiplier_test is
end entity multiplier_test;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue953/ent.vhdl | 1 | 270 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity ent is
end;
architecture a of ent is
signal x : unsigned(7 downto 0);
signal y : unsigned(7 downto 0);
signal z : unsigned(15 downto 0);
begin
y <= x / 2;
z <= x * 2;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd | 4 | 3059 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_sequencer is
port ( rd, wr, sel, width, burst : out std_ulogic;
addr_low_2 : out std_ulogic_vector(1 downto 0);
ready : out std_ulogic;
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
other_signal : out std_ulogic );
end entity bus_sequencer;
----------------
library ieee; use ieee.std_logic_1164.all;
entity state_register is
port ( phi1, phi2 : in std_ulogic;
next_state : in std_ulogic_vector(3 downto 0);
current_state : out std_ulogic_vector(3 downto 0) );
end entity state_register;
architecture std_cell of state_register is
begin
end architecture std_cell;
-- end not in book
architecture fsm of bus_sequencer is
-- This architecture implements the sequencer as a finite state machine.
-- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm.
signal next_state_vector : -- . . .;
-- not in book
std_ulogic_vector(3 downto 0);
signal current_state_vector : std_ulogic_vector(3 downto 0);
-- end not in book
begin
bus_sequencer_state_register : entity work.state_register(std_cell)
port map ( phi1 => work.clock_pkg.clock_phase1,
phi2 => work.clock_pkg.clock_phase2,
next_state => next_state_vector,
-- . . . );
-- not in book
current_state => current_state_vector );
-- end not in book
-- . . .
end architecture fsm;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2594.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2594.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02594ent IS
END c13s03b01x00p02n01i02594ent;
ARCHITECTURE c13s03b01x00p02n01i02594arch OF c13s03b01x00p02n01i02594ent IS
BEGIN
TESTING: PROCESS
variable k{ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02594 - Identifier can not end with '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02594arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd | 4 | 1347 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity real_subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end entity real_subcircuit;
architecture basic of real_subcircuit is
begin
y1 <= a and b after 10 ns;
y2 <= a nand b after 10 ns;
end architecture basic;
-- code from book
configuration full of circuit is
for with_pad_delays -- configure the architecture
for functionality -- configure the block
for all : subcircuit
use entity work.real_subcircuit(basic);
end for;
end for;
end for;
end configuration full;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/mem02/tb_ram4.vhdl | 1 | 996 | entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal rdat : std_logic_vector(1 downto 0);
signal raddr : std_logic_vector(1 downto 0);
signal init : std_logic_vector(7 downto 0);
signal rst : std_logic;
signal clk : std_logic;
begin
dut: entity work.ram4
port map (raddr => raddr, rdat => rdat, rst => rst, init => init,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
init <= b"01_11_00_10";
pulse;
rst <= '0';
init <= b"00_00_00_00";
raddr <= "00";
pulse;
assert rdat = "10" severity failure;
raddr <= "11";
pulse;
assert rdat = "01" severity failure;
raddr <= "01";
pulse;
assert rdat = "00" severity failure;
raddr <= "10";
pulse;
assert rdat = "11" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue692/repro.vhdl | 1 | 396 | entity repro is
end;
architecture behav of repro
is
function test (l : natural) return boolean is
variable v : bit_vector (l - 1 downto 0);
begin
assert v (l / 2) = '0';
assert v (0) = '0';
assert v (l - 1) = '0';
return True;
end test;
begin
process
variable res : boolean;
begin
res := test (128 * 1024);
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd | 4 | 1486 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mac is
port ( clk, clr : in std_ulogic;
x_real : in std_ulogic_vector(15 downto 0);
x_imag : in std_ulogic_vector(15 downto 0);
y_real : in std_ulogic_vector(15 downto 0);
y_imag : in std_ulogic_vector(15 downto 0);
s_real : out std_ulogic_vector(15 downto 0);
s_imag : out std_ulogic_vector(15 downto 0);
ovf : out std_ulogic );
end entity mac;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug24324/tb_thingy1.vhdl | 2 | 304 | entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
port (
x_x : in bit;
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
port map (
x-x => stimuli, -- <== spelling error
y_y => response
);
end tb;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/oper02/tb_min01.vhdl | 1 | 398 | entity tb_min01 is
end tb_min01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_min01 is
signal l, r : natural;
signal res : natural;
begin
min01_1: entity work.min01
port map (
a => l,
b => r,
o => res);
process
begin
l <= 12;
r <= 15;
wait for 1 ns;
assert res = 12 severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/mul_210.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_210 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_210;
architecture augh of mul_210 is
signal tmp_res : signed(63 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(40 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd | 4 | 1079 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity to_fp_test is
end entity to_fp_test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd | 4 | 2847 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc571.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:32 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00571ent IS
END c03s04b01x00p01n01i00571ent;
ARCHITECTURE c03s04b01x00p01n01i00571arch OF c03s04b01x00p01n01i00571ent IS
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vector_file is file of integer_cons_vector;
constant C19 : integer_cons_vector := (others => 3);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_cons_vector_file open read_mode is "iofile.30";
variable v : integer_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00571"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00571 - File reading operation (integer_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00571arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1603.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01603ent IS
END c08s11b00x00p04n01i01603ent;
ARCHITECTURE c08s11b00x00p04n01i01603arch OF c08s11b00x00p04n01i01603ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when i = 6;
k := i;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p04n01i01603"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p04n01i01603 - Exit from the labeled loop when the condition of the WHEN clause evaluates to be true"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01603arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd | 4 | 2162 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02452ent IS
END c07s03b02x02p03n02i02452ent;
ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 5 );
function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
begin
return A;
end F;
function F2 return CONSTRAINED_ARRAY is
begin
return F( ( others => 'c' ) );
-- sole "others" choice is legal.
end F2;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F2;
assert NOT(k="ccccc")
report "***PASSED TEST: c07s03b02x02p03n02i02452"
severity NOTE;
assert (k="ccccc")
report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02452arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd | 4 | 3849 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package counter_types is
-- code in book (in text)
subtype digit is bit_vector(3 downto 0);
-- end code in book (in text)
end package counter_types;
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
use work.counter_types.all;
-- end not in book
entity counter is
port ( clk, clr : in bit;
q0, q1 : out digit );
end entity counter;
--------------------------------------------------
architecture registered of counter is
signal current_val0, current_val1, next_val0, next_val1 : digit;
begin
val0_reg : entity work.reg4(struct)
port map ( d0 => next_val0(0), d1 => next_val0(1),
d2 => next_val0(2), d3 => next_val0(3),
q0 => current_val0(0), q1 => current_val0(1),
q2 => current_val0(2), q3 => current_val0(3),
clk => clk, clr => clr );
val1_reg : entity work.reg4(struct)
port map ( d0 => next_val1(0), d1 => next_val1(1),
d2 => next_val1(2), d3 => next_val1(3),
q0 => current_val1(0), q1 => current_val1(1),
q2 => current_val1(2), q3 => current_val1(3),
clk => clk, clr => clr );
incr0 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val0(0), d1 => current_val0(1),
d2 => current_val0(2), d3 => current_val0(3),
y0 => next_val0(0), y1 => next_val0(1),
y2 => next_val0(2), y3 => next_val0(3) );
-- end not in book
incr1 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val1(0), d1 => current_val1(1),
d2 => current_val1(2), d3 => current_val1(3),
y0 => next_val1(0), y1 => next_val1(1),
y2 => next_val1(2), y3 => next_val1(3) );
-- end not in book
buf0 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val0(0), a1 => current_val0(1),
a2 => current_val0(2), a3 => current_val0(3),
y0 => q0(0), y1 => q0(1),
y2 => q0(2), y3 => q0(3) );
-- end not in book
buf1 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val1(0), a1 => current_val1(1),
a2 => current_val1(2), a3 => current_val1(3),
y0 => q1(0), y1 => q1(1),
y2 => q1(2), y3 => q1(3) );
-- end not in book
end architecture registered;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd | 4 | 1653 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_23a is
end entity inline_23a;
architecture test of inline_23a is
signal digital_level : integer;
constant num_levels : integer := 63;
constant max_voltage : real := 10.0;
begin
block_1 : block is
quantity analog_voltage : real;
begin
-- code from book
analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
-- end code from book
end block block_1;
block_2 : block is
signal real_digital_level : real;
quantity analog_voltage : real;
begin
-- code from book
real_digital_level <= real(digital_level);
analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
-- end code from book
end block block_2;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd | 4 | 2489 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc586.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:38 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:52 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:15 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00586ent IS
END c03s04b01x00p01n01i00586ent;
ARCHITECTURE c03s04b01x00p01n01i00586arch OF c03s04b01x00p01n01i00586ent IS
type real_cons_vector is array (15 downto 0) of real;
type real_cons_vector_file is file of real_cons_vector;
constant C19 : real_cons_vector := (others => 3.0);
BEGIN
TESTING: PROCESS
file filein : real_cons_vector_file open write_mode is "iofile.31";
BEGIN
for i in 1 to 100 loop
write(filein, C19);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00586 - The output file will be verified by test s010244.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00586arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd | 4 | 2824 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_02_a is
end entity fg_18_02_a;
architecture writer of fg_18_02_a is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity fg_18_02 is
end entity fg_18_02;
architecture test of fg_18_02 is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc245.vhd | 4 | 1698 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc245.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00245ent IS
END c03s01b02x00p04n01i00245ent;
ARCHITECTURE c03s01b02x00p04n01i00245arch OF c03s01b02x00p04n01i00245ent IS
type I1 is range 1 to 9.0; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00245 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00245arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue317/OSVVM/OsvvmGlobalPkg.vhd | 3 | 13180 | --
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Global Settings for OSVVM packages
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2014: 2015.01 Initial revision
--
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use std.textio.all ;
use work.NamePkg.all ;
package OsvvmGlobalPkg is
-- FILE IO Global File Identifier -- Open using AlertLogPkg.TranscriptOpen
-- file TranscriptFile : text ;
-- Shared Options Type used in OSVVM
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
function IsEnabled (A : OsvvmOptionsType) return boolean ; -- Requires that TRUE is last and ENABLED is 2nd to last
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
-- Accessor Functions
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType ;
function IsOsvvmStringSet (A : string) return boolean ;
function ResolveOsvvmOption(A, B : string) return string ;
function ResolveOsvvmOption(A, B, C : string) return string ;
function ResolveOsvvmOption(A, B, C, D : string) return string ;
impure function ResolveOsvvmWritePrefix(A : String) return string ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string ;
impure function ResolveOsvvmDoneName(A : String) return string ;
impure function ResolveOsvvmDoneName(A, B : String) return string ;
impure function ResolveOsvvmPassName(A : String) return string ;
impure function ResolveOsvvmPassName(A, B : String) return string ;
impure function ResolveOsvvmFailName(A : String) return string ;
impure function ResolveOsvvmFailName(A, B : String) return string ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
procedure OsvvmDeallocate ;
type OptionsPType is protected
procedure Set (A: OsvvmOptionsType) ;
impure function get return OsvvmOptionsType ;
end protected OptionsPType ;
end OsvvmGlobalPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body OsvvmGlobalPkg is
type OptionsPType is protected body
variable GlobalVar : OsvvmOptionsType ;
procedure Set (A : OsvvmOptionsType) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return OsvvmOptionsType is
begin
return GlobalVar ;
end function get ;
end protected body OptionsPType ;
shared variable WritePrefixVar : NamePType ;
shared variable DoneNameVar : NamePType ;
shared variable PassNameVar : NamePType ;
shared variable FailNameVar : NamePType ;
shared variable WritePassFailVar : OptionsPType ; -- := FALSE ;
shared variable WriteBinInfoVar : OptionsPType ; -- := TRUE ;
shared variable WriteCountVar : OptionsPType ; -- := TRUE ;
shared variable WriteAnyIllegalVar : OptionsPType ; -- := FALSE ;
function IsEnabled (A : OsvvmOptionsType) return boolean is
begin
return A >= ENABLED ;
end function IsEnabled ;
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType is
begin
if A then
return TRUE ;
else
return FALSE ;
end if ;
end function to_OsvvmOptionsType ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= OPT_INIT_PARM_DETECT then
WritePassFailVar.Set(WritePassFail) ;
end if ;
if WriteBinInfo /= OPT_INIT_PARM_DETECT then
WriteBinInfoVar.Set(WriteBinInfo) ;
end if ;
if WriteCount /= OPT_INIT_PARM_DETECT then
WriteCountVar.Set(WriteCount) ;
end if ;
if WriteAnyIllegal /= OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar.Set(WriteAnyIllegal) ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetOsvvmGlobalOptions ;
------------------------------------------------------------
-- Accessor Functions
-- Local Function
function IsOsvvmOptionSet (A : OsvvmOptionsType) return boolean is
begin
return A > OPT_USE_DEFAULT ;
end function IsOsvvmOptionSet ;
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
elsif IsOsvvmOptionSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
-- Local Function
function IsOsvvmStringSet (A : string) return boolean is
begin
if A'length = 0 then -- Null strings permitted
return TRUE ;
else
return A(A'left) /= NUL ;
end if;
end function IsOsvvmStringSet ;
function ResolveOsvvmOption(A, B : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
else
return B ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
elsif IsOsvvmStringSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
impure function ResolveOsvvmWritePrefix(A : String) return string is
begin
return ResolveOsvvmOption(A, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmDoneName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A : String) return string is
begin
return ResolveOsvvmOption(A, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmPassName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A : String) return string is
begin
return ResolveOsvvmOption(A, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveOsvvmFailName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
procedure OsvvmDeallocate is
begin
-- Free up space used by NamePType within OsvvmGlobalPkg
WritePrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
WritePassFailVar.Set(FALSE) ; -- := FALSE ;
WriteBinInfoVar.Set(TRUE ) ; -- := TRUE ;
WriteCountVar.Set(TRUE ) ; -- := TRUE ;
WriteAnyIllegalVar.Set(FALSE) ; -- := FALSE ;
end procedure OsvvmDeallocate ;
end package body OsvvmGlobalPkg ; | gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2069.vhd | 4 | 1853 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2069.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02069ent IS
END c07s02b04x00p01n02i02069ent;
ARCHITECTURE c07s02b04x00p01n02i02069arch OF c07s02b04x00p01n02i02069ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable TIMEV : TIME := 1 ns;
BEGIN
POSV := POSV + TIMEV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02069 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02069arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc823.vhd | 4 | 1675 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc823.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00823ent IS
END c01s02b02x00p02n01i00823ent;
ARCHITECTURE c01s02b02x00p02n01i00823arch OF c01s02b02x00p02n01i00823ent IS
BEGIN
L: loop -- illegal location for loop statement
end loop L;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00823 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00823arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd | 4 | 2342 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book:
entity and3 is
port ( a, b, c : in bit := '1';
z, not_z : out bit);
end entity and3;
-- end of code from book
----------------------------------------------------------------
architecture functional of and3 is
begin
non_inverting:
z <= a and b and c;
inverting:
not_z <= not (a and b and c);
end architecture functional;
----------------------------------------------------------------
entity inline_24 is
end entity inline_24;
----------------------------------------------------------------
library util; use util.stimulus_generators.all;
architecture test of inline_24 is
signal s1, s2, ctrl1_a, ctrl1_b : bit;
signal test_input : bit_vector(1 to 2);
begin
block_4_a : block is
port ( ctrl1 : out bit );
port map ( ctrl1 => ctrl1_a );
begin
-- code from book:
g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 );
-- end of code from book
end block block_4_a;
----------------
block_4_b : block is
port ( ctrl1 : out bit );
port map ( ctrl1 => ctrl1_b );
begin
-- code from book:
g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1,
c => open, z => open );
-- end of code from book
end block block_4_b;
----------------
stimulus : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(s1, s2) <= test_input;
verifier :
assert ctrl1_a = ctrl1_b
report "versions differ";
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd | 4 | 2221 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end entity buf;
architecture basic of buf is
begin
y <= a;
end architecture basic;
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end entity fanout_tree;
--------------------------------------------------
architecture recursive of fanout_tree is
begin
degenerate_tree : if height = 0 generate
begin
output(0) <= input;
end generate degenerate_tree;
compound_tree : if height > 0 generate
signal buffered_input_0, buffered_input_1 : std_logic;
begin
buf_0 : entity work.buf(basic)
port map ( a => input, y => buffered_input_0 );
subtree_0 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_0,
output => output(0 to 2**(height - 1) - 1) );
buf_1 : entity work.buf(basic)
port map ( a => input, y => buffered_input_1 );
subtree_1 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_1,
output => output(2**(height - 1) to 2**height - 1) );
end generate compound_tree;
end architecture recursive;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc828.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc828.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00828ent IS
END c01s02b02x00p02n01i00828ent;
ARCHITECTURE c01s02b02x00p02n01i00828arch OF c01s02b02x00p02n01i00828ent IS
BEGIN
wait 3 ns; -- illegal location for wait statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00828 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00828arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1772.vhd | 4 | 1814 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1772.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p11n01i01772ent IS
END c09s05b02x00p11n01i01772ent;
ARCHITECTURE c09s05b02x00p11n01i01772arch OF c09s05b02x00p11n01i01772ent IS
signal i, j : integer := 1;
BEGIN
j <= transport 1 when 1,
2 when 2;
-- Failure_here
-- Not every value of select expressions is represented.
-- 'others' choice is needed.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b02x00p11n01i01772 - Each value of the type of the select expression is represented once and only once in teh set of choices."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b02x00p11n01i01772arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd | 4 | 2917 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3126.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p12n01i03126ent_a IS
generic ( g1 : integer := 3 );
END c05s02b01x02p12n01i03126ent_a;
ARCHITECTURE c05s02b01x02p12n01i03126arch_a OF c05s02b01x02p12n01i03126ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert g1 /= 2 report "g1 = 2" severity FAILURE;
assert g1 /= 3 report "g1 = 3" severity FAILURE;
assert g1 = 4 report "g1 /= 4" severity FAILURE;
assert g1 /= 5 report "g1 = 5" severity FAILURE;
assert g1 /= 6 report "g1 = 6" severity FAILURE;
assert NOT( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***PASSED TEST: c05s02b01x02p12n01i03126"
severity NOTE;
assert ( g1 /= 2 and
g1 /= 3 and
g1 = 4 and
g1 /= 5 and
g1 /= 6 )
report "***FAILED TEST: c05s02b01x02p12n01i03126 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p12n01i03126arch_a;
ENTITY c05s02b01x02p12n01i03126ent IS
END c05s02b01x02p12n01i03126ent;
ARCHITECTURE c05s02b01x02p12n01i03126arch OF c05s02b01x02p12n01i03126ent IS
component ic_socket
generic ( g1 : integer := 2 );
end component;
for instance : ic_socket use entity work.c05s02b01x02p12n01i03126ent_a (c05s02b01x02p12n01i03126arch_a)
generic map ( g1 => g1 + g1 );
BEGIN
instance : ic_socket ;
END c05s02b01x02p12n01i03126arch;
configuration c05s02b01x02p12n01i03126cfg of c05s02b01x02p12n01i03126ent is
for c05s02b01x02p12n01i03126arch
end for;
end c05s02b01x02p12n01i03126cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2654.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2654.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02654ent IS
END c13s03b01x00p02n01i02654ent;
ARCHITECTURE c13s03b01x00p02n01i02654arch OF c13s03b01x00p02n01i02654ent IS
BEGIN
TESTING: PROCESS
variable /k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02654 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02654arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1290.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1290.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01290ent IS
port (X : in BIT; COUT : out BIT);
END c08s04b00x00p04n01i01290ent;
ARCHITECTURE c08s04b00x00p04n01i01290arch OF c08s04b00x00p04n01i01290ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
X(2) <= S1;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01290 - A port whose mode is "IN" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01290arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd | 4 | 1948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00285ent IS
END c03s01b03x00p12n01i00285ent;
ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
type time is range 0 to 1E8 units
fs;
ps = 10 fs;
end units;
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i:=time'pos(ps);
assert NOT(i=10)
report "***PASSED TEST: c03s01b03x00p12n01i00285"
severity NOTE;
assert (i=10)
report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00285arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd | 4 | 1886 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02270ent IS
END c07s02b06x00p14n01i02270ent;
ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
variable k : phys := 10 p2;
BEGIN
assert NOT(k = 2 p3)
report "***PASSED TEST: c07s02b06x00p14n01i02270"
severity NOTE;
assert (k = 2 p3)
report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02270arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug22868/fails2.vhdl | 3 | 407 | library ieee;
use ieee.std_logic_1164.all;
entity fails2 is
port(
x : in std_logic;
y : out std_logic_vector(7 downto 0);
z : out std_logic
);
end fails2;
architecture a of fails2 is
component subcomponent is
port(
x : in std_logic;
y : out std_logic_vector(8 downto 0)
);
end component;
begin
s : subcomponent
port map(
x => x,
y(cheese downto 1) => y,
y(0) => z
);
end a;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd | 4 | 2444 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3101.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p11n01i03101ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p11n01i03101ent;
ARCHITECTURE c05s01b00x00p11n01i03101arch OF c05s01b00x00p11n01i03101ent IS
FUNCTION one ( par1 : INTEGER ) RETURN INTEGER IS BEGIN END;
FUNCTION two ( par1 : INTEGER ) RETURN INTEGER IS BEGIN END;
FUNCTION tww ( par1,par2 : STRING ) RETURN INTEGER IS BEGIN END;
ATTRIBUTE attr1 OF all: FUNCTION IS 99;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT one'attr1 = 99 REPORT "ERROR: Wrong value for one 'attr1" SEVERITY FAILURE;
ASSERT two'attr1 = 99 REPORT "ERROR: Wrong value for two 'attr1" SEVERITY FAILURE;
ASSERT tww'attr1 = 99 REPORT "ERROR: Wrong value for tww 'attr1" SEVERITY FAILURE;
assert NOT( one'attr1 = 99 and
two'attr1 = 99 and
tww'attr1 = 99 )
report "***PASSED TEST: c05s01b00x00p11n01i03101"
severity NOTE;
assert ( one'attr1 = 99 and
two'attr1 = 99 and
tww'attr1 = 99 )
report "***FAILED TEST: c05s01b00x00p11n01i03101 - Reserved word all as attribute specification test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p11n01i03101arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd | 4 | 1879 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p05n01i02500ent IS
END c07s03b03x00p05n01i02500ent;
ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
BEGIN
TESTING: PROCESS
function f1(constant p : in STRING) return INTEGER is
begin
return P'LENGTH;
end;
constant C : STRING := "Testing";
BEGIN
wait for 5 ns;
assert NOT(f1(c) = c'LENGTH)
report "***PASSED TEST: c07s03b03x00p05n01i02500"
severity NOTE;
assert (f1(c) = c'LENGTH)
report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p05n01i02500arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dispin01/pkg_rec02.vhdl | 2 | 168 | library ieee;
use ieee.std_logic_1164.all;
package rec02_pkg is
type myrec is record
a : natural range 0 to 5;
b : std_logic;
end record;
end rec02_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1615.vhd | 4 | 1682 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1615.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p02n01i01615ent IS
END c08s12b00x00p02n01i01615ent;
ARCHITECTURE c08s12b00x00p02n01i01615arch OF c08s12b00x00p02n01i01615ent IS
function ts (x1:bit) return integer is
begin
return(1)
end ts;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := ts('1');
assert FALSE
report "***FAILED TEST: c08s12b00x00p02n01i01615 - Missing semicolon in the loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p02n01i01615arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue418/repro.vhdl | 1 | 2292 | entity repro is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of repro is
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
subtype ST_AXILite_32 is t_axilite_if (
write_address_channel (
awaddr(31 downto 0) ),
write_data_channel (
wdata(31 downto 0),
wstrb(3 downto 0) ),
read_address_channel (
araddr(31 downto 0) ),
read_data_channel (
rdata(31 downto 0) )
);
signal s : st_axilite_32;
begin
s.write_address_channel.awaddr <= x"0000_1000", x"1000_ffff" after 2 ns;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd | 4 | 2942 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc591.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:54 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:16 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00591ent IS
END c03s04b01x00p01n01i00591ent;
ARCHITECTURE c03s04b01x00p01n01i00591arch OF c03s04b01x00p01n01i00591ent IS
type severity_level_vector is array (natural range <>) of severity_level;
type severity_level_vector_file is file of severity_level_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_file open read_mode is "iofile.24";
variable v : severity_level_vector(0 to 1);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 2) report "wrong length passed during read operation";
if (v /= (note,error)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00591"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00591 - File reading operation (severity_level_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00591arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl | 4 | 892 | entity forty_two is
port (
bv_out : out bit_vector );
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
bv_out <= "0110";
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two_component
port (
c_bv_out : out bit_vector );
end component;
for ft0 : forty_two_component
use entity work.forty_two(only)
port map (
bv_out => c_bv_out );
signal bv_signal : bit_vector( 3 downto 0 );
begin -- only
ft0 : component forty_two_component
port map (
c_bv_out => bv_signal );
test: process
begin -- process test
wait for 1 ms;
assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2658.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2658.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02658ent IS
END c13s03b01x00p02n01i02658ent;
ARCHITECTURE c13s03b01x00p02n01i02658arch OF c13s03b01x00p02n01i02658ent IS
BEGIN
TESTING: PROCESS
variable =k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02658 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02658arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd | 4 | 1946 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity and2 is
generic ( Tpd : time );
port ( a, b : in bit; y : out bit );
end entity and2;
architecture simple of and2 is
begin
and2_function :
y <= a and b after Tpd;
end architecture simple;
-- end code from book
entity ch_12_01 is
end entity ch_12_01;
library stimulus;
use stimulus.stimulus_generators.all;
architecture test of ch_12_01 is
signal a1, b1, sig1, sig2, sig_out : bit;
signal test_vector : bit_vector(1 to 3);
begin
-- code from book
gate1 : entity work.and2(simple)
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, y => sig_out );
gate2 : entity work.and2(simple)
generic map ( Tpd => 3 ns )
port map ( a => a1, b => b1, y => sig1 );
-- end code from book
stimulus : all_possible_values ( bv => test_vector,
delay_between_values => 10 ns );
(sig2, a1, b1) <= test_vector;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1211/tb_repro1.vhdl | 1 | 900 | entity tb_repro1 is
end tb_repro1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro1 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.repro1
port map (
sig_out => dout,
sig_in => din,
clock => clk,
reset => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
rst <= '0';
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
rst <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd | 4 | 3385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_03 is
end entity ch_04_03;
----------------------------------------------------------------
architecture test of ch_04_03 is
subtype coeff_ram_address is integer range 0 to 63;
-- code from book:
type coeff_array is array (coeff_ram_address) of real;
-- end of code from book
begin
process_04_1_c : process is
-- code from book:
type point is array (1 to 3) of real;
constant origin : point := (0.0, 0.0, 0.0);
variable view_point : point := (10.0, 20.0, 0.0);
-- end of code from book
begin
wait;
end process process_04_1_c;
process_04_1_d : process is
type point is array (1 to 3) of real;
-- code from book:
variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_d;
process_04_1_e : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_e;
process_04_1_f : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_f;
process_04_1_g : process is
-- code from book:
variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_g;
process_04_1_h : process is
-- code from book:
-- error: Associations in array aggregate must be all named or all positional
-- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal
-- end of code from book
begin
wait;
end process process_04_1_h;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3105.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3105.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p16n02i03105ent IS
END c05s01b00x00p16n02i03105ent;
ARCHITECTURE c05s01b00x00p16n02i03105arch OF c05s01b00x00p16n02i03105ent IS
attribute ill1 : real;
signal s1, s2 : integer;
attribute ill1 of s1 : signal is 10.0;
attribute ill1 of others : signal is 10; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p16n02i03105 - The type of the expression in the attribute specification is not the same as (or implicitly convertible to) the type mark in the corresponding attribute declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p16n02i03105arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1250.vhd | 4 | 1614 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1250.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01250ent IS
END c08s02b00x00p04n02i01250ent;
ARCHITECTURE c08s02b00x00p04n02i01250arch OF c08s02b00x00p04n02i01250ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
severity 3.0;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01250 - Static expression must be of type SEVERITY_LEVEL"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01250_arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01993ent IS
END c07s02b02x00p07n01i01993ent;
ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m /= 4.5) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01993"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01993arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd | 4 | 3099 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
type integer_file is file of integer;
begin
process is
-- code from book:
file lookup_table_file, result_file : integer_file;
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
-- end of code from book
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file open read_mode is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file;
-- . . .
-- end of code from book
begin
-- code from book:
file_open ( lookup_table_file,
external_name => "lookup-values", open_kind => read_mode );
-- end of code from book
wait;
end process;
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type file_open_status is (open_ok, status_error, name_error, mode_error);
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
procedure file_close ( file f : file_type );
-- end of code from book
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
procedure file_close ( file f : file_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd | 4 | 1328 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_join.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
entity join is
generic ( name : string;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_vector;
out_arc : out arc_type;
info_detail : in info_detail_type );
end join;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/slice02/tb_slice01.vhdl | 1 | 406 | entity tb_slice01 is
end tb_slice01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice01 is
signal di : std_logic_vector (7 downto 0);
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice01
port map (di, do);
process
begin
di <= b"11_10_01_00";
wait for 1 ns;
assert do = b"10_11" severity error;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd | 4 | 2186 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc676.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00676ent IS
END c03s04b01x00p23n01i00676ent;
ARCHITECTURE c03s04b01x00p23n01i00676arch OF c03s04b01x00p23n01i00676ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.54";
-- Declare a variable.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00676 - The output file will tested by test file s010422.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00676arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1320.vhd | 4 | 1780 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1320.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n03i01320ent IS
END c08s04b00x00p08n03i01320ent;
ARCHITECTURE c08s04b00x00p08n03i01320arch OF c08s04b00x00p08n03i01320ent IS
type BIT_VECTOR is array (natural range <>) of bit;
subtype BVI is BIT_VECTOR(0 to 31);
signal S : BVI;
BEGIN
TESTING: PROCESS
BEGIN
(S(0 to 5), S(6), S(7 to 7)) <= BVI'(0 to 5 => '0', 6 => '1', others => '0');
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n03i01320 - The expression in element association can not be a discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n03i01320arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd | 4 | 2045 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2016.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p16n02i02016ent IS
END c07s02b02x00p16n02i02016ent;
ARCHITECTURE c07s02b02x00p16n02i02016arch OF c07s02b02x00p16n02i02016ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable array_1 : array_three := (6,5,4,3,2,1);
variable array_2 : array_three := (6,5,4,1,2,3);
variable k : integer := 0;
BEGIN
if array_1 > array_2 then
k := 5;
end if;
wait for 5 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p16n02i02016"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p16n02i02016 - The relations > (greater than) and >= (greater than or equal) are defined to be the complements of the <= and < operators respectively for the same two operands."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p16n02i02016arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1286.vhd | 4 | 1774 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1286.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01286ent IS
port (X : in BIT_VECTOR; COUT : out BIT);
alias ALIAN_1 : BIT_VECTOR (1 to 10) is X (1 to 10);
END c08s04b00x00p04n01i01286ent;
ARCHITECTURE c08s04b00x00p04n01i01286arch OF c08s04b00x00p04n01i01286ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
ALIAN_1 <= S1;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01286 - An alias for a port whose mode is "IN" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01286arch;
| gpl-2.0 |
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